diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 7c6111b6d4e..41107d7d35e 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -104,7 +104,7 @@

NuttX RTOS

-

Last Updated: May 19, 2019

+

Last Updated: July 11, 2019

@@ -2771,14 +2771,21 @@ nsh>

NXP LPC11xx. Support is provided for the NXP LPC11xx family of processors. - In particular, support is provided for LPCXpression LPC1115 board. + In particular, support is provided for LPCXpresso LPC1115 board. This port was contributed by Alan Carvalho de Assis.

diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html index 7746ee3c5ce..d2c7b292d86 100644 --- a/Documentation/NuttxPortingGuide.html +++ b/Documentation/NuttxPortingGuide.html @@ -6273,7 +6273,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta

Examples: - arch/arm/src/lpc17xx/lpc17_usbhost.c, + arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c, arch/arm/src/stm32/stm32_otgfshost.c, arch/arm/src/sama5/sam_ohci.c, and arch/arm/src/sama5/sam_ehci.c. @@ -6366,7 +6366,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta

Examples: - The function nsh_waiter() in the file configs/olimex-lpc1766stk/src/lpc17_appinit.c. + The function nsh_waiter() in the file configs/olimex-lpc1766stk/src/lpc17_40_appinit.c.

  • @@ -6409,7 +6409,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta

    Examples: - arch/arm/src/dm320/dm320_usbdev.c, arch/arm/src/lpc17xx/lpc17_usbdev.c, + arch/arm/src/dm320/dm320_usbdev.c, arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c, arch/arm/src/lpc214x/lpc214x_usbdev.c, arch/arm/src/lpc313x/lpc313x_usbdev.c, and arch/arm/src/stm32/stm32_usbdev.c.

    diff --git a/Documentation/README.html b/Documentation/README.html index fa56f3d72df..18f537a3096 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -153,8 +153,6 @@ nuttx/ | | `- README.txt | |- lpc4370-link2/ | | `- README.txt - | |- lpcxpresso-lpc1115/ - | | `- README.txt | |- lpcxpresso-lpc1768/ | | `- README.txt | |- lpcxpresso-lpc54628/ diff --git a/Documentation/UsbTrace.html b/Documentation/UsbTrace.html index 2b26986e7f9..895b524df4d 100644 --- a/Documentation/UsbTrace.html +++ b/Documentation/UsbTrace.html @@ -112,7 +112,7 @@
  • For the USB device driver, that 8-bit event data is provided within the USB device driver itself. - So, for example, the 8-bit event data for the LPC1768 USB device driver is found in arch/arm/src/lpc17xx/lpc17_usbdev.c. + So, for example, the 8-bit event data for the LPC1768 USB device driver is found in arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c.

    • 16-bit Trace Data. @@ -237,28 +237,28 @@ 3 TRACE_INTENTRY_ID1 1 - LPC17_TRACEINTID_USB2 + LPC17_40_TRACEINTID_USB2 0039 4 TRACE_INTDECODE_ID2 7 - LPC17_TRACEINTID_DEVSTAT2 + LPC17_40_TRACEINTID_DEVSTAT2 0019 5 TRACE_INTDECODE_ID2 32 - LPC17_TRACEINTID_SUSPENDCHG2 + LPC17_40_TRACEINTID_SUSPENDCHG2 0019 6 TRACE_INTDECODE_ID2 6 - LPC17_TRACEINTID_DEVRESET2 + LPC17_40_TRACEINTID_DEVRESET2 0019 @@ -279,13 +279,13 @@ 9 TRACE_INTEXIT_ID1 1 - LPC17_TRACEINTID_USB2 + LPC17_40_TRACEINTID_USB2 0000

    NOTES:
    1See include/nuttx/usb/usbdev_trace.h
    - 2See arch/arm/src/lpc17xx/lpc17_usbdev.c + 2See arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c

    diff --git a/README.txt b/README.txt index 3ab4d62b2f1..1391538b2b7 100644 --- a/README.txt +++ b/README.txt @@ -1848,8 +1848,6 @@ nuttx/ | | `- README.txt | |- lpc4370-link2/ | | `- README.txt - | |- lpcxpresso-lpc1115/ - | | `- README.txt | |- lpcxpresso-lpc1768/ | | `- README.txt | |- lpcxpresso-lpc54628/ diff --git a/arch/README.txt b/arch/README.txt index 51bccd4ad56..551dd2d5f4f 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -166,9 +166,8 @@ arch/arm - ARM-based micro-controllers arch/arm/include/imx6 and arch/arm/src/imrt arch/arm/include/kinetis and arch/arm/src/kinetis arch/arm/include/kl and arch/arm/src/kl - arch/arm/include/lpc11xx and arch/arm/src/lc823450 - arch/arm/include/lpc11xx and arch/arm/src/lpc11xx - arch/arm/include/lpc17xx and arch/arm/src/lpc17xx + arch/arm/include/lc823450 and arch/arm/src/lc823450 + arch/arm/include/lpc17xx_40xx and arch/arm/src/lpc17xx_40xx arch/arm/include/lpc214x and arch/arm/src/lpc214x arch/arm/include/lpc2378 and arch/arm/src/lpc2378. arch/arm/include/lpc31xx and arch/arm/src/lpc31xx diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1a0e67c6881..15bc202557a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -133,21 +133,14 @@ config ARCH_CHIP_LM ---help--- TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4) -config ARCH_CHIP_LPC11XX - bool "NXP LPC11xx" - select ARCH_CORTEXM0 - ---help--- - NXP LPC11xx architectures (ARM Cortex-M0) - -config ARCH_CHIP_LPC17XX - bool "NXP LPC17xx" - select ARCH_CORTEXM3 +config ARCH_CHIP_LPC17XX_40XX + bool "NXP LPC17xx/LPC40xx" select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_FETCHADD select ARMV7M_HAVE_STACKCHECK ---help--- - NXP LPC17xx architectures (ARM Cortex-M3) + NXP LPC17xx & LPC40xx architectures (ARM Cortex-M3/4) config ARCH_CHIP_LPC214X bool "NXP LPC214x" @@ -665,9 +658,8 @@ config ARCH_CHIP default "kinetis" if ARCH_CHIP_KINETIS default "kl" if ARCH_CHIP_KL default "lc823450" if ARCH_CHIP_LC823450 - default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA ||ARCH_CHIP_SIMPLELINK - default "lpc11xx" if ARCH_CHIP_LPC11XX - default "lpc17xx" if ARCH_CHIP_LPC17XX + default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA || ARCH_CHIP_SIMPLELINK + default "lpc17xx_40xx" if ARCH_CHIP_LPC17XX_40XX default "lpc214x" if ARCH_CHIP_LPC214X default "lpc2378" if ARCH_CHIP_LPC2378 default "lpc31xx" if ARCH_CHIP_LPC31XX @@ -877,11 +869,8 @@ endif if ARCH_CHIP_LM || ARCH_CHIP_TIVA || ARCH_CHIP_SIMPLELINK source arch/arm/src/tiva/Kconfig endif -if ARCH_CHIP_LPC11XX -source arch/arm/src/lpc11xx/Kconfig -endif -if ARCH_CHIP_LPC17XX -source arch/arm/src/lpc17xx/Kconfig +if ARCH_CHIP_LPC17XX_40XX +source arch/arm/src/lpc17xx_40xx/Kconfig endif if ARCH_CHIP_LPC214X source arch/arm/src/lpc214x/Kconfig diff --git a/arch/arm/include/cxd56xx/geofence.h b/arch/arm/include/cxd56xx/geofence.h new file mode 100644 index 00000000000..0f400d2dda4 --- /dev/null +++ b/arch/arm/include/cxd56xx/geofence.h @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/arm/include/cxd56xx/geofence.h + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_CXD56XX_GEOFENCE_H +#define __ARCH_ARM_INCLUDE_CXD56XX_GEOFENCE_H + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Start geofence monitoring. + * This command is used to start the geofence monitoring. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GEOFENCE_IOCTL_START 1 + +/* Stop geofence monitoring. + * This command is used to stop the geofence monitoring. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GEOFENCE_IOCTL_STOP 2 + +/* Add region. + * This command is used to add the region. + * + * param arg + * Parameter is struct cxd56_geofence_region_s. + */ + +#define CXD56_GEOFENCE_IOCTL_ADD 3 + +/* Modify region. + * This command is used to modify the region. + * + * param arg + * Parameter is struct cxd56_geofence_region_s. + */ + +#define CXD56_GEOFENCE_IOCTL_MODIFY 4 + +/* Delete region. + * This command is used to delete the region. + * + * param arg + * Parameter is region id. + */ + +#define CXD56_GEOFENCE_IOCTL_DELETE 5 + +/* Delete all region. + * This command is used to delete all region. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GEOFENCE_IOCTL_ALL_DELETE 6 + +/* Get region data. + * This command is used to get region data. + * + * param arg + * Parameter is struct cxd56_geofence_region_s pointer + * Latitude and longitude and radius data of specified id is stored. + */ + +#define CXD56_GEOFENCE_IOCTL_GET_REGION_DATA 7 + +/* Get used id. + * This command is used to get used region id. + * + * param arg + * Parameter is uint32_t data pointer. + * The used id is represented by bit field. + * For example, when ID0 and ID19 are used, + * since bit0 and bit19 are set, the return value is 0x00080001. + */ + +#define CXD56_GEOFENCE_IOCTL_GET_USED_ID 8 + +/* Get all status. + * This command is used to get all region status. + * + * param arg + * Parameter is Unnecessary. Set Zero. + * All region status will stored in next read data. + */ + +#define CXD56_GEOFENCE_IOCTL_GET_ALL_STATUS 9 + +/* Set goefence operation mode + * This command is used to set operation mode. + * + * param arg + * Parameter is struct cxd56_geofence_mode_s. + */ + +#define CXD56_GEOFENCE_IOCTL_SET_MODE 10 + +/* check macros for GNSS commands */ + +#define CXD56_GEOFENCE_IOCTL_INVAL 0 +#define CXD56_GEOFENCE_IOCTL_MAX 11 + +/* The transition type indicating that the user exits the region. */ + +#define CXD56_GEOFENCE_TRANSITION_EXIT 0 + +/* The transition type indicating that the user enters the region. */ + +#define CXD56_GEOFENCE_TRANSITION_ENTER 1 + +/* The transition type indicating that the user enters and + * dwells in region for a given period of time. + */ + +#define CXD56_GEOFENCE_TRANSITION_DWELL 2 + +/* MAX number of region on the CXD56xx. */ + +#define CXD56_GEOFENCE_REGION_CAPACITY 20 + +/* Region center point and radius data + * + * The latitude and longtitude data format is + * integer value multiplied by 1000000. + * Example: When latitude is 35.123456, specify 35123456. + */ + +struct cxd56_geofence_region_s +{ + /* Region ID The range of ID is 0 to 19. */ + + uint8_t id; + + /* Latitude (degree) of the center position of the region. */ + + long latitude; + + /* Longitude (degree) of the center position of the region. */ + + long longitude; + + /* Radius (m) of the region. */ + + uint16_t radius; +}; + +/* Geofence mode setting parameter */ + +struct cxd56_geofence_mode_s +{ + uint16_t deadzone; /* dead zone [meter] */ + uint16_t dwell_detecttime; /* Dewlling period time [sec] */ +}; + +/* The transition data */ + +struct cxd56_geofence_trans_s +{ + /* Region ID */ + + uint8_t id; + + /* Transition status. + * The status is #CXD56_GEOFENCE_TRANSITION_EXIT or + * #CXD56_GEOFENCE_TRANSITION_ENTER or #CXD56_GEOFENCE_TRANSITION_DWELL. + */ + + uint8_t status; +}; + +/* Geofence output data structer. */ + +struct cxd56_geofence_status_s +{ + /* Updated region ID count */ + + uint8_t update; + + /* The detail data od updated region ID */ + + struct cxd56_geofence_trans_s status[CXD56_GEOFENCE_REGION_CAPACITY]; +}; + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_ARM_INCLUDE_ARCH_CXD56XX_GEOFENCE_H */ diff --git a/arch/arm/include/cxd56xx/gnss.h b/arch/arm/include/cxd56xx/gnss.h new file mode 100644 index 00000000000..0bee9d46d00 --- /dev/null +++ b/arch/arm/include/cxd56xx/gnss.h @@ -0,0 +1,869 @@ +/**************************************************************************** + * arch/arm/include/cxd56xx/gnss.h + * + * Copyright 2018,2019 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_CXD56XX_GNSS_H +#define __ARCH_ARM_INCLUDE_CXD56XX_GNSS_H + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * include files + ****************************************************************************/ + +#include + +/* Start the positioning. + * This command is used to start the positioning. + * + * param arg + * Start mode value of uint32_t. Not address pointer. + * One of #CXD56_GNSS_STMOD_COLD, #CXD56_GNSS_STMOD_WARM, #CXD56_GNSS_STMOD_HOT + */ + +#define CXD56_GNSS_IOCTL_START 1 + +/* Stop the positioning. + * This command is used to stop the positioning. GNSS will transition to idle + * mode. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_STOP 2 + +/* Select the satellite systems. + * This command is used to select the satellite systems to be used for + * positioning. + * The satellite system is defined as a bit, and you can select mutiple + * sattelites using OR value. + * Do not specify zero, please select at least one system. + * This command must be issued in idle mode. + * + * param[in] arg + * Satellite system bitmap value of uint32_t. Not address pointer. + * Bit OR of #CXD56_GNSS_SAT_GPS, #CXD56_GNSS_SAT_GLONASS, + * #CXD56_GNSS_SAT_SBAS, #CXD56_GNSS_SAT_QZ_L1CA, #CXD56_GNSS_SAT_QZ_L1S. + */ + +#define CXD56_GNSS_IOCTL_SELECT_SATELLITE_SYSTEM 3 + +/* Get satellite system to be used for measurement GNSS. + * The satellite system setting of the subscriber that a + * SF_COMMAND_COMMON_START command was published is acquired. + * + * param[out] arg + * Address pinting to of uint32_t object. + * Bit OR of #CXD56_GNSS_SAT_GPS, #CXD56_GNSS_SAT_GLONASS, + * #CXD56_GNSS_SAT_SBAS, #CXD56_GNSS_SAT_QZ_L1CA, #CXD56_GNSS_SAT_QZ_L1S. + */ + +#define CXD56_GNSS_IOCTL_GET_SATELLITE_SYSTEM 4 + +/* Set the receiver approximate position. + * The receiver position is set using ellipsoidal coordinates (latitude, + * longitude, altitude). + * If ellipsoidal coordinates setting, north latitude and east longitude + * direction as positive. + * When specifying south latitude or west longitude, set it to a negative + * value. + * + * The receiver position, current time and TCXO offset value, ephemeris data + * are required in order to initiate a hot start + * so the position must have been set to GNSS using this command prior to hot + * start. + * Set GNSS configure with this command before hot start if receiver position + * is not stored in the memory. + * This command must be issued in idle mode. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_ellipsoidal_position_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_RECEIVER_POSITION_ELLIPSOIDAL 5 + +/* Set the receiver approximate position. + * The receiver position is set using orthogonal coordinates (x, y, z). + * The receiver position, current time and TCXO offset value, ephemeris data + * are required in order to initiate a hot start. + * Set the position with this command before hot start if no position + * information in GNSS. + * This command must be issued in idle mode. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_orthogonal_position_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_RECEIVER_POSITION_ORTHOGONAL 6 + +/* Set receiver operation mode. + * Can set operation mode and measurement cycle. + * The cycle data is 1000msec aligned only and cannot set 0msec. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_ope_mode_param_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_OPE_MODE 7 + +/* Get receiver operation mode. + * + * param[out] arg + * Address pointing to struct #cxd56_gnss_ope_mode_param_s object. + */ + +#define CXD56_GNSS_IOCTL_GET_OPE_MODE 8 + +/* Set receiver TCXO offset value to GNSS. + * Receiver TCXO offset value set in "Hz". It can specify positive direction + * or negative direction by a sign int the argument. + * The receiver position, current time and TCXO offset value, ephemeris data + * are required in order to initiate a hot start. + * Set the offset with this command before hot start if no offset information + * in GNSS. + * This command must be issued in idle mode. + * + * param[in] arg + * TCXO offset value of uint32_t. Not address pointer. + * Address pointing to a offset value(int32_t) object. + */ + +#define CXD56_GNSS_IOCTL_SET_TCXO_OFFSET 9 + +/* Get receiver TCXO offset value. + * + * param[out] arg + * Address pointing to int32_t object. + */ + +#define CXD56_GNSS_IOCTL_GET_TCXO_OFFSET 10 + +/* Set receiver time to GNSS. + * The UTC time standard is used for the receiver time stored in a argument of + * cxd56_gnss_datetime type. + * The receiver position, current time and TCXO offset value, ephemeris data + * are required in order to initiate a hot start. + * Set the time with this command before hot start if GPS time is not counted + * in RTC. + * This command must be issued in idle mode. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_datetime_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_TIME 11 + +/* Get the latest almanac data extracted from the satellite signal. + * Almanac data size is 2048(GPS) or 576(GLONASS) bytes. + * This command must be issued in idle mode. + * + * param[out] arg + * Address pointing to struct #cxd56_gnss_orbital_param_s object. + */ + +#define CXD56_GNSS_IOCTL_GET_ALMANAC 12 + +/* Set almanac data. + * Almanac data size is 2048(GPS) or 576(GLONASS) bytes. + * This command must be issued in idle mode. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_orbital_param_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_ALMANAC 13 + +/* Get the latest ephemeris data extracted from the satellite signal. + * Ephemeris data size is 3072(GPS) or 1152(GLONASS) bytes. + * This command must be issued in idle mode. + * + * param[out] arg + * Address pointing to struct #cxd56_gnss_orbital_param_s object. + */ + +#define CXD56_GNSS_IOCTL_GET_EPHEMERIS 14 + +/* Set ephemeris data. + * Ephemeris data size is 3072(GPS) or 1152(GLONASS) bytes. + * This command must be issued in idle mode. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_orbital_param_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_EPHEMERIS 15 + +/* This command is used to save the backup data. The backup data contents are + * saved in the flash memory. + * The backup data saved in the flash memory is automatically restored at + * boot-up of GNSS. + * The receiver position, ephemeris, almanac, TCXO offset and other + * information required + * for hot start are included in the backup data. + * By saving it with this command, you can restore the information necessary + * for starting except time at boot time. + * This command must be issued in idle mode. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_SAVE_BACKUP_DATA 16 + +/* Erase backup data on flash memory. + * This command must be issued in idle mode. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_ERASE_BACKUP_DATA 17 + +/* Open CEP data file for GNSS device. + * + * Open the CEP data file and make the data available from the device. + * The file name to be opened is specified by Kconfig. + * This command must be issued in idle mode, between calling open function + * for GNSS device and issuing the command CXD56_GNSS_IOCTL_START. + * + * param[in] arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_OPEN_CEP_DATA 18 + +/* Close the CEP data file opened with the command + * CXD56_GNSS_IOCTL_OPEN_CEP_DATA. + * This command must be issued in idle mode. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_CLOSE_CEP_DATA 19 + +/* Check the validity of the CEP assist data. + * Return error code if the data file dose not exist or data is invalid. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_CHECK_CEP_DATA 20 + +/* Get age(lifetime) information of assist data. + * Age includes start date and time represented by the Julian date(MJD), and + * validity period. + * Conversion MJD to YMD is following formula. + * (Assist data start time must 0:00 (GPS time))\n + * If the data file dose not exist, an error will be returned. + * + * JD12 = floor(MJD + 2400001) + * e = floor((JD12 - 1867216.25) / 36524.25) + * f = JD12 + (e - floor(e / 4) + 1) + * g = f + 1524 + * h = floor((g - 122.1) / 365.25) + * i = floor(365.25 * h) + * j = floor((g - i) / 30.6001) + * + * d = g - i - floor(30.6001 * j) + * m = j - 12 * floor(j / 14) - 1 + * w = h - 4716 + floor((14 - m) / 12) + * + * if w > 0 then y = w else y = w - 1 + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_cep_age_s object. + */ + +#define CXD56_GNSS_IOCTL_GET_CEP_AGE 21 + +/* Reset CEP assist data init flag & valid flag. + * This command for notifying that the data has been updated. + * Execute this command before measurement if assist data updated. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_RESET_CEP_FLAG 22 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_START 23 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_STOP 24 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_SET_INTERVAL 25 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_GET_INTERVAL 26 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_SELECT_SATELLITE_SYSTEM 27 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_GET_SATELLITE_SYSTEM 28 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_SET_EPHEMERIS_ENABLER 29 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_RTK_GET_EPHEMERIS_ENABLER 30 + +/* Set acquist data. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_agps_acquist_s object. + */ + +#define CXD56_GNSS_IOCTL_AGPS_SET_ACQUIST 31 + +/* Set frame time. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_agps_frametime_s object. + */ + +#define CXD56_GNSS_IOCTL_AGPS_SET_FRAMETIME 32 + +/* Set tau_GPS(τGPS: Differnece of system time between GPS and Glonass + * system). + * + * param[in] arg + * Address pointing to tau GPS value(τGPS, double) object. + */ + +#define CXD56_GNSS_IOCTL_AGPS_SET_TAU_GPS 33 + +/* Set high precision receiver time. + * + * param arg + * Address pointing to struct #cxd56_gnss_agps_time_gps_s object. + */ + +#define CXD56_GNSS_IOCTL_AGPS_SET_TIME_GPS 34 + +/* Clear info(s) for hot start. + * + * param arg + * Bit OR of #CXD56_GNSS_GCLR_EPH, #CXD56_GNSS_GCLR_ALM, #CXD56_GNSS_GCLR_PV, + * #CXD56_GNSS_GCLR_TIME, #CXD56_GNSS_GCLR_TCXO, #CXD56_GNSS_GCLR_ALL. + */ + +#define CXD56_GNSS_IOCTL_AGPS_CLEAR_RECEIVER_INFO 35 + +/* Set acquist data. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_agps_tow_assist_s object. + */ + +#define CXD56_GNSS_IOCTL_AGPS_SET_TOW_ASSIST 36 + +/* Set acquist data. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_agps_utc_model_s object. + */ + +#define CXD56_GNSS_IOCTL_AGPS_SET_UTC_MODEL 37 + +/* Enable or not to output spectrum data of GNSS signal. + * + * param arg + * Address pointing to struct #cxd56_gnss_spectrum_control_s object. + */ + +#define CXD56_GNSS_IOCTL_SPECTRUM_CONTROL 38 + +/* Start GPS factory test. + * Test results can get by CXD56_GNSS_IOCTL_FACTORY_GET_TEST_RESULT command + * after execute this command and waiting 1 second. + * This command execute during measurement stop. + * After executing this command, it is not accepted except for + * CXD56_GNSS_IOCTL_FACTORY_GET_TEST_RESULT and + * CXD56_GNSS_IOCTL_FACTORY_STOP_TEST. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_test_info_s object. + */ + +#define CXD56_GNSS_IOCTL_FACTORY_START_TEST 39 + +/* Stop GPS factory test. + * + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_FACTORY_STOP_TEST 40 + +/* Get GPS factory test result. + * + * param[out] arg + * Address pointing to struct #cxd56_gnss_test_result_s object. + */ + +#define CXD56_GNSS_IOCTL_FACTORY_GET_TEST_RESULT 41 + +/* Set signal information for GNSS events from GNSS device driver. + * The field 'enable' of struct #cxd56_gnss_signal_setting_s to be given + * as a parameter must be specified as 1 when setting and 0 when unsetting. + * param[out] arg + * Address pointing to struct #cxd56_gnss_signal_setting_s object. + */ + +#define CXD56_GNSS_IOCTL_SIGNAL_SET 42 + +/* Start PVTLOG. + * Automatically saves the PVT log in the GNSS core. + * + * param arg + * Address pointing to #cxd56_pvtlog_setting_s object. + */ + +#define CXD56_GNSS_IOCTL_PVTLOG_START 43 + +/* Stop PVTLOG. + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_PVTLOG_STOP 44 + +/* Delete PVTlog data. + * Delete the log data saved in the GNSS core. + * param arg + * Parameter is Unnecessary. Set Zero. + */ + +#define CXD56_GNSS_IOCTL_PVTLOG_DELETE_LOG 45 + +/* Get PVTLOG status. + * This command is for getting the log stored status. + * The status data include stored log data count and logging time. + * + * param arg + * Address pointing to #cxd56_pvtlog_status_s. + */ + +#define CXD56_GNSS_IOCTL_PVTLOG_GET_STATUS 46 + +/* Currently version not supported. */ + +#define CXD56_GNSS_IOCTL_NAVMSG_START 47 + +/* Set ephemeris data. + * Only satellites with data are output. + * Ephemeris data size is variable. + * Ephemeris data max size is 3072(GPS) or 1152(GLONASS) bytes. + * This command must be issued in idle mode. + * + * param[in] arg + * Address pointing to struct #cxd56_gnss_set_var_ephemeris_s object. + */ + +#define CXD56_GNSS_IOCTL_SET_VAR_EPHEMERIS 48 + +/* Get the latest ephemeris data extracted from the satellite signal. + * Only satellites with data are output. + * Ephemeris data size is variable. + * Ephemeris data max size is 3072(GPS) or 1152(GLONASS) bytes. + * This command must be issued in idle mode. + * + * param[out] arg + * Address pointing to struct #cxd56_gnss_get_var_ephemeris_s object. + */ + +#define CXD56_GNSS_IOCTL_GET_VAR_EPHEMERIS 49 + +/* check macros for GNSS commands */ + +#define CXD56_GNSS_IOCTL_INVAL 0 +#define CXD56_GNSS_IOCTL_MAX 50 + +/* Same value to GD Start mode CXD56_GNSS_STMOD_XXXX for GD_Start */ + +#define CXD56_GNSS_STMOD_COLD 0 /* Cold Start */ +#define CXD56_GNSS_STMOD_WARM 1 /* Warm Start */ +#define CXD56_GNSS_STMOD_WARM_ACC2 2 /* Warm Start, better accuracy, less TTFF than WARM */ +#define CXD56_GNSS_STMOD_HOT 3 /* Hot Start */ +#define CXD56_GNSS_STMOD_HOT_ACC 4 /* Hot Start, better accuracy, less TTFF than HOT */ +#define CXD56_GNSS_STMOD_HOT_ACC2 5 /* Hot Start, better accuracy, less TTFF than ACC */ +#define CXD56_GNSS_STMOD_HOT_ACC3 6 /* Optimized hot start, better TTFF than HOT */ +#define CXD56_GNSS_STMOD_GSPQ CXD56_GNSS_STMOD_HOT_ACC3 + +#define CXD56_GNSS_GPS_ALMANAC_SIZE 2048 /* GPS Almanac Size */ + +#define CXD56_GNSS_GPS_EPHEMERIS_SIZE 3072 /* GPS Ephemeris Size */ + +#define CXD56_GNSS_GLONASS_ALMANAC_SIZE 576 /* GLONASS Almanac Size */ + +#define CXD56_GNSS_GLONASS_EPHEMERIS_SIZE 1152 /* GLONASS Ephemeris Size */ + +#define CXD56_GNSS_QZSSL1CA_ALMANAC_SIZE 640 /* GPS Almanac Size */ + +#define CXD56_GNSS_QZSSL1CA_EPHEMERIS_SIZE 960 /* GPS Ephemeris Size */ + +/* PVTLOG notify threshold of the stored data. */ + +#define CXD56_GNSS_PVTLOG_THRESHOLD_FULL 0 /* Limit of the storage size */ +#define CXD56_GNSS_PVTLOG_THRESHOLD_HALF 1 /* 1/2 of the Storage size */ +#define CXD56_GNSS_PVTLOG_THRESHOLD_ONE_DATA 2 /* Each log stored */ + +/* Offset for last GNSS data */ + +#define CXD56_GNSS_READ_OFFSET_LAST_GNSS 0x0000 + +/* Offset for GNSS data */ + +#define CXD56_GNSS_READ_OFFSET_GNSS(N) (0x1000 + 0x800 * (N)) + +/* Offset for AGPS data */ + +#define CXD56_GNSS_READ_OFFSET_AGPS 0x5000 + +/* Offset for RTK data */ + +#define CXD56_GNSS_READ_OFFSET_RTK 0x6000 + +/* Offset for RTK GPS Ephemeris data */ + +#define CXD56_GNSS_READ_OFFSET_GPSEPHEMERIS 0x7000 + +/* Offset for RTK GLONASS Ephemeris data */ + +#define CXD56_GNSS_READ_OFFSET_GLNEPHEMERIS 0x8000 + +/* Offset for SBAS data */ + +#define CXD56_GNSS_READ_OFFSET_SBAS 0x9000 + +/* Offset for DC report */ + +#define CXD56_GNSS_READ_OFFSET_DCREPORT 0x9800 + +/* Offset for Spectrum data */ + +#define CXD56_GNSS_READ_OFFSET_SPECTRUM 0xa000 + +/* Offset for GNSS info */ + +#define CXD56_GNSS_READ_OFFSET_INFO 0xf000 + +/* Offset for PVTLOG data */ + +#define CXD56_GNSS_READ_OFFSET_PVTLOG 0x10000 + +/* Signal types from GNSS */ + +/* Signal type is GNSS */ + +#define CXD56_GNSS_SIG_GNSS 0 + +/* Signal type is PVTLog */ + +#define CXD56_GNSS_SIG_PVTLOG 2 + +/* Signal type is AGPS */ + +#define CXD56_GNSS_SIG_AGPS 3 + +/* Signal type is RTK Career Phase */ + +#define CXD56_GNSS_SIG_RTK 4 + +/* Signal type is Soectrum */ + +#define CXD56_GNSS_SIG_SPECTRUM 5 + +/* Signal type is RTK GPS Ephemeris */ + +#define CXD56_GNSS_SIG_GPSEPHEMERIS 11 + +/* Signal type is RTK GLONASS Ephemeris */ + +#define CXD56_GNSS_SIG_GLNEPHEMERIS 12 + +/* Signal type is SBAS */ + +#define CXD56_GNSS_SIG_SBAS 14 + +/* Signal type is QZSS DC report */ + +#define CXD56_GNSS_SIG_DCREPORT 15 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* GNSS operation mode and cycle */ + +struct cxd56_gnss_ope_mode_param_s +{ + + /* receiver operation mode + * 0: No Change Operation + * 1: Normal(default) + */ + + uint32_t mode; + + /* Positioning cycle[ms] + * The cycle data is 1000msec aligned only and + * cannot set 0msec. + * (Init value 1000) + */ + + uint32_t cycle; +}; + +/* Sattelite almanac, ephemeris data */ + +struct cxd56_gnss_orbital_param_s +{ + uint32_t type; /* One of #CXD56_GNSS_DATA_GPS, + * #CXD56_GNSS_DATA_GLONASS or + * #CXD56_GNSS_DATA_QZSSL1CA. + */ + FAR uint32_t *data; /* Address pointing to almanac or ephemeris data buffer */ +}; + +/* date and time */ + +struct cxd56_gnss_datetime_s +{ + struct cxd56_gnss_date_s date; /* date */ + struct cxd56_gnss_time_s time; /* time */ +}; + +/* ellipsoidal position */ + +struct cxd56_gnss_ellipsoidal_position_s +{ + double latitude; /* latitude[degree] */ + double longitude; /* longitude[degree] */ + double altitude; /* altitude[meter] */ +}; + +/* ellipsoidal position */ + +struct cxd56_gnss_orthogonal_position_s +{ + int32_t x; /* x[meter] */ + int32_t y; /* y[meter] */ + int32_t z; /* z[meter] */ +}; + +/* Currently version not supported. */ + +struct cxd56_gnss_cep_data_s +{ + FAR uint32_t *data; + uint32_t size; + uint32_t counter; +}; + +/* CEP age info */ + +struct cxd56_gnss_cep_age_s +{ + float age; /* age */ + float cepi; /* cepi */ +}; + +/* acquist data and size for AGPS */ + +struct cxd56_gnss_agps_acquist_s +{ + FAR uint8_t *data; /* Address pointing to aquist data buffer */ + uint16_t size; /* Aquist data size */ +}; + +/* tow assist data and size for AGPS */ + +struct cxd56_gnss_agps_tow_assist_s +{ + FAR uint8_t *data; /* Address pointing to tow assist data buffer */ + uint16_t size; /* assist data size */ +}; + +/* utc model data and size for AGPS */ + +struct cxd56_gnss_agps_utc_model_s +{ + FAR uint8_t *data; /* Address pointing to utc model data buffer */ + uint16_t size; /* utc model data size */ +}; + +/* Time from frame start[sec]. */ + +struct cxd56_gnss_agps_frametime_s +{ + uint16_t sec; /* Integer part */ + uint32_t frac; /* Fraction part */ +}; + +/* High precision receiver time */ + +struct cxd56_gnss_agps_time_gps_s +{ + struct cxd56_gnss_date_s date; /* Date */ + struct cxd56_gnss_time_s time; /* Time */ +}; + +/* different time between AGPS and GLONASS Time */ + +struct cxd56_gnss_agps_tau_gps_s +{ + double taugps; /* tau Time */ +}; + +/* Signal spectrum output control parameter */ + +struct cxd56_gnss_spectrum_control_s +{ + uint8_t enable; /* Spectrum data output enable */ + uint32_t time; /* Passed Time */ + uint8_t point1; /* Monitor point1 (7-9) */ + uint8_t point2; /* Monitor point2 (7-9) */ + uint8_t step1; /* Sampling step1 (0-7) */ + uint8_t step2; /* Sampling step2 (0-7) */ +}; + +struct cxd56_gnss_test_info_s +{ + uint32_t satellite; /* Specify satellite by svID */ + uint32_t reserve1; /* Reserve (always specify 0) */ + uint32_t reserve2; /* Reserve (always specify 0) */ + uint32_t reserve3; /* Reserve (always specify 0) */ +}; + +struct cxd56_gnss_test_result_s +{ + float cn; /* CN ratio [dB-Hz] */ + float doppler; /* Doppler [Hz] */ +}; + +/* signal setting for reading data asychronously + * The field 'enable' of struct #cxd56_gnss_signal_setting_s to be given as a + * parameter must be specified as 1 when setting and 0 when unsetting. + * Field 'gnsssig' specifies the value of 'Signal types from GNSS', + * this is not POSIX signal. + * Field 'signo' is application specific number of POSIX signal. + * 'data' will be passed as an argument to the handler. + */ + +struct cxd56_gnss_signal_setting_s +{ + int fd; /* The descriptor for signal handler */ + uint8_t enable; /* 1 when set this setting, 0 is clear */ + uint8_t gnsssig; /* GNSS signal as CXD56_GNSS_SIG_GNSS, _AGPS, etc. */ + int signo; /* system signal number to notify read completion */ + FAR void *data; /* user data */ +}; + +/* Information for use after being signaled to read data asychronously */ + +struct cxd56_gnss_signal_info_s +{ + int fd; /* The file descriptor to use in signal handler */ + uint8_t gnsssig; /* GNSS signal as CXD56_GNSS_SIG_GNSS, _AGPS, etc. */ + int signo; /* system signal number to notify read completion */ + FAR void *data; /* user data */ +}; + +/* PVTLOG setting Parameter. + * If the log interval(cycle) is smaller than the positioning interval, + * it is logged every positioning interval. + * The output timing is specified by the ratio to the log buffer in the + * GNSS device by threshold. Possible values are + * #CXD56_GNSS_PVTLOG_THRESHOLD_FULL, #CXD56_GNSS_PVTLOG_THRESHOLD_HALF, + * and #CXD56_GNSS_PVTLOG_THRESHOLD_ONE_DATA. + */ + +struct cxd56_pvtlog_setting_s +{ + uint32_t cycle; /* PVT log interval in seconds */ + uint32_t threshold; /* Notification threshold of log storage amount */ +}; + +struct cxd56_pvtlog_status_s +{ + struct cxd56_gnss_status_s status; /* The stored logs status */ +}; + +struct cxd56_rtk_setting_s +{ + int interval; /* RTK data output interval */ + uint32_t gnss; /* RTK satellite setting */ + int ephout; /* Ephemeris notify enable setting */ + uint64_t sbasout; /* sbas notify enable setting */ +}; + +struct cxd56_gnss_set_var_ephemeris_s +{ + uint32_t *data; /* Address pointing to ephemeris data buffer */ + uint32_t size; /* ephemeris data buffer size */ +}; + +struct cxd56_gnss_get_var_ephemeris_s +{ + uint32_t type; /* One of #CXD56_GNSS_DATA_GPS, #CXD56_GNSS_DATA_GLONASS. */ + uint32_t *data; /* Address pointing to ephemeris data buffer */ + uint32_t size; /* ephemeris data buffer size */ +}; + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* ARCH_ARM_INCLUDE_CXD56XX_GNSS_H */ diff --git a/arch/arm/include/cxd56xx/gnss_type.h b/arch/arm/include/cxd56xx/gnss_type.h new file mode 100644 index 00000000000..85111b8b084 --- /dev/null +++ b/arch/arm/include/cxd56xx/gnss_type.h @@ -0,0 +1,710 @@ +/**************************************************************************** + * arch/arm/include/cxd56xx/gnss_type.h + * + * Copyright 2018,2019 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_CXD56XX_GNSS_TYPE_H +#define __ARCH_ARM_INCLUDE_CXD56XX_GNSS_TYPE_H + +/* NOTICE: + * This file defines a structure that stores GNSS positioning + * data of CXD 56xx. The public header file gnss_type.h for NuttX + * of the CXD 56xx SDK has been copied as gd_type.h in the nxloader + * build system and used. Therefore, if you change the definitions + * in this file, please synchronize and change the other. + */ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * include files + ****************************************************************************/ + +#include + +/* Max number of satellites */ + +#define CXD56_GNSS_MAX_SV_NUM 32 + +/* GNSS satellite system */ + +#define CXD56_GNSS_SAT_NONE (0) /* None */ +#define CXD56_GNSS_SAT_GPS (1U << 0) /* GPS */ +#define CXD56_GNSS_SAT_GLONASS (1U << 1) /* Glonass */ +#define CXD56_GNSS_SAT_SBAS (1U << 2) /* SBAS */ +#define CXD56_GNSS_SAT_QZ_L1CA (1U << 3) /* QZSS/L1CA */ +#define CXD56_GNSS_SAT_IMES (1U << 4) /* IMES */ +#define CXD56_GNSS_SAT_QZ_L1S (1U << 5) /* QZSS/L1S */ +#define CXD56_GNSS_SAT_BEIDOU (1U << 6) /* BeiDou */ +#define CXD56_GNSS_SAT_GALILEO (1U << 7) /* Galileo */ + +/* GNSS positioning type */ + +#define CXD56_GNSS_PVT_TYPE_NONE 0 /* Positioning data none */ +#define CXD56_GNSS_PVT_TYPE_GNSS 1 /* by GNSS */ +#define CXD56_GNSS_PVT_TYPE_IMES 2 /* by IMES */ +#define CXD56_GNSS_PVT_TYPE_USER 3 /* API setting */ + +/* GNSS position fix mode */ + +#define CXD56_GNSS_PVT_POSFIX_INVALID 1 /* No measurement */ +#define CXD56_GNSS_PVT_POSFIX_2D 2 /* 2D fix */ +#define CXD56_GNSS_PVT_POSFIX_3D 3 /* 3D fix */ + +/* GNSS velocity fix mode */ + +#define CXD56_GNSS_PVT_VELFIX_INVALID 1 /* No measurement */ +#define CXD56_GNSS_PVT_VELFIX_2DVZ 2 /* 2D VZ fix */ +#define CXD56_GNSS_PVT_VELFIX_2DOFFSET 3 /* 2D Offset fix */ +#define CXD56_GNSS_PVT_VELFIX_3D 4 /* 3D fix */ +#define CXD56_GNSS_PVT_VELFIX_1D 5 /* 1D fix */ +#define CXD56_GNSS_PVT_VELFIX_PRED 6 /* Prediction */ + +/* GNSS oribital infomation data type, almanac & ephemeris */ + +#define CXD56_GNSS_DATA_GPS 0 /* GPS data type */ +#define CXD56_GNSS_DATA_GLONASS 1 /* Glonass data type */ +#define CXD56_GNSS_DATA_QZSSL1CA 2 /* QZSS/L1CA data type */ + +/* GNSS satellite status */ + +#define CXD56_GNSS_SV_STAT_NONE (0) /* None */ +#define CXD56_GNSS_SV_STAT_TRACKING (1 << 0) /* Tracking */ +#define CXD56_GNSS_SV_STAT_POSITIONING (1 << 1) /* Positioning */ +#define CXD56_GNSS_SV_STAT_CALC_VELOCITY (1 << 2) /* Calc Velocity */ +#define CXD56_GNSS_SV_STAT_VISIBLE (1 << 3) /* Visible */ +#define CXD56_GNSS_SV_STAT_SUB_CH (1 << 4) /* Sub Ch */ + +/* GNSS 1PPS synchronization status (internal use) */ + +#define CXD56_GNSS_PPS_NOT_ADJUSTED 0 /* not adjusted */ +#define CXD56_GNSS_PPS_ADJUSTED 1 /* adjusted */ +#define CXD56_GNSS_PPS_ADJUSTED_SSDGLN 2 /* adjusted SSDGLN */ +#define CXD56_GNSS_PPS_ADJUSTED_SSD 3 /* adjusted SSD */ +#define CXD56_GNSS_PPS_ADJUSTED_POS 4 /* adjusted POS */ +#define CXD56_GNSS_PPS_DEGRADE2 5 /* Degrade2 */ +#define CXD56_GNSS_PPS_DEGRADE 6 /* Degrade */ +#define CXD56_GNSS_PPS_COMPLETE 7 /* Complete */ + +/* GNSS Output interval of carrier phase info. */ + +#define CXD56_GNSS_RTK_INTERVAL_1HZ 1000 /* 1Hz */ +#define CXD56_GNSS_RTK_INTERVAL_2HZ 500 /* 2Hz */ +#define CXD56_GNSS_RTK_INTERVAL_5HZ 200 /* 5Hz */ +#define CXD56_GNSS_RTK_INTERVAL_10HZ 100 /* 10Hz */ +#define CXD56_GNSS_RTK_INTERVAL_20HZ 50 /* 20H */ + +/* Carrier phase max satellite number */ + +#define CXD56_GNSS_RTK_MAX_SV_NUM 24 + +/* GNSS Spectrum data size */ + +/* Spectrum Data Max(adjusted as CXD56_GNSS_SPECTRUM_DATA will be 116byte.) */ + +#define CXD56_GNSS_SPECTRUM_MAXNUM 37 + +/* Peak Spectrum Data */ + +#define CXD56_GNSS_PEAK_SPECTRUM_MAXNUM 3 + +/* SPZ_INT_API */ + +/* DC Report data size */ + +#define CXD56_GNSS_QSM_MSG_BIT_NUM 250 +#define CXD56_GNSS_QSM_NUM_BITS_IN_BYTE 8 + +/* AGPS Measurement tracking data */ + +#define CXD56_GNSS_SUPL_TRK_DATA_SIZE (16) + +/* PVTLOG Max stored log number */ + +#define CXD56_GNSS_PVTLOG_MAXNUM 170 + +/* assist bit fields */ + +#define CXD56_GNSS_PVT_RECEIVER_ASSIST_NONE (0x00) +#define CXD56_GNSS_PVT_RECEIVER_ASSIST_USER (0x01) +#define CXD56_GNSS_PVT_RECEIVER_ASSIST_CEPPOS (0x02) +#define CXD56_GNSS_PVT_RECEIVER_ASSIST_CEPVEL (0x04) +#define CXD56_GNSS_PVT_RECEIVER_ASSIST_AEPPOS (0x08) +#define CXD56_GNSS_PVT_RECEIVER_ASSIST_AEPVEL (0x10) + +/* GNSS positionig data elements */ + +/* Day (UTC) */ + +struct cxd56_gnss_date_s +{ + uint16_t year; /* year */ + uint8_t month; /* month */ + uint8_t day; /* day */ +}; + +/* Time (UTC) */ + +struct cxd56_gnss_time_s +{ + uint8_t hour; /* hour */ + uint8_t minute; /* minitue */ + uint8_t sec; /* sec */ + uint32_t usec; /* usec */ +}; + +/* Time (GPS) */ + +struct cxd56_gnss_wntow_s +{ + uint32_t tow; /* truncated TOW (1 = 6sec, 0 ... 100799) */ + uint16_t weeknumber; /* week number (0 ... 1023) */ + uint8_t sec; /* offset (0 ... 5) */ + uint8_t rollover; /* Number of WN Roll Over (0 ... 255) */ + double frac; /* fraction */ +}; + +/* struct cxd56_gnss_dop_s - Dilution Of Precision */ + +struct cxd56_gnss_dop_s +{ + float pdop; /* Position DOP */ + float hdop; /* Horizontal DOP */ + float vdop; /* Vertical DOP */ + float tdop; /* Time DOP */ + float ewdop; /* East-West DOP */ + float nsdop; /* North-South DOP */ + float majdop; /* Stdev of semi-major axis */ + float mindop; /* Stdev of semi-minor axis */ + float oridop; /* Orientation of semi-major axis [deg] */ +}; + +/* struct cxd56_gnss_var_s - Variance */ + +struct cxd56_gnss_var_s +{ + float hvar; /* Horizontal */ + float vvar; /* Vertical */ +}; + +/* Extra data for debugging */ + +#define CXD56_GNSS_PVT_RECEIVER_EXTRA_DATA_SIZE (520) +#define CXD56_GNSS_PVT_RECEIVER_EXTRA_DATA \ + uint8_t extra[CXD56_GNSS_PVT_RECEIVER_EXTRA_DATA_SIZE] +#define CXD56_GNSS_PVT_SV_EXTRA_DATA_SIZE 40 +#define CXD56_GNSS_PVT_SV_EXTRA_DATA \ + uint8_t extra[CXD56_GNSS_PVT_SV_EXTRA_DATA_SIZE] +#define CXD56_GNSS_FFT_MAXPOOLNUM (8) + +/* GNSS AGPS clear flag */ + +#define CXD56_GNSS_GCLR_EPH 0x00000001 /* ephemeris */ +#define CXD56_GNSS_GCLR_ALM 0x00000002 /* almanac */ +#define CXD56_GNSS_GCLR_PV 0x00000004 /* position and velocity */ +#define CXD56_GNSS_GCLR_TIME 0x00000008 /* time */ +#define CXD56_GNSS_GCLR_TCXO 0x00010000 /* TCXO offset */ +#define CXD56_GNSS_GCLR_ALL 0xffffffff /* all of above */ + +/* GNSS Receiver data */ + +struct cxd56_gnss_receiver_s +{ + uint8_t type; /* [out] Position type; 0:Invalid, 1:GNSS, + * 2:IMES, 3:user set, 4:previous + */ + uint8_t dgps; /* [out] FALSE:SGPS, TRUE:DGPS */ + uint8_t pos_fixmode; /* [out] 1:Invalid, 2:2D, 3:3D */ + uint8_t vel_fixmode; /* [out] 1:Invalid, 2:2D VZ, 3:2D Offset, + * 4:3D, 5:1D, 6:PRED + */ + uint8_t numsv; /* [out] Nr of visible satellites */ + uint8_t numsv_tracking; /* [out] Nr of tracking satellites */ + uint8_t numsv_calcpos; /* [out] Nr of satellites to calculate position */ + uint8_t numsv_calcvel; /* [out] Nr of satellites to calculate velocity */ + uint8_t assist; /* [out] bit field + * [7..5]Reserved + * [4]AEP Velocity + * [3]AEP Position + * [2]CEP Velocity + * [1]CEP Position, + * [0]user set + */ + uint8_t pos_dataexist; /* [out] 0:none, 1:exist */ + uint16_t svtype; /* [out] Using sv system, bit field; + * bit0:GPS, bit1:GLONASS, bit2:SBAS, + * bit3:QZSS_L1CA, bit4:IMES, + * bit5:QZSS_L1SAIF, bit6:Beidu, + * bit7:Galileo + */ + uint16_t pos_svtype; /* [out] using sv system, bit field; + * bit0:GPS, bit1:GLONASS, bit2:SBAS, + * bit3:QZSS_L1CA, bit4:IMES, + * bit5:QZSS_L1SAIF, bit6:Beidu, + * bit7:Galileo + * */ + uint16_t vel_svtype; /* [out] using sv system, bit field; bit0:GPS, + * bit0:GPS, bit1:GLONASS, bit2:SBAS, + * bit3:QZSS_L1CA, bit4:IMES, + * bit5:QZSS_L1SAIF, bit6:Beidu, + * bit7:Galileo + */ + uint32_t possource; /* [out] position source; 0:Invalid, 1:GNSS, + * 2:IMES, 3:user set, 4:previous + */ + int32_t tcxo_offset; /* [out] TCXO offset[Hz] */ + struct cxd56_gnss_dop_s pos_dop; /* [out] DOPs of Position */ + struct cxd56_gnss_dop_s vel_idx; /* [out] Weighted DOPs of Velocity */ + struct cxd56_gnss_var_s pos_accuracy; /* [out] Accuracy of Position */ + double latitude; /* [out] Latitude [degree] */ + double longitude; /* [out] Longitude [degree] */ + double altitude; /* [out] Altitude [m] */ + double geoid; /* [out] Geoid height [m] */ + float velocity; /* [out] Velocity [m/s] */ + float direction; /* [out] Direction [degree] */ + struct cxd56_gnss_date_s date; /* [out] Current day (UTC) */ + struct cxd56_gnss_time_s time; /* [out] Current time (UTC) */ + struct cxd56_gnss_date_s gpsdate; /* [out] Current day (GPS) */ + struct cxd56_gnss_time_s gpstime; /* [out] Current time (GPS) */ + struct cxd56_gnss_time_s receivetime; /* [out] Receive time (UTC) */ + uint32_t priv; /* [out] For internal use */ + CXD56_GNSS_PVT_RECEIVER_EXTRA_DATA; /* [out] Receiver extra data */ +}; + +/* GNSS satellite data */ + +struct cxd56_gnss_sv_s +{ + uint16_t type; /* [out] Using sv system, bit field; bit0:GPS, + * bit1:GLONASS, bit2:SBAS, bit3:QZSS_L1CA, + * bit4:IMES, bit5:QZSS_L1SAIF, bit6:Beidu, + * bit7:Galileo + * same as struct cxd56_gnss_receiver_s::svtype + */ + uint8_t svid; /* [out] Satellite id */ + uint8_t stat; /* Using sv info, bit field; bit0:tracking, + * bit1:positioning, bit2:calculating velocity, + * bit3:visible satellite + */ + uint8_t elevation; /* [out] Elevation [degree] */ + int16_t azimuth; /* [out] Azimuth [degree] */ + float siglevel; /* [out] CN */ + CXD56_GNSS_PVT_SV_EXTRA_DATA; /* [out] Sv extra data */ +}; + +/* Positioning data with SV data */ + +struct cxd56_gnss_positiondata_s +{ + uint64_t data_timestamp; /* [out] Timestamp */ + uint32_t status; /* [out] Positioning data status 0 : Valid, <0: Invalid */ + uint32_t svcount; /* [out] Sv data count */ + struct cxd56_gnss_receiver_s receiver; /* [out] Receiver data */ + struct cxd56_gnss_sv_s sv[CXD56_GNSS_MAX_SV_NUM]; /* [out] Sv data array */ +}; + +/* QZSS DC report data */ + +struct cxd56_gnss_dcreport_data_s +{ + uint8_t sf[CXD56_GNSS_QSM_MSG_BIT_NUM / + CXD56_GNSS_QSM_NUM_BITS_IN_BYTE + 1]; /* [out] Message body */ + uint8_t svid; /* [out] Satellite id */ +}; + +/* SF_EVENT_GNSS_MEASUREMENT_VALUE */ + +/* SUPL tracking data */ + +struct cxd56_supl_trkdata_s +{ + uint8_t gnssid; /* [out] sv system + * GPS: 0x01 + * GLONASS: 0x02 + * SBAS : 0x04 + * QZSS_L1C/A:0x08 + */ + uint8_t signalid; /* [out] Always 0 */ + uint8_t svid; /* [out] Satellite Id + * GPS: 1-32 + * GLONASS: 1-24 + * SBAS: 120-158 + * QZSS_L1C/A 193-197 + */ + uint8_t cn; /* [out] CN ratio [dBHz] */ + uint8_t codephase_ambiguty; /* Currently version not supported. */ + uint8_t carriorquality_indicator; /* Currently version not supported. */ + uint8_t codephase_rmserr; /* Currently version not supported. */ + uint8_t multipath_indicator; /* Currently version not supported. */ + uint32_t codephase; /* [out] Code Phase[ms] scale: 2-21[ms] */ + uint16_t wholechip; /* [out] Chip integer part */ + uint16_t fracchip; /* [out] Chip frac part */ + uint32_t adr; /* Currently version not supported. */ + int16_t doppler; /* [out] Doppler [Hz] */ +}; + +/* SUPL positioning data */ + +struct cxd56_supl_posdata_s +{ + double uncertainty_semi_major; /* [out] Uncertainty semi-major */ + double uncertainty_semi_minor; /* [out] Uncertainty semi-minor */ + double orientation_of_major_axis; /* [out] Orientation of major axis */ + double uncertainty_altitude; /* [out] Uncertainty Altitude */ + uint32_t tow; /* [out] Time of week [sec] + * acquisition TOW : 0-604799 + * no acquisition TOW : 0xffffffff + */ + float frac_sec; /* [out] Under second part[sec] + * no acquisition TOW : -1 + */ + float horizontal_accuracy; /* [out] Horizontal accuracy [m] + * disable : -1 + */ + uint16_t ref_frame; /* Currently version not supported */ + uint8_t tod_unc; /* [out] Acquisition : 1 + * no acquisition : 0 + */ + uint8_t num_of_sat; /* [out] Tracking Sv number */ +}; + +/* SUPL Measurement data struct */ + +struct cxd56_supl_mesurementdata_s +{ + /* [out] Supl positioning data */ + + struct cxd56_supl_posdata_s supl_pos; + + /* [out] Tracking satellite data */ + + struct cxd56_supl_trkdata_s trackingsat[CXD56_GNSS_SUPL_TRK_DATA_SIZE]; +}; + +/* struct cxd56_gnss_timetag_s - Internal time tag */ + +struct cxd56_gnss_timetag_s +{ + uint32_t msec; /* [ms] whole millisecond part */ + uint32_t frac; /* Under millisecond part (0 ... cycle-1) */ + uint16_t cycle; /* Resolution of 1ms */ +}; + +/* Time and frequency information for RTK */ + +struct cxd56_rtk_info_s +{ + uint64_t timestamp; /* [out] system timestamp */ + uint64_t timesnow; /* [out] system now times */ + struct cxd56_gnss_wntow_s wntow; /* [out] GPS time */ + struct cxd56_gnss_date_s date; /* [out] Date (UTC time) */ + struct cxd56_gnss_time_s time; /* [out] Time (UTC time) */ + struct cxd56_gnss_timetag_s tag; /* [out] TimeTag */ + double clockdrift; /* [out] [Hz] clock drift @1.5GHz + * (valid only if cdvalidity is 1) + */ + int8_t cdvalidity; /* [out] clock drift validity + * (0: invalid, 1: valid) + */ + uint8_t ppsstatus; /* [out] 1PPS synchronization status */ + int8_t svcount; /* [out] Num of sv */ +}; + +/* Carrier phase and related data for RTK */ + +struct cxd56_rtk_sv_s +{ + double pseudorange; /* [out] [m] pseudo range */ + double carrierphase; /* [out] [wave number] carrier phase */ + uint32_t gnss; /* [out] GNSS type (CXD56_GNSS_GNSS_XXX) */ + int8_t svid; /* [out] Satellite id */ + int8_t fdmch; /* [out] Frequency slot for GLONASS (-7 ... 6) */ + int16_t cn; /* [out] [0.01dBHz] CN */ + int8_t polarity; /* [out] Carrier polarity + * (0: not inverted, 1: inverted) + */ + int8_t lastpreamble; /* [out] Parity of last premable (0: ok, 1: ng) */ + int8_t lli; /* [out] Lock loss indicator + * (0: no lock loss, 1: lock loss) + */ + int8_t ch; /* [out] TRK channel number */ + float c2p; /* [out] C2P (0 ... 1.0) */ + float doppler; /* [out] [Hz] Doppler shift */ +}; + +/* RTK Carrier phase data */ + +struct cxd56_rtk_carrierphase_s +{ + /* [out] Time and frequency information */ + + struct cxd56_rtk_info_s infoout; + + /* [out] Carrier phase and related data */ + + struct cxd56_rtk_sv_s svout[CXD56_GNSS_RTK_MAX_SV_NUM]; +}; + +/* Ephemeris data (GPS) */ + +struct cxd56_rtk_gpsephemeris_s +{ + uint64_t timesnow; /* [out] system now times */ + uint8_t ppsstatus; /* [out] 1PPS synchronization status */ + uint16_t t_oc; /* [out] SV Clock Correction */ + double af0; /* [out] SV Clock Correction */ + double af1; /* [out] SV Clock Correction */ + double af2; /* [out] SV Clock Correction */ + double crs; /* [out] Amplitude correction term of orbital radius(sin) */ + double delta_n; /* [out] Average motion difference [rad] */ + double m0; /* [out] Average near point separation at t_oe [rad] */ + double cuc; /* [out] Latitude amplitude correction term(cos) */ + double e; /* [out] Eccentricity of orbit */ + double cus; /* [out] Latitude amplitude correction term(sin) */ + double sqrt_a; /* [out] Square root of the orbital length radius */ + double cic; /* [out] Amplitude correction term of orbital inclination angle(cos) */ + double omega0; /* [out] Rise of ascension at Weekly Epoch [rad] */ + double cis; /* [out] Amplitude correction term of orbital inclination angle(sin) */ + double i0; /* [out] Orbital inclination angle at t_oe */ + double crc; /* [out] Amplitude correction term of orbital radius(cos) */ + double omega; /* [out] Perigee argument [rad] */ + double omega_dot; /* [out] Ascension of ascending node correction [rad] */ + double i_dot; /* [out] Orbital inclination angle correction [rad] */ + double accuracy; /* [out] nominal URA (User Range Accuracy) [m] */ + double tgd; /* [out] Estimated Group Delay Differential */ + + /* tocwntow, tocdate, toctime are valid if ppsstatus >= 1(adjusted) */ + + struct cxd56_gnss_wntow_s tocwntow; /* [out] toc */ + struct cxd56_gnss_date_s tocdate; /* [out] toc Date */ + struct cxd56_gnss_time_s toctime; /* [out] toc Time */ + + int32_t toe; /* [out] Reference time [s] */ + int32_t tow; /* [out] Time of Week (truncated) */ + int16_t id; /* [out] Satellite id */ + uint8_t iode; /* [out] Issue of Data (Ephemeris) Subframe 2 */ + int8_t codes_on_l2; /* [out] Code(s) on L2 Channel */ + int16_t weeknumber; /* [out] Full week number */ + int8_t l2p; /* [out] Data Flag for L2 P-Code */ + uint8_t health; /* [out] SV Health (6bit for ephemeris / 8bit for almanac) */ + int16_t iodc; /* [out] Issue of Data, Clock (IODC) */ + int8_t fitinterval; /* [out] Fit interval flag */ +}; + +/* Ephemeris data (GLONASS) */ + +struct cxd56_rtk_glonassephemeris_s +{ + uint64_t timesnow; /* [out] system now times */ + uint32_t valid; /* [out] valid */ + uint8_t ppsstatus; /* [out] 1PPS synchronization status */ + uint8_t slot; /* [out] slot 1...24 (It generates from svid. Usually same as me->n) */ + int8_t ch; /* [out] ch -7...6 */ + uint8_t p1; /* [out] The difference of t_b from the previous frame */ + uint8_t tk_h; /* [out] Current frame first time (hours) */ + uint8_t tk_m; /* [out] Current frame first time (minutes) */ + uint8_t tk_s; /* [out] Current frame first time (seconds) */ + double xv; /* [out] The velocity vector components of t_b */ + float xa; /* [out] The acceleration components of t_b */ + double xp; /* [out] The position of t_b */ + uint8_t bn; /* [out] The health info */ + uint8_t p2; /* [out] flag of oddness ("1") or evenness ("0") of the value of t_b */ + uint16_t tb; /* [out] Reference time t_b (15...1425) */ + uint8_t hn_e; /* [out] Carrier frequency number (0...31, (25...31)=(7...-1)) */ + double yv; /* [out] The velocity vector components of t_b */ + float ya; /* [out] The acceleration components of t_b */ + double yp; /* [out] The position of t_b */ + uint8_t p3; /* [out] Number of almanacs in the current frame */ + float gn; /* [out] Carrier frequency relative deviation of t_b */ + uint8_t p; /* [out] Origin of tau variable */ + uint8_t health; /* [out] Health flag */ + double zv; /* [out] The velocity vector components of t_b */ + float za; /* [out] The acceleration components of t_b */ + double zp; /* [out] The position of t_b */ + float tn; /* [out] Correction to the satellite time t_n relative to GLONASS time t_c */ + float dtn; /* [out] Difference in internal delay between L2 and L1 */ + uint8_t en; /* [out] Number of days from when data was uploaded until t_b (0...31) */ + uint8_t p4; /* [out] Flag of ephemeris parameters updating */ + uint8_t ft; /* [out] The URA (index) of t_b */ + uint16_t nt; /* [out] Number of days since 1/1 of a leap year */ + uint8_t n; /* [out] Slot number of the signaling satellite (0...31) */ + uint8_t m; /* [out] Satellite type (0...3) */ +}; + +/* Spectrum Data */ + +struct cxd56_gnss_spectrum_s +{ + uint8_t status; /* FFT Sampling Point 0-1 */ + uint8_t samplingstep; /* FFT Sampling Step 1-16 */ + uint8_t sizemode; /* FFT Sampling Num 0:1024 1:512 2:256 */ + uint8_t datacount; /* Spectrum data count */ + uint8_t datanum; /* Spectrum data Size */ + uint8_t ifgain; /* IfGain 0-15 */ + uint16_t dataindex; /* Spectrum data Inex */ + uint16_t spectrum[CXD56_GNSS_SPECTRUM_MAXNUM]; /* Spectrum Data Buffer */ + double peak[CXD56_GNSS_PEAK_SPECTRUM_MAXNUM]; /* Peak Spectrum */ +}; + +#define CXD56_GNSS_SBAS_MESSAGE_DATA_LEN (27) + +/* SBAS Data */ + +struct cxd56_gnss_sbasdata_s +{ + uint64_t timesnow; /* system now times */ + uint32_t gpstow; /* GPS Time of Week */ + uint16_t gpswn; /* GPS week number */ + uint16_t svid; /* satellite id */ + uint8_t msgid; /* sbas message ID */ + uint8_t sbasmsg[CXD56_GNSS_SBAS_MESSAGE_DATA_LEN]; /* sbas message data */ +}; + +/******** PVTLog Parameter ***********/ + +/* Latitude of PVT data */ + +struct cxd56_pvtlog_latitude_s +{ + uint32_t frac :14; /* Decimal */ + uint32_t minute :6; /* Minute */ + uint32_t degree :7; /* Degree */ + uint32_t sign :1; /* Sign */ + uint32_t rsv :4; /* Reserved */ +}; + +/* Longitude of PVT data */ + +struct cxd56_pvtlog_longitude_s +{ + uint32_t frac :14; /* Decimal */ + uint32_t minute :6; /* Minute */ + uint32_t degree :8; /* Degree */ + uint32_t sign :1; /* Sign */ + uint32_t rsv :3; /* Reserved */ +}; + +/* Altitude of PVT data */ + +struct cxd56_pvtlog_altitude_s +{ + uint32_t frac :4; /* Decimal */ + uint32_t rsv1 :12; /* Reserved */ + uint32_t meter :14; /* Integer */ + uint32_t sign :1; /* Sign */ + uint32_t rsv2 :1; /* Reserved */ +}; + +/* Velocity of PVT data */ + +struct cxd56_pvtlog_velocity_s +{ + uint16_t knot :14; /* Integer */ + uint16_t rsv :2; /* Reserved */ +}; + +/* Direction of PVT data */ + +struct cxd56_pvtlog_direction_s +{ + uint16_t frac :4; /* Decimal */ + uint16_t degree :9; /* Integer */ + uint16_t rsv :3; /* Reserved */ +}; + +/* Time (UTC) of PVT data */ + +struct cxd56_pvtlog_time_s +{ + uint32_t msec :7; /* msec */ + uint32_t rsv1 :1; /* Reserved */ + uint32_t sec :6; /* Second */ + uint32_t rsv2 :2; /* Reserved */ + uint32_t minute :6; /* Minute */ + uint32_t rsv3 :2; /* Reserved */ + uint32_t hour :5; /* Hour */ + uint32_t rsv4 :3; /* Reserved */ +}; + +/* Date (UTC) of PVT data */ + +struct cxd56_pvtlog_date_s +{ + uint32_t year :7; /* Year */ + uint32_t day :5; /* Day */ + uint32_t month :4; /* Month */ + uint32_t rsv :16; /* Reserved */ +}; + +/* PVTLog save data struct */ + +struct cxd56_pvtlog_data_s +{ + struct cxd56_pvtlog_latitude_s latitude; /* Latitude of data 4B */ + struct cxd56_pvtlog_longitude_s longitude; /* Longitude of data 4B */ + struct cxd56_pvtlog_altitude_s altitude; /* Altitude of data 4B */ + struct cxd56_pvtlog_velocity_s velocity; /* Velocity of data 2B */ + struct cxd56_pvtlog_direction_s direction; /* Direction of data 2B */ + struct cxd56_pvtlog_time_s time; /* Time (UTC) 4B */ + struct cxd56_pvtlog_date_s date; /* Date (UTC) 4B */ +}; + +/* PVTLog notification data struct */ + +struct cxd56_pvtlog_s +{ + uint32_t log_count; /* [in] Valid log count of log_data */ + struct cxd56_pvtlog_data_s log_data[CXD56_GNSS_PVTLOG_MAXNUM]; /* [in] Stored log data */ +}; + +/* PVTLog Status Data */ + +struct cxd56_gnss_status_s +{ + uint32_t log_count; /* [in] Saved log count */ + struct cxd56_pvtlog_time_s start_time; /* [in] Time (UTC) 4B */ + struct cxd56_pvtlog_date_s start_date; /* [in] Date (UTC) 4B */ + struct cxd56_pvtlog_time_s end_time; /* [in] Time (UTC) 4B */ + struct cxd56_pvtlog_date_s end_date; /* [in] Date (UTC) 4B */ +}; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARCH_ARM_INCLUDE_CXD56XX_GNSS_TYPE_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_wdt.h b/arch/arm/include/cxd56xx/uart0.h similarity index 57% rename from arch/arm/src/lpc11xx/lpc11_wdt.h rename to arch/arm/include/cxd56xx/uart0.h index f2b073b5833..3fd1420646b 100644 --- a/arch/arm/src/lpc11xx/lpc11_wdt.h +++ b/arch/arm/include/cxd56xx/uart0.h @@ -1,8 +1,7 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_wdt.h +/**************************************************************************** + * arch/arm/include/cxd56xx/cxd56_uart0.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright 2018 Sony Semiconductor Solutions Corporation * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -14,9 +13,10 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -31,32 +31,38 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H +#ifndef __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H +#define __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "hardware/lpc11_wdt.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Data - ************************************************************************************/ +#ifndef __ASSEMBLY__ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H */ +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int cxd56_uart0initialize(FAR const char *devname); +void cxd56_uart0uninitialize(FAR const char *devname); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H */ diff --git a/arch/arm/include/lpc11xx/chip.h b/arch/arm/include/lpc11xx/chip.h deleted file mode 100644 index 7d287d325f0..00000000000 --- a/arch/arm/include/lpc11xx/chip.h +++ /dev/null @@ -1,92 +0,0 @@ -/************************************************************************************ - * arch/arm/include/lpc11xx/chip.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H -#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_LPC1115) -# define LPC111x 1 /* LPC111x family */ -# define LPC11_FLASH_SIZE (64*1024) /* 64Kb */ -# define LPC11_SRAM_SIZE (8*1024) /* 8Kb */ -# define LPC11_CPUSRAM_SIZE (8*1024) -# undef LPC11_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC11_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC11_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC11_NUSBHOST 0 /* No USB host controller */ -# define LPC11_NUSBOTG 0 /* No USB OTG controller */ -# define LPC11_NUSBDEV 1 /* One USB device controller */ -# define LPC11_NCAN 1 /* One CAN controller */ -# define LPC11_NI2S 0 /* No I2S modules */ -# define LPC11_NDAC 0 /* No DAC module */ -#else -# error "Unsupported LPC11xx chip" -#endif - -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:6] of each field, bits[5:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */ diff --git a/arch/arm/include/lpc11xx/irq.h b/arch/arm/include/lpc11xx/irq.h deleted file mode 100644 index bb89a61a576..00000000000 --- a/arch/arm/include/lpc11xx/irq.h +++ /dev/null @@ -1,143 +0,0 @@ -/**************************************************************************** - * arch/arm/include/lpc11xxx/irq.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* This file should never be included directed but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H -#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -# include -#endif -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - */ - -/* Common Processor Exceptions (vectors 0-15) */ - -#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LPC11_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ - /* Vectors 4-10: Reserved */ -#define LPC11_IRQ_SVCALL (11) /* Vector 11: SVC call */ - /* Vector 12-13: Reserved */ -#define LPC11_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LPC11_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16) */ - -#define LPC11_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ - -#if defined(CONFIG_ARCH_CHIP_LPC1115) -#define LPC11_IRQ_PIO0_0 (16) /* Vector 16: PIO0_0 */ -#define LPC11_IRQ_PIO0_1 (17) /* Vector 17: PIO0_1 */ -#define LPC11_IRQ_PIO0_2 (18) /* Vector 18: PIO0_2 */ -#define LPC11_IRQ_PIO0_3 (19) /* Vector 19: PIO0_3 */ -#define LPC11_IRQ_PIO0_4 (20) /* Vector 20: PIO0_4 */ -#define LPC11_IRQ_PIO0_5 (21) /* Vector 21: PIO0_5 */ -#define LPC11_IRQ_PIO0_6 (22) /* Vector 22: PIO0_6 */ -#define LPC11_IRQ_PIO0_7 (23) /* Vector 23: PIO0_7 */ -#define LPC11_IRQ_PIO0_8 (24) /* Vector 24: PIO0_8 */ -#define LPC11_IRQ_PIO0_9 (25) /* Vector 25: PIO0_9 */ -#define LPC11_IRQ_PIO0_10 (26) /* Vector 26: PIO0_10 */ -#define LPC11_IRQ_PIO0_11 (27) /* Vector 27: PIO0_11 */ -#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */ -#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */ -#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */ -#define LPC11_IRQ_I2C0 (31) /* Vector 31: I2C0 */ -#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */ -#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */ -#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */ -#define LPC11_IRQ_CT32B1 (35) /* Vector 35: Clock/Timer1 32 bits */ -#define LPC11_IRQ_SSP0 (36) /* Vector 36: SPI0/SSP0 */ -#define LPC11_IRQ_UART (37) /* Vector 37: UART */ - /* Vector 38: Reserved */ - /* Vector 39: Reserved */ -#define LPC11_IRQ_ADC (40) /* Vector 40: Analog/Digital Converter */ -#define LPC11_IRQ_WDT (41) /* Vector 41: Watchdog timer */ -#define LPC11_IRQ_BOD (42) /* Vector 42: Brownout Detection */ - /* Vector 43: Reserved */ -#define LPC11_IRQ_PIO3 (44) /* Vector 44: PIO3 */ -#define LPC11_IRQ_PIO2 (45) /* Vector 45: PIO2 */ -#define LPC11_IRQ_PIO1 (46) /* Vector 46: PIO1 */ -#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */ -#endif - -#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */ diff --git a/arch/arm/include/lpc17xx/chip.h b/arch/arm/include/lpc17xx/chip.h deleted file mode 100644 index 91b15abad69..00000000000 --- a/arch/arm/include/lpc17xx/chip.h +++ /dev/null @@ -1,388 +0,0 @@ -/************************************************************************************ - * arch/arm/include/lpc17xx/chip.h - * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * with LPC178x support from Rommel Marcelo - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H -#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_LPC1751) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ -# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1752) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ -# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1754) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1756) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1758) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1759) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1764) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1765) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1766) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1767) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 0 /* No USB device controller */ -# define LPC17_NCAN 0 /* No CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) -# define LPC176x 1 /* LPC175/6 family */ -# undef LPC178x /* Not LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1773) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LPC17_NUSBHOST /* No USB host controller */ -# undef LPC17_NUSBOTG /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */ -# undef LPC17_HAVE_LCD /* No LCD controller */ -# undef LPC17_HAVE_QEI /* No QEI interface */ -# undef LPC17_HAVE_SD /* No SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1774) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/ -# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LPC17_NUSBHOST /* One USB host controller */ -# undef LPC17_NUSBOTG /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# undef LPC17_HAVE_LCD /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1776) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# undef LPC17_HAVE_LCD /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1777) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ -# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# undef LPC17_HAVE_LCD /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1778) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# undef LPC17_HAVE_LCD /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1785) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ -# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# define LPC17_HAVE_LCD 1 /* One LCD controller */ -# undef LPC17_HAVE_QEI /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1786) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# define LPC17_HAVE_LCD 1 /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1787) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ -# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# define LPC17_HAVE_LCD 1 /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#elif defined(CONFIG_ARCH_CHIP_LPC1788) -# undef LPC176x /* Not LPC175/6 family */ -# define LPC178x 1 /* LPC177/8 family */ -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */ -# define LPC17_CPUSRAM_SIZE (64*1024) -# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ -# define LPC17_HAVE_LCD 1 /* One LCD controller */ -# define LPC17_HAVE_QEI 1 /* One QEI interface */ -# define LPC17_HAVE_SD 1 /* One SD controller */ -#else -# error "Unsupported LPC17xx chip" -#endif - -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */ diff --git a/arch/arm/include/lpc17xx/lpc176x_irq.h b/arch/arm/include/lpc17xx/lpc176x_irq.h deleted file mode 100644 index ed8b75a6b18..00000000000 --- a/arch/arm/include/lpc17xx/lpc176x_irq.h +++ /dev/null @@ -1,245 +0,0 @@ -/**************************************************************************** - * arch/lpc17xx/lpc176x_irq.h - * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* This file should never be included directed but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H -#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - */ - -/* External interrupts (vectors >= 16) */ - -#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ -#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * Modem Control Change - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 - * Capture 0-1 of PWM1 */ -#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ -#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ -#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ -#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF) - * Mode Fault (MODF) */ -#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 - * Rx FIFO half full of SSP0 - * Rx Timeout of SSP0 - * Rx Overrun of SSP0 */ -#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty - * Rx FIFO half full - * Rx Timeout - * Rx Overrun */ -#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ -#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) - * Alarm (RTCALF) */ -#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ -#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ -#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ -#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) - * Note: EINT3 channel is shared with GPIO interrupts */ -#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ -#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ -#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, - * USB_INT_REQ_DMA */ -#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, - * CAN 1 Tx, CAN 1 Rx */ -#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, - * IntStatus of DMA channel 1 */ -#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ -#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, - * TxFinishedInt, TxErrorInt,* TxUnderrunInt, - * RxDoneInt, RxFinishedInt, RxErrorInt, - * RxOverrunInt */ -#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */ -#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], - * ICAP[2:0], FES */ -#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, - * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int - * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, - * POS2REV_Int */ -#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ -#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ -#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ -#define LPC17_IRQ_NEXTINT (35) -#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) - -/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and - * 2 (only). We go through some special efforts to keep the number of IRQs - * to a minimum in this sparse interrupt case. - * - * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30 - * 14 interrupts on Port 2: p2.0 - p2.13 - * -- - * 42 - */ - -#ifdef CONFIG_LPC17_GPIOIRQ -# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */ -# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ - - /* Set 1: 12 interrupts p0.0-p0.11 */ - -# define LPC17_VALID_GPIOINT0L (0x00000ffful) -# define LPC17_VALID_SHIFT0L (0) -# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) - -# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) -# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) -# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) -# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) -# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) -# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) -# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) -# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) -# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) -# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) -# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) -# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) -# define LPC17_VALID_NIRQS0L (12) - - /* Set 2: 16 interrupts p0.15-p0.30 */ - -# define LPC17_VALID_GPIOINT0H (0x7fff8000ull) -# define LPC17_VALID_SHIFT0H (15) -# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) - -# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0) -# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1) -# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2) -# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3) -# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4) -# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5) -# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6) -# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7) -# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8) -# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9) -# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10) -# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11) -# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12) -# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13) -# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14) -# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15) -# define LPC17_VALID_NIRQS0H (16) - - /* Set 3: 14 interrupts p2.0-p2.13 */ - -# define LPC17_VALID_GPIOINT2 (0x00003ffful) -# define LPC17_VALID_SHIFT2 (0) -# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) - -# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0) -# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1) -# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2) -# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3) -# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4) -# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5) -# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6) -# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7) -# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8) -# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9) -# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10) -# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11) -# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12) -# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13) -# define LPC17_VALID_NIRQS2 (14) -# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2) -#else -# define LPC17_NGPIOAIRQS (0) -#endif - -/* Total number of IRQ numbers */ - -#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */ - diff --git a/arch/arm/include/lpc17xx/lpc178x_irq.h b/arch/arm/include/lpc17xx/lpc178x_irq.h deleted file mode 100644 index c9d5bee15f8..00000000000 --- a/arch/arm/include/lpc17xx/lpc178x_irq.h +++ /dev/null @@ -1,291 +0,0 @@ -/**************************************************************************** - * arch/arm/include/lpc17xxx/lpc178x_irq.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H -#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - */ - -/* External interrupts (vectors >= 16) */ - -#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ -#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * Modem Control Change - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 - * Capture 0-1 of PWM1 */ -#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ -#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ -#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ -#define LPC17_IRQ_RESERVED29 (LPC17_IRQ_EXTINT+13) /* Unused */ -#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 - * Rx FIFO half full of SSP0 - * Rx Timeout of SSP0 - * Rx Overrun of SSP0 */ -#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty - * Rx FIFO half full - * Rx Timeout - * Rx Overrun */ -#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ -#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) - * Alarm (RTCALF) */ -#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ -#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ -#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ -#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) - * Note: EINT3 channel is shared with GPIO interrupts */ -#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ -#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ -#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, - * USB_INT_REQ_DMA */ -#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, - * CAN 1 Tx, CAN 1 Rx */ -#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, - * IntStatus of DMA channel 1 */ -#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ -#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, - * TxFinishedInt, TxErrorInt,* TxUnderrunInt, - * RxDoneInt, RxFinishedInt, RxErrorInt, - * RxOverrunInt */ -#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */ -#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], - * ICAP[2:0], FES */ -#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, - * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int - * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, - * POS2REV_Int */ -#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ -#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ -#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ -#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2 - * Rx FIFO half full of SSP2 - * Rx Timeout of SSP2 - * Rx Overrun of SSP2 */ -#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt - * BER, VCompI, LNBUI, FUFI, CrsrI */ -#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt - * P0xREI, P2xREI, P0xFEI, P2xFEI */ -#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0 - * Capture 0-1 of PWM0 */ -#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt - * EE_PROG_DONE, EE_RW_DONE */ -#define LPC17_IRQ_NEXTINT (41) -#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) - -/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and - * 2 (only). We go through some special efforts to keep the number of IRQs - * to a minimum in this sparse interrupt case. - * - * 31 interrupts on Port 0: p0.0 - p0.30 - * 31 interrupts on Port 2: p2.0 - p2.30 - * -- - * 42 - */ - -#ifdef CONFIG_LPC17_GPIOIRQ -# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */ -# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */ - - /* Set 1: 16 interrupts p0.0-p0.15 */ - -# define LPC17_VALID_SHIFT0L (0) -# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) - -# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) -# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) -# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) -# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) -# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) -# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) -# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) -# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) -# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) -# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) -# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) -# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) -# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12) -# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13) -# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14) -# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15) -# define LPC17_VALID_NIRQS0L (16) - - /* Set 2: 16 interrupts p0.16-p0.31 */ - -# define LPC17_VALID_SHIFT0H (16) -# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) - -# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0) -# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1) -# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2) -# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3) -# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4) -# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5) -# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6) -# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7) -# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8) -# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9) -# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10) -# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11) -# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12) -# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13) -# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14) -# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15) -# define LPC17_VALID_NIRQS0H (16) - - /* Set 3: 16 interrupts p2.0-p2.15 */ - -# define LPC17_VALID_SHIFT2L (0) -# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) - -# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0) -# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1) -# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2) -# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3) -# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4) -# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5) -# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6) -# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7) -# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8) -# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9) -# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10) -# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11) -# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12) -# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13) -# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14) -# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15) -# define LPC17_VALID_NIRQS2L (16) - - /* Set 4: 16 interrupts p2.16 - p2.31 */ - -# define LPC17_VALID_SHIFT2H (16) -# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L) - -# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0) -# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1) -# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2) -# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3) -# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4) -# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5) -# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6) -# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7) -# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8) -# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9) -# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10) -# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11) -# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12) -# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13) -# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14) -# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15) -# define LPC17_VALID_NIRQS2H (16) - -# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H) -#else -# define LPC17_NGPIOAIRQS (0) -#endif - -/* Total number of IRQ numbers */ - -#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */ - diff --git a/arch/arm/include/lpc17xx_40xx/chip.h b/arch/arm/include/lpc17xx_40xx/chip.h new file mode 100644 index 00000000000..faa36ac8a34 --- /dev/null +++ b/arch/arm/include/lpc17xx_40xx/chip.h @@ -0,0 +1,468 @@ +/************************************************************************************ + * arch/arm/include/lpc17xx_40xx/chip.h + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * with LPC178x support from Rommel Marcelo + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H +#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_LPC1751) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (32*1024) /* 32Kb */ +# define LPC17_40_SRAM_SIZE (8*1024) /* 8Kb */ +# define LPC17_40_CPUSRAM_SIZE (8*1024) +# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 0 /* No USB host controller */ +# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 1 /* One CAN controller */ +# define LPC17_40_NI2S 0 /* No I2S modules */ +# define LPC17_40_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1752) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (64*1024) /* 65Kb */ +# define LPC17_40_SRAM_SIZE (16*1024) /* 16Kb */ +# define LPC17_40_CPUSRAM_SIZE (16*1024) +# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 0 /* No USB host controller */ +# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 1 /* One CAN controller */ +# define LPC17_40_NI2S 0 /* No I2S modules */ +# define LPC17_40_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1754) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_40_CPUSRAM_SIZE (16*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 1 /* One CAN controller */ +# define LPC17_40_NI2S 0 /* No I2S modules */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1756) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_40_CPUSRAM_SIZE (16*1024) +# define LPC17_40_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1758) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1759) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1764) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_40_CPUSRAM_SIZE (16*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 0 /* No USB host controller */ +# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 0 /* No I2S modules */ +# define LPC17_40_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1765) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1766) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1767) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 0 /* No USB host controller */ +# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 0 /* No USB device controller */ +# define LPC17_40_NCAN 0 /* No CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_NCAN 2 /* Two CAN controllers */ +# define LPC17_40_NI2S 1 /* One I2S module */ +# define LPC17_40_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1773) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LPC17_40_NUSBHOST /* No USB host controller */ +# undef LPC17_40_NUSBOTG /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# undef LPC17_40_HAVE_QEI /* No QEI interface */ +# undef LPC17_40_HAVE_SD /* No SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1774) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/ +# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LPC17_40_NUSBHOST /* One USB host controller */ +# undef LPC17_40_NUSBOTG /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1776) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1777) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1778) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1785) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_40_HAVE_LCD 1 /* One LCD controller */ +# undef LPC17_40_HAVE_QEI /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1786) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_40_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1787) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_40_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1788) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_40_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC4072) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (64*1024) /* 64Kb */ +# define LPC17_40_SRAM_SIZE (24*1024) /* 24Kb */ +# define LPC17_40_CPUSRAM_SIZE (16*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */ +# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */ +# undef LPC17_40_NUSBHOST /* No USB host controller */ +# undef LPC17_40_NUSBOTG /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# undef LPC17_40_HAVE_QEI /* No QEI interface */ +# undef LPC17_40_HAVE_SD /* No SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC4074) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */ +# define LPC17_40_CPUSRAM_SIZE (32*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/ +# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */ +# undef LPC17_40_NUSBHOST /* No USB host controller */ +# undef LPC17_40_NUSBOTG /* No USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* One LCD controller */ +# undef LPC17_40_HAVE_QEI /* No QEI interface */ +# undef LPC17_40_HAVE_SD /* No SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC4076) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC4078) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_40_HAVE_LCD /* No LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC4088) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */ +# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */ +# define LPC17_40_CPUSRAM_SIZE (64*1024) +# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_40_NUSBHOST 1 /* One USB host controller */ +# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_40_NUSBDEV 1 /* One USB device controller */ +# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */ +# define LPC17_40_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_40_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_40_HAVE_SD 1 /* One SD controller */ +#else +# error "Unsupported LPC17xx/LPC40xx chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H */ diff --git a/arch/arm/include/lpc17xx/irq.h b/arch/arm/include/lpc17xx_40xx/irq.h similarity index 70% rename from arch/arm/include/lpc17xx/irq.h rename to arch/arm/include/lpc17xx_40xx/irq.h index 99bffe17ebb..3b8e4c50ed2 100644 --- a/arch/arm/include/lpc17xx/irq.h +++ b/arch/arm/include/lpc17xx_40xx/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/lpc17xxx/irq.h + * arch/arm/include/lpc17xx_40xxx/irq.h * * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H -#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ #ifndef __ASSEMBLY__ # include #endif -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -59,32 +59,32 @@ /* Common Processor Exceptions (vectors 0-15) */ -#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define LPC17_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define LPC17_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LPC17_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define LPC17_40_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LPC17_40_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LPC17_40_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LPC17_40_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LPC17_40_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LPC17_40_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LPC17_40_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LPC17_40_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LPC17_40_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LPC17_40_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16) */ -#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ +#define LPC17_40_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ /* Family Specfic Interrupts */ #if defined(LPC176x) /* LPC175/6 family */ -# include -#elif defined(LPC178x) /* LPC177/8 family */ -# include +# include +#elif defined(LPC178x_40xx) /* LPC177/8 or LPC40xx family */ +# include #else -# error "Unknown LPC17xx family" +# error "Unknown LPC17xx/LPC40xx family" #endif /**************************************************************************** @@ -116,4 +116,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H */ diff --git a/arch/arm/include/lpc17xx_40xx/lpc176x_irq.h b/arch/arm/include/lpc17xx_40xx/lpc176x_irq.h new file mode 100644 index 00000000000..c91ddc78c1a --- /dev/null +++ b/arch/arm/include/lpc17xx_40xx/lpc176x_irq.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/lpc17xx_40xx/lpc176x_irq.h + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* External interrupts (vectors >= 16) */ + +#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ +#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3 + * Capture 0-1 */ +#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3 + * Capture 0-1 */ +#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * Modem Control Change + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 + * Capture 0-1 of PWM1 */ +#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */ +#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */ +#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */ +#define LPC17_40_IRQ_SPIF (LPC17_40_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF) + * Mode Fault (MODF) */ +#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 + * Rx FIFO half full of SSP0 + * Rx Timeout of SSP0 + * Rx Overrun of SSP0 */ +#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty + * Rx FIFO half full + * Rx Timeout + * Rx Overrun */ +#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ +#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) + * Alarm (RTCALF) */ +#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ +#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ +#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ +#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) + * Note: EINT3 channel is shared with GPIO interrupts */ +#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ +#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */ +#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, + * USB_INT_REQ_DMA */ +#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, + * CAN 1 Tx, CAN 1 Rx */ +#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, + * IntStatus of DMA channel 1 */ +#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ +#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, + * TxFinishedInt, TxErrorInt,* TxUnderrunInt, + * RxDoneInt, RxFinishedInt, RxErrorInt, + * RxOverrunInt */ +#define LPC17_40_IRQ_RITINT (LPC17_40_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */ +#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], + * ICAP[2:0], FES */ +#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, + * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int + * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, + * POS2REV_Int */ +#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ +#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ +#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ +#define LPC17_40_IRQ_NEXTINT (35) +#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT) + +/* GPIO interrupts. The LPC17xx/LPC40xx supports several interrupts on ports 0 and + * 2 (only). We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30 + * 14 interrupts on Port 2: p2.0 - p2.13 + * -- + * 42 + */ + +#ifdef CONFIG_LPC17_40_GPIOIRQ +# define LPC17_40_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */ +# define LPC17_40_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ + + /* Set 1: 12 interrupts p0.0-p0.11 */ + +# define LPC17_40_VALID_GPIOINT0L (0x00000ffful) +# define LPC17_40_VALID_SHIFT0L (0) +# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT) + +# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0) +# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1) +# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2) +# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3) +# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4) +# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5) +# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6) +# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7) +# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8) +# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9) +# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10) +# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11) +# define LPC17_40_VALID_NIRQS0L (12) + + /* Set 2: 16 interrupts p0.15-p0.30 */ + +# define LPC17_40_VALID_GPIOINT0H (0x7fff8000ull) +# define LPC17_40_VALID_SHIFT0H (15) +# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L) + +# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0H+0) +# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+1) +# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+2) +# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+3) +# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+4) +# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+5) +# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+6) +# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+7) +# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+8) +# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+9) +# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+10) +# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+11) +# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+12) +# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+13) +# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+14) +# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+15) +# define LPC17_40_VALID_NIRQS0H (16) + + /* Set 3: 14 interrupts p2.0-p2.13 */ + +# define LPC17_40_VALID_GPIOINT2 (0x00003ffful) +# define LPC17_40_VALID_SHIFT2 (0) +# define LPC17_40_VALID_FIRST2 (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H) + +# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2+0) +# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2+1) +# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2+2) +# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2+3) +# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2+4) +# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2+5) +# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2+6) +# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2+7) +# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2+8) +# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2+9) +# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2+10) +# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2+11) +# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2+12) +# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2+13) +# define LPC17_40_VALID_NIRQS2 (14) +# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2) +#else +# define LPC17_40_NGPIOAIRQS (0) +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H */ + diff --git a/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h b/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h new file mode 100644 index 00000000000..b35ef750f56 --- /dev/null +++ b/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h @@ -0,0 +1,291 @@ +/**************************************************************************** + * arch/arm/include/lpc17xx_40xxx/lpc178x_40xx_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* External interrupts (vectors >= 16) */ + +#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ +#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3 + * Capture 0-1 */ +#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3 + * Capture 0-1 */ +#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * Modem Control Change + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 + * Capture 0-1 of PWM1 */ +#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */ +#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */ +#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */ +#define LPC17_40_IRQ_RESERVED29 (LPC17_40_IRQ_EXTINT+13) /* Unused */ +#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 + * Rx FIFO half full of SSP0 + * Rx Timeout of SSP0 + * Rx Overrun of SSP0 */ +#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty + * Rx FIFO half full + * Rx Timeout + * Rx Overrun */ +#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ +#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) + * Alarm (RTCALF) */ +#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ +#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ +#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ +#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) + * Note: EINT3 channel is shared with GPIO interrupts */ +#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ +#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */ +#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, + * USB_INT_REQ_DMA */ +#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, + * CAN 1 Tx, CAN 1 Rx */ +#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, + * IntStatus of DMA channel 1 */ +#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ +#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, + * TxFinishedInt, TxErrorInt,* TxUnderrunInt, + * RxDoneInt, RxFinishedInt, RxErrorInt, + * RxOverrunInt */ +#define LPC17_40_IRQ_MCI (LPC17_40_IRQ_EXTINT+29) /* MCI SD Card Interface */ +#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], + * ICAP[2:0], FES */ +#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, + * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int + * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, + * POS2REV_Int */ +#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ +#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ +#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ +#define LPC17_40_IRQ_UART4 (LPC17_40_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_40_IRQ_SSP2 (LPC17_40_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2 + * Rx FIFO half full of SSP2 + * Rx Timeout of SSP2 + * Rx Overrun of SSP2 */ +#define LPC17_40_IRQ_LCD (LPC17_40_IRQ_EXTINT+37) /* LCD interrupt + * BER, VCompI, LNBUI, FUFI, CrsrI */ +#define LPC17_40_IRQ_GPIO (LPC17_40_IRQ_EXTINT+38) /* GPIO Interrupt + * P0xREI, P2xREI, P0xFEI, P2xFEI */ +#define LPC17_40_IRQ_PWM0 (LPC17_40_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0 + * Capture 0-1 of PWM0 */ +#define LPC17_40_IRQ_EEPROM (LPC17_40_IRQ_EXTINT+40) /* EEPROM Interrupt + * EE_PROG_DONE, EE_RW_DONE */ +#define LPC17_40_IRQ_NEXTINT (41) +#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT) + +/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and + * 2 (only). We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * 31 interrupts on Port 0: p0.0 - p0.30 + * 31 interrupts on Port 2: p2.0 - p2.30 + * -- + * 42 + */ + +#ifdef CONFIG_LPC17_40_GPIOIRQ +# define LPC17_40_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */ +# define LPC17_40_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */ + + /* Set 1: 16 interrupts p0.0-p0.15 */ + +# define LPC17_40_VALID_SHIFT0L (0) +# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT) + +# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0) +# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1) +# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2) +# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3) +# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4) +# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5) +# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6) +# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7) +# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8) +# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9) +# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10) +# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11) +# define LPC17_40_IRQ_P0p12 (LPC17_40_VALID_FIRST0L+12) +# define LPC17_40_IRQ_P0p13 (LPC17_40_VALID_FIRST0L+13) +# define LPC17_40_IRQ_P0p14 (LPC17_40_VALID_FIRST0L+14) +# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0L+15) +# define LPC17_40_VALID_NIRQS0L (16) + + /* Set 2: 16 interrupts p0.16-p0.31 */ + +# define LPC17_40_VALID_SHIFT0H (16) +# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L) + +# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+0) +# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+1) +# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+2) +# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+3) +# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+4) +# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+5) +# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+6) +# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+7) +# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+8) +# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+9) +# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+10) +# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+11) +# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+12) +# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+13) +# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+14) +# define LPC17_40_IRQ_P0p31 (LPC17_40_VALID_FIRST0H+15) +# define LPC17_40_VALID_NIRQS0H (16) + + /* Set 3: 16 interrupts p2.0-p2.15 */ + +# define LPC17_40_VALID_SHIFT2L (0) +# define LPC17_40_VALID_FIRST2L (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H) + +# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2L+0) +# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2L+1) +# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2L+2) +# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2L+3) +# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2L+4) +# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2L+5) +# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2L+6) +# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2L+7) +# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2L+8) +# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2L+9) +# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2L+10) +# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2L+11) +# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2L+12) +# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2L+13) +# define LPC17_40_IRQ_P2p14 (LPC17_40_VALID_FIRST2L+14) +# define LPC17_40_IRQ_P2p15 (LPC17_40_VALID_FIRST2L+15) +# define LPC17_40_VALID_NIRQS2L (16) + + /* Set 4: 16 interrupts p2.16 - p2.31 */ + +# define LPC17_40_VALID_SHIFT2H (16) +# define LPC17_40_VALID_FIRST2H (LPC17_40_VALID_FIRST2L+LPC17_40_VALID_NIRQS2L) + +# define LPC17_40_IRQ_P2p16 (LPC17_40_VALID_FIRST2H+0) +# define LPC17_40_IRQ_P2p17 (LPC17_40_VALID_FIRST2H+1) +# define LPC17_40_IRQ_P2p18 (LPC17_40_VALID_FIRST2H+2) +# define LPC17_40_IRQ_P2p19 (LPC17_40_VALID_FIRST2H+3) +# define LPC17_40_IRQ_P2p20 (LPC17_40_VALID_FIRST2H+4) +# define LPC17_40_IRQ_P2p21 (LPC17_40_VALID_FIRST2H+5) +# define LPC17_40_IRQ_P2p22 (LPC17_40_VALID_FIRST2H+6) +# define LPC17_40_IRQ_P2p23 (LPC17_40_VALID_FIRST2H+7) +# define LPC17_40_IRQ_P2p24 (LPC17_40_VALID_FIRST2H+8) +# define LPC17_40_IRQ_P2p25 (LPC17_40_VALID_FIRST2H+9) +# define LPC17_40_IRQ_P2p26 (LPC17_40_VALID_FIRST2H+10) +# define LPC17_40_IRQ_P2p27 (LPC17_40_VALID_FIRST2H+11) +# define LPC17_40_IRQ_P2p28 (LPC17_40_VALID_FIRST2H+12) +# define LPC17_40_IRQ_P2p29 (LPC17_40_VALID_FIRST2H+13) +# define LPC17_40_IRQ_P2p30 (LPC17_40_VALID_FIRST2H+14) +# define LPC17_40_IRQ_P2p31 (LPC17_40_VALID_FIRST2H+15) +# define LPC17_40_VALID_NIRQS2H (16) + +# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2L+LPC17_40_VALID_NIRQS2H) +#else +# define LPC17_40_NGPIOAIRQS (0) +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H */ + diff --git a/arch/arm/src/armv7-m/up_ramvec_initialize.c b/arch/arm/src/armv7-m/up_ramvec_initialize.c index 2e00cf2d4ce..0e0c4eb194e 100644 --- a/arch/arm/src/armv7-m/up_ramvec_initialize.c +++ b/arch/arm/src/armv7-m/up_ramvec_initialize.c @@ -86,7 +86,7 @@ * vector table must be zero). In this case alignment to a 128 byte address * boundary is sufficient. * - * Some parts, such as the LPC17xx family, require alignment to a 256 byte + * Some parts, such as the LPC17xx/LPC40xx family, require alignment to a 256 byte * address boundary. Any other unusual alignment requirements for the vector * can be specified for a given architecture be redefining * NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the diff --git a/arch/arm/src/cxd56xx/Kconfig b/arch/arm/src/cxd56xx/Kconfig index 14ca69e6d9f..3dcfe81281d 100644 --- a/arch/arm/src/cxd56xx/Kconfig +++ b/arch/arm/src/cxd56xx/Kconfig @@ -224,6 +224,46 @@ config CXD56_GPIO_IRQ ---help--- Enable support for GPIO interrupts +config CXD56_UART0 + bool "UART0" + default n + ---help--- + UART interface with hardware flow control in the application subsystem. + +if CXD56_UART0 + +config CXD56_UART0_BAUD + int "CXD56 UART0 BAUD" + default 921600 + +config CXD56_UART0_PARITY + int "CXd56 UART0 parity" + default 0 + range 0 2 + ---help--- + CXD56 UART0 parity. 0=None, 1=Odd, 2=Even. Default: None + +config CXD56_UART0_BITS + int "CXD56 UART0 number of bits" + default 8 + range 5 8 + ---help--- + CXD56 UART0 number of bits. Default: 8 + +config CXD56_UART0_2STOP + int "CXD56 UART0 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config CXD56_UART0_FLOWCONTROL + bool "CXD56 UART0 flow control" + default n + ---help--- + Enable CXD56 UART0 RTS flow control + +endif + config CXD56_UART1 bool "UART1" default y @@ -1183,4 +1223,71 @@ config CXD56_GE2D default n ---help--- A hardware image processor device. + +config CXD56_GNSS + bool "GNSS device" + default n + +if CXD56_GNSS + +menu "GNSS settings" + +config CXD56_GNSS_NPOLLWAITERS + int "GNSS max poll waiters" + default 4 + +config CXD56_GNSS_NSIGNALRECEIVERS + int "GNSS max signal receivers" + default 4 + +config CXD56_GNSS_WORKER_STACKSIZE + int "GNSS worker thread stack size" + default 128 + +config CXD56_GNSS_WORKER_THREAD_PRIORITY + int "GNSS worker thread priority" + default 255 + +config CXD56_GNSS_BACKUP_FILENAME + string "GNSS backup file name" + default "/mnt/spif/gnss_backup.bin" + ---help--- + Specify the path and file name of backup data. + +config CXD56_GNSS_CEP_FILENAME + string "GNSS CEP file name" + default "/mnt/sd0/gnss_cep.bin" + ---help--- + Specify the path and file name of cep data. + +config CXD56_GNSS_FW_RTK + bool "Support carrier-phase data output for Real-Time Kinematic" + default n + ---help--- + This is experimental function. + +config CXD56_GNSS_DEBUG_FEATURE + bool "GNSS debug feature" + +if CXD56_GNSS_DEBUG_FEATURE + +config CXD56_GNSS_DEBUG_ERROR + bool "GNSS debug error" + +config CXD56_GNSS_DEBUG_WARN + bool "GNSS debug warn" + +config CXD56_GNSS_DEBUG_INFO + bool "GNSS debug info" + +endif # CXD56_GNSS_DEBUG_FEATURE + +endmenu +config CXD56_GEOFENCE + bool "Geofence Support" + default y + depends on CXD56_GNSS + +endif + endmenu diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs index 9a2c000a580..65a79318df7 100644 --- a/arch/arm/src/cxd56xx/Make.defs +++ b/arch/arm/src/cxd56xx/Make.defs @@ -101,6 +101,10 @@ CHIP_CSRCS += cxd56_powermgr.c CHIP_CSRCS += cxd56_farapi.c CHIP_CSRCS += cxd56_sysctl.c +ifeq ($(CONFIG_CXD56_UART0),y) +CHIP_CSRCS += cxd56_uart0.c +endif + ifeq ($(CONFIG_CXD56_PM_PROCFS),y) CHIP_CSRCS += cxd56_powermgr_procfs.c endif @@ -181,3 +185,12 @@ endif ifeq ($(CONFIG_CXD56_WDT),y) CHIP_CSRCS += cxd56_wdt.c endif + +ifeq ($(CONFIG_CXD56_GNSS),y) +CHIP_CSRCS += cxd56_gnss.c +CHIP_CSRCS += cxd56_cpu1signal.c +endif + +ifeq ($(CONFIG_CXD56_GEOFENCE),y) +CHIP_CSRCS += cxd56_geofence.c +endif diff --git a/arch/arm/src/cxd56xx/cxd56_cpu1signal.c b/arch/arm/src/cxd56xx/cxd56_cpu1signal.c new file mode 100644 index 00000000000..7dac15dd2f2 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpu1signal.c @@ -0,0 +1,281 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpu1signal.c + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "cxd56_icc.h" +#include "cxd56_cpu1signal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_CXD56CPU1_WORKER_STACKSIZE +# define CONFIG_CXD56CPU1_WORKER_STACKSIZE 1024 +#endif + +#ifndef CONFIG_CXD56CPU1_WORKER_THREAD_PRIORITY +# define CONFIG_CXD56CPU1_WORKER_THREAD_PRIORITY (SCHED_PRIORITY_MAX) +#endif + +#define CXD56CPU1_CPUID 1 + +/**************************************************************************** + * Private Type + ****************************************************************************/ + +struct cxd56_sigtype_s +{ + int use; + cxd56_cpu1sighandler_t handler; + FAR void * data; +}; + +struct cxd56cpu1_info_s +{ + pthread_t workertid; + int ndev; + struct cxd56_sigtype_s sigtype[CXD56_CPU1_DATA_TYPE_MAX]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct cxd56cpu1_info_s g_cpu1_info = {0}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static FAR void *cxd56cpu1_worker(FAR void *arg) +{ + struct cxd56cpu1_info_s *priv = (struct cxd56cpu1_info_s *)arg; + iccmsg_t msg; + uint8_t sigtype; + int ret; + + msg.cpuid = CXD56CPU1_CPUID; + + while (1) + { + ret = cxd56_iccrecvmsg(&msg, 0); + if (ret < 0) + { + continue; + } + sigtype = (uint8_t)CXD56_CPU1_GET_DEV(msg.data); + if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX) + { + _info("Caught invalid sigtype %d.\n", sigtype); + continue; + } + + if (priv->sigtype[sigtype].handler) + { + priv->sigtype[sigtype].handler(msg.data, + priv->sigtype[sigtype].data); + } + } + + return arg; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int cxd56_cpu1sigsend(uint8_t sigtype, uint32_t data) +{ + iccmsg_t msg; + + msg.cpuid = CXD56CPU1_CPUID; + msg.msgid = sigtype; + msg.data = data; + + return cxd56_iccsend(CXD56_PROTO_GNSS, &msg, 0); +} + +void cxd56_cpu1sigregisterhandler(uint8_t sigtype, + cxd56_cpu1sighandler_t handler) +{ + struct cxd56cpu1_info_s *priv = &g_cpu1_info; + + if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX) + { + return; + } + + priv->sigtype[sigtype].handler = handler; +} + +void cxd56_cpu1sigunregisterhandler(uint8_t sigtype) +{ + struct cxd56cpu1_info_s *priv = &g_cpu1_info; + + if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX) + { + return; + } + + priv->sigtype[sigtype].handler = NULL; +} + +int cxd56_cpu1siginit(uint8_t sigtype, FAR void *data) +{ + struct cxd56cpu1_info_s *priv = &g_cpu1_info; + pthread_attr_t tattr; + struct sched_param param; + pthread_t tid; + int ret; + + if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX) + { + return -ENODEV; + } + + sched_lock(); + + if (priv->sigtype[sigtype].use) + { + ret = -EBUSY; + goto _err1; + } + + priv->sigtype[sigtype].use = true; + priv->sigtype[sigtype].data = data; + + if (priv->ndev > 0) + { + ret = OK; + goto _err1; + } + + priv->ndev++; + + sched_unlock(); + + cxd56_iccinit(CXD56_PROTO_GNSS); + + ret = cxd56_iccinitmsg(CXD56CPU1_CPUID); + if (ret < 0) + { + _err("Failed to initialize ICC for GPS CPU: %d\n", ret); + goto _err0; + } + + pthread_attr_init(&tattr); + tattr.stacksize = CONFIG_CXD56CPU1_WORKER_STACKSIZE; + param.sched_priority = CONFIG_CXD56CPU1_WORKER_THREAD_PRIORITY; + pthread_attr_setschedparam(&tattr, ¶m); + + ret = pthread_create(&tid, &tattr, cxd56cpu1_worker, + (pthread_addr_t)priv); + if (ret != 0) + { + cxd56_iccuninitmsg(CXD56CPU1_CPUID); + ret = -ret; /* pthread_create does not modify errno. */ + goto _err0; + } + priv->workertid = tid; + + return ret; + +_err0: + priv->sigtype[sigtype].use = false; + priv->sigtype[sigtype].data = NULL; + return ret; + +_err1: + sched_unlock(); + return ret; +} + +int cxd56_cpu1siguninit(uint8_t sigtype) +{ + struct cxd56cpu1_info_s *priv = &g_cpu1_info; + pthread_t tid; + int ret; + + if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX) + { + return -ENODEV; + } + + sched_lock(); + + if (!priv->sigtype[sigtype].use) + { + ret = -EBUSY; + goto _err1; + } + + priv->ndev--; + priv->sigtype[sigtype].use = false; + priv->sigtype[sigtype].data = NULL; + + if (priv->ndev > 0) + { + ret = OK; + goto _err0; + } + + tid = priv->workertid; + priv->workertid = 0; + + sched_unlock(); + + pthread_cancel(tid); + pthread_join(tid, NULL); + + cxd56_iccuninit(CXD56CPU1_CPUID); + + return 0; + +_err1: + sched_unlock(); + +_err0: + return ret; +} diff --git a/arch/arm/src/cxd56xx/cxd56_cpu1signal.h b/arch/arm/src/cxd56xx/cxd56_cpu1signal.h new file mode 100644 index 00000000000..5898da67f9e --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpu1signal.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpu1signal.h + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H +#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H + +/* CPU1 Notifyable functions */ + +#define CXD56_CPU1_DATA_TYPE_GNSS 0 +#define CXD56_CPU1_DATA_TYPE_GEOFENCE 1 +#define CXD56_CPU1_DATA_TYPE_PVTLOG 2 +#define CXD56_CPU1_DATA_TYPE_AGPS 3 +#define CXD56_CPU1_DATA_TYPE_RTK 4 +#define CXD56_CPU1_DATA_TYPE_SPECTRUM 5 +#define CXD56_CPU1_DATA_TYPE_INFO 6 +#define CXD56_CPU1_DATA_TYPE_BACKUP 7 +#define CXD56_CPU1_DATA_TYPE_CEP 8 +#define CXD56_CPU1_DATA_TYPE_CEPFILE 9 +#define CXD56_CPU1_DATA_TYPE_BKUPFILE 10 +#define CXD56_CPU1_DATA_TYPE_GPSEPHEMERIS 11 +#define CXD56_CPU1_DATA_TYPE_GLNEPHEMERIS 12 +#define CXD56_CPU1_DATA_TYPE_CPUFIFOAPI 13 +#define CXD56_CPU1_DATA_TYPE_SBAS 14 +#define CXD56_CPU1_DATA_TYPE_DCREPORT 15 +#define CXD56_CPU1_DATA_TYPE_MAX 16 + +/* CPU1 devices */ + +#define CXD56_CPU1_DEV_GNSS (CXD56_CPU1_DATA_TYPE_GNSS) +#define CXD56_CPU1_DEV_GEOFENCE (CXD56_CPU1_DATA_TYPE_GEOFENCE) + +#define CXD56_CPU1_DEV_MASK 0xff +#define CXD56_CPU1_GET_DEV(DATA) ((DATA) & CXD56_CPU1_DEV_MASK) +#define CXD56_CPU1_GET_DATA(DATA) ((DATA) >> 8) + +#if CXD56_CPU1_DATA_TYPE_MAX > (CXD56_CPU1_DEV_MASK + 1) +#error "CXD56_CPU1_DEV must be smaller than 0xf" +#endif + +typedef void (*cxd56_cpu1sighandler_t)(uint32_t data, FAR void *userdata); + +extern int cxd56_cpu1siginit(uint8_t cpu1dev, FAR void *data); +extern int cxd56_cpu1siguninit(uint8_t cpu1dev); +extern void cxd56_cpu1sigregisterhandler(uint8_t cpu1dev, + cxd56_cpu1sighandler_t handler); +extern void cxd56_cpu1sigunregisterhandler(uint8_t cpu1dev); +extern int cxd56_cpu1sigsend(uint8_t sigtype, uint32_t data); + +#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_geofence.c b/arch/arm/src/cxd56xx/cxd56_geofence.c new file mode 100644 index 00000000000..8454bf02f92 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_geofence.c @@ -0,0 +1,777 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_geofence.c + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "cxd56_gnss_api.h" +#include "cxd56_cpu1signal.h" +#include "cxd56_gnss.h" + +#if defined(CONFIG_CXD56_GEOFENCE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_GEOFENCE_NPOLLWAITERS +# define CONFIG_GEOFENCE_NPOLLWAITERS 4 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct cxd56_geofence_dev_s +{ + sem_t devsem; + FAR struct pollfd *fds[CONFIG_GEOFENCE_NPOLLWAITERS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* file operation functions */ + +static int cxd56_geofence_open(FAR struct file *filep); +static int cxd56_geofence_close(FAR struct file *filep); +static ssize_t cxd56_geofence_read(FAR struct file *filep, FAR char *buffer, + size_t len); +static int cxd56_geofence_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +#ifndef CONFIG_DISABLE_POLL +static int cxd56_geofence_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup); +#endif + +/* ioctl command functions */ + +static int cxd56_geofence_start(unsigned long arg); +static int cxd56_geofence_stop(unsigned long arg); +static int cxd56_geofence_add_region(unsigned long arg); +static int cxd56_geofence_modify_region(unsigned long arg); +static int cxd56_geofence_delete_region(unsigned long arg); +static int cxd56_geofence_delete_all_region(unsigned long arg); +static int cxd56_geofence_get_region_data(unsigned long arg); +static int cxd56_geofence_get_used_id(unsigned long arg); +static int cxd56_geofence_get_all_status(unsigned long arg); +static int cxd56_geofence_set_mode(unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This the vtable that supports the character driver interface */ + +static const struct file_operations g_geofencefops = +{ + cxd56_geofence_open, /* open */ + cxd56_geofence_close, /* close */ + cxd56_geofence_read, /* read */ + 0, /* write */ + 0, /* seek */ + cxd56_geofence_ioctl, /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + cxd56_geofence_poll, /* poll */ +#endif +}; + +/* ioctl command list */ + +FAR static int (*g_cmdlist[CXD56_GEOFENCE_IOCTL_MAX])(unsigned long) = +{ + NULL, /* CXD56_GEOFENCE_IOCTL_INVAL = 0 */ + cxd56_geofence_start, + cxd56_geofence_stop, + cxd56_geofence_add_region, + cxd56_geofence_modify_region, + cxd56_geofence_delete_region, + cxd56_geofence_delete_all_region, + cxd56_geofence_get_region_data, + cxd56_geofence_get_used_id, + cxd56_geofence_get_all_status, + cxd56_geofence_set_mode, + + /* max CXD56_GEOFENCE_IOCTL_MAX */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cxd56_geofence_start + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_START command. + * Start GEOFENCE Detect + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_start(unsigned long arg) +{ + return GD_RegisterGeofence(); +} + +/**************************************************************************** + * Name: cxd56_geofence_stop + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_STOP command. + * Stop GEOFENCE Detect + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_stop(unsigned long arg) +{ + return GD_ReleaseGeofence(); +} + +/**************************************************************************** + * Name: cxd56_geofence_add_region + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_ADD command. + * Add region + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_add_region(unsigned long arg) +{ + int ret; + FAR struct cxd56_geofence_region_s *reg_data; + + if (!arg) + { + return -EINVAL; + } + reg_data = (FAR struct cxd56_geofence_region_s *)arg; + + ret = GD_GeoAddRegion(reg_data->id, reg_data->latitude, reg_data->longitude, + reg_data->radius); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_modify_region + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_MODIFY command. + * Modify region + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_modify_region(unsigned long arg) +{ + int ret; + FAR struct cxd56_geofence_region_s *reg_data; + + if (!arg) + { + return -EINVAL; + } + reg_data = (FAR struct cxd56_geofence_region_s *)arg; + + ret = GD_GeoModifyRegion(reg_data->id, reg_data->latitude, + reg_data->longitude, reg_data->radius); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_delete_region + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_DELETE command. + * Delete region + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_delete_region(unsigned long arg) +{ + int ret; + FAR uint8_t id; + + if (UINT8_MAX < arg) + { + return -EINVAL; + } + + id = (uint8_t)arg; + ret = GD_GeoDeleteRegione(id); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_delete_all_region + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_ALL_DELETE command. + * All delete region + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_delete_all_region(unsigned long arg) +{ + int ret; + + ret = GD_GeoDeleteAllRegion(); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_get_region_data + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_GET_REGION_DATA command. + * Get used region ID + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_get_region_data(unsigned long arg) +{ + int ret; + FAR struct cxd56_geofence_region_s *reg_data; + + if (!arg) + { + return -EINVAL; + } + reg_data = (FAR struct cxd56_geofence_region_s *)arg; + + ret = GD_GeoGetRegionData(reg_data->id, ®_data->latitude, + ®_data->longitude, ®_data->radius); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_get_used_id + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_GET_USED_ID command. + * Get used region ID + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_get_used_id(unsigned long arg) +{ + if (!arg) + { + return -EINVAL; + } + + *(uint32_t *)arg = GD_GeoGetUsedRegionId(); + + return 0; +} + +/**************************************************************************** + * Name: cxd56_geofence_get_all_status + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_GET_ALL_STATUS command. + * Get All transition status + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_get_all_status(unsigned long arg) +{ + int ret; + + ret = GD_GeoSetAllRgionNotifyRequest(); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_set_mode + * + * Description: + * Process CXD56_GEOFENCE_IOCTL_SET_MODE command. + * Set geofence operation mode + * + * Input Parameters: + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_set_mode(unsigned long arg) +{ + int ret; + FAR struct cxd56_geofence_mode_s *mode; + + if (!arg) + { + return -EINVAL; + } + mode = (FAR struct cxd56_geofence_mode_s *)arg; + + ret = GD_GeoSetOpMode(mode->deadzone, mode->dwell_detecttime); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_sighandler + * + * Description: + * Common signal handler from GNSS CPU. + * + * Input Parameters: + * data - Received data from GNSS CPU + * userdata - User data, this is the device information specified by the + * second argument of the function cxd56_cpu1siginit. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void cxd56_geofence_sighandler(uint32_t data, FAR void *userdata) +{ + FAR struct cxd56_geofence_dev_s *priv = + (FAR struct cxd56_geofence_dev_s *)userdata; + int i; + int ret; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return; + } + + for (i = 0; i < CONFIG_GEOFENCE_NPOLLWAITERS; i++) + { + struct pollfd *fds = priv->fds[i]; + if (fds) + { + fds->revents |= POLLIN; + gnssinfo("Report events: %02x\n", fds->revents); + sem_post(fds->sem); + } + } + + sem_post(&priv->devsem); +} + +/**************************************************************************** + * Name: cxd56_geofence_initialize + * + * Description: + * initialize GEOFENCE device + * + * Input Parameters: + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_initialize(FAR struct cxd56_geofence_dev_s* dev) +{ + int32_t ret = 0; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_open + * + * Description: + * Standard character driver open method. + * + * Input Parameters: + * filep - File structure pointer + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_open(FAR struct file *filep) +{ + int32_t ret = 0; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_close + * + * Description: + * Standard character driver close method. + * + * Input Parameters: + * filep - File structure pointer + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_close(FAR struct file *filep) +{ + int32_t ret = 0; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_read + * + * Description: + * Standard character driver read method. + * + * Input Parameters: + * filep - File structure pointer + * buffer - Buffer to write + * buflen - The write length of the buffer + * + * Returned Value: + * Always returns -ENOENT error. + * + ****************************************************************************/ + +static ssize_t cxd56_geofence_read(FAR struct file *filep, FAR char *buffer, + size_t len) +{ + int32_t ret = 0; + + /* Check argument */ + + if (!buffer) + { + ret = -EINVAL; + goto _err; + } + if (len == 0) + { + ret = 0; + goto _err; + } + + /* GD_ReadBuffer returns copied data size or negative error code */ + + ret = GD_ReadBuffer(CXD56_CPU1_DEV_GEOFENCE, 0, buffer, len); + +_err: + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofence_ioctl + * + * Description: + * Standard character driver ioctl method. + * + * Input Parameters: + * filep - File structure pointer + * fds - Array of file descriptor + * setup - 1 if start poll, 0 if stop poll + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_ioctl(FAR struct file *filep, int cmd, + unsigned long arg) +{ + if (cmd <= CXD56_GEOFENCE_IOCTL_INVAL || cmd >= CXD56_GEOFENCE_IOCTL_MAX) + { + return -EINVAL; + } + + return g_cmdlist[cmd](arg); +} + +/**************************************************************************** + * Name: cxd56_geofence_poll + * + * Description: + * Standard character driver poll method. + * + * Input Parameters: + * filep - File structure pointer + * fds - array of file descriptor + * setup - 1 if start poll, 0 if stop poll + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_POLL +static int cxd56_geofence_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup) +{ + FAR struct inode * inode; + FAR struct cxd56_geofence_dev_s *priv; + int ret = OK; + int i; + + inode = filep->f_inode; + priv = (FAR struct cxd56_geofence_dev_s *)inode->i_private; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + if (setup) + { + if ((fds->events & POLLIN) == 0) + { + ret = -EDEADLK; + goto errout; + } + + for (i = 0; i < CONFIG_GEOFENCE_NPOLLWAITERS; i++) + { + /* Find an unused slot */ + + if (priv->fds[i] == NULL) + { + /* Bind the poll structure and this slot */ + + priv->fds[i] = fds; + fds->priv = &priv->fds[i]; + GD_SetNotifyMask(CXD56_CPU1_DEV_GEOFENCE, FALSE); + break; + } + } + + /* No space in priv fds array for poll handling */ + + if (i >= CONFIG_GEOFENCE_NPOLLWAITERS) + { + fds->priv = NULL; + ret = -EBUSY; + goto errout; + } + } + else if (fds->priv) + { + /* This is a request to tear down the poll. */ + + struct pollfd **slot = (struct pollfd **)fds->priv; + + /* Remove all memory of the poll setup */ + + *slot = NULL; + fds->priv = NULL; + } + +errout: + sem_post(&priv->devsem); + return ret; +} +#endif + +/**************************************************************************** + * Name: cxd56_geofence_register + * + * Description: + * Register the GEOFENCE character device as 'devpath' + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/geofence" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_geofence_register(FAR const char *devpath) +{ + FAR struct cxd56_geofence_dev_s *priv; + int ret; + + priv = (FAR struct cxd56_geofence_dev_s *)kmm_malloc( + sizeof(struct cxd56_geofence_dev_s)); + if (!priv) + { + gnsserr("Failed to allocate instance\n"); + return -ENOMEM; + } + + memset(priv, 0, sizeof(struct cxd56_geofence_dev_s)); + sem_init(&priv->devsem, 0, 1); + + ret = cxd56_geofence_initialize(priv); + if (ret < 0) + { + gnsserr("Failed to initialize geofence device!\n"); + goto _err0; + } + + ret = register_driver(devpath, &g_geofencefops, 0666, priv); + if (ret < 0) + { + gnsserr("Failed to register driver: %d\n", ret); + goto _err0; + } + + ret = cxd56_cpu1siginit(CXD56_CPU1_DEV_GEOFENCE, priv); + if (ret < 0) + { + gnsserr("Failed to initialize ICC for GPS CPU: %d\n", ret); + goto _err2; + } + + cxd56_cpu1sigregisterhandler(CXD56_CPU1_DEV_GEOFENCE, + cxd56_geofence_sighandler); + + gnssinfo("GEOFENCE driver loaded successfully!\n"); + + return ret; + +_err2: + unregister_driver(devpath); +_err0: + kmm_free(priv); + return ret; +} + +/**************************************************************************** + * Name: cxd56_geofenceinitialize + * + * Description: + * Initialize GEOFENCE device + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/geofence" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int cxd56_geofenceinitialize(FAR const char *devpath) +{ + int ret; + + gnssinfo("Initializing GEOFENCE..\n"); + + ret = cxd56_geofence_register(devpath); + if (ret < 0) + { + gnsserr("Error registering GEOFENCE\n"); + } + + return ret; +} + +#endif diff --git a/arch/arm/src/cxd56xx/cxd56_geofence.h b/arch/arm/src/cxd56xx/cxd56_geofence.h new file mode 100644 index 00000000000..cb6c764a095 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_geofence.h @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_geofence.h + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GEOFENCE_H +#define __ARCH_ARM_SRC_CXD56XX_CXD56_GEOFENCE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cxd56_geofenceinitialize + * + * Description: + * Initialize GEOFENCE device + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/geofence" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int cxd56_geofenceinitialize(FAR const char *devpath); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GEOFENCE_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_gnss.c b/arch/arm/src/cxd56xx/cxd56_gnss.c new file mode 100644 index 00000000000..a5c809f6d18 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_gnss.c @@ -0,0 +1,2937 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_gnss.c + * + * Copyright 2018,2019 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include "cxd56_gnss_api.h" +#include "cxd56_cpu1signal.h" +#include "cxd56_gnss.h" + +#if defined(CONFIG_CXD56_GNSS) + +/**************************************************************************** + * External Defined Functions + ****************************************************************************/ + +extern int PM_LoadImage(int cpuid, const char* filename); +extern int PM_StartCpu(int cpuid, int wait); +extern int PM_SleepCpu(int cpuid, int mode); + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_CXD56_GNSS_NPOLLWAITERS +# define CONFIG_CXD56_GNSS_NPOLLWAITERS 4 +#endif + +#ifndef CONFIG_CXD56_GNSS_NSIGNALRECEIVERS +# define CONFIG_CXD56_GNSS_NSIGNALRECEIVERS 4 +#endif + +#ifndef CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE +# define CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE 1024 +#endif + +#ifndef CONFIG_CXD56_GNSS_BACKUP_FILENAME +# define CONFIG_CXD56_GNSS_BACKUP_FILENAME "/mnt/spif/gnss_backup.bin" +#endif + +#ifndef CONFIG_CXD56_GNSS_CEP_FILENAME +# define CONFIG_CXD56_GNSS_CEP_FILENAME "/mnt/spif/gnss_cep.bin" +#endif + +#define CXD56_GNSS_GPS_CPUID 1 +#ifdef CONFIG_CXD56_GNSS_FW_RTK +# define CXD56_GNSS_FWNAME "gnssfwrtk" +#else +# define CXD56_GNSS_FWNAME "gnssfw" +#endif +#ifndef PM_SLEEP_MODE_COLD +# define PM_SLEEP_MODE_COLD 2 +#endif +#ifndef PM_SLEEP_MODE_HOT_ENABLE +# define PM_SLEEP_MODE_HOT_ENABLE 7 +#endif +#ifndef PM_SLEEP_MODE_HOT_DISABLE +# define PM_SLEEP_MODE_HOT_DISABLE 8 +#endif + +/* Notify data of PUBLISH_TYPE_GNSS */ + +#define CXD56_GNSS_NOTIFY_TYPE_POSITION 0 +#define CXD56_GNSS_NOTIFY_TYPE_BOOTCOMP 1 +#define CXD56_GNSS_NOTIFY_TYPE_REQBKUPDAT 2 +#define CXD56_GNSS_NOTIFY_TYPE_REQCEPOPEN 3 +#define CXD56_GNSS_NOTIFY_TYPE_REQCEPCLOSE 4 +#define CXD56_GNSS_NOTIFY_TYPE_REQCEPDAT 5 +#define CXD56_GNSS_NOTIFY_TYPE_REQCEPBUFFREE 6 + +/* GNSS core CPU FIFO interface API */ + +#define CXD56_GNSS_GD_GNSS_START 0 +#define CXD56_GNSS_GD_GNSS_STOP 1 +#define CXD56_GNSS_GD_GNSS_CEPINITASSISTDATA 2 + +/* CPU FIFO API bitfield converter */ + +#define CXD56_GNSS_CPUFIFOAPI_SET_DATA(API, DATA) (((DATA) << 8) | (API)) + +/* Common info shared with GNSS core */ + +#define GNSS_SHARED_INFO_MAX_ARGC 6 + +/* GDSP File read/write arguments */ + +#define GNSS_ARGS_FILE_OFFSET 0 +#define GNSS_ARGS_FILE_BUF 1 +#define GNSS_ARGS_FILE_LENGTH 2 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_SIGNAL +struct cxd56_gnss_sig_s +{ + uint8_t enable; + int pid; + FAR struct cxd56_gnss_signal_info_s info; +}; +#endif + +struct cxd56_gnss_shared_info_s +{ + int retval; + uint32_t argc; + uint32_t argv[GNSS_SHARED_INFO_MAX_ARGC]; +}; + +struct cxd56_gnss_dev_s +{ + sem_t devsem; + sem_t syncsem; + uint8_t num_open; + uint8_t notify_data; + FAR FILE * cepfp; + FAR void * cepbuf; + FAR struct pollfd *fds[CONFIG_CXD56_GNSS_NPOLLWAITERS]; +#if !defined(CONFIG_DISABLE_SIGNAL) && \ + (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) + struct cxd56_gnss_sig_s sigs[CONFIG_CXD56_GNSS_NSIGNALRECEIVERS]; +#endif + struct cxd56_gnss_shared_info_s shared_info; + sem_t ioctllock; + sem_t apiwait; + int apiret; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* ioctl command functions */ + +static int cxd56_gnss_start(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_stop(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_select_satellite_system(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_satellite_system(FAR struct file *filep, + unsigned long arg); +static int +cxd56_gnss_set_receiver_position_ellipsoidal(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_receiver_position_orthogonal(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_ope_mode(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_get_ope_mode(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_set_tcxo_offset(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_tcxo_offset(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_time(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_get_almanac(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_set_almanac(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_get_ephemeris(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_ephemeris(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_save_backup_data(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_erase_backup_data(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_open_cep_data(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_close_cep_data(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_check_cep_data(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_cep_age(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_reset_cep_flag(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_acquist_data(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_frametime(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_tau_gps(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_set_time_gps(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_clear_receiver_info(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_tow_assist(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_utc_model(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_control_spectrum(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_start_test(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_stop_test(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_get_test_result(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_start_pvtlog(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_stop_pvtlog(FAR struct file *filep, unsigned long arg); +static int cxd56_gnss_delete_pvtlog(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_pvtlog_status(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_start_rtk_output(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_stop_rtk_output(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_rtk_interval(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_rtk_interval(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_select_rtk_satellite(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_rtk_satellite(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_rtk_ephemeris_enable(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_rtk_ephemeris_enable(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_start_navmsg_output(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_get_var_ephemeris(FAR struct file *filep, + unsigned long arg); +static int cxd56_gnss_set_var_ephemeris(FAR struct file *filep, + unsigned long arg); + +/* file operation functions */ + +static int cxd56_gnss_open(FAR struct file *filep); +static int cxd56_gnss_close(FAR struct file *filep); +static ssize_t cxd56_gnss_read(FAR struct file *filep, FAR char *buffer, + size_t len); +static ssize_t cxd56_gnss_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); +static int cxd56_gnss_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +#ifndef CONFIG_DISABLE_POLL +static int cxd56_gnss_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup); +#endif +static int8_t cxd56_gnss_select_notifytype(off_t fpos, uint32_t *offset); + +static int cxd56_gnss_cpufifo_api(FAR struct file *filep, unsigned int api, + unsigned int data); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This the vtable that supports the character driver interface */ + +static const struct file_operations g_gnssfops = +{ + cxd56_gnss_open, /* open */ + cxd56_gnss_close, /* close */ + cxd56_gnss_read, /* read */ + cxd56_gnss_write, /* write */ + 0, /* seek */ + cxd56_gnss_ioctl, /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + cxd56_gnss_poll, /* poll */ +#endif +}; + +/* GNSS ioctl command list */ + +static int (*g_cmdlist[CXD56_GNSS_IOCTL_MAX])(FAR struct file *filep, + unsigned long arg) = +{ + NULL, /* CXD56_GNSS_IOCTL_INVAL = 0 */ + cxd56_gnss_start, + cxd56_gnss_stop, + cxd56_gnss_select_satellite_system, + cxd56_gnss_get_satellite_system, + cxd56_gnss_set_receiver_position_ellipsoidal, + cxd56_gnss_set_receiver_position_orthogonal, + cxd56_gnss_set_ope_mode, + cxd56_gnss_get_ope_mode, + cxd56_gnss_set_tcxo_offset, + cxd56_gnss_get_tcxo_offset, + cxd56_gnss_set_time, + cxd56_gnss_get_almanac, + cxd56_gnss_set_almanac, + cxd56_gnss_get_ephemeris, + cxd56_gnss_set_ephemeris, + cxd56_gnss_save_backup_data, + cxd56_gnss_erase_backup_data, + cxd56_gnss_open_cep_data, + cxd56_gnss_close_cep_data, + cxd56_gnss_check_cep_data, + cxd56_gnss_get_cep_age, + cxd56_gnss_reset_cep_flag, + cxd56_gnss_start_rtk_output, + cxd56_gnss_stop_rtk_output, + cxd56_gnss_set_rtk_interval, + cxd56_gnss_get_rtk_interval, + cxd56_gnss_select_rtk_satellite, + cxd56_gnss_get_rtk_satellite, + cxd56_gnss_set_rtk_ephemeris_enable, + cxd56_gnss_get_rtk_ephemeris_enable, + cxd56_gnss_set_acquist_data, + cxd56_gnss_set_frametime, + cxd56_gnss_set_tau_gps, + cxd56_gnss_set_time_gps, + cxd56_gnss_clear_receiver_info, + cxd56_gnss_set_tow_assist, + cxd56_gnss_set_utc_model, + cxd56_gnss_control_spectrum, + cxd56_gnss_start_test, + cxd56_gnss_stop_test, + cxd56_gnss_get_test_result, + cxd56_gnss_set_signal, + cxd56_gnss_start_pvtlog, + cxd56_gnss_stop_pvtlog, + cxd56_gnss_delete_pvtlog, + cxd56_gnss_get_pvtlog_status, + cxd56_gnss_start_navmsg_output, + cxd56_gnss_set_var_ephemeris, + cxd56_gnss_get_var_ephemeris, + + /* max CXD56_GNSS_IOCTL_MAX */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IOCTL private functions */ + +/**************************************************************************** + * Name: cxd56_gnss_start + * + * Description: + * Process CXD56_GNSS_IOCTL_START command. + * Start a positioning + * begining to search the satellites and measure the receiver position + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_start(FAR struct file *filep, unsigned long arg) +{ + int ret; + int retry = 50; + uint8_t start_mode = (uint8_t)arg; + + ret = board_lna_power_control(true); + if (ret < 0) + { + return ret; + } + + while (!g_rtc_enabled && 0 < retry--) + { + /* GNSS requires stable RTC */ + + usleep(100 * 1000); + } + + ret = cxd56_gnss_cpufifo_api(filep, CXD56_GNSS_GD_GNSS_START, + start_mode); + if (ret < 0) + { + board_lna_power_control(false); + } + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_stop + * + * Description: + * Process CXD56_GNSS_IOCTL_STOP command. + * Stop a positioning. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_stop(FAR struct file *filep, unsigned long arg) +{ + int ret; + + ret = cxd56_gnss_cpufifo_api(filep, CXD56_GNSS_GD_GNSS_STOP, 0); + board_lna_power_control(false); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_get_satellite_system + * + * Description: + * Process CXD56_GNSS_IOCTL_SELECT_SATELLITE_SYSTEM command. + * Select GNSSs to positioning + * These are able to specified by CXD56_GNSS_B_SAT_XXX defines. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_select_satellite_system(FAR struct file *filep, + unsigned long arg) +{ + uint32_t system = (uint32_t)arg; + + return GD_SelectSatelliteSystem(system); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_satellite_system + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_SATELLITE_SYSTEM command. + * Get current using GNSSs to positioning + * A argument 'satellite' indicates current GNSSs by bit fields defined by + * CXD56_GNSS_B_SAT_XXX. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_satellite_system(FAR struct file *filep, + unsigned long arg) +{ + int ret; + uint32_t system; + + if (!arg) + { + return -EINVAL; + } + + ret = GD_GetSatelliteSystem(&system); + *(uint32_t *)arg = system; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_set_receiver_position_ellipsoidal + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_RECEIVER_POSITION_ELLIPSOIDAL command. + * Set the rough receiver position + * arg = { double lat, double lon, double height } + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int +cxd56_gnss_set_receiver_position_ellipsoidal(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_ellipsoidal_position_s *pos; + + if (!arg) + { + return -EINVAL; + } + + pos = (FAR struct cxd56_gnss_ellipsoidal_position_s *)arg; + + return GD_SetReceiverPositionEllipsoidal(&pos->latitude, &pos->longitude, + &pos->altitude); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_receiver_position_orthogonal + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_RECEIVER_POSITION_ORTHOGONAL command. + * Set the rough receiver position as orgothonal + * arg = { int32_t x, int32_t y, int32_t z } + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_receiver_position_orthogonal(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_orthogonal_position_s *pos; + + if (!arg) + { + return -EINVAL; + } + + pos = (FAR struct cxd56_gnss_orthogonal_position_s *)arg; + return GD_SetReceiverPositionOrthogonal(pos->x, pos->y, pos->z); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_ope_mode + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_OPE_MODE command. + * Set GNSS operation mode. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_ope_mode(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_ope_mode_param_s *ope_mode; + if (!arg) + { + return -EINVAL; + } + + ope_mode = (FAR struct cxd56_gnss_ope_mode_param_s *)arg; + + return GD_SetOperationMode(ope_mode->mode, ope_mode->cycle); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_ope_mode + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_OPE_MODE command. + * Set the TCXO offset + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_ope_mode(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_ope_mode_param_s *ope_mode; + if (!arg) + { + return -EINVAL; + } + + ope_mode = (FAR struct cxd56_gnss_ope_mode_param_s *)arg; + + return GD_GetOperationMode(&ope_mode->mode, &ope_mode->cycle); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_tcxo_offset + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_TCXO_OFFSET command. + * Set the TCXO offset + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_tcxo_offset(FAR struct file *filep, + unsigned long arg) +{ + int32_t offset = (int32_t)arg; + + return GD_SetTcxoOffset(offset); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_tcxo_offset + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_TCXO_OFFSET command. + * Get the TCXO offset + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_tcxo_offset(FAR struct file *filep, + unsigned long arg) +{ + int ret; + int32_t offset; + + if (!arg) + { + return -EINVAL; + } + + ret = GD_GetTcxoOffset(&offset); + *(uint32_t *)arg = offset; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_set_time + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_TIME command. + * Set the estimated current time of the receiver. + * 1st argument date & time are in UTC. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_time(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_datetime_s *date_time; + + if (!arg) + { + return -EINVAL; + } + + date_time = (FAR struct cxd56_gnss_datetime_s *)arg; + + return GD_SetTime(&date_time->date, &date_time->time); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_almanac + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_ALMANAC command. + * Get the almanac data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_almanac(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_orbital_param_s *param; + uint32_t almanac_size; + + if (!arg) + { + return -EINVAL; + } + + param = (FAR struct cxd56_gnss_orbital_param_s *)arg; + + return GD_GetAlmanac(param->type, param->data, &almanac_size); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_almanac + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_ALMANAC command. + * Set the almanac data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_almanac(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_orbital_param_s *param; + + if (!arg) + { + return -EINVAL; + } + + param = (FAR struct cxd56_gnss_orbital_param_s *)arg; + + return GD_SetAlmanac(param->type, param->data); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_ephemeris + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_EPHEMERIS command. + * Get the Ephemeris data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_ephemeris(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_orbital_param_s *param; + uint32_t ephemeris_size; + + if (!arg) + { + return -EINVAL; + } + + param = (FAR struct cxd56_gnss_orbital_param_s *)arg; + + return GD_GetEphemeris(param->type, param->data, &ephemeris_size); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_ephemeris + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_EPHEMERIS command. + * Set the Ephemeris data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_ephemeris(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_orbital_param_s *param; + + if (!arg) + { + return -EINVAL; + } + + param = (FAR struct cxd56_gnss_orbital_param_s *)arg; + + return GD_SetEphemeris(param->type, param->data); +} + +/**************************************************************************** + * Name: cxd56_gnss_save_backup_data + * + * Description: + * Process CXD56_GNSS_IOCTL_SAVE_BACKUP_DATA command. + * Save the backup data to a Flash memory. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_save_backup_data(FAR struct file *filep, + unsigned long arg) +{ + FAR char *buf; + FAR FILE *fp; + int n = 0; + int32_t offset = 0; + + buf = (char *)malloc(CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE); + if (buf == NULL) + { + return -ENOMEM; + } + + fp = fopen(CONFIG_CXD56_GNSS_BACKUP_FILENAME, "wb"); + if (fp == NULL) + { + free(buf); + return -ENOENT; + } + + do + { + n = GD_ReadBuffer(CXD56_CPU1_DATA_TYPE_BACKUP, offset, buf, + CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE); + if (n <= 0) + { + break; + } + n = fwrite(buf, 1, n, fp); + offset += n; + } + while (n == CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE); + + free(buf); + fclose(fp); + + return n < 0 ? n : 0; +} + +/**************************************************************************** + * Name: cxd56_gnss_erase_backup_data + * + * Description: + * Process CXD56_GNSS_IOCTL_ERASE_BACKUP_DATA command. + * Erase the backup data on a Flash memory. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_erase_backup_data(FAR struct file *filep, + unsigned long arg) +{ + return unlink(CONFIG_CXD56_GNSS_BACKUP_FILENAME); +} + +/**************************************************************************** + * Name: cxd56_gnss_open_cep_data + * + * Description: + * Process CXD56_GNSS_IOCTL_OPEN_CEP_DATA command. + * Open CEP data file + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_open_cep_data(FAR struct file *filep, unsigned long arg) +{ + return cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CEPFILE, TRUE); +} + +/**************************************************************************** + * Name: cxd56_gnss_close_cep_data + * + * Description: + * Process CXD56_GNSS_IOCTL_CLOSE_CEP_DATA command. + * Close CEP data file + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_close_cep_data(FAR struct file *filep, + unsigned long arg) +{ + return cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CEPFILE, FALSE); +} + +/**************************************************************************** + * Name: cxd56_gnss_check_cep_data + * + * Description: + * Process CXD56_GNSS_IOCTL_CHECK_CEP_DATA command. + * Check CEP data valid + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_check_cep_data(FAR struct file *filep, + unsigned long arg) +{ + return GD_CepCheckAssistData(); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_cep_age + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_CEP_AGE command. + * Get CEP valid term + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_cep_age(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_cep_age_s *age; + + if (!arg) + { + return -EINVAL; + } + + age = (FAR struct cxd56_gnss_cep_age_s *)arg; + + return GD_CepGetAgeData(&age->age, &age->cepi); +} + +/**************************************************************************** + * Name: cxd56_gnss_reset_cep_flag + * + * Description: + * Process CXD56_GNSS_IOCTL_RESET_CEP_FLAG command. + * Reset CEP data init flag & valid flag + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_reset_cep_flag(FAR struct file *filep, + unsigned long arg) +{ + return cxd56_gnss_cpufifo_api(filep, + CXD56_GNSS_GD_GNSS_CEPINITASSISTDATA, 0); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_acquist_data + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_SET_ACQUIST command. + * AGPS set acquist data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_acquist_data(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_agps_acquist_s *acquist; + + if (!arg) + { + return -EINVAL; + } + + acquist = (FAR struct cxd56_gnss_agps_acquist_s *)arg; + + return GD_SetAcquist(acquist->data, acquist->size); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_frametime + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_SET_FRAMETIME command. + * AGPS set frame time + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_frametime(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_agps_frametime_s *frametime; + + if (!arg) + { + return -EINVAL; + } + + frametime = (FAR struct cxd56_gnss_agps_frametime_s *)arg; + + return GD_SetFrameTime(frametime->sec, frametime->frac); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_tau_gps + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_SET_TAU_GPS command. + * AGPS set TAU GPS + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_tau_gps(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_agps_tau_gps_s *taugpstime; + + if (!arg) + { + return -EINVAL; + } + + taugpstime = (FAR struct cxd56_gnss_agps_tau_gps_s *)arg; + + return GD_SetTauGps(&taugpstime->taugps); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_time_gps + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_SET_TIME_GPS command. + * Set high precision receiver time + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_time_gps(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_agps_time_gps_s *time_gps; + + if (!arg) + { + return -EINVAL; + } + + time_gps = (FAR struct cxd56_gnss_agps_time_gps_s *)arg; + + return GD_SetTimeGps(&time_gps->date, &time_gps->time); +} + +/**************************************************************************** + * Name: cxd56_gnss_clear_receiver_info + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_CLEAR_RECEIVER_INFO command. + * Clear info(s) for hot start such as ephemeris. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_clear_receiver_info(FAR struct file *filep, + unsigned long arg) +{ + uint32_t clear_type = arg; + + return GD_ClearReceiverInfo(clear_type); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_tow_assist + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_SET_TOW_ASSIST command. + * AGPS set acquist data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_tow_assist(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_agps_tow_assist_s *assist; + + if (!arg) + { + return -EINVAL; + } + + assist = (FAR struct cxd56_gnss_agps_tow_assist_s *)arg; + + return GD_SetTowAssist(assist->data, assist->size); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_utc_model + * + * Description: + * Process CXD56_GNSS_IOCTL_AGPS_SET_UTC_MODEL command. + * AGPS set UTC model + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_utc_model(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_gnss_agps_utc_model_s *model; + + if (!arg) + { + return -EINVAL; + } + + model = (FAR struct cxd56_gnss_agps_utc_model_s *)arg; + + return GD_SetUtcModel(model->data, model->size); +} + +/**************************************************************************** + * Name: cxd56_gnss_control_spectrum + * + * Description: + * Process CXD56_GNSS_IOCTL_SPECTRUM_CONTROL command. + * Enable or not to output spectrum data of GNSS signal + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_control_spectrum(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_spectrum_control_s *control; + + if (!arg) + { + return -EINVAL; + } + + control = (FAR struct cxd56_gnss_spectrum_control_s *)arg; + + return GD_SpectrumControl(control->time, control->enable, control->point1, + control->step1, control->point2, control->step2); +} + +/**************************************************************************** + * Name: cxd56_gnss_start_test + * + * Description: + * Process CXD56_GNSS_IOCTL_FACTORY_START_TEST command. + * Start GPS factory test + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_start_test(FAR struct file *filep, unsigned long arg) +{ + int ret; + int retry = 50; + FAR struct cxd56_gnss_test_info_s *info; + + /* check argument */ + + if (!arg) + { + ret = -EINVAL; + } + else + { + /* Power on the LNA device */ + + ret = board_lna_power_control(true); + if (ret < 0) + { + return ret; + } + + while (!g_rtc_enabled && 0 < retry--) + { + /* GNSS requires stable RTC */ + + usleep(100 * 1000); + } + + /* set parameter */ + + info = (FAR struct cxd56_gnss_test_info_s *)arg; + GD_StartGpsTest(info->satellite, info->reserve1, + info->reserve2, info->reserve3); + + /* start test */ + + ret = GD_Start(CXD56_GNSS_STMOD_COLD); + } + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_stop_test + * + * Description: + * Process CXD56_GNSS_IOCTL_FACTORY_STOP_TEST command. + * Stop GPS factory test + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_stop_test(FAR struct file *filep, unsigned long arg) +{ + int ret; + + /* term test */ + + ret = GD_StopGpsTest(); + if(ret == OK) + { + /* stop test */ + + ret = GD_Stop(); + } + + /* Power off the LNA device */ + + board_lna_power_control(false); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_get_test_result + * + * Description: + * Process CXD56_GNSS_IOCTL_FACTORY_GET_TEST_RESULT command. + * Get GPS factory test result + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_test_result(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_test_result_s *result; + + if (!arg) + { + return -EINVAL; + } + + result = (FAR struct cxd56_gnss_test_result_s *)arg; + + return GD_GetGpsTestResult(&result->cn, &result->doppler); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_signal + * + * Description: + * Process CXD56_GNSS_IOCTL_SIGNAL_SET command. + * Set signal information for synchronous reading data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg) +{ + int ret = 0; + +#if !defined(CONFIG_DISABLE_SIGNAL) && \ + (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) + FAR struct inode *inode; + FAR struct cxd56_gnss_dev_s *priv; + FAR struct cxd56_gnss_signal_setting_s *setting; + FAR struct cxd56_gnss_sig_s *sig; + FAR struct cxd56_gnss_sig_s *checksig; + int pid; + int i; + + if (!arg) + { + return -EINVAL; + } + + setting = (FAR struct cxd56_gnss_signal_setting_s *)arg; + if (setting->gnsssig >= CXD56_CPU1_DATA_TYPE_MAX) + { + return -EPROTOTYPE; + } + + inode = filep->f_inode; + priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + sig = NULL; + pid = getpid(); + for (i = 0; i < CONFIG_CXD56_GNSS_NSIGNALRECEIVERS; i++) + { + checksig = &priv->sigs[i]; + if (setting->enable) + { + if (sig == NULL && !checksig->enable) + { + sig = checksig; + } + else if (checksig->info.gnsssig == setting->gnsssig && + checksig->pid == pid) + { + sig = checksig; + break; + } + } + else if (checksig->info.gnsssig == setting->gnsssig && + checksig->pid == pid) + { + checksig->enable = 0; + goto _success; + } + } + if (sig == NULL) + { + ret = -ENOENT; + goto _err; + } + + GD_SetNotifyMask(setting->gnsssig, FALSE); + + sig->enable = 1; + sig->pid = pid; + sig->info.fd = setting->fd; + sig->info.gnsssig = setting->gnsssig; + sig->info.signo = setting->signo; + sig->info.data = setting->data; + +_success: +_err: + sem_post(&priv->devsem); +#endif /* if !defined(CONFIG_DISABLE_SIGNAL) && \ + (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) */ + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_start_pvtlog + * + * Description: + * Process CXD56_GNSS_IOCTL_PVTLOG_START command. + * Start saving PVT logs. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_start_pvtlog(FAR struct file *filep, unsigned long arg) +{ + FAR struct cxd56_pvtlog_setting_s *setting; + + if (!arg) + { + return -EINVAL; + } + + setting = (FAR struct cxd56_pvtlog_setting_s *)arg; + + return GD_RegisterPvtlog(setting->cycle, setting->threshold); +} + +/**************************************************************************** + * Name: cxd56_gnss_stop_pvtlog + * + * Description: + * Process CXD56_GNSS_IOCTL_PVTLOG_STOP command. + * Stop saving PVT logs. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_stop_pvtlog(FAR struct file *filep, unsigned long arg) +{ + return GD_ReleasePvtlog(); +} + +/**************************************************************************** + * Name: cxd56_gnss_delete_pvtlog + * + * Description: + * Process CXD56_GNSS_IOCTL_PVTLOG_STOP command. + * Delete stored PVT logs. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_delete_pvtlog(FAR struct file *filep, unsigned long arg) +{ + return GD_PvtlogDeleteLog(); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_pvtlog_status + * + * Description: + * Process CXD56_GNSS_IOCTL_PVTLOG_GET_STATUS command. + * Get stored log status of PVTLOG. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_pvtlog_status(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_pvtlog_status_s *status; + + if (!arg) + { + return -EINVAL; + } + + status = (FAR struct cxd56_pvtlog_status_s *)arg; + + return GD_PvtlogGetLogStatus(&status->status); +} + +/**************************************************************************** + * Name: cxd56_gnss_start_rtk_output + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_START command. + * Start RTK data output + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_start_rtk_output(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_rtk_setting_s *setting; + + if (!arg) + { + return -EINVAL; + } + + setting = (FAR struct cxd56_rtk_setting_s *)arg; + setting->sbasout = 0; + + return GD_RtkStart(setting); +} + +/**************************************************************************** + * Name: cxd56_gnss_stop_rtk_output + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_STOP command. + * Stop RTK data output + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_stop_rtk_output(FAR struct file *filep, + unsigned long arg) +{ + return GD_RtkStop(); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_rtk_interval + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_SET_INTERVAL command. + * Set RTK data output interval + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_rtk_interval(FAR struct file *filep, + unsigned long arg) +{ + int interval = (int)arg; + + return GD_RtkSetOutputInterval(interval); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_rtk_interval + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_GET_INTERVAL command. + * Get RTK data output interval setting + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_rtk_interval(FAR struct file *filep, + unsigned long arg) +{ + int ret; + int interval; + + if (!arg) + { + return -EINVAL; + } + + ret = GD_RtkGetOutputInterval(&interval); + *(uint32_t *)arg = interval; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_select_rtk_satellite + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_SELECT_SATELLITE_SYSTEM command. + * Select RTK satellite type + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_select_rtk_satellite(FAR struct file *filep, + unsigned long arg) +{ + uint32_t gnss = (uint32_t)arg; + + return GD_RtkSetGnss(gnss); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_rtk_ephemeris_enable + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_GET_SATELLITE_SYSTEM command. + * Get RTK satellite type setting + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_rtk_satellite(FAR struct file *filep, + unsigned long arg) +{ + int ret; + uint32_t gnss; + + if (!arg) + { + return -EINVAL; + } + + ret = GD_RtkGetGnss(&gnss); + *(uint32_t *)arg = gnss; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_get_rtk_ephemeris_enable + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_SET_EPHEMERIS_ENABLER command. + * Set RTK ephemeris notify enable setting + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_rtk_ephemeris_enable(FAR struct file *filep, + unsigned long arg) +{ + int enable = (int)arg; + + return GD_RtkSetEphNotify(enable); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_rtk_ephemeris_enable + * + * Description: + * Process CXD56_GNSS_IOCTL_RTK_GET_EPHEMERIS_ENABLER command. + * Get RTK ephemeris notify enable setting. + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_rtk_ephemeris_enable(FAR struct file *filep, + unsigned long arg) +{ + int ret; + int enable; + + if (!arg) + { + return -EINVAL; + } + + ret = GD_RtkGetEphNotify(&enable); + *(uint32_t *)arg = enable; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_start_navmsg_output + * + * Description: + * Process CXD56_GNSS_IOCTL_NAVMSG_START command. + * Start NAVMSG data output + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_start_navmsg_output(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_rtk_setting_s *setting; + + if (!arg) + { + return -EINVAL; + } + + setting = (FAR struct cxd56_rtk_setting_s *)arg; + + return GD_RtkStart(setting); +} + +/**************************************************************************** + * Name: cxd56_gnss_set_var_ephemeris + * + * Description: + * Process CXD56_GNSS_IOCTL_SET_VAR_EPHEMERIS command. + * Set the Ephemeris data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_set_var_ephemeris(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_set_var_ephemeris_s *param; + + if (!arg) + { + return -EINVAL; + } + param = (FAR struct cxd56_gnss_set_var_ephemeris_s *)arg; + + return GD_SetVarEphemeris(param->data, param->size); +} + +/**************************************************************************** + * Name: cxd56_gnss_get_var_ephemeris + * + * Description: + * Process CXD56_GNSS_IOCTL_GET_VAR_EPHEMERIS command. + * Get the Ephemeris data + * + * Input Parameters: + * filep - File structure pointer + * arg - Data for command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_get_var_ephemeris(FAR struct file *filep, + unsigned long arg) +{ + FAR struct cxd56_gnss_get_var_ephemeris_s *param; + + if (!arg) + { + return -EINVAL; + } + + param = (FAR struct cxd56_gnss_get_var_ephemeris_s *)arg; + + return GD_GetVarEphemeris(param->type, param->data, param->size); +} + +/* Synchronized with processes and CPUs + * CXD56_GNSS signal handler and utils + */ + +/**************************************************************************** + * Name: cxd56_gnss_wait_notify + * + * Description: + * Wait notify from GNSS CPU with timeout. + * + * Input Parameters: + * sem - Semaphore for waiting + * waitset - Wait time in seconds + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_wait_notify(FAR sem_t *sem, time_t waitsec) +{ + int ret; + struct timespec timeout; + + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + return ret; + } + + timeout.tv_sec += waitsec; /* seconds timeout for wait */ + + return sem_timedwait(sem, &timeout); +} + +/**************************************************************************** + * Name: cxd56_gnss_read_cep_file + * + * Description: + * Read a CEP data packet from file and notify to GNSS CPU. + * + * Input Parameters: + * fp - File pointer + * offset - File offset of last read + * len - packet size to read + * retval - Status to read file + * + * Returned Value: + * Buffer address allocated in this function for reading data. + * + ****************************************************************************/ + +static FAR char *cxd56_gnss_read_cep_file(FAR FILE *fp, int32_t offset, + size_t len, FAR int *retval) +{ + FAR char *buf; + size_t n = 0; + int ret; + + if (fp == NULL) + { + ret = -ENOENT; + goto _err0; + } + + buf = (char *)malloc(len); + if (buf == NULL) + { + ret = -ENOMEM; + goto _err0; + } + + ret = fseek(fp, offset, SEEK_SET); + if (ret < 0) + { + goto _err1; + } + + n = fread(buf, 1, len, fp); + if (n <= 0) + { + ret = n < 0 ? n : ferror(fp) ? -errno : 0; + clearerr(fp); + goto _err1; + } + + *retval = n; + cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CEP, (uint32_t)buf); + + return buf; + + /* send signal to CPU1 in error for just notify completion of read sequence */ + +_err1: + free(buf); +_err0: + *retval = ret; + cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CEP, 0); + + return NULL; +} + +/**************************************************************************** + * Name: cxd56_gnss_read_backup_file + * + * Description: + * Read a backup data packet from file and notify to GNSS CPU. + * + * Input Parameters: + * retval - Status to read file + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void cxd56_gnss_read_backup_file(FAR int *retval) +{ + FAR char * buf; + FAR FILE * fp; + int32_t offset = 0; + size_t n; + int ret = 0; + + buf = (char *)malloc(CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE); + if (buf == NULL) + { + ret = -ENOMEM; + goto _err; + } + + fp = fopen(CONFIG_CXD56_GNSS_BACKUP_FILENAME, "rb"); + if (fp == NULL) + { + free(buf); + ret = -ENOENT; + goto _err; + } + + do + { + n = fread(buf, 1, CONFIG_CXD56_GNSS_BACKUP_BUFFER_SIZE, fp); + if (n <= 0) + { + ret = n < 0 ? n : ferror(fp) ? -ENFILE : 0; + break; + } + ret = GD_WriteBuffer(CXD56_CPU1_DATA_TYPE_BACKUP, offset, buf, n); + if (ret < 0) + { + break; + } + offset += n; + } + while (n > 0); + + fclose(fp); + free(buf); + + /* Notify the termination of backup sequence by write zero length data */ + +_err: + *retval = ret; + cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_BKUPFILE, 0); +} + +#if !defined(CONFIG_DISABLE_SIGNAL) && \ + (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) + +/**************************************************************************** + * Name: cxd56_gnss_common_signalhandler + * + * Description: + * Common signal handler from GNSS CPU. + * + * Input Parameters: + * data - Received data from GNSS CPU + * userdata - User data, this is the device information specified by the + * second argument of the function cxd56_cpu1siginit. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata) +{ + FAR struct cxd56_gnss_dev_s *priv = (FAR struct cxd56_gnss_dev_s *)userdata; + uint8_t sigtype = CXD56_CPU1_GET_DEV(data); + int issetmask = 0; + int i; + int ret; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return; + } + + for (i = 0; i < CONFIG_CXD56_GNSS_NSIGNALRECEIVERS; i++) + { + struct cxd56_gnss_sig_s *sig = &priv->sigs[i]; + if (sig->enable && sig->info.gnsssig == sigtype) + { +#ifdef CONFIG_CAN_PASS_STRUCTS + union sigval value; + value.sival_ptr = &sig->info; + (void)sigqueue(sig->pid, sig->info.signo, value); +#else + (void)sigqueue(sig->pid, sig->info.signo, &sig->info); +#endif + issetmask = 1; + } + } + + if (issetmask) + { + GD_SetNotifyMask(sigtype, FALSE); + } + + sem_post(&priv->devsem); +} + +#endif /* if !defined(CONFIG_DISABLE_SIGNAL) && \ + (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) */ + +/**************************************************************************** + * Name: cxd56_gnss_default_sighandler + * + * Description: + * Handler for GNSS type notification from GNSS CPU for signal and poll. + * + * Input Parameters: + * data - Received data from GNSS CPU + * userdata - User data, this is the device information specified by the + * second argument of the function cxd56_cpu1siginit. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata) +{ + FAR struct cxd56_gnss_dev_s *priv = (FAR struct cxd56_gnss_dev_s *)userdata; + int i; + int ret; + int dtype = CXD56_CPU1_GET_DATA(data); + + switch (dtype) + { + case CXD56_GNSS_NOTIFY_TYPE_REQCEPDAT: + { + priv->cepbuf = cxd56_gnss_read_cep_file( + priv->cepfp, priv->shared_info.argv[GNSS_ARGS_FILE_OFFSET], + priv->shared_info.argv[GNSS_ARGS_FILE_LENGTH], + &priv->shared_info.retval); + return; + } + + case CXD56_GNSS_NOTIFY_TYPE_REQCEPBUFFREE: + if (priv->cepbuf) + { + free(priv->cepbuf); + } + return; + + case CXD56_GNSS_NOTIFY_TYPE_BOOTCOMP: + if (priv->num_open == 0) + { + /* Post to wait-semaphore in cxd56_gnss_open to notify completion + * of GNSS core initialization in first device open. + */ + + priv->notify_data = dtype; + sem_post(&priv->syncsem); + } + return; + + case CXD56_GNSS_NOTIFY_TYPE_REQBKUPDAT: + cxd56_gnss_read_backup_file(&priv->shared_info.retval); + return; + + case CXD56_GNSS_NOTIFY_TYPE_REQCEPOPEN: + if (priv->cepfp != NULL) + { + fclose(priv->cepfp); + } + priv->cepfp = fopen(CONFIG_CXD56_GNSS_CEP_FILENAME, "rb"); + return; + + case CXD56_GNSS_NOTIFY_TYPE_REQCEPCLOSE: + if (priv->cepfp != NULL) + { + fclose(priv->cepfp); + priv->cepfp = NULL; + } + return; + + default: + break; + } + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return; + } + + for (i = 0; i < CONFIG_CXD56_GNSS_NPOLLWAITERS; i++) + { + struct pollfd *fds = priv->fds[i]; + if (fds) + { + fds->revents |= POLLIN; + gnssinfo("Report events: %02x\n", fds->revents); + sem_post(fds->sem); + } + } + + sem_post(&priv->devsem); + +#if !defined(CONFIG_DISABLE_SIGNAL) && \ + (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) + cxd56_gnss_common_signalhandler(data, userdata); +#endif +} + +/**************************************************************************** + * Name: cxd56_gnss_cpufifoapi_signalhandler + * + * Description: + * Handler for API type notification from GNSS CPU. + * + * Input Parameters: + * data - Received data from GNSS CPU + * userdata - User data, this is the device information specified by the + * second argument of the function cxd56_cpu1siginit. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void cxd56_gnss_cpufifoapi_signalhandler(uint32_t data, + FAR void *userdata) +{ + FAR struct cxd56_gnss_dev_s *priv = (FAR struct cxd56_gnss_dev_s *)userdata; + + priv->apiret = CXD56_CPU1_GET_DATA((int)data); + sem_post(&priv->apiwait); + + return; +} + +/**************************************************************************** + * Name: cxd56_gnss_cpufifo_api + * + * Description: + * Send API type event to GNSS CPU. + * + * Input Parameters: + * filep - File structure pointer + * api - Signal type + * data - Any data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_cpufifo_api(FAR struct file *filep, unsigned int api, + unsigned int data) +{ + FAR struct inode *inode; + FAR struct cxd56_gnss_dev_s *priv; + unsigned int type; + int ret = OK; + + inode = filep->f_inode; + priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private; + + type = CXD56_GNSS_CPUFIFOAPI_SET_DATA(api, data); + cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CPUFIFOAPI, type); + + ret = sem_wait(&priv->apiwait); + if (ret < 0) + { + /* If sem_wait returns -EINTR, there is a possibility that the signal + * for GNSS set with CXD56_GNSS_IOCTL_SIGNAL_SET is unmasked + * by SIG_UNMASK in the signal mask. + */ + + ret = -errno; + _warn("Cannot wait GNSS semaphore %d\n", ret); + goto _err; + } + + ret = priv->apiret; + +_err: + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_select_notifytype + * + * Description: + * Decide notify type about data from GNSS device + * + * Input Parameters: + * fpos - file offset indicated about data type + * offset - Actual offset value + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int8_t cxd56_gnss_select_notifytype(off_t fpos, FAR uint32_t *offset) +{ + int8_t type; + + if ((fpos >= CXD56_GNSS_READ_OFFSET_LAST_GNSS) && + (fpos < CXD56_GNSS_READ_OFFSET_AGPS)) + { + type = CXD56_CPU1_DATA_TYPE_GNSS; + *offset = fpos; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_AGPS) + { + type = CXD56_CPU1_DATA_TYPE_AGPS; + *offset = 0; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_RTK) + { + type = CXD56_CPU1_DATA_TYPE_RTK; + *offset = 0; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_GPSEPHEMERIS) + { + type = CXD56_CPU1_DATA_TYPE_GPSEPHEMERIS; + *offset = 0; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_GLNEPHEMERIS) + { + type = CXD56_CPU1_DATA_TYPE_GLNEPHEMERIS; + *offset = 0; + } + else if ((fpos == CXD56_GNSS_READ_OFFSET_SPECTRUM) || + (fpos == CXD56_GNSS_READ_OFFSET_INFO)) + { + type = CXD56_CPU1_DATA_TYPE_SPECTRUM; + *offset = 0; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_PVTLOG) + { + type = CXD56_CPU1_DATA_TYPE_PVTLOG; + *offset = 0; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_SBAS) + { + type = CXD56_CPU1_DATA_TYPE_SBAS; + *offset = 0; + } + else if (fpos == CXD56_GNSS_READ_OFFSET_DCREPORT) + { + type = CXD56_CPU1_DATA_TYPE_DCREPORT; + *offset = 0; + } + else + { + type = -1; + } + + return type; +} + +/**************************************************************************** + * Name: cxd56_gnss_initialize + * + * Description: + * initialize gnss device + * + * Input Parameters: + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + + static int cxd56_gnss_initialize(FAR struct cxd56_gnss_dev_s* dev) +{ + int32_t ret = 0; + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_open + * + * Description: + * Standard character driver open method. + * + * Input Parameters: + * filep - File structure pointer + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_open(FAR struct file *filep) +{ + FAR struct inode * inode; + FAR struct cxd56_gnss_dev_s *priv; + int ret = OK; + + inode = filep->f_inode; + priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + if (priv->num_open == 0) + { + ret = sem_init(&priv->syncsem, 0, 0); + if (ret < 0) + { + goto _err0; + } + + ret = PM_LoadImage(CXD56_GNSS_GPS_CPUID, CXD56_GNSS_FWNAME); + if (ret < 0) + { + goto _err1; + } + ret = PM_StartCpu(CXD56_GNSS_GPS_CPUID, 1); + if (ret < 0) + { + goto _err2; + } + +#ifndef CONFIG_CXD56_GNSS_HOT_SLEEP + PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_HOT_DISABLE); +#endif + + /* Wait the request from GNSS core to restore backup data, + * or for completion of initialization of GNSS core here. + * It is post the semaphore syncsem from cxd56_gnss_default_sighandler. + */ + + ret = cxd56_gnss_wait_notify(&priv->syncsem, 5); + if (ret < 0) + { + goto _err2; + } + + ret = GD_WriteBuffer(CXD56_CPU1_DATA_TYPE_INFO, 0, &priv->shared_info, + sizeof(priv->shared_info)); + if (ret < 0) + { + goto _err2; + } + + sem_destroy(&priv->syncsem); + } + + priv->num_open++; + goto _success; + +_err2: +#ifndef CONFIG_CXD56_GNSS_HOT_SLEEP + PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_HOT_ENABLE); +#endif + PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_COLD); +_err1: + sem_destroy(&priv->syncsem); +_err0: +_success: + sem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_close + * + * Description: + * Standard character driver close method. + * + * Input Parameters: + * filep - File structure pointer + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_close(FAR struct file *filep) +{ + FAR struct inode * inode; + FAR struct cxd56_gnss_dev_s *priv; + int ret = OK; + + inode = filep->f_inode; + priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + priv->num_open--; + if (priv->num_open == 0) + { +#ifndef CONFIG_CXD56_GNSS_HOT_SLEEP + PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_HOT_ENABLE); +#endif + + ret = PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_COLD); + if (ret < 0) + { + goto errout; + } + } + +errout: + sem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_read + * + * Description: + * Standard character driver read method. + * + * Input Parameters: + * filep - File structure pointer + * buffer - Buffer to read from GNSS device + * buflen - The read length of the buffer + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static ssize_t cxd56_gnss_read(FAR struct file *filep, FAR char *buffer, + size_t len) +{ + int32_t ret = 0; + uint32_t offset = 0; + int8_t type; + + if (!buffer) + { + ret = -EINVAL; + goto _err; + } + if (len == 0) + { + goto _success; + } + + /* setect data type */ + + type = cxd56_gnss_select_notifytype(filep->f_pos, &offset); + if (type < 0) + { + ret = -ESPIPE; + goto _err; + } + + if (type == CXD56_CPU1_DATA_TYPE_GNSS) + { + /* Trim len if read would go beyond end of device */ + + if ((offset + len) > sizeof(struct cxd56_gnss_positiondata_s)) + { + len = sizeof(struct cxd56_gnss_positiondata_s) - offset; + } + } + else if (type == CXD56_CPU1_DATA_TYPE_AGPS) + { + if ((offset + len) > sizeof(struct cxd56_supl_mesurementdata_s)) + { + len = sizeof(struct cxd56_supl_mesurementdata_s) - offset; + } + } + + /* GD_ReadBuffer returns copied data size or negative error code */ + + ret = GD_ReadBuffer(type, offset, buffer, len); + +_err: +_success: + filep->f_pos = 0; + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_write + * + * Description: + * Standard character driver write method. + * + * Input Parameters: + * filep - File structure pointer + * buffer - Buffer to write + * buflen - The write length of the buffer + * + * Returned Value: + * Always returns -ENOENT error. + * + *****************************************************************************/ + +static ssize_t cxd56_gnss_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen) +{ + return -ENOENT; +} + +/**************************************************************************** + * Name: cxd56_gnss_ioctl + * + * Description: + * Standard character driver ioctl method. + * + * Input Parameters: + * filep - File structure pointer + * fds - Array of file descriptor + * setup - 1 if start poll, 0 if stop poll + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_ioctl(FAR struct file *filep, int cmd, + unsigned long arg) +{ + FAR struct inode * inode; + FAR struct cxd56_gnss_dev_s *priv; + int ret; + + inode = filep->f_inode; + priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private; + + if (cmd <= CXD56_GNSS_IOCTL_INVAL || cmd >= CXD56_GNSS_IOCTL_MAX) + { + return -EINVAL; + } + + ret = sem_wait(&priv->ioctllock); + if (ret < 0) + { + return ret; + } + + ret = g_cmdlist[cmd](filep, arg); + + sem_post(&priv->ioctllock); + + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnss_poll + * + * Description: + * Standard character driver poll method. + * + * Input Parameters: + * filep - File structure pointer + * fds - array of file descriptor + * setup - 1 if start poll, 0 if stop poll + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_POLL +static int cxd56_gnss_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup) +{ + FAR struct inode *inode; + FAR struct cxd56_gnss_dev_s *priv; + int ret = OK; + int i; + + inode = filep->f_inode; + priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private; + + ret = sem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + if (setup) + { + if ((fds->events & POLLIN) == 0) + { + ret = -EDEADLK; + goto errout; + } + + for (i = 0; i < CONFIG_CXD56_GNSS_NPOLLWAITERS; i++) + { + /* Find an unused slot */ + + if (priv->fds[i] == NULL) + { + /* Bind the poll structure and this slot */ + + priv->fds[i] = fds; + fds->priv = &priv->fds[i]; + GD_SetNotifyMask(CXD56_CPU1_DEV_GNSS, FALSE); + break; + } + } + + /* No space in priv fds array for poll handling */ + + if (i >= CONFIG_CXD56_GNSS_NPOLLWAITERS) + { + fds->priv = NULL; + ret = -EBUSY; + goto errout; + } + } + else if (fds->priv) + { + /* This is a request to tear down the poll. */ + + struct pollfd **slot = (struct pollfd **)fds->priv; + + /* Remove all memory of the poll setup */ + + *slot = NULL; + fds->priv = NULL; + } + +errout: + sem_post(&priv->devsem); + return ret; +} +#endif + +/**************************************************************************** + * Name: cxd56_gnss_register + * + * Description: + * Register the GNSS character device as 'devpath' + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/gps" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int cxd56_gnss_register(FAR const char *devpath) +{ + FAR struct cxd56_gnss_dev_s *priv; + int i; + int ret; + static struct + { + uint8_t sigtype; + cxd56_cpu1sighandler_t handler; + } devsig_table[] = + { + { + CXD56_CPU1_DATA_TYPE_GNSS, + cxd56_gnss_default_sighandler + }, + { + CXD56_CPU1_DATA_TYPE_AGPS, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_RTK, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_GPSEPHEMERIS, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_GLNEPHEMERIS, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_SPECTRUM, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_PVTLOG, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_CPUFIFOAPI, + cxd56_gnss_cpufifoapi_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_SBAS, + cxd56_gnss_common_signalhandler + }, + { + CXD56_CPU1_DATA_TYPE_DCREPORT, + cxd56_gnss_common_signalhandler + } + }; + + priv = (FAR struct cxd56_gnss_dev_s *)kmm_malloc( + sizeof(struct cxd56_gnss_dev_s)); + if (!priv) + { + gnsserr("Failed to allocate instance\n"); + return -ENOMEM; + } + + memset(priv, 0, sizeof(struct cxd56_gnss_dev_s)); + + ret = sem_init(&priv->devsem, 0, 1); + if (ret < 0) + { + gnsserr("Failed to initialize gnss devsem!\n"); + goto _err0; + } + + ret = sem_init(&priv->apiwait, 0, 0); + if (ret < 0) + { + gnsserr("Failed to initialize gnss apiwait!\n"); + goto _err0; + } + + ret = sem_init(&priv->ioctllock, 0, 1); + if (ret < 0) + { + gnsserr("Failed to initialize gnss ioctllock!\n"); + goto _err0; + } + + ret = cxd56_gnss_initialize(priv); + if (ret < 0) + { + gnsserr("Failed to initialize gnss device!\n"); + goto _err0; + } + + ret = register_driver(devpath, &g_gnssfops, 0666, priv); + if (ret < 0) + { + gnsserr("Failed to register driver: %d\n", ret); + goto _err0; + } + + for (i = 0; i < sizeof(devsig_table) / sizeof(devsig_table[0]); i++) + { + ret = cxd56_cpu1siginit(devsig_table[i].sigtype, priv); + if (ret < 0) + { + gnsserr("Failed to initialize ICC for GPS CPU: %d,%d\n", ret, + devsig_table[i].sigtype); + goto _err2; + } + cxd56_cpu1sigregisterhandler(devsig_table[i].sigtype, + devsig_table[i].handler); + } + + gnssinfo("GNSS driver loaded successfully!\n"); + + return ret; + +_err2: + unregister_driver(devpath); + +_err0: + kmm_free(priv); + return ret; +} + +/**************************************************************************** + * Name: cxd56_gnssinitialize + * + * Description: + * Initialize GNSS device + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/gps" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int cxd56_gnssinitialize(FAR const char *devpath) +{ + int ret; + + gnssinfo("Initializing GNSS..\n"); + + ret = cxd56_gnss_register(devpath); + if (ret < 0) + { + gnsserr("Error registering GNSS\n"); + } + + return ret; +} + +#endif diff --git a/arch/arm/src/cxd56xx/cxd56_gnss.h b/arch/arm/src/cxd56xx/cxd56_gnss.h new file mode 100644 index 00000000000..761e1af2b83 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_gnss.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_gnss.h + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_H +#define __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* GNSS specific debug */ + +#ifdef CONFIG_CXD56_GNSS_DEBUG_ERROR +# define gnsserr(fmt, ...) logerr(fmt, ## __VA_ARGS__) +#else +# define gnsserr(fmt, ...) +#endif + +#ifdef CONFIG_CXD56_GNSS_DEBUG_WARN +# define gnsswarn(fmt, ...) logwarn(fmt, ## __VA_ARGS__) +#else +# define gnsswarn(fmt, ...) +#endif + +#ifdef CONFIG_CXD56_GNSS_DEBUG_INFO +# define gnssinfo(fmt, ...) loginfo(fmt, ## __VA_ARGS__) +#else +# define gnssinfo(fmt, ...) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cxd56_gnssinitialize + * + * Description: + * Initialize GNSS device + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/gps" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int cxd56_gnssinitialize(FAR const char *devpath); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_gnss_api.h b/arch/arm/src/cxd56xx/cxd56_gnss_api.h new file mode 100644 index 00000000000..be4705957ab --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_gnss_api.h @@ -0,0 +1,356 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_gnss_api.h + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_API_H +#define __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_API_H + +#include +#include + +/* GD Start mode */ + +#define CXD56_GNSS_STMOD_COLD 0 +#define CXD56_GNSS_STMOD_WARM 1 +#define CXD56_GNSS_STMOD_WARMACC2 2 +#define CXD56_GNSS_STMOD_HOT 3 +#define CXD56_GNSS_STMOD_HOTACC 4 +#define CXD56_GNSS_STMOD_HOTACC2 5 +#define CXD56_GNSS_STMOD_HOTACC3 6 +#define CXD56_GNSS_STMOD_XTC1 7 +#define CXD56_GNSS_STMOD_XTC2 8 + +/* GD operation mode */ + +/* GD_SetOperationMode, GD_GetOperationMode */ + +#define CXD56_GNSS_OPMOD_NORMAL 1 +#define CXD56_GNSS_OPMOD_LOWPOWER 2 +#define CXD56_GNSS_OPMOD_BALANCE 4 +#define CXD56_GNSS_OPMOD_1PSS 5 + +/* Start a positioning + * begining to search the satellites and measure the receiver position + */ + +int GD_Start(uint8_t startMode); + +/* Stop a positioning */ + +int GD_Stop(void); + +/* Select GNSSs to positioning + * These are able to specified by CXD56_GNSS_B_SAT_XXX defines. + */ + +int GD_SelectSatelliteSystem(uint32_t system); + +/* Get current using GNSSs to positioning + * A argument 'satellite' indicates current GNSSs by bit fields defined + * by CXD56_GNSS_B_SAT_XXX. + */ + +int GD_GetSatelliteSystem(FAR uint32_t *system); + +/* Set the rough receiver position */ + +int GD_SetReceiverPositionEllipsoidal(FAR double *dLat, FAR double *dLon, + FAR double *dHeight); + +/* Set the rough receiver position as orgothonal */ + +int GD_SetReceiverPositionOrthogonal(int32_t dX, int32_t dY, int32_t dZ); + +/* Set enable or disable the 1PPS output. */ + +int GD_Set1ppsOutput(uint32_t enable); + +/* Get the current 1PPS output setting. */ + +int GD_Get1ppsOutput(FAR uint32_t *enable); + +/* Set the receiver operation mode + * 1st argument 'mode' is a operation mode defined by CXD56_GNSS_OPMOD_XXX. + * 2nd argument 'cycle' is a positioning period[ms], default is 1000[ms]. + */ + +int GD_SetOperationMode(uint32_t mode, uint32_t cycle); + +/* Get the receiver operation mode */ + +int GD_GetOperationMode(FAR uint32_t *mode, FAR uint32_t *cycle); + +/* Set the TCXO offset */ + +int GD_SetTcxoOffset(int32_t offset); + +/* Get the TCXO offset */ + +int GD_GetTcxoOffset(FAR int32_t *offset); + +/* Set the estimated current time of the receiver. + * 1st argument date & time are in UTC. + */ + +int GD_SetTime(FAR struct cxd56_gnss_date_s *date, + FAR struct cxd56_gnss_time_s *time); + +/* Set the network time */ + +int GD_SetFrameTime(uint16_t sec, uint32_t fracSec); + +/* Get the almanac data */ + +int GD_GetAlmanac(uint32_t satellite, FAR uint32_t* almanac, + FAR uint32_t *almanacSize); + +/* Set the almanac data */ + +int GD_SetAlmanac(uint32_t satellite, FAR uint32_t *almanac); + +/* Get the Ephemeris data */ + +int GD_GetEphemeris(uint32_t satellite, FAR uint32_t* ephemeris, + FAR uint32_t *ephemerisSize); + +/* Set the Ephemeris data */ + +int GD_SetEphemeris(uint32_t satellite, FAR uint32_t *ephemeris); + +/* Select to use or not use the initial position calculation supporting + * information of the QZSS L1-SAIF. + */ + +int GD_SetQzssPosAssist(uint32_t enable); + +/* Get a setting of the initial position calculation supporting + * information of the QZSS L1-SAIF. + */ + +int GD_GetQzssPosAssist(FAR uint32_t *enable); + +/* Set IMES bitrates. */ + +int GD_SetImesBitrate(uint32_t bitrate); + +/* Get IMES bitrates. */ + +int GD_GetImesBitrate(FAR uint32_t *bitrate); + +/* Set IMES center frequency offset. */ + +int GD_SetImesCenterFreqOffset(uint32_t offset); + +/* Set IMES preamble. */ + +int GD_SetImesPreamble(uint32_t preamble); + +/* Start GPS test */ + +void GD_StartGpsTest(uint32_t satellite, uint32_t reserve1, + uint32_t reserve2, uint32_t reserve3); + +/* Stop GPS test */ + +int GD_StopGpsTest(void); + +/* Get GPS test result */ + +int GD_GetGpsTestResult(FAR float* cn, FAR float* doppler); + +/* Control Spectrum output */ + +int GD_SpectrumControl(unsigned long time, unsigned int enable, + unsigned char moniPoint1, unsigned char step1, + unsigned char moniPoint2, unsigned char step2); + +/* Save the backup data to a Flash memory. */ + +int GD_SaveBackupdata(void); + +/* CEP Check Assist Data Valid */ + +int GD_CepCheckAssistData(void); + +/* CEP Get Age Data */ + +int GD_CepGetAgeData(FAR float *age, FAR float *cepi); + +/* CEP Reset Assist Data init flag & valid flag */ + +int GD_CepInitAssistData(void); + +/* AGPS Set tau */ + +int GD_SetTauGps(FAR double *tau); + +/* AGPS Set Acquist */ + +int GD_SetAcquist(FAR uint8_t *pAcquistData, uint16_t acquistSize); + +/* Set the estimated current time of the receiver. + * 1st argument date & time are in GPS time. + */ + +int GD_SetTimeGps(FAR struct cxd56_gnss_date_s *date, + FAR struct cxd56_gnss_time_s *time); + +/* Clear Receiver Infomation */ + +int GD_ClearReceiverInfo(uint32_t type); + +/* AGPS Set Tow Assist */ + +int GD_SetTowAssist(FAR uint8_t *pAssistData, uint16_t dataSize); + +/* AGPS Set UTC Model */ + +int GD_SetUtcModel(FAR uint8_t *pModelData, uint16_t dataSize); + +/* Read GNSS data to specified buffer */ + +int GD_ReadBuffer(uint8_t type, int32_t offset, FAR void *buf, + uint32_t length); + +/* Write GNSS data from specified buffer */ + +int GD_WriteBuffer(uint8_t type, int32_t offset, FAR void *buf, + uint32_t length); + +/* Set notify mask, this mask flag is cleared when notified(poll/signal) */ + +int GD_SetNotifyMask(uint8_t type, uint8_t clear); + +/* Geofence Add Region */ + +int GD_GeoAddRegion(uint8_t id, long lat, long lon, uint16_t rad); + +/* Geofence Modify Region */ + +int GD_GeoModifyRegion(uint8_t id, long lat, long lon, uint16_t rad); + +/* Geofence Delete Region */ + +int GD_GeoDeleteRegione(uint8_t id); + +/* Geofence All delete Region */ + +int GD_GeoDeleteAllRegion(void); + +/* Geofence Region check */ + +int GD_GeoGetRegionData(uint8_t id, FAR long *lat, FAR long *lon, + FAR uint16_t *rad); + +/* Geofence Get Used Region ID */ + +uint32_t GD_GeoGetUsedRegionId(void); + +/* Geofence Set mode */ + +int GD_GeoSetOpMode(uint16_t deadzone, uint16_t dwell_detecttime); + +/* Geofence Request All region notify */ + +int GD_GeoSetAllRgionNotifyRequest(void); + +/* Geofence Register to gnss_provider */ + +int GD_RegisterGeofence(void); + +/* Geofence Release from gnss_provider */ + +int GD_ReleaseGeofence(void); + +/* Pvtlog Register to gnss_provider */ + +int GD_RegisterPvtlog(uint32_t cycle, uint32_t threshold); + +/* Pvtlog Release */ + +int GD_ReleasePvtlog(void); + +/* Pvtlog Delete log data */ + +int GD_PvtlogDeleteLog(void); + +/* Pvtlog Get Log status */ + +int GD_PvtlogGetLogStatus(FAR struct cxd56_gnss_status_s *pLogStatus); + +/* Start outputting carrier phase info. */ + +int GD_RtkStart(FAR struct cxd56_rtk_setting_s *pParam); + +/* Stop outputting carrier phase info. */ + +int GD_RtkStop(void); + +/* Set output interval of carrier phase info. + * + * interval : CXD56_GNSS_RTK_INTERVAL_XXX (gd_type.h) + */ + +int GD_RtkSetOutputInterval(int interval); + +/* Get output interval of carrier phase info. [ms] */ + +int GD_RtkGetOutputInterval(FAR int* interval); + +/* Set GNSS of outputting carrier phase info. */ + +int GD_RtkSetGnss(uint32_t gnss); + +/* Get GNSS of outputting carrier phase info. */ + +int GD_RtkGetGnss(FAR uint32_t* pGnss); + +/* Set enable/disable GD to notify updating ephemeris */ + +int GD_RtkSetEphNotify(int enable); + +/* Get enable/disable GD to notify updating ephemeris */ + +int GD_RtkGetEphNotify(FAR int* enable); + +/* Set the Ephemeris data Ephemeris data size is variable. */ + +int GD_SetVarEphemeris(uint32_t *ephemeris, uint32_t ephemerisSize); + +/* Get the Ephemeris data Ephemeris data size is variable. */ + +int GD_GetVarEphemeris(uint32_t satellite, uint32_t* ephemeris, + uint32_t ephemerisSize); + +#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_API_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_uart0.c b/arch/arm/src/cxd56xx/cxd56_uart0.c new file mode 100644 index 00000000000..de7275b92a0 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_uart0.c @@ -0,0 +1,325 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_uart0.c + * + * Copyright 2018 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of Sony Semiconductor Solutions Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "cxd56_pinconfig.h" + +#ifdef CONFIG_CXD56_UART0 + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_CXD56_UART0_BAUD +# define CONFIG_CXD56_UART0_BAUD 921600 +#endif +#ifndef CONFIG_CXD56_UART0_BITS +# define CONFIG_CXD56_UART0_BITS 8 +#endif +#ifndef CONFIG_CXD56_UART0_PARITY +# define CONFIG_CXD56_UART0_PARITY 0 +#endif +#ifndef CONFIG_CXD56_UART0_2STOP +# define CONFIG_CXD56_UART0_2STOP 0 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int uart0_open(FAR struct file *filep); +static int uart0_close(FAR struct file *filep); +static ssize_t uart0_read(FAR struct file *filep, + FAR char *buffer, size_t len); +static ssize_t uart0_write(FAR struct file *filep, + FAR const char *buffer, size_t len); +static int uart0_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int uart0_semtake(sem_t *id); +static void uart0_semgive(sem_t *id); + +/**************************************************************************** + * FarAPI prototypes + ****************************************************************************/ + +int PD_UartInit(int ch); +int PD_UartUninit(int ch); +int PD_UartConfiguration(int ch, int baudrate, int databits, + int parity, int stopbit, int flowctrl); +int PD_UartEnable(int ch); +int PD_UartDisable(int ch); +int PD_UartReceive(int ch, void *buf, int size, int leave); +int PD_UartSend(int ch, void *buf, int size, int leave); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_uart0fops = +{ + .open = uart0_open, + .close = uart0_close, + .read = uart0_read, + .write = uart0_write, + .seek = 0, + .ioctl = uart0_ioctl, +}; + +static sem_t g_lock; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart0_semtake + ****************************************************************************/ + +static int uart0_semtake(sem_t *id) +{ + while (sem_wait(id) != 0) + { + ASSERT(errno == EINTR); + } + return OK; +} + +/**************************************************************************** + * Name: uart0_semgive + ****************************************************************************/ + +static void uart0_semgive(sem_t *id) +{ + sem_post(id); +} + +/**************************************************************************** + * Name: uart0_open + ****************************************************************************/ + +static int uart0_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + int flowctl; + int bits; + int stop; + int ret; + + if (inode->i_crefs > 1) + { + return OK; + } + + ret = PD_UartInit(0); + if (ret < 0) + { + set_errno(EFAULT); + return ERROR; + } + + /* 0 = 5bit, 1 = 6bit, 2 = 7bit, 3 = 8bit */ + + bits = CONFIG_CXD56_UART0_BITS - 5; + + /* 1 = 1 stop, 2 = 2 stop bit */ + + stop = CONFIG_CXD56_UART0_2STOP + 1; + + /* Enable UART0 pin configuration */ + +#ifdef CONFIG_UART0_FLOWCONTROL + flowctl = 1; + CXD56_PIN_CONFIGS(PINCONFS_SPI2_UART0); +#else + flowctl = 0; + CXD56_PIN_CONFIGS(PINCONFS_SPI2A_UART0); +#endif + + ret = PD_UartConfiguration(0, CONFIG_CXD56_UART0_BAUD, + bits, + CONFIG_CXD56_UART0_PARITY, + stop, flowctl); + if (ret < 0) + { + PD_UartUninit(0); + set_errno(EINVAL); + return ERROR; + } + + ret = PD_UartEnable(0); + if (ret < 0) + { + PD_UartUninit(0); + set_errno(EFAULT); + return ERROR; + } + + return OK; +} + +/**************************************************************************** + * Name: uart0_close + ****************************************************************************/ + +static int uart0_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + + if (inode->i_crefs == 1) + { + PD_UartDisable(0); + PD_UartUninit(0); + + /* Disable UART0 pin by changing Hi-Z GPIO */ + +#ifdef CONFIG_UART0_FLOWCONTROL + CXD56_PIN_CONFIGS(PINCONFS_SPI2_GPIO); +#else + CXD56_PIN_CONFIGS(PINCONFS_SPI2A_GPIO); +#endif + } + + return 0; +} + +/**************************************************************************** + * Name: uart0_read + ****************************************************************************/ + +static ssize_t uart0_read(FAR struct file *filep, + FAR char *buffer, size_t len) +{ + int ret; + + uart0_semtake(&g_lock); + + /* Always blocking */ + + ret = PD_UartReceive(0, buffer, len, 0); + + uart0_semgive(&g_lock); + + if (ret < 0) + { + set_errno(-ret); + ret = 0; /* Receive no data */ + } + + return (ssize_t)ret; +} + +/**************************************************************************** + * Name: uart0_write + ****************************************************************************/ + +static ssize_t uart0_write(FAR struct file *filep, + FAR const char *buffer, size_t len) +{ + int ret; + + uart0_semtake(&g_lock); + + /* Always blocking */ + + ret = PD_UartSend(0, (FAR void *)buffer, len, 0); + + uart0_semgive(&g_lock); + + if (ret < 0) + { + set_errno(-ret); + ret = 0; + } + return (ssize_t)ret; +} + +/**************************************************************************** + * Name: uart0_ioctl + ****************************************************************************/ + +static int uart0_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: cxd56_uart0initialize + ****************************************************************************/ + +int cxd56_uart0initialize(FAR const char *devname) +{ + int ret; + + sem_init(&g_lock, 0, 1); + + ret = register_driver(devname, &g_uart0fops, 0666, NULL); + if (ret != 0) + { + return ERROR; + } + + return OK; +} + +/**************************************************************************** + * Name: cxd56_uart0uninitialize + ****************************************************************************/ + +void cxd56_uart0uninitialize(FAR const char *devname) +{ + unregister_driver(devname); + sem_destroy(&g_lock); +} + +#endif /* CONFIG_CXD56_UART0 */ diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 8a2b3ebe7c2..3c950f1e42d 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -3017,7 +3017,7 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno) imxrt_clockall_usdhc1(); break; - +#if defined(CONFIG_IMXRT_USDHC2) case IMXRT_USDHC2_BASE: (void)imxrt_config_gpio(PIN_USDHC2_D0); (void)imxrt_config_gpio(PIN_USDHC2_D1); @@ -3027,7 +3027,7 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno) (void)imxrt_config_gpio(PIN_USDHC2_CMD); imxrt_clockall_usdhc2(); break; - +#endif default: return NULL; } diff --git a/arch/arm/src/lpc11xx/Kconfig b/arch/arm/src/lpc11xx/Kconfig deleted file mode 100644 index 820ce783cd1..00000000000 --- a/arch/arm/src/lpc11xx/Kconfig +++ /dev/null @@ -1,241 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "LPC11xx Configuration Options" - -choice - prompt "NXP LPC11XX Chip Selection" - default ARCH_CHIP_LPC1115 - depends on ARCH_CHIP_LPC11XX - -config ARCH_CHIP_LPC1114 - bool "LPC1114" - select ARCH_FAMILY_LPC111X - -config ARCH_CHIP_LPC1115 - bool "LPC1115" - select ARCH_FAMILY_LPC111X - -endchoice - -config ARCH_FAMILY_LPC111X - bool - -menu "LPC11xx Peripheral Support" - -choice - prompt "System Clock:" - default LPC11_INTRCOSC - -config LPC11_INTRCOSC - bool "Internal RC" - -config LPC11_MAINOSC - bool "External Crystal" - -endchoice - -choice - prompt "SysTick clock source" - default LPC11_SYSTICK_CORECLK - -config LPC11_SYSTICK_CORECLK - bool "Cortex-M0 core clock" - -config LPC11_SYSTICK_CORECLK_DIV16 - bool "Cortex-M0 core clock divided by 16" - -endchoice - -config LPC11_PLL - bool "PLL" - default y - -config LPC11_UART0 - bool "UART0" - select UART0_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - default y - -config LPC11_CAN0 - bool "CAN0" - default n - -config LPC11_SPI - bool "SPI" - default n - -config LPC11_SSP0 - bool "SSP0" - default n - -config LPC11_SSP1 - bool "SSP1" - default n - -config LPC11_I2C0 - bool "I2C0" - default n - -config LPC11_TMR0 - bool "Timer 0" - default n - -config LPC11_TMR1 - bool "Timer 1" - default n - -config LPC11_WDT - bool "WDT" - default n - -config LPC11_ADC - bool "ADC" - default n - -config LPC11_FLASH - bool "FLASH" - default n - -endmenu - -menu "ADC driver options" - depends on LPC11_ADC - -config LPC11_ADC0_AVERAGE - int "ADC0 average" - default 200 - -config LPC11_ADC0_MASK - hex "ADC0 mask" - default 0x01 - -config LPC11_ADC0_SPS - int "ADC0 SPS" - default 1000 - -config LPC11_ADC_CHANLIST - bool "Use ADC channel list" - default n - ---help--- - The errata that states: "A/D Global Data register should not be used - with burst mode or hardware triggering". If this option is selected, - then the ADC driver will grab from the individual channel registers - rather than from the global data register as this is the stated - workaround in the errata. - - The ADC interrupt will trigger on conversion complete on the last - channel listed in the array g_adc_chanlist[] (as opposed to - triggering interrupt from the global DONE flag). - - If this option is enabled, then the platform specific code must do - two things: (1) define LPC11_ADC_NCHANNELS in the configuration file - and (2) provide an array g_adc_chanlist[] with the channel numbers - matching the LPC11_ADC0_MASK within the board-specific library. - -config LPC11_ADC_BURSTMODE - bool "One interrupt at the end of all ADC conversions" - default n - ---help--- - Select this if you want to generate only one interrupt once all - selected channels has been converted by the ADC - -config LPC11_ADC_NCHANNELS - int "ADC0 number of channels" - depends on LPC11_ADC_CHANLIST - default 0 - ---help--- - If LPC11_ADC_CHANLIST is enabled, then the platform specific code - must do two things: (1) define LPC11_ADC_NCHANNELS in the configuration - file and (2) provide an array g_adc_chanlist[] with the channel - numbers matching the LPC11_ADC0_MASK within the board-specific - library. - -endmenu - -menu "CAN driver options" - depends on LPC11_CAN1 || LPC11_CAN2 - -config LPC11_CAN1_BAUD - int "CAN1 BAUD" - depends on LPC11_CAN1 - ---help--- - CAN1 BAUD rate. Required if LPC11_CAN1 is defined. - -config LPC11_CAN2_BAUD - int "CAN2 BAUD" - depends on LPC11_CAN2 - ---help--- - CAN2 BAUD rate. Required if LPC11_CAN2 is defined. - -config LPC11_CAN1_DIVISOR - int "CAN1 CCLK divisor" - depends on LPC11_CAN1 - default 4 - ---help--- - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided - by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - -config LPC11_CAN2_DIVISOR - int "CAN2 CCLK divisor" - depends on LPC11_CAN2 - default 4 - ---help--- - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided - by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - -config LPC11_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config LPC11_CAN_TSEG2 - int "TSEG2 quanta" - default 4 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config LPC11_CAN_SAM - bool "CAN sampling" - default n - ---help--- - The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line). - -config CAN_REGDEBUG - bool "Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN debug information. Requires also - CONFIG_DEBUG_CAN_INFO. - -endmenu - -config LPC11_GPIOIRQ - bool "GPIO interrupt support" - default n - ---help--- - Enable support for GPIO interrupts - -menu "I2C driver options" - depends on LPC11_I2C0 || LPC11_I2C1 || LPC11_I2C2 - -config LPC11_I2C0_FREQUENCY - int "I2C0 frequency" - depends on LPC11_I2C0 - default 100000 - -config LPC11_I2C1_FREQUENCY - int "I2C1 frequency" - depends on LPC11_I2C1 - default 100000 - -config LPC11_I2C2_FREQUENCY - int "I2C2 frequency" - depends on LPC11_I2C2 - default 100000 - -endmenu diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs deleted file mode 100644 index 180cdf4fca7..00000000000 --- a/arch/arm/src/lpc11xx/Make.defs +++ /dev/null @@ -1,101 +0,0 @@ -############################################################################ -# arch/arm/src/lpc11xx/Make.defs -# -# Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -HEAD_ASRC = - -CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S -CMN_ASRCS += up_switchcontext.S vfork.S - -CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c -CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c -CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c -CMN_CSRCS += up_puts.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c -CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c -CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c -CMN_CSRCS += up_systemreset.c up_unblocktask.c up_usestack.c up_doirq.c -CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CMN_CSRCS += up_task_start.c up_pthread_start.c -CMN_CSRCS += up_signal_dispatch.c -CMN_UASRCS += up_signal_handler.S -endif - -ifeq ($(CONFIG_STACK_COLORATION),y) -CMN_CSRCS += up_checkstack.c -endif - -ifeq ($(CONFIG_DEBUG_FEATURES),y) -CMN_CSRCS += up_dumpnvic.c -endif - -CHIP_ASRCS = -CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_irq.c -CHIP_CSRCS += lpc11_lowputc.c lpc11_serial.c lpc11_spi.c lpc11_ssp.c -CHIP_CSRCS += lpc11_start.c - -# Configuration-dependent LPC11xx files - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += lpc11_idle.c -endif - -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += lpc11_timerisr.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += lpc11_userspace.c -endif - -ifeq ($(CONFIG_LPC11_GPIOIRQ),y) -CHIP_CSRCS += lpc11_gpioint.c -endif - -ifeq ($(CONFIG_ARCH_IRQPRIO),y) -CHIP_CSRCS += lpc11_irqprio.c -endif - -ifeq ($(CONFIG_LPC11_SPI0),y) -CHIP_CSRCS += lpc11_spi.c -else -ifeq ($(CONFIG_LPC11_SPI1),y) -CHIP_CSRCS += lpc11_spi.c -endif -endif - -ifeq ($(CONFIG_PWM),y) -CHIP_CSRCS += lpc11_pwm.c -endif diff --git a/arch/arm/src/lpc11xx/chip.h b/arch/arm/src/lpc11xx/chip.h deleted file mode 100644 index e9a8f52c747..00000000000 --- a/arch/arm/src/lpc11xx/chip.h +++ /dev/null @@ -1,74 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/chip.h - * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_H -#define __ARCH_ARM_SRC_LPC11XX_CHIP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "nvic.h" - -/* Include the chip capabilities file */ - -#include - -#define ARMV6M_PERIPHERAL_INTERRUPTS 32 - -/* Include the memory map file. Other chip hardware files should then include - * this file for the proper setup. - */ - -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h b/arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h deleted file mode 100644 index 1836d35dc1e..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h +++ /dev/null @@ -1,269 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Rommel Marcelo - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_IOCON_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_IOCON_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#define IOCON_NPINS 12 - -/* Register offsets *****************************************************************/ -/* Note: The IOCON offset is not linear. See User manual UM10398 Page 74 */ - -#define LPC11_IOCON_P0_0_OFFSET 0x00c -#define LPC11_IOCON_P0_1_OFFSET 0x010 -#define LPC11_IOCON_P0_2_OFFSET 0x01c -#define LPC11_IOCON_P0_3_OFFSET 0x02C -#define LPC11_IOCON_P0_4_OFFSET 0x030 -#define LPC11_IOCON_P0_5_OFFSET 0x034 -#define LPC11_IOCON_P0_6_OFFSET 0x04c -#define LPC11_IOCON_P0_7_OFFSET 0x050 -#define LPC11_IOCON_P0_8_OFFSET 0x060 -#define LPC11_IOCON_P0_9_OFFSET 0x064 -#define LPC11_IOCON_P0_10_OFFSET 0x068 -#define LPC11_IOCON_P0_11_OFFSET 0x074 - -#define LPC11_IOCON_P1_0_OFFSET 0x078 -#define LPC11_IOCON_P1_1_OFFSET 0x07c -#define LPC11_IOCON_P1_2_OFFSET 0x080 -#define LPC11_IOCON_P1_3_OFFSET 0x090 -#define LPC11_IOCON_P1_4_OFFSET 0x094 -#define LPC11_IOCON_P1_5_OFFSET 0x0a0 -#define LPC11_IOCON_P1_6_OFFSET 0x0a4 -#define LPC11_IOCON_P1_7_OFFSET 0x0a8 -#define LPC11_IOCON_P1_8_OFFSET 0x014 -#define LPC11_IOCON_P1_9_OFFSET 0x038 -#define LPC11_IOCON_P1_10_OFFSET 0x06c -#define LPC11_IOCON_P1_11_OFFSET 0x098 - -#define LPC11_IOCON_P2_0_OFFSET 0x008 -#define LPC11_IOCON_P2_1_OFFSET 0x028 -#define LPC11_IOCON_P2_2_OFFSET 0x05c -#define LPC11_IOCON_P2_3_OFFSET 0x08c -#define LPC11_IOCON_P2_4_OFFSET 0x040 -#define LPC11_IOCON_P2_5_OFFSET 0x044 -#define LPC11_IOCON_P2_6_OFFSET 0x000 -#define LPC11_IOCON_P2_7_OFFSET 0x020 -#define LPC11_IOCON_P2_8_OFFSET 0x024 -#define LPC11_IOCON_P2_9_OFFSET 0x054 -#define LPC11_IOCON_P2_10_OFFSET 0x058 -#define LPC11_IOCON_P2_11_OFFSET 0x070 - -#define LPC11_IOCON_P3_0_OFFSET 0x084 -#define LPC11_IOCON_P3_1_OFFSET 0x088 -#define LPC11_IOCON_P3_2_OFFSET 0x09C -#define LPC11_IOCON_P3_3_OFFSET 0x0ac -#define LPC11_IOCON_P3_4_OFFSET 0x03c -#define LPC11_IOCON_P3_5_OFFSET 0x048 - -#define LPC11_IOCON_SCK_LOC_OFFSET 0x0b0 -#define LPC11_IOCON_DSR_LOC_OFFSET 0x0b4 -#define LPC11_IOCON_DCD_LOC_OFFSET 0x0b8 -#define LPC11_IOCON_RI_LOC_OFFSET 0x0bc - -/* Register addresses ***************************************************************/ -/* Note: The IOCON base is not linear. See User manual UM10398 Page 74 */ - -#define LPC11_IOCON_P0_0 (LPC11_IOCON_BASE + LPC11_IOCON_P0_0_OFFSET) -#define LPC11_IOCON_P0_1 (LPC11_IOCON_BASE + LPC11_IOCON_P0_1_OFFSET) -#define LPC11_IOCON_P0_2 (LPC11_IOCON_BASE + LPC11_IOCON_P0_2_OFFSET) -#define LPC11_IOCON_P0_3 (LPC11_IOCON_BASE + LPC11_IOCON_P0_3_OFFSET) -#define LPC11_IOCON_P0_4 (LPC11_IOCON_BASE + LPC11_IOCON_P0_4_OFFSET) -#define LPC11_IOCON_P0_5 (LPC11_IOCON_BASE + LPC11_IOCON_P0_5_OFFSET) -#define LPC11_IOCON_P0_6 (LPC11_IOCON_BASE + LPC11_IOCON_P0_6_OFFSET) -#define LPC11_IOCON_P0_7 (LPC11_IOCON_BASE + LPC11_IOCON_P0_7_OFFSET) -#define LPC11_IOCON_P0_8 (LPC11_IOCON_BASE + LPC11_IOCON_P0_8_OFFSET) -#define LPC11_IOCON_P0_9 (LPC11_IOCON_BASE + LPC11_IOCON_P0_9_OFFSET) -#define LPC11_IOCON_P0_10 (LPC11_IOCON_BASE + LPC11_IOCON_P0_10_OFFSET) -#define LPC11_IOCON_P0_11 (LPC11_IOCON_BASE + LPC11_IOCON_P0_11_OFFSET) - -#define LPC11_IOCON_P1_0 (LPC11_IOCON_BASE + LPC11_IOCON_P1_0_OFFSET) -#define LPC11_IOCON_P1_1 (LPC11_IOCON_BASE + LPC11_IOCON_P1_1_OFFSET) -#define LPC11_IOCON_P1_2 (LPC11_IOCON_BASE + LPC11_IOCON_P1_2_OFFSET) -#define LPC11_IOCON_P1_3 (LPC11_IOCON_BASE + LPC11_IOCON_P1_3_OFFSET) -#define LPC11_IOCON_P1_4 (LPC11_IOCON_BASE + LPC11_IOCON_P1_4_OFFSET) -#define LPC11_IOCON_P1_5 (LPC11_IOCON_BASE + LPC11_IOCON_P1_5_OFFSET) -#define LPC11_IOCON_P1_6 (LPC11_IOCON_BASE + LPC11_IOCON_P1_6_OFFSET) -#define LPC11_IOCON_P1_7 (LPC11_IOCON_BASE + LPC11_IOCON_P1_7_OFFSET) -#define LPC11_IOCON_P1_8 (LPC11_IOCON_BASE + LPC11_IOCON_P1_8_OFFSET) -#define LPC11_IOCON_P1_9 (LPC11_IOCON_BASE + LPC11_IOCON_P1_9_OFFSET) -#define LPC11_IOCON_P1_10 (LPC11_IOCON_BASE + LPC11_IOCON_P1_10_OFFSET) -#define LPC11_IOCON_P1_11 (LPC11_IOCON_BASE + LPC11_IOCON_P1_11_OFFSET) - -#define LPC11_IOCON_P2_0 (LPC11_IOCON_BASE + LPC11_IOCON_P2_0_OFFSET) -#define LPC11_IOCON_P2_1 (LPC11_IOCON_BASE + LPC11_IOCON_P2_1_OFFSET) -#define LPC11_IOCON_P2_2 (LPC11_IOCON_BASE + LPC11_IOCON_P2_2_OFFSET) -#define LPC11_IOCON_P2_3 (LPC11_IOCON_BASE + LPC11_IOCON_P2_3_OFFSET) -#define LPC11_IOCON_P2_4 (LPC11_IOCON_BASE + LPC11_IOCON_P2_4_OFFSET) -#define LPC11_IOCON_P2_5 (LPC11_IOCON_BASE + LPC11_IOCON_P2_5_OFFSET) -#define LPC11_IOCON_P2_6 (LPC11_IOCON_BASE + LPC11_IOCON_P2_6_OFFSET) -#define LPC11_IOCON_P2_7 (LPC11_IOCON_BASE + LPC11_IOCON_P2_7_OFFSET) -#define LPC11_IOCON_P2_8 (LPC11_IOCON_BASE + LPC11_IOCON_P2_8_OFFSET) -#define LPC11_IOCON_P2_9 (LPC11_IOCON_BASE + LPC11_IOCON_P2_9_OFFSET) -#define LPC11_IOCON_P2_10 (LPC11_IOCON_BASE + LPC11_IOCON_P2_10_OFFSET) -#define LPC11_IOCON_P2_11 (LPC11_IOCON_BASE + LPC11_IOCON_P2_11_OFFSET) - -#define LPC11_IOCON_P3_0 (LPC11_IOCON_BASE + LPC11_IOCON_P3_0_OFFSET) -#define LPC11_IOCON_P3_1 (LPC11_IOCON_BASE + LPC11_IOCON_P3_1_OFFSET) -#define LPC11_IOCON_P3_2 (LPC11_IOCON_BASE + LPC11_IOCON_P3_2_OFFSET) -#define LPC11_IOCON_P3_3 (LPC11_IOCON_BASE + LPC11_IOCON_P3_3_OFFSET) -#define LPC11_IOCON_P3_4 (LPC11_IOCON_BASE + LPC11_IOCON_P3_4_OFFSET) -#define LPC11_IOCON_P3_5 (LPC11_IOCON_BASE + LPC11_IOCON_P3_5_OFFSET) - -#define LPC11_IOCON_SCK_LOC (LPC11_IOCON_BASE + LPC11_IOCON_SCK_LOC_OFFSET) -#define LPC11_IOCON_DSR_LOC (LPC11_IOCON_BASE + LPC11_IOCON_DSR_LOC_OFFSET) -#define LPC11_IOCON_DCD_LOC (LPC11_IOCON_BASE + LPC11_IOCON_DCD_LOC_OFFSET) -#define LPC11_IOCON_RI_LOC (LPC11_IOCON_BASE + LPC11_IOCON_RI_LOC_OFFSET) - -/* Register bit definitions *********************************************************/ -/* IOCON pin function select */ - -#define IOCON_FUNC_GPIO (0) -#define IOCON_FUNC_ALT1 (1) -#define IOCON_FUNC_ALT2 (2) -#define IOCON_FUNC_ALT3 (3) -#define IOCON_FUNC_ALT4 (4) -#define IOCON_FUNC_ALT5 (5) -#define IOCON_FUNC_ALT6 (6) -#define IOCON_FUNC_ALT7 (7) - -#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ -#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT) -#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ -#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT ) -#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */ -#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT) - /* Bit 6-9: Reserved */ -#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */ -#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) - /* Bit 11-31: Reserved */ - -/* Pin modes */ - -#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ -#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */ -#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */ -#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */ - -/* Pin types */ - -#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */ -#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */ -#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */ -#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */ -#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */ - -/* Analog/Digital mode */ - -#define IOCON_ADMODE_SHIFT (7) -#define IOCON_ADMODE_ANALOG (0 << IOCON_ADMODE_SHIFT) -#define IOCON_ADMODE_DIGITAL (1 << IOCON_ADMODE_SHIFT) - -/* I2C modes */ - -#define IOCON_I2CMODE_SHIFT (8) -#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT) -# define IOCON_I2CMODE_STANDARD (0 << IOCON_I2CMODE_SHIFT) -# define IOCON_I2CMODE_STANDIO (1 << IOCON_I2CMODE_SHIFT) -# define IOCON_I2CMODE_FASTPLUS (2 << IOCON_I2CMODE_SHIFT) - /*(3 << IOCON_I2CMODE_SHIFT) Reserved */ - /* Bits 10-31: Reserved */ - -/* SCK location register */ - -#define IOCON_SCK_LOC_SHIFT (0) -#define IOCON_SCK_LOC_MASK (3 << IOCON_SCK_LOC_SHIFT) -# define IOCON_SCK_LOC_SWCLK (0 << IOCON_SCK_LOC_SHIFT) -# define IOCON_SCK_LOC_PIO2_11 (1 << IOCON_SCK_LOC_SHIFT) -# define IOCON_SCK_LOC_PIO0_6 (2 << IOCON_SCK_LOC_SHIFT) - /*(3 << IOCON_SCK_LOC_SHIFT) Reserved */ - /* Bits 2-31: Reserved */ - -/* DSR location register */ - -#define IOCON_DSR_LOC_SHIFT (0) -#define IOCON_DSR_LOC_MASK (3 << IOCON_DSR_LOC_SHIFT) -# define IOCON_DSR_LOC_PIO2_1 (0 << IOCON_DSR_LOC_SHIFT) -# define IOCON_DSR_LOC_PIO3_1 (1 << IOCON_DSR_LOC_SHIFT) - /*(2 << IOCON_DSR_LOC_SHIFT) Reserved */ - /*(3 << IOCON_DSR_LOC_SHIFT) Reserved */ - /* Bits 2-31: Reserved */ - -/* DCD location register */ - -#define IOCON_DCD_LOC_SHIFT (0) -#define IOCON_DCD_LOC_MASK (3 << IOCON_DCD_LOC_SHIFT) -# define IOCON_DCD_LOC_PIO2_2 (0 << IOCON_DCD_LOC_SHIFT) -# define IOCON_DCD_LOC_PIO3_2 (1 << IOCON_DCD_LOC_SHIFT) - /*(2 << IOCON_DCD_LOC_SHIFT) Reserved */ - /*(3 << IOCON_DCD_LOC_SHIFT) Reserved */ - /* Bits 2-31: Reserved */ - -/* RI location register */ - -#define IOCON_RI_LOC_SHIFT (0) -#define IOCON_RI_LOC_MASK (3 << IOCON_RI_LOC_SHIFT) -# define IOCON_RI_LOC_PIO2_3 (0 << IOCON_RI_LOC_SHIFT) -# define IOCON_RI_LOC_PIO3_3 (1 << IOCON_RI_LOC_SHIFT) - /*(2 << IOCON_RI_LOC_SHIFT) Reserved */ - /*(3 << IOCON_RI_LOC_SHIFT) Reserved */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC118X_IOCON_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h b/arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h deleted file mode 100644 index 948d9e89945..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h +++ /dev/null @@ -1,107 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ - -#define LPC11_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ -#define LPC11_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=16Kb) */ -#define LPC11_ROM_BASE 0x1fff0000 /* -0x1fffffff: 16Kb Boot ROM with flash services */ -#define LPC11_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ -#define LPC11_GPIO_BASE 0x50000000 /* -0x2009ffff: GPIO at AHB Peripherals */ -#define LPC11_APB_BASE 0x40000000 /* -0x4007ffff: APB Peripherals */ -#define LPC11_AHB_BASE 0x50000000 /* -0x501fffff: AHB Peripherals */ -#define LPC11_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ -#define LPC11_SCS_BASE 0xe000e000 -#define LPC11_DEBUGMCU_BASE 0xe0042000 - -/* APB Peripherals *****************************************************************/ - -#define LPC11_I2C0_BASE 0x40000000 /* -0x40003fff: I2C-bus */ -#define LPC11_WDT_BASE 0x40004000 /* -0x40007fff: Watchdog timer */ -#define LPC11_UART0_BASE 0x40008000 /* -0x4000bfff: UART 0 */ -#define LPC11_TMR0_BASE 0x4000c000 /* -0x4000ffff: Timer 0 */ -#define LPC11_TMR1_BASE 0x40010000 /* -0x40013fff: Timer 1 */ -#define LPC11_TMR2_BASE 0x40014000 /* -0x40017fff: Timer 0 */ -#define LPC11_TMR3_BASE 0x40018000 /* -0x4001bfff: Timer 1 */ -#define LPC11_ADC_BASE 0x4001c000 /* -0x4001ffff: ADC */ - /* -0x40037fff: Reserved */ -#define LPC11_PMU_BASE 0x40038000 /* -0x4003bfff: PMU */ - /* -0x40017fff: Reserved */ -#define LPC11_FLASHC_BASE 0x4003c000 /* -0x4003ffff: Flash Controller */ -#define LPC11_SPI0_BASE 0x40040000 /* -0x40043fff: SPI0 */ -#define LPC11_IOCON_BASE 0x40044000 /* -0x40047fff: IOCONFIG */ -#define LPC11_SYSCON_BASE 0x40048000 /* -0x4004bfff: System Control */ - /* -0x4004ffff: Reserved */ -#define LPC11_CAN0_BASE 0x40050000 /* -0x40053fff: CAN0 */ - /* -0x40057ffff: Reserved */ -#define LPC11_SPI1_BASE 0x40058000 /* -0x4005bffff: SPI1 */ - /* -0x4007fffff: Reserved */ - -/* AHB Peripherals ******************************************************************/ - -#define LPC11_GPIO_PIO0 (LPC11_GPIO_BASE + 0) /* -0x5000ffff: GPIO PIO0 */ -#define LPC11_GPIO_PIO1 (LPC11_GPIO_BASE + 0x10000) /* -0x5001ffff: GPIO PIO1 */ -#define LPC11_GPIO_PIO2 (LPC11_GPIO_BASE + 0x20000) /* -0x5002ffff: GPIO PIO1 */ -#define LPC11_GPIO_PIO3 (LPC11_GPIO_BASE + 0x30000) /* -0x5003ffff: GPIO PIO1 */ - /* -0x501fffff: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC116X_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h b/arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h deleted file mode 100644 index e160b554b67..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h +++ /dev/null @@ -1,122 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_PINCONFIG_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_PINCONFIG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* GPIO pin definitions *************************************************************/ -/* NOTE that functions have a alternate pins that can be selected. These alternates - * are identified with a numeric suffix like _1, _2, or _3. Your board.h file - * should select the correct alternative for your board by including definitions - * such as: - * - * #define GPIO_UART1_RXD GPIO_UART1_RXD_1 - * - * (without the suffix) - */ - -#ifdef CONFIG_ARCH_CHIP_LPC1115 - -#define GPIO_CLKOUT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) -#define GPIO_CT32B0_MAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) -#define GPIO_SPI0_SSEL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) -#define GPIO_CT16B0_CAP0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) -#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) -#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_SPI0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) -#define GPIO_UART0_CTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) -#define GPIO_SPI0_MISO (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_CT16B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_SPI0_MOSI (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_CT16B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_JTAG_SWCLK (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_PIO0_10 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_SPI0_SCK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_CT16B0_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_PIO0_11 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_AD_inp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_CT32B0_MAT3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_PIO1_0 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_AD_inp1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_CT32B1_CAP0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_PIO1_1 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_AD_inp2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_CT32B1_MAT0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_PIO1_2 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) -#define GPIO_AD_inp3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) -#define GPIO_CT32B1_MAT1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) -#define GPIO_JTAG_SWDIO (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) -#define GPIO_PIO1_3 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) -#define GPIO_AD_inp4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) -#define GPIO_CT32B1_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) -#define GPIO_AD_inp5 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) -#define GPIO_CT32B1_MAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) -#define GPIO_UART0_RTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) -#define GPIO_CT32B0_CAP0 (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN5) -#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) -#define GPIO_CT32B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) -#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) -#define GPIO_CT32B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) -#define GPIO_CT16B1_CAP0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) -#define GPIO_CT16B1_MAT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9) -#define GPIO_AD_inp6 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) -#define GPIO_CT16B1_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) -#define GPIO_AD_inp7 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) -#define GPIO_UART0_DTR (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) - -#endif /* CONFIG_ARCH_CHIP_LPC1115 */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC116X_PINCONFIG_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_adc.h b/arch/arm/src/lpc11xx/hardware/lpc11_adc.h deleted file mode 100644 index a1566b05140..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_adc.h +++ /dev/null @@ -1,171 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_adc.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ -#define LPC11_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ -#define LPC11_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ - -#define LPC11_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) -#define LPC11_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ -#define LPC11_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ -#define LPC11_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ -#define LPC11_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ -#define LPC11_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ -#define LPC11_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ -#define LPC11_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ -#define LPC11_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ - -#define LPC11_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ - -/* Register addresses ***************************************************************/ - -#define LPC11_ADC_CR (LPC11_ADC_BASE+LPC11_ADC_CR_OFFSET) -#define LPC11_ADC_GDR (LPC11_ADC_BASE+LPC11_ADC_GDR_OFFSET) -#define LPC11_ADC_INTEN (LPC11_ADC_BASE+LPC11_ADC_INTEN_OFFSET) - -#define LPC11_ADC_DR(n) (LPC11_ADC_BASE+LPC11_ADC_DR_OFFSET(n)) -#define LPC11_ADC_DR0 (LPC11_ADC_BASE+LPC11_ADC_DR0_OFFSET) -#define LPC11_ADC_DR1 (LPC11_ADC_BASE+LPC11_ADC_DR1_OFFSET) -#define LPC11_ADC_DR2 (LPC11_ADC_BASE+LPC11_ADC_DR2_OFFSET) -#define LPC11_ADC_DR3 (LPC11_ADC_BASE+LPC11_ADC_DR3_OFFSET) -#define LPC11_ADC_DR4 (LPC11_ADC_BASE+LPC11_ADC_DR4_OFFSET) -#define LPC11_ADC_DR5 (LPC11_ADC_BASE+LPC11_ADC_DR5_OFFSET) -#define LPC11_ADC_DR6 (LPC11_ADC_BASE+LPC11_ADC_DR6_OFFSET) -#define LPC11_ADC_DR7 (LPC11_ADC_BASE+LPC11_ADC_DR7_OFFSET) - -#define LPC11_ADC_STAT (LPC11_ADC_BASE+LPC11_ADC_STAT_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* A/D Control Register */ - -#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */ -#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK) -#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */ -#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT) -#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */ -#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Clocks used on burst mode conv. */ -#define ADC_CR_CLKS_MASK (3 << ADC_CR_CLKS_SHIFT) - /* Bits 20-23: Reserved */ -#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */ -#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT) -# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */ -# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */ -# define ADC_CR_START_P0p2 (2 << ADC_CR_START_SHIFT) /* Start edge on P0.2/SSEL/CT16B0_CAP0 */ -# define ADC_CR_START_P1p5 (3 << ADC_CR_START_SHIFT) /* Start edge on P1.5/DIR/CT32B0_CAP0 */ -# define ADC_CR_START_CT32B0MAT0 (4 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT0 */ -# define ADC_CR_START_CT32B0MAT1 (5 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT1 */ -# define ADC_CR_START_CT16B0MAT0 (6 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT0 */ -# define ADC_CR_START_CT16B0MAT1 (7 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT1 */ -#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */ - /* Bits 28-31: Reserved */ -/* A/D Global Data Register AND Channel 0-7 Data Register */ - /* Bits 0-5: Reserved */ -#define ADC_DR_RESULT_SHIFT (5) /* Bits 6-15: Result of conversion (DONE==1) */ -#define ADC_DR_RESULT_MASK (0x3ff << ADC_DR_RESULT_SHIFT) - /* Bits 16-23: Reserved */ -#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */ -#define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT) - /* Bits 27-29: Reserved */ -#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ -#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/ - -/* A/D Interrupt Enable Register */ - -#define ADC_INTEN_CHAN(n) (1 << (n)) -#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */ -#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */ -#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */ -#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */ -#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */ -#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */ -#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */ -#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */ -#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */ - /* Bits 9-31: Reserved */ -/* A/D Status Register */ - -#define ADC_STAT_DONE(n) (1 << (n)) -#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */ -#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */ -#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */ -#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */ -#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */ -#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */ -#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */ -#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */ -#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8) -#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */ -#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */ -#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */ -#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */ -#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */ -#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */ -#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */ -#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */ -#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */ - /* Bits 17-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_gpio.h b/arch/arm/src/lpc11xx/hardware/lpc11_gpio.h deleted file mode 100644 index 93ae758a090..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_gpio.h +++ /dev/null @@ -1,146 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_gpio.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* GPIO block register offsets ******************************************************/ - -#define LPC11_GPIO0_OFFSET 0x00000 -#define LPC11_GPIO1_OFFSET 0x10000 -#define LPC11_GPIO2_OFFSET 0x20000 -#define LPC11_GPIO3_OFFSET 0x30000 -#define LPC11_GPIO_OFFSET(n) (0x10000*(n)) - -#define LPC11_GPIO_DATA_OFFSET 0x3FFC -#define LPC11_GPIO_DIR_OFFSET 0x8000 /* GPIO Port Direction control */ -#define LPC11_GPIO_IS_OFFSET 0x8004 /* Interrupt Sense register */ -#define LPC11_GPIO_IBE_OFFSET 0x8008 /* Interrupt Both Edges register */ -#define LPC11_GPIO_IEV_OFFSET 0x800c /* Interrupt Event register */ -#define LPC11_GPIO_IE_OFFSET 0x8010 /* Interrupt Mask register */ -#define LPC11_GPIO_RIS_OFFSET 0x8014 /* Raw interrupt status register */ -#define LPC11_GPIO_MIS_OFFSET 0x8018 /* Masked interrupt status register */ -#define LPC11_GPIO_IC_OFFSET 0x801c /* Interrupt clear register */ - -/* Register addresses ***************************************************************/ -/* GPIO block register addresses ****************************************************/ - -#define LPC11_GPIOn_BASE(n) (LPC11_GPIO_BASE+LPC11_GPIO_OFFSET(n)) -#define LPC11_GPIO0_BASE (LPC11_GPIO_BASE+LPC11_GPIO0_OFFSET) -#define LPC11_GPIO1_BASE (LPC11_GPIO_BASE+LPC11_GPIO1_OFFSET) -#define LPC11_GPIO2_BASE (LPC11_GPIO_BASE+LPC11_GPIO2_OFFSET) -#define LPC11_GPIO3_BASE (LPC11_GPIO_BASE+LPC11_GPIO3_OFFSET) - -#define LPC11_GPIO_DIR(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_DIR_OFFSET) /* GPIO Port Direction register */ -#define LPC11_GPIO_IS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IS_OFFSET) /* GPIO Interrupt Sense register */ -#define LPC11_GPIO_IBE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IBE_OFFSET) /* GPIO Interrupt Both Edges sense register */ -#define LPC11_GPIO_IEV(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IVE_OFFSET) /* GPIO Interrupt Event register */ -#define LPC11_GPIO_IE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IE_OFFSET) /* GPIO Interrupt Mask register */ -#define LPC11_GPIO_RIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_RIS_OFFSET) /* GPIO Raw Interrupt Status register */ -#define LPC11_GPIO_MIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_MIS_OFFSET) /* GPIO Masked Interrupt Status register */ -#define LPC11_GPIO_IC(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IC_OFFSET) /* GPIO Interrupt Clear register */ - -#define LPC11_GPIO0_DATA (LPC11_GPIO0_BASE+LPC11_GPIO_DATA_OFFSET) -#define LPC11_GPIO0_DIR (LPC11_GPIO0_BASE+LPC11_GPIO_DIR_OFFSET) -#define LPC11_GPIO0_IS (LPC11_GPIO0_BASE+LPC11_GPIO_IS_OFFSET) -#define LPC11_GPIO0_IBE (LPC11_GPIO0_BASE+LPC11_GPIO_IBE_OFFSET) -#define LPC11_GPIO0_IEV (LPC11_GPIO0_BASE+LPC11_GPIO_IVE_OFFSET) -#define LPC11_GPIO0_IE (LPC11_GPIO0_BASE+LPC11_GPIO_IE_OFFSET) -#define LPC11_GPIO0_RIS (LPC11_GPIO0_BASE+LPC11_GPIO_RIS_OFFSET) -#define LPC11_GPIO0_MIS (LPC11_GPIO0_BASE+LPC11_GPIO_MIS_OFFSET) -#define LPC11_GPIO0_IC (LPC11_GPIO0_BASE+LPC11_GPIO_IC_OFFSET) - -#define LPC11_GPIO1_DATA (LPC11_GPIO1_BASE+LPC11_GPIO_DATA_OFFSET) -#define LPC11_GPIO1_DIR (LPC11_GPIO1_BASE+LPC11_GPIO_DIR_OFFSET) -#define LPC11_GPIO1_IS (LPC11_GPIO1_BASE+LPC11_GPIO_IS_OFFSET) -#define LPC11_GPIO1_IBE (LPC11_GPIO1_BASE+LPC11_GPIO_IBE_OFFSET) -#define LPC11_GPIO1_IEV (LPC11_GPIO1_BASE+LPC11_GPIO_IVE_OFFSET) -#define LPC11_GPIO1_IE (LPC11_GPIO1_BASE+LPC11_GPIO_IE_OFFSET) -#define LPC11_GPIO1_RIS (LPC11_GPIO1_BASE+LPC11_GPIO_RIS_OFFSET) -#define LPC11_GPIO1_MIS (LPC11_GPIO1_BASE+LPC11_GPIO_MIS_OFFSET) -#define LPC11_GPIO1_IC (LPC11_GPIO1_BASE+LPC11_GPIO_IC_OFFSET) - -#define LPC11_GPIO2_DATA (LPC11_GPIO2_BASE+LPC11_GPIO_DATA_OFFSET) -#define LPC11_GPIO2_DIR (LPC11_GPIO2_BASE+LPC11_GPIO_DIR_OFFSET) -#define LPC11_GPIO2_IS (LPC11_GPIO2_BASE+LPC11_GPIO_IS_OFFSET) -#define LPC11_GPIO2_IBE (LPC11_GPIO2_BASE+LPC11_GPIO_IBE_OFFSET) -#define LPC11_GPIO2_IEV (LPC11_GPIO2_BASE+LPC11_GPIO_IVE_OFFSET) -#define LPC11_GPIO2_IE (LPC11_GPIO2_BASE+LPC11_GPIO_IE_OFFSET) -#define LPC11_GPIO2_RIS (LPC11_GPIO2_BASE+LPC11_GPIO_RIS_OFFSET) -#define LPC11_GPIO2_MIS (LPC11_GPIO2_BASE+LPC11_GPIO_MIS_OFFSET) -#define LPC11_GPIO2_IC (LPC11_GPIO2_BASE+LPC11_GPIO_IC_OFFSET) - -#define LPC11_GPIO3_DATA (LPC11_GPIO3_BASE+LPC11_GPIO_DATA_OFFSET) -#define LPC11_GPIO3_DIR (LPC11_GPIO3_BASE+LPC11_GPIO_DIR_OFFSET) -#define LPC11_GPIO3_IS (LPC11_GPIO3_BASE+LPC11_GPIO_IS_OFFSET) -#define LPC11_GPIO3_IBE (LPC11_GPIO3_BASE+LPC11_GPIO_IBE_OFFSET) -#define LPC11_GPIO3_IEV (LPC11_GPIO3_BASE+LPC11_GPIO_IVE_OFFSET) -#define LPC11_GPIO3_IE (LPC11_GPIO3_BASE+LPC11_GPIO_IE_OFFSET) -#define LPC11_GPIO3_RIS (LPC11_GPIO3_BASE+LPC11_GPIO_RIS_OFFSET) -#define LPC11_GPIO3_MIS (LPC11_GPIO3_BASE+LPC11_GPIO_MIS_OFFSET) -#define LPC11_GPIO3_IC (LPC11_GPIO3_BASE+LPC11_GPIO_IC_OFFSET) - -/* Register bit definitions *********************************************************/ -/* GPIO block register bit definitions **********************************************/ - -#define GPIO(n) (1 << (n)) /* n=0,1,..11 */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_i2c.h b/arch/arm/src/lpc11xx/hardware/lpc11_i2c.h deleted file mode 100644 index 84384fca051..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_i2c.h +++ /dev/null @@ -1,208 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_i2c.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ -#define LPC11_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ -#define LPC11_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ -#define LPC11_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ -#define LPC11_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ -#define LPC11_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ -#define LPC11_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ -#define LPC11_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ -#define LPC11_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ -#define LPC11_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ -#define LPC11_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ -#define LPC11_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ -#define LPC11_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ -#define LPC11_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ -#define LPC11_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ -#define LPC11_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ - -/* Register addresses ***************************************************************/ - -#define LPC11_I2C0_CONSET (LPC11_I2C0_BASE+LPC11_I2C_CONSET_OFFSET) -#define LPC11_I2C0_STAT (LPC11_I2C0_BASE+LPC11_I2C_STAT_OFFSET) -#define LPC11_I2C0_DAT (LPC11_I2C0_BASE+LPC11_I2C_DAT_OFFSET) -#define LPC11_I2C0_ADR0 (LPC11_I2C0_BASE+LPC11_I2C_ADR0_OFFSET) -#define LPC11_I2C0_SCLH (LPC11_I2C0_BASE+LPC11_I2C_SCLH_OFFSET) -#define LPC11_I2C0_SCLL (LPC11_I2C0_BASE+LPC11_I2C_SCLL_OFFSET) -#define LPC11_I2C0_CONCLR (LPC11_I2C0_BASE+LPC11_I2C_CONCLR_OFFSET) -#define LPC11_I2C0_MMCTRL (LPC11_I2C0_BASE+LPC11_I2C_MMCTRL_OFFSET) -#define LPC11_I2C0_ADR1 (LPC11_I2C0_BASE+LPC11_I2C_ADR1_OFFSET) -#define LPC11_I2C0_ADR2 (LPC11_I2C0_BASE+LPC11_I2C_ADR2_OFFSET) -#define LPC11_I2C0_ADR3 (LPC11_I2C0_BASE+LPC11_I2C_ADR3_OFFSET) -#define LPC11_I2C0_BUFR (LPC11_I2C0_BASE+LPC11_I2C_BUFR_OFFSET) -#define LPC11_I2C0_MASK0 (LPC11_I2C0_BASE+LPC11_I2C_MASK0_OFFSET) -#define LPC11_I2C0_MASK1 (LPC11_I2C0_BASE+LPC11_I2C_MASK1_OFFSET) -#define LPC11_I2C0_MASK2 (LPC11_I2C0_BASE+LPC11_I2C_MASK2_OFFSET) -#define LPC11_I2C0_MASK3 (LPC11_I2C0_BASE+LPC11_I2C_MASK3_OFFSET) - -#define LPC11_I2C1_CONSET (LPC11_I2C1_BASE+LPC11_I2C_CONSET_OFFSET) -#define LPC11_I2C1_STAT (LPC11_I2C1_BASE+LPC11_I2C_STAT_OFFSET) -#define LPC11_I2C1_DAT (LPC11_I2C1_BASE+LPC11_I2C_DAT_OFFSET) -#define LPC11_I2C1_ADR0 (LPC11_I2C1_BASE+LPC11_I2C_ADR0_OFFSET) -#define LPC11_I2C1_SCLH (LPC11_I2C1_BASE+LPC11_I2C_SCLH_OFFSET) -#define LPC11_I2C1_SCLL (LPC11_I2C1_BASE+LPC11_I2C_SCLL_OFFSET) -#define LPC11_I2C1_CONCLR (LPC11_I2C1_BASE+LPC11_I2C_CONCLR_OFFSET) -#define LPC11_I2C1_MMCTRL (LPC11_I2C1_BASE+LPC11_I2C_MMCTRL_OFFSET) -#define LPC11_I2C1_ADR1 (LPC11_I2C1_BASE+LPC11_I2C_ADR1_OFFSET) -#define LPC11_I2C1_ADR2 (LPC11_I2C1_BASE+LPC11_I2C_ADR2_OFFSET) -#define LPC11_I2C1_ADR3 (LPC11_I2C1_BASE+LPC11_I2C_ADR3_OFFSET) -#define LPC11_I2C1_BUFR (LPC11_I2C1_BASE+LPC11_I2C_BUFR_OFFSET) -#define LPC11_I2C1_MASK0 (LPC11_I2C1_BASE+LPC11_I2C_MASK0_OFFSET) -#define LPC11_I2C1_MASK1 (LPC11_I2C1_BASE+LPC11_I2C_MASK1_OFFSET) -#define LPC11_I2C1_MASK2 (LPC11_I2C1_BASE+LPC11_I2C_MASK2_OFFSET) -#define LPC11_I2C1_MASK3 (LPC11_I2C1_BASE+LPC11_I2C_MASK3_OFFSET) - -#define LPC11_I2C2_CONSET (LPC11_I2C2_BASE+LPC11_I2C_CONSET_OFFSET) -#define LPC11_I2C2_STAT (LPC11_I2C2_BASE+LPC11_I2C_STAT_OFFSET) -#define LPC11_I2C2_DAT (LPC11_I2C2_BASE+LPC11_I2C_DAT_OFFSET) -#define LPC11_I2C2_ADR0 (LPC11_I2C2_BASE+LPC11_I2C_ADR0_OFFSET) -#define LPC11_I2C2_SCLH (LPC11_I2C2_BASE+LPC11_I2C_SCLH_OFFSET) -#define LPC11_I2C2_SCLL (LPC11_I2C2_BASE+LPC11_I2C_SCLL_OFFSET) -#define LPC11_I2C2_CONCLR (LPC11_I2C2_BASE+LPC11_I2C_CONCLR_OFFSET) -#define LPC11_I2C2_MMCTRL (LPC11_I2C2_BASE+LPC11_I2C_MMCTRL_OFFSET) -#define LPC11_I2C2_ADR1 (LPC11_I2C2_BASE+LPC11_I2C_ADR1_OFFSET) -#define LPC11_I2C2_ADR2 (LPC11_I2C2_BASE+LPC11_I2C_ADR2_OFFSET) -#define LPC11_I2C2_ADR3 (LPC11_I2C2_BASE+LPC11_I2C_ADR3_OFFSET) -#define LPC11_I2C2_BUFR (LPC11_I2C2_BASE+LPC11_I2C_BUFR_OFFSET) -#define LPC11_I2C2_MASK0 (LPC11_I2C2_BASE+LPC11_I2C_MASK0_OFFSET) -#define LPC11_I2C2_MASK1 (LPC11_I2C2_BASE+LPC11_I2C_MASK1_OFFSET) -#define LPC11_I2C2_MASK2 (LPC11_I2C2_BASE+LPC11_I2C_MASK2_OFFSET) -#define LPC11_I2C2_MASK3 (LPC11_I2C2_BASE+LPC11_I2C_MASK3_OFFSET) - -/* Register bit definitions *********************************************************/ -/* I2C Control Set Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ - /* Bits 7-31: Reserved */ -/* I2C Control Clear Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ -#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ - /* Bit 4: Reserved */ -#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ -#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ - /* Bits 7-31: Reserved */ -/* I2C Status Register - * - * See tables 399-402 in the "LPC11xx User Manual" (UM10398), Rev. 01, 4 January - * 2010, NXP for definitions of status codes. - */ - -#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status - * Bits 0-1 always zero */ - /* Bits 8-31: Reserved */ -/* I2C Data Register */ - -#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ - /* Bits 8-31: Reserved */ -/* Monitor mode control register */ - -#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ -#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ -#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ - /* Bits 3-31: Reserved */ -/* Data buffer register */ - -#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ - /* Bits 8-31: Reserved */ -/* I2C Slave address registers: - * - * I2C Slave Address Register 0 - * I2C Slave Address Register 1 - * I2C Slave Address Register 2 - * I2C Slave Address Register 3 - */ - -#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ -#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ -#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Slave address mask registers: - * - * I2C Slave address mask register 0 - * I2C Slave address mask register 1 - * I2C Slave address mask register 2 - * I2C Slave address mask register 3 - */ - /* Bit 0: Reserved */ -#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ -#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* SCH Duty Cycle Register High Half Word */ - -#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ - /* Bits 16-31: Reserved */ -/* SCL Duty Cycle Register Low Half Word */ - -#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ - /* Bits 16-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h b/arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h deleted file mode 100644 index 24f6cdf1cce..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h +++ /dev/null @@ -1,73 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/* This file is only a thin shell that includes the correct memory map definitions - * for the selected LPC11xx family. - */ - -#include - -#if defined(LPC111x) -# include "hardware/lpc111x_memorymap.h" -#else -# error "Unrecognized LPC11xx family" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h b/arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h deleted file mode 100644 index 08c6ab11d1e..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h +++ /dev/null @@ -1,73 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/* This file is only a thin shell that includes the correct pin configuration - * definitions for the selected LPC11xx family. - */ - -#include - -#if defined(LPC111x) -# include "hardware/lpc111x_pinconfig.h" -#else -# error "Unrecognized LPC11xx family" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_pmu.h b/arch/arm/src/lpc11xx/hardware/lpc11_pmu.h deleted file mode 100644 index 226405bc038..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_pmu.h +++ /dev/null @@ -1,106 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_pmu.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_PMU_PCON_OFFSET 0x0000 /* Power control register */ -#define LPC11_PMU_GPREG0 0x0004 /* General purpose register 0 */ -#define LPC11_PMU_GPREG1 0x0008 /* General purpose register 1 */ -#define LPC11_PMU_GPREG2 0x000C /* General purpose register 2 */ -#define LPC11_PMU_GPREG3 0x0010 /* General purpose register 3 */ -#define LPC11_PMU_GPREG4 0x0014 /* General purpose register 0 */ - -/* Register addresses ***************************************************************/ - -#define LPC11_PMU_PCON (LPC11_PMU_BASE+LPC11_PMU_PCON_OFFSET) -#define LPC11_PMU_GPREG0 (LPC11_PMU_BASE+LPC11_PMU_GPREG0) -#define LPC11_PMU_GPREG1 (LPC11_PMU_BASE+LPC11_PMU_GPREG1) -#define LPC11_PMU_GPREG2 (LPC11_PMU_BASE+LPC11_PMU_GPREG2) -#define LPC11_PMU_GPREG3 (LPC11_PMU_BASE+LPC11_PMU_GPREG3) -#define LPC11_PMU_GPREG4 (LPC11_PMU_BASE+LPC11_PMU_GPREG4) - -/* Register bit definitions *********************************************************/ - -/* Power control register */ - /* Bit 0: Reserved. Do not write 1 to this bit */ -#define PMU_PCON_DPDEN (1 << 1) /* Deep power-down mode enable */ - /* Bits 2-7: Reserved. Do not write ones to this bit */ -#define PMU_PCON_SLEEPFLAG (1 << 8) /* Sleep mode flag */ - /* Bits 9-10: Reserved. Do not write ones to this bit */ -#define PMU_PCON_DPDFLAG (1 << 11) /* Deep power-down flag. */ - /* Bits 12-31: Reserved. Do not write ones to this bit */ - - -/* General Purpose REG */ - -#define PMU_GPREG03_GPDATA_MASK (0xffffffff) /* Bits 0-31: Data retained during Deep power-down mode */ - - -/* General Purpose REG4 Register */ - - /* Bits 0-9: Reserved. Do not write ones to this bit */ -#define PMU_GPREG4_WAKEUPHYS (1 << 10) /* WAKEUP pin hysteresis enable */ -#define PMU_GPREG4_GPDATA_SHIFT 11 /* Data retained during Deep power-down mode. */ -#define PMU_GPREG4_GPDATA_MASK (0x1fffff << PMU_GPREG4_GPDATA_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_ssp.h b/arch/arm/src/lpc11xx/hardware/lpc11_ssp.h deleted file mode 100644 index ad64d838408..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_ssp.h +++ /dev/null @@ -1,182 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_ssp.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SSP_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SSP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */ -#define LPC11_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */ -#define LPC11_SSP_DR_OFFSET 0x0008 /* Data Register */ -#define LPC11_SSP_SR_OFFSET 0x000c /* Status Register */ -#define LPC11_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */ -#define LPC11_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set/Clear Register */ -#define LPC11_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */ -#define LPC11_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */ -#define LPC11_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */ - -/* Register addresses ***************************************************************/ -/* SPI 0 */ -#define LPC11_SSP0_CR0 (LPC11_SPI0_BASE+LPC11_SSP_CR0_OFFSET) -#define LPC11_SSP0_CR1 (LPC11_SPI0_BASE+LPC11_SSP_CR1_OFFSET) -#define LPC11_SSP0_DR (LPC11_SPI0_BASE+LPC11_SSP_DR_OFFSET) -#define LPC11_SSP0_SR (LPC11_SPI0_BASE+LPC11_SSP_SR_OFFSET) -#define LPC11_SSP0_CPSR (LPC11_SPI0_BASE+LPC11_SSP_CPSR_OFFSET) -#define LPC11_SSP0_IMSC (LPC11_SPI0_BASE+LPC11_SSP_IMSC_OFFSET) -#define LPC11_SSP0_RIS (LPC11_SPI0_BASE+LPC11_SSP_RIS_OFFSET) -#define LPC11_SSP0_MIS (LPC11_SPI0_BASE+LPC11_SSP_MIS_OFFSET) -#define LPC11_SSP0_ICR (LPC11_SPI0_BASE+LPC11_SSP_ICR_OFFSET) - -/* SPI 1 */ -#define LPC11_SSP1_CR0 (LPC11_SPI1_BASE+LPC11_SSP_CR0_OFFSET) -#define LPC11_SSP1_CR1 (LPC11_SPI1_BASE+LPC11_SSP_CR1_OFFSET) -#define LPC11_SSP1_DR (LPC11_SPI1_BASE+LPC11_SSP_DR_OFFSET) -#define LPC11_SSP1_SR (LPC11_SPI1_BASE+LPC11_SSP_SR_OFFSET) -#define LPC11_SSP1_CPSR (LPC11_SPI1_BASE+LPC11_SSP_CPSR_OFFSET) -#define LPC11_SSP1_IMSC (LPC11_SPI1_BASE+LPC11_SSP_IMSC_OFFSET) -#define LPC11_SSP1_RIS (LPC11_SPI1_BASE+LPC11_SSP_RIS_OFFSET) -#define LPC11_SSP1_MIS (LPC11_SPI1_BASE+LPC11_SSP_MIS_OFFSET) -#define LPC11_SSP1_ICR (LPC11_SPI1_BASE+LPC11_SSP_ICR_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* SPI/SSP Control Register 0 */ - -#define SSP_CR0_DSS_SHIFT (0) /* Data Size Select */ -#define SSP_CR0_DSS_MASK (15 << SSP_CR0_SHIFT) -# define SSP_CR0_DSS_4BITS (3 << SSP_CR0_DSS_SHIFT) /* 4 bits per transfer */ -# define SSP_CR0_DSS_5BITS (4 << SSP_CR0_DSS_SHIFT) /* 5 bits per transfer */ -# define SSP_CR0_DSS_6BITS (5 << SSP_CR0_DSS_SHIFT) /* 6 bits per transfer */ -# define SSP_CR0_DSS_7BITS (6 << SSP_CR0_DSS_SHIFT) /* 7 bits per transfer */ -# define SSP_CR0_DSS_8BITS (7 << SSP_CR0_DSS_SHIFT) /* 8 bits per transfer */ -# define SSP_CR0_DSS_9BITS (8 << SSP_CR0_DSS_SHIFT) /* 9 bits per transfer */ -# define SSP_CR0_DSS_10BITS (9 << SSP_CR0_DSS_SHIFT) /* 10 bits per transfer */ -# define SSP_CR0_DSS_11BITS (10 << SSP_CR0_DSS_SHIFT) /* 11 bits per transfer */ -# define SSP_CR0_DSS_12BITS (11 << SSP_CR0_DSS_SHIFT) /* 12 bits per transfer */ -# define SSP_CR0_DSS_13BITS (12 << SSP_CR0_DSS_SHIFT) /* 13 bits per transfer */ -# define SSP_CR0_DSS_14BITS (13 << SSP_CR0_DSS_SHIFT) /* 14 bits per transfer */ -# define SSP_CR0_DSS_15BITS (14 << SSP_CR0_DSS_SHIFT) /* 15 bits per transfer */ -# define SSP_CR0_DSS_16BITS (15 << SSP_CR0_DSS_SHIFT) /* 16 bits per transfer */ -#define SSP_CR0_FRF_SHIFT (4) /* Frame Format */ -#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) /* SPI Frame Format */ -# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) /* TI Frame Format */ -# define SSP_CR0_FRF_MWIRE (2 << SSP_CR0_FRF_SHIFT) /* Microwire Frame Format */ - /* (3 << SSP_CR0_FRF_SHIFT) format is not supported */ -#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock polarity control */ -#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock phase control */ -#define SSP_CR0_SCR_SHIFT (8) /* Bit 8-15: Serial Clock Rate. PCLK/(CPSDVSR x [SCR + 1] */ -#define SSP_CR0_SCR_MASK (255 << SSP_CR0_SCR_SHIFT) - -/* SPI/SSP Control Register 1 */ - -#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */ -#define SSP_CR1_SSE (1 << 1) /* Bit 1: SPI Enable */ -#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */ -#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */ - /* Bits 4-31: Reserved */ - -/* SPI/SSP Data Register */ - -#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */ - /* Bits 16-31: Reserved */ -/* SPI/SSP Status Register */ - -#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */ -#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ -#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */ -#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */ -#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */ - /* Bits 5-31: Reserved */ -/* SPI/SSP Clock Prescale Register */ - -#define SSP_CPSR_DVSR_MASK (0xff) /* Even values between 2 and 254 */ - -/* SPI/SSP Interrupt Mask Set/Clear Register */ - -#define SSP_IMSC_RORIM (1 << 0) /* Bit 0: Enable Receive Overrun Interrupt */ -#define SSP_IMSC_RTIM (1 << 1) /* Bit 1: Enable Receive Timeout Interrupt */ -#define SSP_IMSC_RXIM (1 << 2) /* Bit 2: Enable Rx FIFO half full Interrupt */ -#define SSP_IMSC_TXIM (1 << 3) /* Bit 3: Enable Tx FIFO halt empty */ - /* Bits 4-31: Reserved */ - -/* SPI/SSP Raw Interrupt Status */ - -#define SSP_RIS_RORIS (1 << 0) /* Bit 0: An Overrun event occurred */ -#define SSP_RIS_RTRIS (1 << 1) /* Bit 1: Rx FIFO has data and MCU didn't read it */ -#define SSP_RIS_RXRIS (1 << 2) /* Bit 2: The Rx FIFO is at least half full */ -#define SSP_RIS_TXRIS (1 << 3) /* Bit 3: Tx FIFO is at least halt empty */ - /* Bits 4-31: Reserved */ - -/* SPI/SSP Masked Interrupt Status Register */ - -#define SSP_MIS_RORMIS (1 << 0) /* Bit 0: An Overrun occurred and this interrupt is enabled */ -#define SSP_MIS_RTMIS (1 << 1) /* Bit 1: An Rx FIFO timeout happened and this int is enabled */ -#define SSP_MIS_RXMIS (1 << 2) /* Bit 2: Rx FIFO is at least half empty and this int is enabled */ -#define SSP_MIS_TXMIS (1 << 3) /* Bit 3: Tx FIFO is at least halt full and this int is enabled */ - /* Bits 4-31: Reserved */ -/* SPI/SSP Interrupt Clear Register */ - -#define SSP_ICR_RORIC (1 << 0) /* Bit 0: Clear Rx FIFO Overrun Interrupt */ -#define SSP_ICR_RTIC (1 << 1) /* Bit 1: Clear Rx FIFO read timeout Interrupt */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SPI_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_syscon.h b/arch/arm/src/lpc11xx/hardware/lpc11_syscon.h deleted file mode 100644 index ac9a15477c1..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_syscon.h +++ /dev/null @@ -1,449 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/lpc11xx/hardware/lpc11_syscon.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define LPC11_SYSCON_SYSMEMREMAP_OFFSET 0x0000 /* System memory remap */ -#define LPC11_SYSCON_PRESETCTRL_OFFSET 0x0004 /* Pefipheral reset control */ -#define LPC11_SYSCON_SYSPLLCTRL_OFFSET 0x0008 /* System PLL control */ -#define LPC11_SYSCON_SYSPLLSTAT_OFFSET 0x000C /* System PLL status */ - /* 0x010 - 0x01c: Reserved */ - -#define LPC11_SYSCON_SYSOSCCTRL_OFFSET 0x0020 /* System oscillator control */ -#define LPC11_SYSCON_WDTOSCCTRL_OFFSET 0x0024 /* Watchdog oscillator control */ -#define LPC11_SYSCON_IRCCTRL_OFFSET 0x0028 /* IRC control */ - /* 0x02c: Reserved */ - -#define LPC11_SYSCON_SYSRSTSTAT_OFFSET 0x0030 /* System reset status register */ - /* 0x034 - 0x03c: Reserved */ - -#define LPC11_SYSCON_SYSPLLCLKSEL_OFFSET 0x0040 /* System PLL clock source select */ -#define LPC11_SYSCON_SYSPLLCLKUEN_OFFSET 0x0044 /* System PLL clock source update enable */ - /* 0x048 - 0x06c: Reserved */ - -#define LPC11_SYSCON_MAINCLKSEL_OFFSET 0x0070 /* Main clock source select */ -#define LPC11_SYSCON_MAINCLKUEN_OFFSET 0x0074 /* Main clock source update enable */ -#define LPC11_SYSCON_SYSAHBCLKDIV_OFFSET 0x0078 /* System AHB clock divider */ - /* 0x07c: Reserved */ - -#define LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET 0x0080 /* System AHB clock control */ - /* 0x084 - 0x090: Reserved */ - -#define LPC11_SYSCON_SSP0CLKDIV_OFFSET 0x0094 /* SPI0 clock divider */ -#define LPC11_SYSCON_UARTCLKDIV_OFFSET 0x0098 /* UART clock divider */ -#define LPC11_SYSCON_SSP1CLKDIV_OFFSET 0x009c /* SPI1 clock divider */ - /* 0x0a0 - 0x0cc: Reserved */ - -#define LPC11_SYSCON_WDTCLKSEL_OFFSET 0x00d0 /* WDT clock source select */ -#define LPC11_SYSCON_WDTCLKUEN_OFFSET 0x00d4 /* WDT clock source update enable */ -#define LPC11_SYSCON_WDTCLKDIV_OFFSET 0x00d8 /* WDT clock divider */ - /* 0x0dc: Reserved */ - -#define LPC11_SYSCON_CLKOUTCLKSEL_OFFSET 0x00e0 /* CLKOUT clock source select */ -#define LPC11_SYSCON_CLKOUTUEN_OFFSET 0x00e4 /* CLKOUT clock source update enable */ -#define LPC11_SYSCON_CLKOUTCLKDIV_OFFSET 0x00e8 /* CLKOUT clock divider */ - /* 0x0ec - 0x0fc: Reserved */ - -#define LPC11_SYSCON_PIOPORCAP0_OFFSET 0x0100 /* POR captured PIO status 0 */ -#define LPC11_SYSCON_PIOPORCAP1_OFFSET 0x0104 /* POR captured PIO status 1 */ - /* 0x108 - 0x14c: Reserved */ - -#define LPC11_SYSCON_BODCTRL_OFFSET 0x0150 /* BOD control */ -#define LPC11_SYSCON_SYSTCKCAL_OFFSET 0x0154 /* System tick counter calibration */ - /* 0x158 - 0x16c: Reserved */ - -#define LPC11_SYSCON_IRQLATENCY_OFFSET 0x0170 /* IRQ delay */ -#define LPC11_SYSCON_NMISRC_OFFSET 0x0174 /* NMI source selection */ - /* 0x178 - 0x1fc: Reserved */ - -#define LPC11_SYSCON_STARTAPRP0_OFFSET 0x0200 /* Start logic edge control register 0 */ -#define LPC11_SYSCON_STARTERP0_OFFSET 0x0204 /* Start logic signal enable register 0 */ -#define LPC11_SYSCON_STARTRSRP0CLR_OFFSET 0x0208 /* Start logic reset register 0 */ -#define LPC11_SYSCON_STARTSRP0_OFFSET 0x020c /* Start logic status register 0 */ - /* 0x210 - 0x22c: Reserved */ - -#define LPC11_SYSCON_PDSLEEPCFG_OFFSET 0x0230 /* Power-down states in Deep-sleep mode */ -#define LPC11_SYSCON_PDAWAKECFG_OFFSET 0x0234 /* Power-down states after wake-up from Deep-sleep mode */ -#define LPC11_SYSCON_PDRUNCFG_OFFSET 0x0238 /* Power-down configuration register */ - /* 0x023c - 0x3f0: Reserved */ -#define LPC11_SYSCON_DEVICE_ID_OFFSET 0x03f4 /* Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L */ - - -/* Register addresses ***********************************************************************/ - -#define LPC11_SYSCON_SYSMEMREMAP (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSMEMREMAP_OFFSET) - -#define LPC11_SYSCON_PRESETCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_PRESETCTRL_OFFSET) -#define LPC11_SYSCON_SYSPLLCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCTRL_OFFSET) -#define LPC11_SYSCON_SYSPLLSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLSTAT_OFFSET) - -#define LPC11_SYSCON_SYSOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSOSCCTRL_OFFSET) -#define LPC11_SYSCON_WDTOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTOSCCTRL_OFFSET) -#define LPC11_SYSCON_IRCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_IRCCTRL_OFFSET) - -#define LPC11_SYSCON_SYSRSTSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSRSTSTAT_OFFSET) - -#define LPC11_SYSCON_SYSPLLCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKSEL_OFFSET) -#define LPC11_SYSCON_SYSPLLCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKUEN_OFFSET) - -#define LPC11_SYSCON_MAINCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKSEL_OFFSET) -#define LPC11_SYSCON_MAINCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKUEN_OFFSET) - -#define LPC11_SYSCON_SYSAHBCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKDIV_OFFSET) -#define LPC11_SYSCON_SYSAHBCLKCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET) - -#define LPC11_SYSCON_SSP0CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP0CLKDIV_OFFSET) -#define LPC11_SYSCON_UARTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_UARTCLKDIV_OFFSET) -#define LPC11_SYSCON_SSP1CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP1CLKDIV_OFFSET) - -#define LPC11_SYSCON_WDTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKSEL_OFFSET) -#define LPC11_SYSCON_WDTCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKUEN_OFFSET) -#define LPC11_SYSCON_WDTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKDIV_OFFSET) - -#define LPC11_SYSCON_CLKOUTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKSEL_OFFSET) -#define LPC11_SYSCON_CLKOUTUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTUEN_OFFSET_OFFSET) -#define LPC11_SYSCON_CLKOUTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKDIV_OFFSET) - -#define LPC11_SYSCON_PIOPORCAP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP0_OFFSET) -#define LPC11_SYSCON_PIOPORCAP1 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP1_OFFSET) - -#define LPC11_SYSCON_BODCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_BODCTRL_OFFSET) -#define LPC11_SYSCON_SYSTCKCAL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSTCKCAL_OFFSET) - -#define LPC11_SYSCON_IRQLATENCY (LPC11_SYSCON_BASE + LPC11_SYSCON_IRQLATENCY_OFFSET) -#define LPC11_SYSCON_NMISRC (LPC11_SYSCON_BASE + LPC11_SYSCON_NMISRC_OFFSET) - -#define LPC11_SYSCON_STARTAPRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTAPRP0_OFFSET) -#define LPC11_SYSCON_STARTERP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTERP0_OFFSET) -#define LPC11_SYSCON_STARTRSRP0CLR (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTRSRP0CLR_OFFSET) -#define LPC11_SYSCON_STARTSRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTSRP0_OFFSET) - -#define LPC11_SYSCON_PDSLEEPCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDSLEEPCFG_OFFSET) -#define LPC11_SYSCON_PDAWAKECFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDAWAKECFG_OFFSET) -#define LPC11_SYSCON_PDRUNCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDRUNCFG_OFFSET) - -#define LPC11_SYSCON_DEVICE_ID (LPC11_SYSCON_BASE + LPC11_SYSCON_DEVICE_ID_OFFSET) - -/* Register bit definitions *****************************************************************/ - -#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0) /* Bits 0-1: System memory remap register */ -#define SYSCON_SYSMEMREMAP_MAP_MASK (3 << SYSCON_SYSMEMREMAP_MAP_SHIFT) -# define SYSCON_SYSMEMREMAP_MAP_BOOTLOADER (0 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Boot ROM */ -# define SYSCON_SYSMEMREMAP_MAP_RAM (1 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Static RAM */ -# define SYSCON_SYSMEMREMAP_MAP_FLASH (2 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are keeped in flash */ - /* Bits 2-31: Reserved */ - -#define SYSCON_PRESETCTRL_SSP0_RST_N (1 << 0) /* SPI0 reset control */ -#define SYSCON_PRESETCTRL_I2C0_RST_N (1 << 1) /* I2C0 reset control */ -#define SYSCON_PRESETCTRL_SSP1_RST_N (1 << 2) /* SPI1 reset control */ -#define SYSCON_PRESETCTRL_CAN_RST_N (1 << 3) /* C_CAN reset control */ - /* Bits 4-31: Reserved */ - -#define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0) /* Bits 0-4: Feedback divider value. */ -#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1f << SYSCON_SYSPLLCTRL_MSEL_SHIFT) -# define SYSCON_SYSPLLCTRL_MSEL_DIV(n) ((n-1) << SYSCON_SYSPLLCTRL_MSEL_SHIFT) /* n=1,2,3,..32 */ -#define SYSCON_SYSPLLCTRL_PSEL_SHIFT (5) /* Bits 5-6: Post divider ratio P. The division ratio is 2 x P */ -#define SYSCON_SYSPLLCTRL_PSEL_MASK (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) -# define SYSCON_SYSPLLCTRL_PSEL_DIV1 (0 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) -# define SYSCON_SYSPLLCTRL_PSEL_DIV2 (1 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) -# define SYSCON_SYSPLLCTRL_PSEL_DIV4 (2 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) -# define SYSCON_SYSPLLCTRL_PSEL_DIV8 (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) - /* Bits 7-31: Reserved */ - -#define SYSCON_SYSPLLSTAT_LOCK (1 << 0) /* PLL lock status. 0 = PLL not locked, 1 = PLL locked */ - /* Bits 1-31: Reserved */ - -#define SYSCON_SYSOSCCTRL_BYPASS (1 << 0) /* Bypass system oscillator */ -#define SYSCON_SYSOSCCTRL_FREQRANGE (1 << 1) /* Determines freq. range for low-power oscillator */ - /* Bits 2-31: Reserved */ -#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0) /* Bits 0-4: Select divider for Fclkana. wdt_osc_clk = Fclkana/(2x(1+DIVSEL)) */ -#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1f << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) -# define SYSCON_WDTOSCCTRL_DIVSEL(n) (((n-2)/2) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) /* n = 2,4,8,..64 */ -#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5) /* Bits 5-8: Select watchdog oscillator analog output frequency */ -#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) -# define SYSCON_WDTOSCCTRL_FREQSEL_0p6Mhz (1 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 0.6 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_1p05Mhz (2 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.05 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_1p4Mhz (3 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.4 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_1p75Mhz (4 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.75 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_2p1Mhz (5 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.1 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_2p4Mhz (6 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.4 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_2p7Mhz (7 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.7 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_3Mhz (8 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.0 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_3p25Mhz (9 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.25 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_3p5Mhz (10 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.5 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_3p75Mhz (11 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.75 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_4Mhz (12 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_4p2Mhz (13 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.2 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_4p4Mhz (14 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.4 MHz */ -# define SYSCON_WDTOSCCTRL_FREQSEL_4p6Mhz (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.6 MHz */ - /* Bits 9-31: Reserved */ - -#define SYSCON_IRCCTRL_TRIM_MASK (0xff) /* Bits 0-7: Trim value used to adjust on-chip 12 MHz oscillator */ - /* Bits 8-31: Reserved */ - -#define SYSCON_SYSRSTSTAT_POR (1 << 0) /* POR reset status */ -#define SYSCON_SYSRSTSTAT_EXTRST (1 << 1) /* Status of the external /RESET pin */ -#define SYSCON_SYSRSTSTAT_WDT (1 << 2) /* Status of the Watchdog reset */ -#define SYSCON_SYSRSTSTAT_BOD (1 << 3) /* Status of Brown-out detect reset */ -#define SYSCON_SYSRSTSTAT_SYSRST (1 << 4) /* Status of the software system reset */ - /* Bits 5-31: Reserved */ - -#define SYSCON_SYSPLLCLKSEL_SHIFT (0) /* Bits 0-1: System PLL clock source */ -#define SYSCON_SYSPLLCLKSEL_MASK (3 << SYSCON_SYSPLLCLKSEL_SHIFT) -# define SYSCON_SYSPLLCLKSEL_IRCOSC (0 << SYSCON_SYSPLLCLKSEL_SHIFT) -# define SYSCON_SYSPLLCLKSEL_SYSOSC (1 << SYSCON_SYSPLLCLKSEL_SHIFT) - /* Bits 2-31: Reserved */ - -#define SYSCON_SYSPLLCLKUEN_ENA (1 << 0) /* Bit 0: Enable system PLL clock source update */ - /* Bits 1-31: Reserved */ - -#define SYSCON_MAINCLKSEL_SHIFT (0) /* Bits 0-1: Clock source for main clock */ -#define SYSCON_MAINCLKSEL_MASK (3 << SYSCON_MAINCLKSEL_SHIFT) -# define SYSCON_MAINCLKSEL_IRCOSC (0 << SYSCON_MAINCLKSEL_SHIFT) /* IRC oscillator */ -# define SYSCON_MAINCLKSEL_PLLOSC (1 << SYSCON_MAINCLKSEL_SHIFT) /* Input clock to system PLL */ -# define SYSCON_MAINCLKSEL_WDTOSC (2 << SYSCON_MAINCLKSEL_SHIFT) /* WDT oscillator */ -# define SYSCON_MAINCLKSEL_SYSPLLCLKOUT (3 << SYSCON_MAINCLKSEL_SHIFT) /* System PLL clock out */ - /* Bits 2-31: Reserved */ - -#define SYSCON_MAINCLKUEN_ENA (1 << 0) /* Bit 0: Enable main clock source update */ - /* Bits 1-31: Reserved */ - -#define SYSCON_SYSAHBCLKDIV_SHIFT (0) /* Bits 0-7: 0=System clock disabled, 1=Divide by 1 ... 255 = Divide by 255 */ -#define SYSCON_SYSAHBCLKDIV_MASK (0xff << SYSCON_SYSAHBCLKDIV_SHIFT) - /* Bits 8-31: Reserved */ -//# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ - -#define SYSCON_SYSAHBCLKCTRL_SYS (1 << 0) /* Bit 0: Enables clock for AHB to APB bridge */ -#define SYSCON_SYSAHBCLKCTRL_ROM (1 << 1) /* Bit 1: Enables clock for ROM */ -#define SYSCON_SYSAHBCLKCTRL_RAM (1 << 2) /* Bit 2: Enables clock for RAM */ -#define SYSCON_SYSAHBCLKCTRL_FLASHREG (1 << 3) /* Bit 3: Enables clock for flash register interface */ -#define SYSCON_SYSAHBCLKCTRL_FLASHARRAY (1 << 4) /* Bit 4: Enables clock for flash array access */ -#define SYSCON_SYSAHBCLKCTRL_I2C0 (1 << 5) /* Bit 5: Enables clock for I2C0 */ -#define SYSCON_SYSAHBCLKCTRL_GPIO (1 << 6) /* Bit 6: Enables clock for GPIO */ -#define SYSCON_SYSAHBCLKCTRL_CT16B0 (1 << 7) /* Bit 7: Enables clock for 16-bit counter/timer 0 */ -#define SYSCON_SYSAHBCLKCTRL_CT16B1 (1 << 8) /* Bit 8: Enables clock for 16-bit counter/timer 1 */ -#define SYSCON_SYSAHBCLKCTRL_CT32B0 (1 << 9) /* Bit 9: Enables clock for 32-bit counter/timer 0 */ -#define SYSCON_SYSAHBCLKCTRL_CT32B1 (1 << 10) /* Bit 10: Enables clock for 32-bit counter/timer 1 */ -#define SYSCON_SYSAHBCLKCTRL_SSP0 (1 << 11) /* Bit 11: Enables clock for SPI0 */ -#define SYSCON_SYSAHBCLKCTRL_UART (1 << 12) /* Bit 12: Enables clock for UART */ -#define SYSCON_SYSAHBCLKCTRL_ADC (1 << 13) /* Bit 13: Enables clock for ADC */ - /* Bit 14: Reserved */ -#define SYSCON_SYSAHBCLKCTRL_WDT (1 << 15) /* Bit 15: Enables clock for WDT */ -#define SYSCON_SYSAHBCLKCTRL_IOCON (1 << 16) /* Bit 16: Enables clock for I/O configuration block */ -#define SYSCON_SYSAHBCLKCTRL_CAN (1 << 17) /* Bit 17: Enables clock for C_CAN */ -#define SYSCON_SYSAHBCLKCTRL_SSP1 (1 << 18) /* Bit 18: Enables clock for SPI1 */ - /* Bits 19-31: Reserved */ - -#define SYSCON_SSP0CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI0_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */ - /* Bits 8-31: Reserved */ - -#define SYSCON_UARTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable UART_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */ - /* Bits 8-31: Reserved */ - -#define SYSCON_SSP1CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI1_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */ - /* Bits 8-31: Reserved */ - -#define SYSCON_WDTCLKSEL_SHIFT (0) /* Bits 0-1: WDT clock source */ -#define SYSCON_WDTCLKSEL_MASK (3 << SYSCON_WDTCLKSEL_SHIFT) -# define SYSCON_WDTCLKSEL_IRCOSC (0 << SYSCON_WDTCLKSEL_SHIFT) /* IRC oscillator */ -# define SYSCON_WDTCLKSEL_MAINCLK (1 << SYSCON_WDTCLKSEL_SHIFT) /* Main clock */ -# define SYSCON_WDTCLKSEL_WDTOSC (2 << SYSCON_WDTCLKSEL_SHIFT) /* Watchdog oscillator */ - /* Bits 2-31: reserved */ - -#define SYSCON_WDTCLKUEN_ENA (1 << 0) /* Bit 0: Enable WDT clock source update */ - /* Bits 1-31: Reserved */ - -#define SYSCON_WDTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable WDCLK, 1=Divide by 1 ... 255 = Divide by 255 */ - /* Bits 8-31: Reserved */ - -#define SYSCON_CLKOUTCLKSEL_SHIFT (0) /* Bits 0-1: CLKOUT clock source */ -#define SYSCON_CLKOUTCLKSEL_MASK (3 << SYSCON_CLKOUTCLKSEL_SHIFT) -# define SYSCON_CLKOUTCLKSEL_IRCOSC (0 << SYSCON_CLKOUTCLKSEL_SHIFT) /* IRC oscillator */ -# define SYSCON_CLKOUTCLKSEL_SYSOSC (1 << SYSCON_CLKOUTCLKSEL_SHIFT) /* System oscillator */ -# define SYSCON_CLKOUTCLKSEL_WDTOSC (2 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Watchdog oscillator */ -# define SYSCON_CLKOUTCLKSEL_MAINCLK (3 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Main clock */ - /* Bits 2-31: Reserved */ - -#define SYSCON_CLKOUTUEN_ENA (1 << 0) /* Bit 0: Enable CLKOUT clock source update */ - /* Bits 1-31: Reserved */ - -#define SYSCON_CLKOUTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable CLKOUT, 1=Divide by 1 ... 255 = Divide by 255 */ - /* Bits 1-31: Reserved */ - -#define SYSCON_PIOPORCAP0_CAPPIO0_SHIFT (0) /* Bits 0-11: Raw reset stats input PIO0_n: PIO0_11 to PIO0_0 */ -#define SYSCON_PIOPORCAP0_CAPPIO0_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT) -# define SYSCON_PIOPORCAP0_CAPPIO0_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT) /* n = 0 to 11 */ - -#define SYSCON_PIOPORCAP0_CAPPIO1_SHIFT (12) /* Bits 12-23: Raw reset stats input PIO0_n: PIO1_11 to PIO1_0 */ -#define SYSCON_PIOPORCAP0_CAPPIO1_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT) -# define SYSCON_PIOPORCAP0_CAPPIO1_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT) /* n = 0 to 11 */ - -#define SYSCON_PIOPORCAP0_CAPPIO2_SHIFT (24) /* Bits 24-31: Raw reset stats input PIO0_n: PIO2_11 to PIO2_0 */ -#define SYSCON_PIOPORCAP0_CAPPIO2_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT) -# define SYSCON_PIOPORCAP0_CAPPIO2_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT) /* n = 0 to 11 */ - - -#define SYSCON_PIOPORCAP1_CAPPIO2_8 (1 << 0) /* Bit 0: Raw reset status input PIO2_8 */ -#define SYSCON_PIOPORCAP1_CAPPIO2_9 (1 << 1) /* Bit 1: Raw reset status input PIO2_9 */ -#define SYSCON_PIOPORCAP1_CAPPIO2_10 (1 << 2) /* Bit 2: Raw reset status input PIO2_10 */ -#define SYSCON_PIOPORCAP1_CAPPIO2_11 (1 << 3) /* Bit 3: Raw reset status input PIO2_11 */ -#define SYSCON_PIOPORCAP1_CAPPIO3_0 (1 << 4) /* Bit 4: Raw reset status input PIO3_0 */ -#define SYSCON_PIOPORCAP1_CAPPIO3_1 (1 << 5) /* Bit 5: Raw reset status input PIO3_1 */ -#define SYSCON_PIOPORCAP1_CAPPIO3_2 (1 << 6) /* Bit 6: Raw reset status input PIO3_2 */ -#define SYSCON_PIOPORCAP1_CAPPIO3_3 (1 << 7) /* Bit 7: Raw reset status input PIO3_3 */ -#define SYSCON_PIOPORCAP1_CAPPIO3_4 (1 << 8) /* Bit 8: Raw reset status input PIO3_4 */ -#define SYSCON_PIOPORCAP1_CAPPIO3_5 (1 << 9) /* Bit 9: Raw reset status input PIO3_5 */ - /* Bits 10-31: Reserved */ - -#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0) /* Bits 0-1: BOD reset level */ -#define SYSCON_BODCTRL_BODRSTLEV_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) -# define SYSCON_BODCTRL_BODRSTLEV_LEVEL0 (0 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 0: assert 1.46V, de-assert 1.63V */ -# define SYSCON_BODCTRL_BODRSTLEV_LEVEL1 (1 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 1: assert 2.06V, de-assert 2.15V */ -# define SYSCON_BODCTRL_BODRSTLEV_LEVEL2 (2 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 2: assert 2.35V, de-assert 2.43V */ -# define SYSCON_BODCTRL_BODRSTLEV_LEVEL3 (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 3: assert 2.63V, de-assert 2.71V */ -#define SYSCON_BODCTRL_BODINTVAL_SHIFT (2) /* Bits 2-3: BOD interrupt level */ -#define SYSCON_BODCTRL_BODINTVAL_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_BODINTVAL_SHIFT) -# define SYSCON_BODCTRL_BODINTVAL_LEVEL0 (0 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 0: Reserved */ -# define SYSCON_BODCTRL_BODINTVAL_LEVEL1 (1 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 1: int. assert 2.22V,de-a. 2.35V */ -# define SYSCON_BODCTRL_BODINTVAL_LEVEL2 (2 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 2: int. assert 2.52V,de-a. 2.66V */ -# define SYSCON_BODCTRL_BODINTVAL_LEVEL3 (3 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 3: int. assert 2.80V,de-a. 2.90V */ -#define SYSCON_BODCTRL_BODRSTENA (1 << 4) /* BOD reset enable */ - /* Bits 5-31: Reserved */ - -#define SYSCON_SYSTCKCAL_CAL 0x3ffffff /* Bits 0-25: System tick timer calibration value */ - /* Bits 26-31: Reserved */ - -#define SYSCON_IRQLATENCY_LATENCY_MASK (0xff) /* Bits 0-7: 8-bit latency value */ - /* Bits 8-31: Reserved */ - -#define SYSCON_NMISRC_IRQNO_SHIFT (0) /* Bits 0-4: The IRQ number of interrupt that acts as NMI if bit 31 is 1 */ -#define SYSCON_NMISRC_IRQNO_MASK (31 << SYSCON_NMISRC_IRQNO_SHIFT) - /* Bits 5-30: Reserved */ -#define SYSCON_NMISRC_NMIEN (1 << 31) /* Write 1 to this bit to enable NMI source selected by bits 4:0 */ - -#define SYSCON_STARTAPRP0_APRPIO0_SHIFT (0) /* Bits 0-11: Edge select for start logic input PIO0_[0-11], 0=fall/1=rise */ -#define SYSCON_STARTAPRP0_APRPIO0_MASK (0xfff << SYSCON_STARTAPRP0_APRPIO0_SHIFT) -# define SYSCON_STARTAPRP0_APRPIO0_BIT(n) ((1 << n) << SYSCON_STARTAPRP0_APRPIO0_SHIFT) /* n = 0 to 11 */ -#define SYSCON_STARTAPRP0_APRPIO1_0 (1 << 12) /* Bit 12: Edge select start logic input PIO1_0, 0=falling/1=rising */ - /* Bits 13-31: Reserved */ - -#define SYSCON_STARTERP0_ERPIO0_SHIFT (0) /* Bits 0-11: Enable start signal for start logic input PIO0[0-11] */ -#define SYSCON_STARTERP0_ERPIO0_MASK (0xfff << SYSCON_STARTERP0_ERPIO0_SHIFT) -# define SYSCON_STARTERP0_ERPIO0_BIT(n) ((1 << n) << SYSCON_STARTERP0_ERPIO0_SHIFT) /* n = 0 to 11 */ -#define SYSCON_STARTERP0_ERPIO1_0 (1 << 12) /* Bit 12: Enable start signal for start logic input PIO1_0 */ - /* Bits 13-31: Reserved */ - -#define SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT (0) /* Bits 0-11: Start logic reset register 0 */ -#define SYSCON_STARTRSRP0CLR_RSRPIO0_MASK (0xfff << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT) -# define SYSCON_STARTRSRP0CLR_RSRPIO0_BIT(n) ((1 << n) << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT) /* n = 0 to 11 */ -#define SYSCON_STARTRSRP0CLR_RSRPIO1_0 (1 << 12) /* Bit 12: Start signal reset for start logic input PIO1_0 */ - /* Bits 13-31: Reserved */ - -#define SYSCON_STARTSRP0_SRPIO0_SHIFT (0) /* Bits 0-11: Start logic status register 0 */ -#define SYSCON_STARTSRP0_SRPIO0_MASK (0xfff << SYSCON_STARTSRP0_SRPIO0_SHIFT) -# define SYSCON_STARTSRP0_SRPIO0_BIT(n) ((1 << n) << SYSCON_STARTSRP0_SRPIO0_SHIFT) /* n = 0 to 11 */ -#define SYSCON_STARTSRP0_SRPIO1_0 (1 << 12) /* Bit 12: Start signal status for start logic input PIO1_0 */ - /* Bits 13-31: Reserved */ - - /* Bits 0-2: Reserved. NOTE: Always write these bits as 111 */ -#define SYSCON_PDSLEEPCFG_BOD_PD (1 << 3) /* BOD power-down control in Deep-sleep mode */ - /* Bits 4-5: Reserved. NOTE: Always write these bits as 11 */ -#define SYSCON_PDSLEEPCFG_WDTOSC_PD (1 << 6) /* Watchdog oscillator power control in Deep-sleep mode */ - /* Bit 7: Reserved. NOTE: Always write this bit as 1 */ - /* Bits 8-10: Reserved NOTE: Always write these bits as 000 */ - /* Bits 11-12: Reserved. NOTE: Always write these bits as 11 */ - /* Bits 13-31: Reserved */ - -#define SYSCON_PDAWAKECFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output wake-up configuration */ -#define SYSCON_PDAWAKECFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator wake-up configuration */ -#define SYSCON_PDAWAKECFG_FLASH_PD (1 << 2) /* Bit 2: Flash wake-up configuration */ -#define SYSCON_PDAWAKECFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection wake-up configuration */ -#define SYSCON_PDAWAKECFG_ADC_PD (1 << 4) /* Bit 4: ADC wake-up configuration */ -#define SYSCON_PDAWAKECFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator wake-up configuration */ -#define SYSCON_PDAWAKECFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator wake-up configuration */ -#define SYSCON_PDAWAKECFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL wake-up configuration */ - /* Bit 8: Reserved. NOTE: Always write this bit as 1 */ - /* Bit 9: Reserved. NOTE: Always write this bit as 0 */ - /* Bit 10: Reserved. NOTE: Always write this bit as 1 */ - /* Bit 11: Reserved. NOTE: Always write this bit as 1 */ - /* Bit 12: Reserved. NOTE: Always write this bit as 0 */ - /* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */ - /* Bits 16-31: Reserved */ - -#define SYSCON_PDRUNCFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output power-down */ -#define SYSCON_PDRUNCFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator power-down */ -#define SYSCON_PDRUNCFG_FLASH_PD (1 << 2) /* Bit 2: Flash power-down */ -#define SYSCON_PDRUNCFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection power-down */ -#define SYSCON_PDRUNCFG_ADC_PD (1 << 4) /* Bit 4: ADC power-down */ -#define SYSCON_PDRUNCFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator power-down */ -#define SYSCON_PDRUNCFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator power-down */ -#define SYSCON_PDRUNCFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL power-down */ - /* Bit 8: Reserved. NOTE: Always write this bit as 1 */ - /* Bit 9: Reserved. NOTE: Always write this bit as 0 */ - /* Bit 10: Reserved. NOTE: Always write this bit as 1 */ - /* Bit 11: Reserved. NOTE: Always write this bit as 1 */ - /* Bit 12: Reserved. NOTE: Always write this bit as 0 */ - /* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */ - /* Bits 16-31: Reserved */ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -/******************************************************************************************** - * Public Data - ********************************************************************************************/ - -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_timer.h b/arch/arm/src/lpc11xx/hardware/lpc11_timer.h deleted file mode 100644 index cc343f28c0a..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_timer.h +++ /dev/null @@ -1,271 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_timer.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ -#define LPC11_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */ -#define LPC11_TMR_TC_OFFSET 0x0008 /* Timer Counter */ -#define LPC11_TMR_PR_OFFSET 0x000c /* Prescale Register */ -#define LPC11_TMR_PC_OFFSET 0x0010 /* Prescale Counter */ -#define LPC11_TMR_MCR_OFFSET 0x0014 /* Match Control Register */ -#define LPC11_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */ -#define LPC11_TMR_MR1_OFFSET 0x001c /* Match Register 1 */ -#define LPC11_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */ -#define LPC11_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */ -#define LPC11_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */ -#define LPC11_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */ -#define LPC11_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */ -#define LPC11_TMR_EMR_OFFSET 0x003c /* External Match Register */ -#define LPC11_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */ -#define LPC11_TMR_PWMC_OFFSET 0x0074 /* PWM Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC11_TMR16B0IR (LPC11_TMR16B0_BASE+LPC11_TMR_IR_OFFSET) -#define LPC11_TMR16B0TCR (LPC11_TMR16B0_BASE+LPC11_TMR_TCR_OFFSET) -#define LPC11_TMR16B0TC (LPC11_TMR16B0_BASE+LPC11_TMR_TC_OFFSET) -#define LPC11_TMR16B0PR (LPC11_TMR16B0_BASE+LPC11_TMR_PR_OFFSET) -#define LPC11_TMR16B0PC (LPC11_TMR16B0_BASE+LPC11_TMR_PC_OFFSET) -#define LPC11_TMR16B0MCR (LPC11_TMR16B0_BASE+LPC11_TMR_MCR_OFFSET) -#define LPC11_TMR16B0MR0 (LPC11_TMR16B0_BASE+LPC11_TMR_MR0_OFFSET) -#define LPC11_TMR16B0MR1 (LPC11_TMR16B0_BASE+LPC11_TMR_MR1_OFFSET) -#define LPC11_TMR16B0MR2 (LPC11_TMR16B0_BASE+LPC11_TMR_MR2_OFFSET) -#define LPC11_TMR16B0MR3 (LPC11_TMR16B0_BASE+LPC11_TMR_MR3_OFFSET) -#define LPC11_TMR16B0CCR (LPC11_TMR16B0_BASE+LPC11_TMR_CCR_OFFSET) -#define LPC11_TMR16B0CR0 (LPC11_TMR16B0_BASE+LPC11_TMR_CR0_OFFSET) -#define LPC11_TMR16B0CR1 (LPC11_TMR16B0_BASE+LPC11_TMR_CR1_OFFSET) -#define LPC11_TMR16B0EMR (LPC11_TMR16B0_BASE+LPC11_TMR_EMR_OFFSET) -#define LPC11_TMR16B0CTCR (LPC11_TMR16B0_BASE+LPC11_TMR_CTCR_OFFSET) -#define LPC11_TMR16B0PWMC (LPC11_TMR16B0_BASE+LPC11_TMR_PWMC_OFFSET) - -#define LPC11_TMR16B1IR (LPC11_TMR16B1_BASE+LPC11_TMR_IR_OFFSET) -#define LPC11_TMR16B1TCR (LPC11_TMR16B1_BASE+LPC11_TMR_TCR_OFFSET) -#define LPC11_TMR16B1TC (LPC11_TMR16B1_BASE+LPC11_TMR_TC_OFFSET) -#define LPC11_TMR16B1PR (LPC11_TMR16B1_BASE+LPC11_TMR_PR_OFFSET) -#define LPC11_TMR16B1PC (LPC11_TMR16B1_BASE+LPC11_TMR_PC_OFFSET) -#define LPC11_TMR16B1MCR (LPC11_TMR16B1_BASE+LPC11_TMR_MCR_OFFSET) -#define LPC11_TMR16B1MR0 (LPC11_TMR16B1_BASE+LPC11_TMR_MR0_OFFSET) -#define LPC11_TMR16B1MR1 (LPC11_TMR16B1_BASE+LPC11_TMR_MR1_OFFSET) -#define LPC11_TMR16B1MR2 (LPC11_TMR16B1_BASE+LPC11_TMR_MR2_OFFSET) -#define LPC11_TMR16B1MR3 (LPC11_TMR16B1_BASE+LPC11_TMR_MR3_OFFSET) -#define LPC11_TMR16B1CCR (LPC11_TMR16B1_BASE+LPC11_TMR_CCR_OFFSET) -#define LPC11_TMR16B1CR0 (LPC11_TMR16B1_BASE+LPC11_TMR_CR0_OFFSET) -#define LPC11_TMR16B1CR1 (LPC11_TMR16B1_BASE+LPC11_TMR_CR1_OFFSET) -#define LPC11_TMR16B1EMR (LPC11_TMR16B1_BASE+LPC11_TMR_EMR_OFFSET) -#define LPC11_TMR16B1CTCR (LPC11_TMR16B1_BASE+LPC11_TMR_CTCR_OFFSET) -#define LPC11_TMR16B1PWMC (LPC11_TMR16B1_BASE+LPC11_TMR_PWMC_OFFSET) - -#define LPC11_TMR32B0IR (LPC11_TMR32B0_BASE+LPC11_TMR_IR_OFFSET) -#define LPC11_TMR32B0TCR (LPC11_TMR32B0_BASE+LPC11_TMR_TCR_OFFSET) -#define LPC11_TMR32B0TC (LPC11_TMR32B0_BASE+LPC11_TMR_TC_OFFSET) -#define LPC11_TMR32B0PR (LPC11_TMR32B0_BASE+LPC11_TMR_PR_OFFSET) -#define LPC11_TMR32B0PC (LPC11_TMR32B0_BASE+LPC11_TMR_PC_OFFSET) -#define LPC11_TMR32B0MCR (LPC11_TMR32B0_BASE+LPC11_TMR_MCR_OFFSET) -#define LPC11_TMR32B0MR0 (LPC11_TMR32B0_BASE+LPC11_TMR_MR0_OFFSET) -#define LPC11_TMR32B0MR1 (LPC11_TMR32B0_BASE+LPC11_TMR_MR1_OFFSET) -#define LPC11_TMR32B0MR2 (LPC11_TMR32B0_BASE+LPC11_TMR_MR2_OFFSET) -#define LPC11_TMR32B0MR3 (LPC11_TMR32B0_BASE+LPC11_TMR_MR3_OFFSET) -#define LPC11_TMR32B0CCR (LPC11_TMR32B0_BASE+LPC11_TMR_CCR_OFFSET) -#define LPC11_TMR32B0CR0 (LPC11_TMR32B0_BASE+LPC11_TMR_CR0_OFFSET) -#define LPC11_TMR32B0CR1 (LPC11_TMR32B0_BASE+LPC11_TMR_CR1_OFFSET) -#define LPC11_TMR32B0EMR (LPC11_TMR32B0_BASE+LPC11_TMR_EMR_OFFSET) -#define LPC11_TMR32B0CTCR (LPC11_TMR32B0_BASE+LPC11_TMR_CTCR_OFFSET) -#define LPC11_TMR32B0PWMC (LPC11_TMR32B0_BASE+LPC11_TMR_PWMC_OFFSET) - -#define LPC11_TMR32B1IR (LPC11_TMR32B1_BASE+LPC11_TMR_IR_OFFSET) -#define LPC11_TMR32B1TCR (LPC11_TMR32B1_BASE+LPC11_TMR_TCR_OFFSET) -#define LPC11_TMR32B1TC (LPC11_TMR32B1_BASE+LPC11_TMR_TC_OFFSET) -#define LPC11_TMR32B1PR (LPC11_TMR32B1_BASE+LPC11_TMR_PR_OFFSET) -#define LPC11_TMR32B1PC (LPC11_TMR32B1_BASE+LPC11_TMR_PC_OFFSET) -#define LPC11_TMR32B1MCR (LPC11_TMR32B1_BASE+LPC11_TMR_MCR_OFFSET) -#define LPC11_TMR32B1MR0 (LPC11_TMR32B1_BASE+LPC11_TMR_MR0_OFFSET) -#define LPC11_TMR32B1MR1 (LPC11_TMR32B1_BASE+LPC11_TMR_MR1_OFFSET) -#define LPC11_TMR32B1MR2 (LPC11_TMR32B1_BASE+LPC11_TMR_MR2_OFFSET) -#define LPC11_TMR32B1MR3 (LPC11_TMR32B1_BASE+LPC11_TMR_MR3_OFFSET) -#define LPC11_TMR32B1CCR (LPC11_TMR32B1_BASE+LPC11_TMR_CCR_OFFSET) -#define LPC11_TMR32B1CR0 (LPC11_TMR32B1_BASE+LPC11_TMR_CR0_OFFSET) -#define LPC11_TMR32B1CR1 (LPC11_TMR32B1_BASE+LPC11_TMR_CR1_OFFSET) -#define LPC11_TMR32B1EMR (LPC11_TMR32B1_BASE+LPC11_TMR_EMR_OFFSET) -#define LPC11_TMR32B1CTCR (LPC11_TMR32B1_BASE+LPC11_TMR_CTCR_OFFSET) -#define LPC11_TMR32B1PWMC (LPC11_TMR32B1_BASE+LPC11_TMR_PWMC_OFFSET) - - -/* Register bit definitions *********************************************************/ -/* Registers holding 32-bit numeric values (no bit field definitions): - * - * Timer Counter (TC) - * Prescale Register (PR) - * Prescale Counter (PC) - * Match Register 0 (MR0) - * Match Register 1 (MR1) - * Match Register 2 (MR2) - * Match Register 3 (MR3) - * Capture Register 0 (CR0) - * Capture Register 1 (CR1) - */ - -/* Interrupt Register */ - -#define TMR_MR0INT (1 << 0) /* Bit 0: Match channel 0 interrupt */ -#define TMR_MR1INT (1 << 1) /* Bit 1: Match channel 1 interrupt */ -#define TMR_MR2INT (1 << 2) /* Bit 2: Match channel 2 interrupt */ -#define TMR_MR3INT (1 << 3) /* Bit 3: Match channel 3 interrupt */ -#define TMR_CR0INT (1 << 4) /* Bit 4: Capture channel 0 interrupt */ -#define TMR_CR1INT (1 << 5) /* Bit 5: Capture channel 1 interrupt */ - /* Bits 6-31: Reserved */ -/* Timer Control Register */ - -#define TMR_TCR_CEN (1 << 0) /* Bit 0: Counter Enable */ -#define TMR_TCR_CRST (1 << 1) /* Bit 1: Counter Reset */ - /* Bits 2-31: Reserved */ -/* Match Control Register */ - -#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ -#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ -#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ -#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ -#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ -#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ -#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ -#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ -#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ -#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ -#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ -#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ - /* Bits 12-31: Reserved */ -/* Capture Control Register */ - -#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ -#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */ -#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ -#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ -#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */ -#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ - /* Bits 6-31: Reserved */ -/* External Match Register */ - -#define TMR_EMR_NOTHING (0) /* Do Nothing */ -#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */ -#define TMR_EMR_SET (2) /* Set external match bit MATn.m */ -#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */ - -#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */ -#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */ -#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */ -#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */ -#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */ -#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy) -# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT) -#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */ -#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT) -#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */ -#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT) -#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */ -#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT) - /* Bits 12-31: Reserved */ -/* Count Control Register */ - -#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ -#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT) -# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */ -# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ -# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ -# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ -#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ -#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT) -# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ -# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */ -#define TMR_CTCR_ENCC (1 << 4) /* Enable Clear Timer/Prescale when capture event happens */ -#define TMR_CTCR_SELCC_SHIFT (5) /* Bits 5-7: Selects which capture event will clear Timer/Prescale */ -#define TMR_CTCR_SELCC_MASK (3 << TMR_CTCR_SELCC_SHIFT) -# define TMR_CTCR_SELCC_RECAP0 (0 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP0 clears timer (if bit 4 is set) */ -# define TMR_CTCR_SELCC_FECAP0 (1 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP0 clears timer (if bit 4 is set) */ -# define TMR_CTCR_SELCC_RECAP1 (2 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP1 clears timer (if bit 4 is set) */ -# define TMR_CTCR_SELCC_FECAP1 (3 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP1 clears timer (if bit 4 is set) */ - /* Bits 8-31: Reserved */ - -/* PWM Control register */ - -#define TMR_PWMC_PWMEN0 (1 << 0) /* PWM channel0 enable */ -#define TMR_PWMC_PWMEN1 (1 << 1) /* PWM channel1 enable */ -#define TMR_PWMC_PWMEN2 (1 << 2) /* PWM channel2 enable */ -#define TMR_PWMC_PWMEN3 (1 << 3) /* PWM channel3 enable */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_uart.h b/arch/arm/src/lpc11xx/hardware/lpc11_uart.h deleted file mode 100644 index a8be2e9bbe0..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_uart.h +++ /dev/null @@ -1,261 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_uart.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */ -#define LPC11_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */ -#define LPC11_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */ -#define LPC11_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */ -#define LPC11_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */ -#define LPC11_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */ -#define LPC11_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */ -#define LPC11_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */ -#define LPC11_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */ -#define LPC11_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */ -#define LPC11_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */ -#define LPC11_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */ -#define LPC11_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */ -#define LPC11_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */ -#define LPC11_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */ -#define LPC11_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */ -#define LPC11_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */ -#define LPC11_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */ - -/* Register addresses ***************************************************************/ - -#define LPC11_UART0_RBR (LPC11_UART0_BASE+LPC11_UART_RBR_OFFSET) -#define LPC11_UART0_THR (LPC11_UART0_BASE+LPC11_UART_THR_OFFSET) -#define LPC11_UART0_DLL (LPC11_UART0_BASE+LPC11_UART_DLL_OFFSET) -#define LPC11_UART0_DLM (LPC11_UART0_BASE+LPC11_UART_DLM_OFFSET) -#define LPC11_UART0_IER (LPC11_UART0_BASE+LPC11_UART_IER_OFFSET) -#define LPC11_UART0_IIR (LPC11_UART0_BASE+LPC11_UART_IIR_OFFSET) -#define LPC11_UART0_FCR (LPC11_UART0_BASE+LPC11_UART_FCR_OFFSET) -#define LPC11_UART0_LCR (LPC11_UART0_BASE+LPC11_UART_LCR_OFFSET) -#define LPC11_UART0_MCR (LPC11_UART0_BASE+LPC11_UART_MCR_OFFSET) -#define LPC11_UART0_LSR (LPC11_UART0_BASE+LPC11_UART_LSR_OFFSET) -#define LPC11_UART0_SCR (LPC11_UART0_BASE+LPC11_UART_SCR_OFFSET) -#define LPC11_UART0_ACR (LPC11_UART0_BASE+LPC11_UART_ACR_OFFSET) -#define LPC11_UART0_ICR (LPC11_UART0_BASE+LPC11_UART_ICR_OFFSET) -#define LPC11_UART0_FDR (LPC11_UART0_BASE+LPC11_UART_FDR_OFFSET) -#define LPC11_UART0_TER (LPC11_UART0_BASE+LPC11_UART_TER_OFFSET) -#define LPC11_UART0_RS485CTRL (LPC11_UART0_BASE+LPC11_UART_RS485CTRL_OFFSET) -#define LPC11_UART0_ADRMATCH (LPC11_UART0_BASE+LPC11_UART_ADRMATCH_OFFSET) -#define LPC11_UART0_RS485DLY (LPC11_UART0_BASE+LPC11_UART_RS485DLY_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* RBR (DLAB =0) Receiver Buffer Register (all) */ - -#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ - /* Bits 8-31: Reserved */ - -/* THR (DLAB =0) Transmit Holding Register (all) */ - -#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ - /* Bits 8-31: Reserved */ - -/* DLL (DLAB =1) Divisor Latch LSB (all) */ - -#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ - /* Bits 8-31: Reserved */ - -/* DLM (DLAB =1) Divisor Latch MSB (all) */ - -#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ - /* Bits 8-31: Reserved */ - -/* IER (DLAB =0) Interrupt Enable Register (all) */ - -#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */ -#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */ -#define UART_IER_RXLIE (1 << 2) /* Bit 2: RX Line Interrupt Enable */ - /* Bits 3-7: Reserved */ -#define UART_IER_ABEOINTEN (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ -#define UART_IER_ABTOINTEN (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ - /* Bits 10-31: Reserved */ -#define UART_IER_ALLIE (0x038f) - -/* IIR Interrupt ID Register (all) */ - -#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ -#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ -#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) -# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Interrupt */ -# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ -# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */ -# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ -# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ - /* Bits 4-5: Reserved */ -#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ -#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) -#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ -#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ - /* Bits 10-31: Reserved */ -/* FCR FIFO Control Register (all) */ - -#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ -#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ -#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ - /* Bits 3-5: Reserved */ -#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ -#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) -# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ -# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ -# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ -# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ - /* Bits 8-31: Reserved */ -/* LCR Line Control Register (all) */ - -#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ -#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) -#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */ -#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */ -#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */ -#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT) -# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */ -# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */ -# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */ -# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */ -#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ -#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ - /* Bits 8-31: Reserved */ -/* MCR Modem Control Register (UART1 only) */ - -#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ -#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ - /* Bits 2-3: Reserved */ -#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ - /* Bit 5: Reserved */ -#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */ -#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */ - /* Bits 8-31: Reserved */ -/* LSR Line Status Register (all) */ - -#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */ -#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ -#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ -#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ -#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ -#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ -#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ -#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ - /* Bits 8-31: Reserved */ -/* MSR Modem Status Register (UART1 only) */ - -#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */ -#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */ -#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */ -#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */ -#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */ -#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */ -#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */ -#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */ - /* Bits 8-31: Reserved */ -/* SCR Scratch Pad Register (all) */ - -#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ - /* Bits 8-31: Reserved */ -/* ACR Auto-baud Control Register (all) */ - -#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/ -#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/ -#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/ - /* Bits 3-7: Reserved */ -#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ -#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ - /* Bits 10-31: Reserved */ - -/* FDR Fractional Divider Register (all) */ - -#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */ -#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT) -#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT) - /* Bits 8-31: Reserved */ -/* TER Transmit Enable Register (all) */ - /* Bits 0-6: Reserved */ -#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */ - /* Bits 8-31: Reserved */ -/* RS-485/EIA-485 Control */ - -#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */ -#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */ -#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */ -#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */ -#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */ -#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */ - /* Bits 6-31: Reserved */ -/* RS-485/EIA-485 address match */ - -#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */ - /* Bits 8-31: Reserved */ -/* RS-485/EIA-485 direction control delay (UART1 only) */ - -#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */ - /* Bits 8-31: Reserved */ -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H */ diff --git a/arch/arm/src/lpc11xx/hardware/lpc11_wdt.h b/arch/arm/src/lpc11xx/hardware/lpc11_wdt.h deleted file mode 100644 index 9f3f5a99dc4..00000000000 --- a/arch/arm/src/lpc11xx/hardware/lpc11_wdt.h +++ /dev/null @@ -1,102 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/hardware/lpc11_wdt.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H -#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc11_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC11_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */ -#define LPC11_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */ -#define LPC11_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */ -#define LPC11_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */ - -/* Register addresses ***************************************************************/ - -#define LPC11_WDT_MOD (LPC11_WDT_BASE+LPC11_WDT_MOD_OFFSET) -#define LPC11_WDT_TC (LPC11_WDT_BASE+LPC11_WDT_TC_OFFSET) -#define LPC11_WDT_FEED (LPC11_WDT_BASE+LPC11_WDT_FEED_OFFSET) -#define LPC11_WDT_TV (LPC11_WDT_BASE+LPC11_WDT_TV_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Watchdog mode register */ - -#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ -#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ -#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ -#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ - /* Bits 4-31: Reserved */ -/* Watchdog timer constant register */ - -#define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */ - /* Bits 24-31: Reserved */ - -/* Watchdog feed sequence register */ - -#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa - * followed by 0x55 */ - /* Bits 14-31: Reserved */ -/* Watchdog timer value register */ - -#define WDT_TV (0x00ffffff) /* Bits 0-23: Watchdog timer value */ - /* Bits 24-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H */ diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.c b/arch/arm/src/lpc11xx/lpc111x_gpio.c deleted file mode 100644 index 630d68f9b16..00000000000 --- a/arch/arm/src/lpc11xx/lpc111x_gpio.c +++ /dev/null @@ -1,725 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc111x_gpio.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include - -#include "up_arch.h" -#include "chip.h" -#include "hardware/lpc111x_iocon.h" -#include "lpc11_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Default input pin configuration */ - -#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ -/* These tables have global scope because they are also used in - * lpc11_gpiodbg.c - */ - -/* We have to remember the configured interrupt setting.. PINs are not - * actually set up to interrupt until the interrupt is enabled. - */ - -#ifdef CONFIG_LPC11_GPIOIRQ -uint64_t g_intedge0; -uint64_t g_intedge2; -#endif - -/* GPIO register base addresses */ - -const uint32_t g_gpiobase[GPIO_NPORTS] = -{ - LPC11_GPIO0_BASE, - LPC11_GPIO1_BASE, - LPC11_GPIO2_BASE, - LPC11_GPIO3_BASE -}; - -/* Port 0 and Port 2 can provide a single interrupt for any combination of - * port pins - */ - -const uint32_t g_intbase[GPIO_NPORTS] = -{ -}; - -/* Note: The IOCON offset is not linear. See User manual UM10398 Page 74 */ -/* Note: The IOCON base is not linear. See User manual UM10398 Page 74 */ - -const uint8_t iocon_port0[IOCON_NPINS] = -{ - LPC11_IOCON_P0_0_OFFSET, - LPC11_IOCON_P0_1_OFFSET, - LPC11_IOCON_P0_2_OFFSET, - LPC11_IOCON_P0_3_OFFSET, - LPC11_IOCON_P0_4_OFFSET, - LPC11_IOCON_P0_5_OFFSET, - LPC11_IOCON_P0_6_OFFSET, - LPC11_IOCON_P0_7_OFFSET, - LPC11_IOCON_P0_8_OFFSET, - LPC11_IOCON_P0_9_OFFSET, - LPC11_IOCON_P0_10_OFFSET, - LPC11_IOCON_P0_11_OFFSET -}; - -const uint8_t iocon_port1[IOCON_NPINS] = -{ - LPC11_IOCON_P1_0_OFFSET, - LPC11_IOCON_P1_1_OFFSET, - LPC11_IOCON_P1_2_OFFSET, - LPC11_IOCON_P1_3_OFFSET, - LPC11_IOCON_P1_4_OFFSET, - LPC11_IOCON_P1_5_OFFSET, - LPC11_IOCON_P1_6_OFFSET, - LPC11_IOCON_P1_7_OFFSET, - LPC11_IOCON_P1_8_OFFSET, - LPC11_IOCON_P1_9_OFFSET, - LPC11_IOCON_P1_10_OFFSET, - LPC11_IOCON_P1_11_OFFSET -}; - -const uint8_t iocon_port2[IOCON_NPINS] = -{ - LPC11_IOCON_P2_0_OFFSET, - LPC11_IOCON_P2_1_OFFSET, - LPC11_IOCON_P2_2_OFFSET, - LPC11_IOCON_P2_3_OFFSET, - LPC11_IOCON_P2_4_OFFSET, - LPC11_IOCON_P2_5_OFFSET, - LPC11_IOCON_P2_6_OFFSET, - LPC11_IOCON_P2_7_OFFSET, - LPC11_IOCON_P2_8_OFFSET, - LPC11_IOCON_P2_9_OFFSET, - LPC11_IOCON_P2_10_OFFSET, - LPC11_IOCON_P2_11_OFFSET -}; - -/* There is only IOCON_P3_[0-5] */ -const uint8_t iocon_port3[IOCON_NPINS - 6] = -{ - LPC11_IOCON_P3_0_OFFSET, - LPC11_IOCON_P3_1_OFFSET, - LPC11_IOCON_P3_2_OFFSET, - LPC11_IOCON_P3_3_OFFSET, - LPC11_IOCON_P3_4_OFFSET, - LPC11_IOCON_P3_5_OFFSET -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_pinfunc - * - * Description: - * Set the PIN function in the IOCON register. - * - ****************************************************************************/ - -static int lpc11_pinfunc(unsigned int port, unsigned int pin, - unsigned int value) -{ - const uint8_t *table = NULL; - uint32_t regaddr; - uint32_t regval; - - switch (port) - { - case 0: - table = iocon_port0; - break; - case 1: - table = iocon_port1; - break; - case 2: - table = iocon_port2; - break; - case 3: - table = iocon_port3; - break; - } - - regaddr = LPC11_IOCON_BASE + table[pin]; - if (regaddr != 0) - { - /* Set the requested value in the IOCON register */ - - regval = getreg32(regaddr); - regval &= ~(IOCON_FUNC_MASK); - regval |= (value << IOCON_FUNC_SHIFT); - putreg32(regval, regaddr); - return OK; - - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: lpc11_pullup - * - * Description: - * Get the address of the PINMODE register corresponding to this port and - * pin number. - * - ****************************************************************************/ - -static int lpc11_pullup(lpc11_pinset_t cfgset, unsigned int port, - unsigned int pin) -{ - const uint8_t *table = NULL; - uint32_t regaddr; - uint32_t regval; - uint32_t value; - - switch (cfgset & GPIO_PUMODE_MASK) - { - default: - case GPIO_PULLUP: /* Pull-up resistor enabled */ - value = IOCON_MODE_PU; - break; - - case GPIO_REPEATER: /* Repeater mode enabled */ - value = IOCON_MODE_RM; - break; - - case GPIO_FLOAT: /* Neither pull-up nor -down */ - value = IOCON_MODE_FLOAT; - break; - - case GPIO_PULLDN: /* Pull-down resistor enabled */ - value = IOCON_MODE_PD; - break; - } - - switch (port) - { - case 0: - table = iocon_port0; - break; - case 1: - table = iocon_port1; - break; - case 2: - table = iocon_port2; - break; - case 3: - table = iocon_port3; - break; - } - - - /* Fetch the IOCON register address for this port/pin combination */ - - regaddr = LPC11_IOCON_BASE + table[pin]; - if (regaddr != 0) - { - /* Set the requested value in the IOCON register */ - - regval = getreg32(regaddr); - regval &= ~(IOCON_MODE_MASK); - regval |= (value << IOCON_MODE_SHIFT); - putreg32(regval, regaddr); - return OK; - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: lpc11_setintedge - * - * Description: - * Remember the configured interrupt edge. We can't actually enable the - * the edge interrupts until the called calls IRQ enabled function. - * - ****************************************************************************/ - -#ifdef CONFIG_LPC11_GPIOIRQ -static void lpc11_setintedge(unsigned int port, unsigned int pin, - unsigned int value) -{ - uint64_t *intedge; - unsigned int shift; - - /* Which word to we use? */ - - if (port == 0) - { - intedge = &g_intedge0; - } - else if (port == 2) - { - intedge = &g_intedge2; - } - else - { - return; - } - - /* Set the requested value in the IOCON register */ - - shift = pin << 1; - *intedge &= ~((uint64_t)3 << shift); - *intedge |= ((uint64_t)value << shift); -} -#endif /* CONFIG_LPC11_GPIOIRQ */ - -/**************************************************************************** - * Name: lpc11_setopendrain - * - * Description: - * Set the ODMODE register for open drain mode - * - ****************************************************************************/ - -static void lpc11_setopendrain(unsigned int port, unsigned int pin) -{ - const uint8_t *table = NULL; - uint32_t regaddr; - uint32_t regval; - - switch (port) - { - case 0: - table = iocon_port0; - break; - case 1: - table = iocon_port1; - break; - case 2: - table = iocon_port2; - break; - case 3: - table = iocon_port3; - break; - } - - regaddr = LPC11_IOCON_BASE + table[pin]; - if (regaddr != 0) - { - /* Set the requested value in the IOCON register */ - - regval = getreg32(regaddr); - regval &= ~(IOCON_OD_MASK); - regval |= (1 << IOCON_OD_SHIFT); - putreg32(regval, regaddr); - } -} - -/**************************************************************************** - * Name: lpc11_clropendrain - * - * Description: - * Reset the ODMODE register to disable open drain mode - * - ****************************************************************************/ - -static void lpc11_clropendrain(unsigned int port, unsigned int pin) -{ - const uint8_t *table = NULL; - uint32_t regaddr; - uint32_t regval; - - switch (port) - { - case 0: - table = iocon_port0; - break; - case 1: - table = iocon_port1; - break; - case 2: - table = iocon_port2; - break; - case 3: - table = iocon_port3; - break; - } - - regaddr = LPC11_IOCON_BASE + table[pin]; - if (regaddr != 0) - { - /* Set the requested value in the IOCON register */ - - regval = getreg32(regaddr); - regval &= ~(1 << IOCON_OD_SHIFT); - putreg32(regval, regaddr); - } -} - -/**************************************************************************** - * Name: lpc11_configinput - * - * Description: - * Configure a GPIO input pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -static inline int lpc11_configinput(lpc11_pinset_t cfgset, unsigned int port, - unsigned int pin) -{ - uint32_t regval; - uint32_t gpiobase; - uint32_t intbase; - uint32_t pinmask = (1 << pin); - - /* Set up GPIO registers */ - - gpiobase = g_gpiobase[port]; - - /* Set as input */ - - regval = getreg32(gpiobase + LPC11_GPIO_DIR_OFFSET); - regval &= ~pinmask; - putreg32(regval, gpiobase + LPC11_GPIO_DIR_OFFSET); - - /* Set up interrupt registers */ - - intbase = g_intbase[port]; - if (intbase != 0) - { - /* Disable any rising edge interrupts */ - - regval = getreg32(intbase + LPC11_GPIO_DIR_OFFSET); - regval &= ~pinmask; - putreg32(regval, intbase + LPC11_GPIO_DIR_OFFSET); - - /* Disable any falling edge interrupts */ - - regval = getreg32(intbase + LPC11_GPIO_DIR_OFFSET); - regval &= ~pinmask; - putreg32(regval, intbase + LPC11_GPIO_DIR_OFFSET); - - /* Forget about any falling/rising edge interrupt enabled */ - -#ifdef CONFIG_LPC11_GPIOIRQ - lpc11_setintedge(port, pin, 0); -#endif - } - - /* Set up IOCON registers */ - /* Configure as GPIO */ - - lpc11_pinfunc(port, pin, IOCON_FUNC_GPIO); - - /* Set pull-up mode */ - - lpc11_pullup(cfgset, port, pin); - - /* Open drain only applies to outputs */ - - lpc11_clropendrain(port, pin); - - return OK; -} - -/**************************************************************************** - * Name: lpc11_configinterrupt - * - * Description: - * Configure a GPIO interrupt pin based on bit-encoded description of the - * pin. - * - ****************************************************************************/ - -static inline int lpc11_configinterrupt(lpc11_pinset_t cfgset, unsigned int port, - unsigned int pin) -{ - /* First, configure the port as a generic input so that we have a known - * starting point and consistent behavior during the re-configuration. - */ - - (void)lpc11_configinput(cfgset, port, pin); - - /* Then just remember the rising/falling edge interrupt enabled */ - - DEBUGASSERT(port == 0 || port == 2); -#ifdef CONFIG_LPC11_GPIOIRQ - lpc11_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); -#endif - return OK; -} - -/**************************************************************************** - * Name: lpc11_configoutput - * - * Description: - * Configure a GPIO output pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -static inline int lpc11_configoutput(lpc11_pinset_t cfgset, unsigned int port, - unsigned int pin) -{ - uint32_t gpiobase; - uint32_t regval; - - /* First, configure the port as a generic input so that we have a known - * starting point and consistent behavior during the re-configuration. - */ - - (void)lpc11_configinput(DEFAULT_INPUT, port, pin); - - /* Now, reconfigure the pin as an output */ - - gpiobase = g_gpiobase[port]; - regval = getreg32(gpiobase + LPC11_GPIO_DIR_OFFSET); - regval |= (1 << pin); - putreg32(regval, gpiobase + LPC11_GPIO_DIR_OFFSET); - - /* Check for open drain output */ - - if ((cfgset & GPIO_OPEN_DRAIN) != 0) - { - /* Set pull-up mode. This normally only applies to input pins, but does have - * meaning if the port is an open drain output. - */ - - lpc11_pullup(cfgset, port, pin); - - /* Select open drain output */ - - lpc11_setopendrain(port, pin); - } - - /* Set the initial value of the output */ - - lpc11_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); - - return OK; -} - -/**************************************************************************** - * Name: lpc11_configalternate - * - * Description: - * Configure a GPIO alternate function pin based on bit-encoded description - * of the pin. - * - ****************************************************************************/ - -static int lpc11_configalternate(lpc11_pinset_t cfgset, unsigned int port, - unsigned int pin, uint32_t alt) -{ - /* First, configure the port as an input so that we have a known - * starting point and consistent behavior during the re-configuration. - */ - - (void)lpc11_configinput(DEFAULT_INPUT, port, pin); - - /* Set up IOCON registers */ - /* Configure as GPIO */ - - lpc11_pinfunc(port, pin, alt); - - /* Set pull-up mode */ - - lpc11_pullup(cfgset, port, pin); - - /* Check for open drain output */ - - if ((cfgset & GPIO_OPEN_DRAIN) != 0) - { - /* Select open drain output */ - - lpc11_setopendrain(port, pin); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -int lpc11_configgpio(lpc11_pinset_t cfgset) -{ - unsigned int port; - unsigned int pin; - int ret = -EINVAL; - - /* Verify that this hardware supports the select GPIO port */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < GPIO_NPORTS) - { - /* Get the pin number and select the port configuration register for - * that pin. - */ - - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Handle according to pin function */ - - switch (cfgset & GPIO_FUNC_MASK) - { - case GPIO_INPUT: /* GPIO input pin */ - ret = lpc11_configinput(cfgset, port, pin); - break; - - case GPIO_INTFE: /* GPIO interrupt falling edge */ - case GPIO_INTRE: /* GPIO interrupt rising edge */ - case GPIO_INTBOTH: /* GPIO interrupt both edges */ - ret = lpc11_configinterrupt(cfgset, port, pin); - break; - - case GPIO_OUTPUT: /* GPIO outpout pin */ - ret = lpc11_configoutput(cfgset, port, pin); - break; - - case GPIO_ALT1: /* Alternate function 1 */ - ret = lpc11_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1); - break; - - case GPIO_ALT2: /* Alternate function 2 */ - ret = lpc11_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2); - break; - - case GPIO_ALT3: /* Alternate function 3 */ - ret = lpc11_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3); - break; - - default: - break; - } - } - - return ret; -} - -/**************************************************************************** - * Name: lpc11_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void lpc11_gpiowrite(lpc11_pinset_t pinset, bool value) -{ - uint32_t gpiobase; - uint32_t offset; - uint32_t regval; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < GPIO_NPORTS) - { - /* Get the port base address */ - - gpiobase = g_gpiobase[port]; - - /* Get the pin number */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set or clear the output on the pin */ - - offset = LPC11_GPIO_DATA_OFFSET; - - regval = getreg32(gpiobase + offset); - regval &= ~(1 << pin); - regval |= (value << pin); - putreg32(regval, gpiobase + offset); - } -} - -/**************************************************************************** - * Name: lpc11_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool lpc11_gpioread(lpc11_pinset_t pinset) -{ - uint32_t gpiobase; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < GPIO_NPORTS) - { - /* Get the port base address */ - - gpiobase = g_gpiobase[port]; - - /* Get the pin number and return the input state of that pin */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(gpiobase + LPC11_GPIO_DATA_OFFSET) & (1 << pin)) != 0); - } - - return false; -} diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.h b/arch/arm/src/lpc11xx/lpc111x_gpio.h deleted file mode 100644 index aec89ce4f73..00000000000 --- a/arch/arm/src/lpc11xx/lpc111x_gpio.h +++ /dev/null @@ -1,178 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc111x_gpio.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H -#define __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Bit-encoded input to lpc11_configgpio() ******************************************/ - -/* Encoding: FFFF xxMM OVPP NNNN - * - * Pin Function: FFF - * Pin Mode bits: MM - * Open drain: O (output pins) - * Initial value: V (output pins) - * Port number: PP (0-3) - * Pin number: NNNN (0-11) - */ - -/* Pin Function bits: FFF - * Only meaningful when the GPIO function is GPIO_PIN - */ - -#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */ -#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT) -# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */ -# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */ -# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */ -# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */ -# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO output pin */ -# define GPIO_ALT_GPIO (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function is a GPIO */ -# define GPIO_ALT0 (5 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 0 */ -# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 1 */ -# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 2 */ -# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 3 */ - -#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ -#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) - -#define GPIO_INOUT_MASK GPIO_OUTPUT -#define GPIO_FE_MASK GPIO_INTFE -#define GPIO_RE_MASK GPIO_INTRE - -#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) < GPIO_ALT0) -#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) >= GPIO_ALT0) -#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) -#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) -#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0) -#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0) -#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) -#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0) -#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0) - -/* Pin Mode: MM */ - -#define GPIO_PUMODE_SHIFT (8) /* Bits 8-9: Pin pull-up mode */ -#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT) -# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */ -# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */ -# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */ -# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */ - -/* Open drain: O */ - -#define GPIO_OPEN_DRAIN (1 << 7) /* Bit 7: Open drain mode */ - -/* Initial value: V */ - -#define GPIO_VALUE (1 << 6) /* Bit 6: Initial GPIO output value */ -#define GPIO_VALUE_ONE GPIO_VALUE -#define GPIO_VALUE_ZERO (0) - -/* Port number: PP (0-3) */ - -#define GPIO_PORT_SHIFT (4) /* Bit 4-5: Port number */ -#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) -# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) -# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) -# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) -# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) - -#define GPIO_NPORTS 4 - -/* Pin number: NNNN (0-11) */ - -#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-11 */ -#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) -# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -typedef uint16_t lpc11_pinset_t; - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* These tables have global scope only because they are shared between lpc11_gpio.c, - * lpc11_gpioint.c, and lpc11_gpiodbg.c - */ - -EXTERN const uint32_t g_lopinsel[GPIO_NPORTS]; -EXTERN const uint32_t g_hipinsel[GPIO_NPORTS]; -EXTERN const uint32_t g_lopinmode[GPIO_NPORTS]; -EXTERN const uint32_t g_hipinmode[GPIO_NPORTS]; -EXTERN const uint32_t g_odmode[GPIO_NPORTS]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_clockconfig.h b/arch/arm/src/lpc11xx/lpc11_clockconfig.h deleted file mode 100644 index ebec697945a..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_clockconfig.h +++ /dev/null @@ -1,84 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_clockconfig.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc11_clockconfig - * - * Description: - * Called to initialize the LPC11XX. This does whatever setup is needed to put the - * MCU in a usable state. This includes the initialization of clocking using the - * settings in board.h. - * - ************************************************************************************/ - -void lpc11_clockconfig(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h deleted file mode 100644 index dea2a0cef8f..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_gpio.h +++ /dev/null @@ -1,194 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_gpio.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GPIO_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -#include - -#include "hardware/lpc11_gpio.h" -#include "hardware/lpc11_pinconfig.h" - -/* Include the GPIO definitions for the selected LPC17xx family. */ - -#if defined(LPC111x) -# include "lpc111x_gpio.h" -#elif defined(LPC11C) -# include "lpc11c_gpio.h" -#else -# error "Unrecognized LPC11xx family" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* These tables have global scope only because they are shared between lpc11_gpio.c, - * lpc11_gpioint.c, and lpc11_gpiodbg.c - */ - -#ifdef CONFIG_LPC11_GPIOIRQ -EXTERN uint64_t g_intedge0; -EXTERN uint64_t g_intedge2; -#endif - -EXTERN const uint32_t g_fiobase[GPIO_NPORTS]; -EXTERN const uint32_t g_intbase[GPIO_NPORTS]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/************************************************************************************ - * Name: lpc11_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. - * - ************************************************************************************/ - -#ifdef CONFIG_LPC11_GPIOIRQ -void lpc11_gpioirqinitialize(void); -#else -# define lpc11_gpioirqinitialize() -#endif - -/************************************************************************************ - * Name: lpc11_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ************************************************************************************/ - -int lpc11_configgpio(lpc11_pinset_t cfgset); - -/************************************************************************************ - * Name: lpc11_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ************************************************************************************/ - -void lpc11_gpiowrite(lpc11_pinset_t pinset, bool value); - -/************************************************************************************ - * Name: lpc11_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ************************************************************************************/ - -bool lpc11_gpioread(lpc11_pinset_t pinset); - -/************************************************************************************ - * Name: lpc11_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_LPC11_GPIOIRQ -void lpc11_gpioirqenable(int irq); -#else -# define lpc11_gpioirqenable(irq) -#endif - -/************************************************************************************ - * Name: lpc11_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_LPC11_GPIOIRQ -void lpc11_gpioirqdisable(int irq); -#else -# define lpc11_gpioirqdisable(irq) -#endif - -/************************************************************************************ - * Function: lpc11_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_GPIO_INFO -int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg); -#else -# define lpc11_dumpgpio(p,m) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GPIO_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c deleted file mode 100644 index 86b3098dcda..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c +++ /dev/null @@ -1,179 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_gpiodbg.c - * - * Copyright (C) 2010-2011, 2013, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Output debug info even if debug output is not selected. */ - -#undef CONFIG_DEBUG_INFO -#define CONFIG_DEBUG_INFO 1 - -#include -#include -#include -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "lpc11_gpio.h" - -#ifdef CONFIG_DEBUG_GPIO_INFO - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_pinsel - * - * Description: - * Get the address of the PINSEL register corresponding to this port and - * pin number. - * - ****************************************************************************/ - -#ifdef LPC176x -static uint32_t lpc11_pinsel(unsigned int port, unsigned int pin) -{ - if (pin < 16) - { - return g_lopinsel[port]; - } - else - { - return g_hipinsel[port]; - } -} -#endif /* LPC176x */ - -/**************************************************************************** - * Name: lpc11_pinmode - * - * Description: - * Get the address of the PINMODE register corresponding to this port and - * pin number. - * - ****************************************************************************/ - -#ifdef LPC176x -static uint32_t lpc11_pinmode(unsigned int port, unsigned int pin) -{ - if (pin < 16) - { - return g_lopinmode[port]; - } - else - { - return g_hipinmode[port]; - } -} -#endif /* LPC176x */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lpc11_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg) -{ - irqstate_t flags; - uint32_t base; -#if defined(LPC176x) - uint32_t pinsel; - uint32_t pinmode; -#elif defined(LPC178x) - uint32_t iocon; -#endif /* LPC176x */ - unsigned int port; - unsigned int pin; - - /* Get the base address associated with the GPIO port */ - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - -#if defined(LPC176x) - pinsel = lpc11_pinsel(port, pin); - pinmode = lpc11_pinmode(port, pin); -#elif defined(LPC178x) - iocon = LPC11_IOCON_P(port, pin); -#endif /* LPC176x */ - - /* The following requires exclusive access to the GPIO registers */ - - flags = enter_critical_section(); - gpioinfo("GPIO%c pin%d (pinset: %08x) -- %s\n", - port + '0', pin, pinset, msg); - -#if defined(LPC176x) - gpioinfo(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n", - pinsel, pinsel ? getreg32(pinsel) : 0, - pinmode, pinmode ? getreg32(pinmode) : 0, - g_odmode[port], getreg32(g_odmode[port])); -#elif defined(LPC178x) - gpioinfo(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon)); -#endif - - base = g_fiobase[port]; - gpioinfo(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n", - base+LPC11_FIO_DIR_OFFSET, getreg32(base+LPC11_FIO_DIR_OFFSET), - base+LPC11_FIO_MASK_OFFSET, getreg32(base+LPC11_FIO_MASK_OFFSET), - base+LPC11_FIO_PIN_OFFSET, getreg32(base+LPC11_FIO_PIN_OFFSET)); - - base = g_intbase[port]; - gpioinfo(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n", - LPC11_GPIOINT_IOINTSTATUS, getreg32(LPC11_GPIOINT_IOINTSTATUS), - base+LPC11_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATR_OFFSET), - base+LPC11_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATF_OFFSET)); - gpioinfo(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n", - base+LPC11_GPIOINT_INTENR_OFFSET, getreg32(base+LPC11_GPIOINT_INTENR_OFFSET), - base+LPC11_GPIOINT_INTENF_OFFSET, getreg32(base+LPC11_GPIOINT_INTENF_OFFSET)); - - leave_critical_section(flags); - return OK; -} -#endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c deleted file mode 100644 index 5327b9e9ff8..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_gpioint.c +++ /dev/null @@ -1,547 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_gpioint.c - * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "lpc11_gpio.h" - -#ifdef CONFIG_LPC11_GPIOIRQ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_getintedge - * - * Description: - * Get the stored interrupt edge configuration. - * - ****************************************************************************/ - -static unsigned int lpc11_getintedge(unsigned int port, unsigned int pin) -{ - uint64_t *intedge; - - /* Which word to we use? */ - - if (port == 0) - { - intedge = &g_intedge0; - } - else if (port == 2) - { - intedge = &g_intedge2; - } - else - { - return 0; - } - - /* Return the value for the PINSEL */ - - return (unsigned int)(((*intedge) >> (pin << 1)) & 3); -} - -/**************************************************************************** - * Name: lpc11_setintedge - * - * Description: - * Set the edge interrupt enabled bits for this pin. - * - ****************************************************************************/ - -static void lpc11_setintedge(uint32_t intbase, unsigned int pin, - unsigned int edges) -{ - irqstate_t flags; - int regval; - - /* These must be atomic */ - - flags = enter_critical_section(); - - /* Set/clear the rising edge enable bit */ - - regval = getreg32(intbase + LPC11_GPIOINT_INTENR_OFFSET); - if ((edges & 2) != 0) - { - regval |= GPIOINT(pin); - } - else - { - regval &= ~GPIOINT(pin); - } - - putreg32(regval, intbase + LPC11_GPIOINT_INTENR_OFFSET); - - /* Set/clear the falling edge enable bit */ - - regval = getreg32(intbase + LPC11_GPIOINT_INTENF_OFFSET); - if ((edges & 1) != 0) - { - regval |= GPIOINT(pin); - } - else - { - regval &= ~GPIOINT(pin); - } - - putreg32(regval, intbase + LPC11_GPIOINT_INTENF_OFFSET); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: lpc11_irq2port - * - * Description: - * Given an IRQ number, return the GPIO port number (0 or 2) of the interrupt. - * - ****************************************************************************/ - -static int lpc11_irq2port(int irq) -{ - /* Set 1: - * LPC176x: 12 interrupts p0.0-p0.11 - * LPC178x: 16 interrupts p0.0-p0.15 - */ - - if (irq >= LPC11_VALID_FIRST0L && - irq < (LPC11_VALID_FIRST0L + LPC11_VALID_NIRQS0L)) - { - return 0; - } - - /* Set 2: - * LPC176x: 16 interrupts p0.15-p0.30 - * LPC178x: 16 interrupts p0.16-p0.31 - */ - - else if (irq >= LPC11_VALID_FIRST0H && - irq < (LPC11_VALID_FIRST0H + LPC11_VALID_NIRQS0H)) - { - return 0; - } - -#if defined (LPC176x) - /* Set 3: - * LPC17x: 14 interrupts p2.0-p2.13 - */ - - else if (irq >= LPC11_VALID_FIRST2 && - irq < (LPC11_VALID_FIRST2 + LPC11_VALID_NIRQS2)) - { - return 2; - } - -#elif defined (LPC178x) - /* Set 3: - * LPC18x: 16 interrupts p2.0-p2.15 - */ - - else if (irq >= LPC11_VALID_FIRST2L && - irq < (LPC11_VALID_FIRST2L + LPC11_VALID_NIRQS2L)) - { - return 2; - } - - /* Set 4: - * LPC178x: 16 interrupts p2.16-p2.31 - */ - - else if (irq >= LPC11_VALID_FIRST2H && - irq < (LPC11_VALID_FIRST2H + LPC11_VALID_NIRQS2H)) - { - return 2; - } - -#endif - - return -EINVAL; -} - -/**************************************************************************** - * Name: lpc11_irq2pin - * - * Description: - * Given an IRQ number, return the GPIO pin number (0..31) of the interrupt. - * - ****************************************************************************/ - -static int lpc11_irq2pin(int irq) -{ - /* Set 1: - * LPC17x: 12 interrupts p0.0-p0.11 - * LPC18x: 16 interrupts p0.0-p0.15 - * - * See arch/arm/include/lpc11xx/irq.h: - * LPC11_VALID_SHIFT0L 0 - Bit 0 is thre first bit in the group of - * 12/16 interrupts - * LPC11_VALID_FIRST0L irq - IRQ number associated with p0.0 - * LPC11_VALID_NIRQS0L 12/16 - Number of interrupt bits in the group - */ - - if (irq >= LPC11_VALID_FIRST0L && - irq < (LPC11_VALID_FIRST0L + LPC11_VALID_NIRQS0L)) - { - return irq - LPC11_VALID_FIRST0L + LPC11_VALID_SHIFT0L; - } - - /* Set 2: - * LPC176x: 16 interrupts p0.15-p0.30 - * LPC178x: 16 interrupts p0.16-p0.31 - * - * LPC11_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group - * of 16 interrupts - * LPC11_VALID_FIRST0L irq - IRQ number associated with p0.15/16 - * LPC11_VALID_NIRQS0L 16 - 16 interrupt bits in the group - */ - - else if (irq >= LPC11_VALID_FIRST0H && - irq < (LPC11_VALID_FIRST0H + LPC11_VALID_NIRQS0H)) - { - return irq - LPC11_VALID_FIRST0H + LPC11_VALID_SHIFT0H; - } - -#if defined(LPC176x) - /* Set 3: - * LPC17x: 14 interrupts p2.0-p2.13 - * - * LPC11_VALID_SHIFT2 0 - Bit 0 is the first bit in a group of 14 - * interrupts - * LPC11_VALID_FIRST2 irq - IRQ number associated with p2.0 - * LPC11_VALID_NIRQS2 14 - 14 interrupt bits in the group - */ - - else if (irq >= LPC11_VALID_FIRST2 && - irq < (LPC11_VALID_FIRST2 + LPC11_VALID_NIRQS2)) - { - return irq - LPC11_VALID_FIRST2 + LPC11_VALID_SHIFT2; - } - -#elif defined(LPC178x) - - /* Set 3: - * LPC18x: 16 interrupts p2.0-p2.15 - * - * LPC11_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 16 - * interrupts - * LPC11_VALID_FIRST2L irq - IRQ number associated with p2.0 - * LPC11_VALID_NIRQS2L 16 - 16 interrupt bits in the group - */ - - else if (irq >= LPC11_VALID_FIRST2L && - irq < (LPC11_VALID_FIRST2L + LPC11_VALID_NIRQS2L)) - { - return irq - LPC11_VALID_FIRST2L + LPC11_VALID_SHIFT2L; - } - - /* Set 3: - * LPC18x: 16 interrupts p2.16-p2.31 - * - * LPC11_VALID_SHIFT2L 16 - Bit 16 is the first bit in a group of 16 - * interrupts - * LPC11_VALID_FIRST2L irq - IRQ number associated with p2.0 - * LPC11_VALID_NIRQS2L 16 - 16 interrupt bits in the group - */ - - else if (irq >= LPC11_VALID_FIRST2H && - irq < (LPC11_VALID_FIRST2H + LPC11_VALID_NIRQS2H)) - { - return irq - LPC11_VALID_FIRST2H + LPC11_VALID_SHIFT2H; - } - -#endif - - return -EINVAL; -} - -/**************************************************************************** - * Name: lpc11_gpiodemux - * - * Description: - * Demux all interrupts on one GPIO interrupt status register. - * - ****************************************************************************/ - -static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask, - int irqbase, void *context) -{ - uint32_t intstatr; - uint32_t intstatf; - uint32_t intstatus; - uint32_t bit; - int irq; - - /* Get the interrupt rising and falling edge status and mask out only the - * interrupts that are enabled. - */ - - intstatr = getreg32(intbase + LPC11_GPIOINT_INTSTATR_OFFSET); - intstatr &= getreg32(intbase + LPC11_GPIOINT_INTENR_OFFSET); - - intstatf = getreg32(intbase + LPC11_GPIOINT_INTSTATF_OFFSET); - intstatf &= getreg32(intbase + LPC11_GPIOINT_INTENF_OFFSET); - - /* And get the OR of the enabled interrupt sources. We do not make any - * distinction between rising and falling edges (but the hardware does support - * the ability to handle them differently if needed). - */ - - intstatus = intstatr | intstatf; - - /* Now march through the (valid) bits and dispatch each interrupt */ - - irq = irqbase; - bit = 1; - while (intstatus != 0) - { - /* Does this pin support an interrupt? If no, skip over it WITHOUT - * incrementing irq. - */ - - if ((intmask & bit) != 0) - { - /* This pin can support an interrupt. Is there an interrupt pending - * and enabled? - */ - - if ((intstatus & bit) != 0) - { - /* Clear the interrupt status */ - - putreg32(bit, intbase + LPC11_GPIOINT_INTCLR_OFFSET); - - /* And dispatch the interrupt */ - - irq_dispatch(irq, context); - } - - /* Increment the IRQ number on each interrupt pin */ - - irq++; - } - - /* Next bit */ - - intstatus &= ~bit; - bit <<= 1; - } -} - -/**************************************************************************** - * Name: lpc11_gpiointerrupt - * - * Description: - * Handle the GPIO interrupt. For the LPC176x family, that interrupt could - * also that also indicates that an EINT3 interrupt has occurred. NOTE: - * This logic would have to be extended if EINT3 is actually used for - * External Interrupt 3 on an LPC176x platform. - * - ****************************************************************************/ - -static int lpc11_gpiointerrupt(int irq, void *context, FAR void *arg) -{ - /* Get the GPIO interrupt status */ - - uint32_t intstatus = getreg32(LPC11_GPIOINT_IOINTSTATUS); - - /* Check for an interrupt on GPIO0 */ - - if ((intstatus & GPIOINT_IOINTSTATUS_P0INT) != 0) - { - lpc11_gpiodemux(LPC11_GPIOINT0_BASE, LPC11_VALID_GPIOINT0, - LPC11_VALID_FIRST0L, context); - } - -#if defined(LPC176x) - /* Check for an interrupt on GPIO2 */ - - if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0) - { - lpc11_gpiodemux(LPC11_GPIOINT2_BASE, LPC11_VALID_GPIOINT2, - LPC11_VALID_FIRST2, context); - } - -#elif defined(LPC178x) - /* Check for an interrupt on GPIO2 */ - - if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0) - { - lpc11_gpiodemux(LPC11_GPIOINT2_BASE, LPC11_VALID_GPIOINT2, - LPC11_VALID_FIRST2L, context); - } - -#endif - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - ****************************************************************************/ - -void lpc11_gpioirqinitialize(void) -{ - /* Disable all GPIO interrupts */ - - putreg32(0, LPC11_GPIOINT0_INTENR); - putreg32(0, LPC11_GPIOINT0_INTENF); - putreg32(0, LPC11_GPIOINT2_INTENR); - putreg32(0, LPC11_GPIOINT2_INTENF); - - /* Attach and enable the GPIO IRQ. */ - -#if defined(LPC176x) - /* For the LPC176x family, GPIO0 and GPIO2 interrupts share the same - * position in the NVIC with External Interrupt 3 - */ - - (void)irq_attach(LPC11_IRQ_EINT3, lpc11_gpiointerrupt, NULL); - up_enable_irq(LPC11_IRQ_EINT3); - -#elif defined(LPC178x) - /* the LPC178x family has a single, dedicated interrupt for GPIO0 and - * GPIO2. - */ - - (void)irq_attach(LPC11_IRQ_GPIO, lpc11_gpiointerrupt, NULL); - up_enable_irq(LPC11_IRQ_GPIO); - -#endif -} - -/**************************************************************************** - * Name: lpc11_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -void lpc11_gpioirqenable(int irq) -{ - /* Map the IRQ number to a port number */ - - int port = lpc11_irq2port(irq); - if (port >= 0) - { - /* The IRQ number does correspond to an interrupt port. Now get the base - * address of the GPIOINT registers for the port. - */ - - uint32_t intbase = g_intbase[port]; - if (intbase != 0) - { - /* And get the pin number associated with the port */ - - unsigned int pin = lpc11_irq2pin(irq); - unsigned int edges = lpc11_getintedge(port, pin); - lpc11_setintedge(intbase, pin, edges); - } - } -} - -/**************************************************************************** - * Name: lpc11_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -void lpc11_gpioirqdisable(int irq) -{ - /* Map the IRQ number to a port number */ - - int port = lpc11_irq2port(irq); - if (port >= 0) - { - /* The IRQ number does correspond to an interrupt port. Now get the base - * address of the GPIOINT registers for the port. - */ - - uint32_t intbase = g_intbase[port]; - if (intbase != 0) - { - /* And get the pin number associated with the port */ - - unsigned int pin = lpc11_irq2pin(irq); - lpc11_setintedge(intbase, pin, 0); - } - } -} - -#endif /* CONFIG_LPC11_GPIOIRQ */ - diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c deleted file mode 100644 index 0fee3d96025..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_i2c.c +++ /dev/null @@ -1,632 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_i2c.c - * - * Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Copyright (C) 2011 Li Zhuoyi. All rights reserved. - * Author: Li Zhuoyi (Original author) - * - * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c - * - * Author: David Hewson - * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" - -#include "chip.h" -#include "hardware/lpc11_syscon.h" -#include "lpc11_gpio.h" -#include "lpc11_i2c.h" - -#if defined(CONFIG_LPC11_I2C0) || defined(CONFIG_LPC11_I2C1) || defined(CONFIG_LPC11_I2C2) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef GPIO_I2C1_SCL -# define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 -# define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 -#endif - -#ifndef CONFIG_LPC11_I2C0_FREQUENCY -# define CONFIG_LPC11_I2C0_FREQUENCY 100000 -#endif - -#ifndef CONFIG_LPC11_I2C1_FREQUENCY -# define CONFIG_LPC11_I2C1_FREQUENCY 100000 -#endif - -#ifndef CONFIG_LPC11_I2C2_FREQUENCY -# define CONFIG_LPC11_I2C2_FREQUENCY 100000 -#endif - -#define I2C_TIMEOUT (20 * 1000/CONFIG_USEC_PER_TICK) /* 20 mS */ -#define LPC11_I2C1_FREQUENCY 400000 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct lpc11_i2cdev_s -{ - struct i2c_master_s dev; /* Generic I2C device */ - unsigned int base; /* Base address of registers */ - uint16_t irqid; /* IRQ for this device */ - - sem_t mutex; /* Only one thread can access at a time */ - sem_t wait; /* Place to wait for state machine completion */ - volatile uint8_t state; /* State of state machine */ - WDOG_ID timeout; /* Watchdog to timeout when bus hung */ - uint32_t frequency; /* Current I2C frequency */ - - struct i2c_msg_s *msgs; /* Remaining transfers - first one is in progress */ - unsigned int nmsg; /* Number of transfer remaining */ - - uint16_t wrcnt; /* Number of bytes sent to tx fifo */ - uint16_t rdcnt; /* Number of bytes read from rx fifo */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int lpc11_i2c_start(struct lpc11_i2cdev_s *priv); -static void lpc11_i2c_stop(struct lpc11_i2cdev_s *priv); -static int lpc11_i2c_interrupt(int irq, FAR void *context, void *arg); -static void lpc11_i2c_timeout(int argc, uint32_t arg, ...); -static void lpc11_i2c_setfrequency(struct lpc11_i2cdev_s *priv, - uint32_t frequency); -static void lpc11_stopnext(struct lpc11_i2cdev_s *priv); - -/* I2C device operations */ - -static int lpc11_i2c_transfer(FAR struct i2c_master_s *dev, - FAR struct i2c_msg_s *msgs, int count); -#ifdef CONFIG_I2C_RESET -static int lpc11_i2c_reset(FAR struct i2c_master_s * dev); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_LPC11_I2C0 -static struct lpc11_i2cdev_s g_i2c0dev; -#endif -#ifdef CONFIG_LPC11_I2C1 -static struct lpc11_i2cdev_s g_i2c1dev; -#endif -#ifdef CONFIG_LPC11_I2C2 -static struct lpc11_i2cdev_s g_i2c2dev; -#endif - -struct i2c_ops_s lpc11_i2c_ops = -{ - .transfer = lpc11_i2c_transfer -#ifdef CONFIG_I2C_RESET - , .reset = lpc11_i2c_reset -#endif -}; - -/**************************************************************************** - * Name: lpc11_i2c_setfrequency - * - * Description: - * Set the frequency for the next transfer - * - ****************************************************************************/ - -static void lpc11_i2c_setfrequency(struct lpc11_i2cdev_s *priv, - uint32_t frequency) -{ - if (frequency != priv->frequency) - { - if (frequency > 100000) - { - /* Asymetric per 400Khz I2C spec */ - - putreg32(LPC11_MCLK / (83 + 47) * 47 / frequency, - priv->base + LPC11_I2C_SCLH_OFFSET); - putreg32(LPC11_MCLK / (83 + 47) * 83 / frequency, - priv->base + LPC11_I2C_SCLL_OFFSET); - } - else - { - /* 50/50 mark space ratio */ - - putreg32(LPC11_MCLK / 100 * 50 / frequency, - priv->base + LPC11_I2C_SCLH_OFFSET); - putreg32(LPC11_MCLK / 100 * 50 / frequency, - priv->base + LPC11_I2C_SCLL_OFFSET); - } - - priv->frequency = frequency; - } -} - -/**************************************************************************** - * Name: lpc11_i2c_start - * - * Description: - * Perform a I2C transfer start - * - ****************************************************************************/ - -static int lpc11_i2c_start(struct lpc11_i2cdev_s *priv) -{ - putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, - priv->base + LPC11_I2C_CONCLR_OFFSET); - putreg32(I2C_CONSET_STA, priv->base + LPC11_I2C_CONSET_OFFSET); - - (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc11_i2c_timeout, 1, - (uint32_t)priv); - nxsem_wait(&priv->wait); - - wd_cancel(priv->timeout); - - return priv->nmsg; -} - -/**************************************************************************** - * Name: lpc11_i2c_stop - * - * Description: - * Perform a I2C transfer stop - * - ****************************************************************************/ - -static void lpc11_i2c_stop(struct lpc11_i2cdev_s *priv) -{ - if (priv->state != 0x38) - { - putreg32(I2C_CONSET_STO | I2C_CONSET_AA, - priv->base + LPC11_I2C_CONSET_OFFSET); - } - - nxsem_post(&priv->wait); -} - -/**************************************************************************** - * Name: lpc11_i2c_timeout - * - * Description: - * Watchdog timer for timeout of I2C operation - * - ****************************************************************************/ - -static void lpc11_i2c_timeout(int argc, uint32_t arg, ...) -{ - struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)arg; - - irqstate_t flags = enter_critical_section(); - priv->state = 0xff; - nxsem_post(&priv->wait); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: lpc11_i2c_transfer - * - * Description: - * Perform a sequence of I2C transfers - * - ****************************************************************************/ - -static int lpc11_i2c_transfer(FAR struct i2c_master_s *dev, - FAR struct i2c_msg_s *msgs, int count) -{ - struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)dev; - int ret; - - DEBUGASSERT(dev != NULL && msgs != NULL && count > 0); - - /* Get exclusive access to the I2C bus */ - - nxsem_wait(&priv->mutex); - - /* Set up for the transfer */ - - priv->wrcnt = 0; - priv->rdcnt = 0; - priv->msgs = msgs; - priv->nmsg = count; - - /* Configure the I2C frequency. - * REVISIT: Note that the frequency is set only on the first message. - * This could be extended to support different transfer frequencies for - * each message segment. - */ - - lpc11_i2c_setfrequency(priv, msgs->frequency); - - /* Perform the transfer */ - - ret = lpc11_i2c_start(priv); - - nxsem_post(&priv->mutex); - return ret; -} - -/**************************************************************************** - * Name: lpc11_stopnext - * - * Description: - * Check if we need to issue STOP at the next message - * - ****************************************************************************/ - -static void lpc11_stopnext(struct lpc11_i2cdev_s *priv) -{ - priv->nmsg--; - - if (priv->nmsg > 0) - { - priv->msgs++; - putreg32(I2C_CONSET_STA, priv->base + LPC11_I2C_CONSET_OFFSET); - } - else - { - lpc11_i2c_stop(priv); - } -} - -/**************************************************************************** - * Name: lpc11_i2c_interrupt - * - * Description: - * The I2C Interrupt Handler - * - ****************************************************************************/ - -static int lpc11_i2c_interrupt(int irq, FAR void *context, void *arg) -{ - struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)arg; - struct i2c_msg_s *msg; - uint32_t state; - - DEBUGASSERT(priv != NULL); - - /* Reference UM10360 19.10.5 */ - - state = getreg32(priv->base + LPC11_I2C_STAT_OFFSET); - msg = priv->msgs; - - priv->state = state; - state &= 0xf8; /* state mask, only 0xX8 is possible */ - switch (state) - { - - case 0x08: /* A START condition has been transmitted. */ - case 0x10: /* A Repeated START condition has been transmitted. */ - /* Set address */ - - putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ) ? - I2C_READADDR8(msg->addr) : - I2C_WRITEADDR8(msg->addr), priv->base + LPC11_I2C_DAT_OFFSET); - - /* Clear start bit */ - - putreg32(I2C_CONCLR_STAC, priv->base + LPC11_I2C_CONCLR_OFFSET); - break; - - /* Write cases */ - - case 0x18: /* SLA+W has been transmitted; ACK has been received */ - priv->wrcnt = 0; - putreg32(msg->buffer[0], priv->base + LPC11_I2C_DAT_OFFSET); /* put first byte */ - break; - - case 0x28: /* Data byte in DAT has been transmitted; ACK has been received. */ - priv->wrcnt++; - - if (priv->wrcnt < msg->length) - { - putreg32(msg->buffer[priv->wrcnt], priv->base + LPC11_I2C_DAT_OFFSET); /* Put next byte */ - } - else - { - lpc11_stopnext(priv); - } - break; - - /* Read cases */ - - case 0x40: /* SLA+R has been transmitted; ACK has been received */ - priv->rdcnt = 0; - if (msg->length > 1) - { - putreg32(I2C_CONSET_AA, priv->base + LPC11_I2C_CONSET_OFFSET); /* Set ACK next read */ - } - else - { - putreg32(I2C_CONCLR_AAC, priv->base + LPC11_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */ - } - break; - - case 0x50: /* Data byte has been received; ACK has been returned. */ - priv->rdcnt++; - msg->buffer[priv->rdcnt - 1] = getreg32(priv->base + LPC11_I2C_BUFR_OFFSET); - - if (priv->rdcnt >= (msg->length - 1)) - { - putreg32(I2C_CONCLR_AAC, priv->base + LPC11_I2C_CONCLR_OFFSET); /* Do not ACK any more */ - } - break; - - case 0x58: /* Data byte has been received; NACK has been returned. */ - msg->buffer[priv->rdcnt] = getreg32(priv->base + LPC11_I2C_BUFR_OFFSET); - lpc11_stopnext(priv); - break; - - default: - lpc11_i2c_stop(priv); - break; - } - - putreg32(I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET); /* clear interrupt */ - - return OK; -} - -/************************************************************************************ - * Name: lpc11_i2c_reset - * - * Description: - * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ************************************************************************************/ - -#ifdef CONFIG_I2C_RESET -static int lpc11_i2c_reset(FAR struct i2c_master_s * dev) -{ - return OK; -} -#endif /* CONFIG_I2C_RESET */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_i2cbus_initialize - * - * Description: - * Initialise an I2C device - * - ****************************************************************************/ - -struct i2c_master_s *lpc11_i2cbus_initialize(int port) -{ - struct lpc11_i2cdev_s *priv; - - if (port > 1) - { - i2cerr("ERROR: LPC I2C only supports ports 0 and 1\n"); - return NULL; - } - - irqstate_t flags; - uint32_t regval; - - flags = enter_critical_section(); - -#ifdef CONFIG_LPC11_I2C0 - if (port == 0) - { - priv = &g_i2c0dev; - priv->base = LPC11_I2C0_BASE; - priv->irqid = LPC11_IRQ_I2C0; - - /* Enable clocking */ - - regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); - regval |= SYSCON_SYSAHBCLKCTRL_I2C0; - putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); - - /* Pin configuration */ - - lpc11_configgpio(GPIO_I2C0_SCL); - lpc11_configgpio(GPIO_I2C0_SDA); - - /* Set default frequency */ - - lpc11_i2c_setfrequency(priv, CONFIG_LPC11_I2C0_FREQUENCY); - } - else -#endif -#ifdef CONFIG_LPC11_I2C1 - if (port == 1) - { - priv = &g_i2c1dev; - priv->base = LPC11_I2C1_BASE; - priv->irqid = LPC11_IRQ_I2C1; - - /* Enable clocking */ - - regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); - regval |= SYSCON_SYSAHBCLKCTRL_I2C1; - putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); - - regval = getreg32(LPC11_SYSCON_PCLKSEL1); - regval &= ~SYSCON_PCLKSEL1_I2C1_MASK; - regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT); - putreg32(regval, LPC11_SYSCON_PCLKSEL1); - - /* Pin configuration */ - - lpc11_configgpio(GPIO_I2C1_SCL); - lpc11_configgpio(GPIO_I2C1_SDA); - - /* Set default frequency */ - - lpc11_i2c_setfrequency(priv, CONFIG_LPC11_I2C1_FREQUENCY); - } - else -#endif -#ifdef CONFIG_LPC11_I2C2 - if (port == 2) - { - priv = &g_i2c2dev; - priv->base = LPC11_I2C2_BASE; - priv->irqid = LPC11_IRQ_I2C2; - - /* Enable clocking */ - - regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); - regval |= SYSCON_SYSAHBCLKCTRL_I2C2; - putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); - - regval = getreg32(LPC11_SYSCON_PCLKSEL1); - regval &= ~SYSCON_PCLKSEL1_I2C2_MASK; - regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT); - putreg32(regval, LPC11_SYSCON_PCLKSEL1); - - /* Pin configuration */ - - lpc11_configgpio(GPIO_I2C2_SCL); - lpc11_configgpio(GPIO_I2C2_SDA); - - /* Set default frequency */ - - lpc11_i2c_setfrequency(priv, CONFIG_LPC11_I2C2_FREQUENCY); - } - else -#endif - { - return NULL; - } - - leave_critical_section(flags); - - putreg32(I2C_CONSET_I2EN, priv->base + LPC11_I2C_CONSET_OFFSET); - - /* Initialize semaphores */ - - nxsem_init(&priv->mutex, 0, 1); - nxsem_init(&priv->wait, 0, 0); - - /* The wait semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - - nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE); - - /* Allocate a watchdog timer */ - - priv->timeout = wd_create(); - DEBUGASSERT(priv->timeout != 0); - - /* Attach Interrupt Handler */ - - irq_attach(priv->irqid, lpc11_i2c_interrupt, priv); - - /* Enable Interrupt Handler */ - - up_enable_irq(priv->irqid); - - /* Install our operations */ - - priv->dev.ops = &lpc11_i2c_ops; - return &priv->dev; -} - -/**************************************************************************** - * Name: lpc11_i2cbus_uninitialize - * - * Description: - * Uninitialise an I2C device - * - ****************************************************************************/ - -int lpc11_i2cbus_uninitialize(FAR struct i2c_master_s * dev) -{ - struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; - - /* Disable I2C */ - - putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC11_I2C_CONCLR_OFFSET); - - /* Reset data structures */ - - nxsem_destroy(&priv->mutex); - nxsem_destroy(&priv->wait); - - /* Free the watchdog timer */ - - wd_delete(priv->timeout); - priv->timeout = NULL; - - /* Disable interrupts */ - - up_disable_irq(priv->irqid); - - /* Detach Interrupt Handler */ - - irq_detach(priv->irqid); - return OK; -} - -#endif /* CONFIG_LPC11_I2C0 || CONFIG_LPC11_I2C1 || CONFIG_LPC11_I2C2 */ diff --git a/arch/arm/src/lpc11xx/lpc11_idle.c b/arch/arm/src/lpc11xx/lpc11_idle.c deleted file mode 100644 index 1ac0d7d9ba2..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_idle.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11/lpc11_idle.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "up_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - -/* If the g_dma_inprogress is zero, then there is no DMA in progress. This - * value is needed in the IDLE loop to determine if the IDLE loop should - * go into lower power power consumption modes. According to the LPC17xx - * User Manual: "The DMA controller can continue to work in Sleep mode, and - * has access to the peripheral SRAMs and all peripheral registers. The - * flash memory and the Main SRAM are not available in Sleep mode, they are - * disabled in order to save power." - */ - -#ifdef CONFIG_LPC11_GPDMA - if (g_dma_inprogress == 0) -#endif - { - /* Sleep until an interrupt occurs in order to save power */ - - BEGIN_IDLE(); - asm("WFI"); - END_IDLE(); - } -#endif -} diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c deleted file mode 100644 index df2fde8405c..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_irq.c +++ /dev/null @@ -1,340 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_irq.c - * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nvic.h" -#include "up_arch.h" -#include "up_internal.h" - -//#include "lpc11_irq.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Get a 32-bit version of the default priority */ - -#define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ - NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_dumpnvic - * - * Description: - * Dump some interesting NVIC registers - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_IRQ_INFO) -static void lpc11_dumpnvic(const char *msg, int irq) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - irqinfo("NVIC (%s, irq=%d):\n", msg, irq); - irqinfo(" ISER: %08x ICER: %08x\n", - getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER)); - irqinfo(" ISPR: %08x ICPR: %08x\n", - getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR)); - irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", - getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1), - getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3)); - irqinfo(" %08x %08x %08x %08x\n", - getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5), - getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7)); - - irqinfo("SYSCON:\n"); - irqinfo(" CPUID: %08x\n", - getreg32(ARMV6M_SYSCON_CPUID)); - irqinfo(" ICSR: %08x AIRCR: %08x\n", - getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR)); - irqinfo(" SCR: %08x CCR: %08x\n", - getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR)); - irqinfo(" SHPR2: %08x SHPR3: %08x\n", - getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3)); - - leave_critical_section(flags); -} - -#else -# define lpc11_dumpnvic(msg, irq) -#endif - -/**************************************************************************** - * Name: lpc11_nmi, lpc11_busfault, lpc11_usagefault, lpc11_pendsv, - * lpc11_dbgmonitor, lpc11_pendsv, lpc11_reserved - * - * Description: - * Handlers for various execptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default - * unexpected interrupt handler is that they provide a diagnostic output. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -static int lpc11_nmi(int irq, FAR void *context, FAR void *arg) -{ - (void)up_irq_save(); - _err("PANIC!!! NMI received\n"); - PANIC(); - return 0; -} - -static int lpc11_pendsv(int irq, FAR void *context, FAR void *arg) -{ - (void)up_irq_save(); - _err("PANIC!!! PendSV received\n"); - PANIC(); - return 0; -} - -static int lpc11_reserved(int irq, FAR void *context, FAR void *arg) -{ - (void)up_irq_save(); - _err("PANIC!!! Reserved interrupt\n"); - PANIC(); - return 0; -} -#endif - -/**************************************************************************** - * Name: lpc11_clrpend - * - * Description: - * Clear a pending interrupt at the NVIC. - * - ****************************************************************************/ - -static inline void lpc11_clrpend(int irq) -{ - /* This will be called on each interrupt exit whether the interrupt can be - * enambled or not. So this assertion is necessarily lame. - */ - - DEBUGASSERT((unsigned)irq < NR_IRQS); - - /* Check for an external interrupt */ - - if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32)) - { - /* Set the appropriate bit in the ISER register to enable the - * interrupt - */ - - putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ICPR); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - uint32_t regaddr; - int i; - - /* Disable all interrupts */ - - putreg32(0xffffffff, ARMV6M_NVIC_ICER); - - /* Set all interrupts (and exceptions) to the default priority */ - - putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2); - putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3); - - /* Now set all of the interrupt lines to the default priority */ - - for (i = 0; i < 8; i++) - { - regaddr = ARMV6M_NVIC_IPR(i); - putreg32(DEFPRIORITY32, regaddr); - } - - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - - /* Attach the SVCall and Hard Fault exception handlers. The SVCall - * exception is used for performing context switches; The Hard Fault - * must also be caught because a SVCall may show up as a Hard Fault - * under certain conditions. - */ - - irq_attach(LPC11_IRQ_SVCALL, up_svcall, NULL); - irq_attach(LPC11_IRQ_HARDFAULT, up_hardfault, NULL); - - /* Attach all other processor exceptions (except reset and sys tick) */ - -#ifdef CONFIG_DEBUG_FEATURES - irq_attach(LPC11_IRQ_NMI, lpc11_nmi, NULL); - irq_attach(LPC11_IRQ_PENDSV, lpc11_pendsv, NULL); - irq_attach(LPC11_IRQ_RESERVED, lpc11_reserved, NULL); -#endif - - lpc11_dumpnvic("initial", NR_IRQS); - - /* Initialize logic to support a second level of interrupt decoding for - * configured pin interrupts. - */ - -#ifdef CONFIG_LPC11_GPIOIRQ - lpc11_gpioirqinitialize(); -#endif - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* And finally, enable interrupts */ - - up_irq_enable(); -#endif -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - DEBUGASSERT((unsigned)irq < NR_IRQS); - - /* Check for an external interrupt */ - - if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32)) - { - /* Set the appropriate bit in the ICER register to disable the - * interrupt - */ - - putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ICER); - } - - /* Handle processor exceptions. Only SysTick can be disabled */ - - else if (irq == LPC11_IRQ_SYSTICK) - { - modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0); - } - - lpc11_dumpnvic("disable", irq); -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - /* This will be called on each interrupt exit whether the interrupt can be - * enabled or not. So this assertion is necessarily lame. - */ - - DEBUGASSERT((unsigned)irq < NR_IRQS); - - /* Check for external interrupt */ - - if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32)) - { - /* Set the appropriate bit in the ISER register to enable the - * interrupt - */ - - putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ISER); - } - - /* Handle processor exceptions. Only SysTick can be disabled */ - - else if (irq == LPC11_IRQ_SYSTICK) - { - modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE); - } - - lpc11_dumpnvic("enable", irq); -} - -/**************************************************************************** - * Name: up_ack_irq - * - * Description: - * Acknowledge the IRQ - * - ****************************************************************************/ - -void up_ack_irq(int irq) -{ - lpc11_clrpend(irq); -} diff --git a/arch/arm/src/lpc11xx/lpc11_lowputc.c b/arch/arm/src/lpc11xx/lpc11_lowputc.c deleted file mode 100644 index 8bf3759f488..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_lowputc.c +++ /dev/null @@ -1,306 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_lowputc.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "hardware/lpc11_syscon.h" -#include "hardware/lpc11_uart.h" - -#include "lpc11_gpio.h" -#include "lpc11_lowputc.h" -#include "lpc11_serial.h" - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -/* Select UART parameters for the selected console */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC11_UART0_BASE -# define CONSOLE_BAUD CONFIG_UART0_BAUD -# define CONSOLE_BITS CONFIG_UART0_BITS -# define CONSOLE_PARITY CONFIG_UART0_PARITY -# define CONSOLE_2STOP CONFIG_UART0_2STOP -#elif defined(HAVE_SERIAL_CONSOLE) -# error "No CONFIG_UART0_SERIAL_CONSOLE Setting" -#endif - -/* Get word length setting for the console */ - -#if CONSOLE_BITS == 5 -# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT -#elif CONSOLE_BITS == 6 -# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT -#elif CONSOLE_BITS == 7 -# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT -#elif CONSOLE_BITS == 8 -# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT -#elif defined(HAVE_SERIAL_CONSOLE) -# error "Invalid CONFIG_UARTn_BITS setting for console " -#endif - -/* Get parity setting for the console */ - -#if CONSOLE_PARITY == 0 -# define CONSOLE_LCR_PAR 0 -#elif CONSOLE_PARITY == 1 -# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) -#elif CONSOLE_PARITY == 2 -# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) -#elif CONSOLE_PARITY == 3 -# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) -#elif CONSOLE_PARITY == 4 -# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) -#elif defined(HAVE_SERIAL_CONSOLE) -# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE" -#endif - -/* Get stop-bit setting for the console and UART0-3 */ - -#if CONSOLE_2STOP != 0 -# define CONSOLE_LCR_STOP UART_LCR_STOP -#else -# define CONSOLE_LCR_STOP 0 -#endif - -/* LCR and FCR values for the console */ - -#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP) -#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ - UART_FCR_RXRST | UART_FCR_FIFOEN) - -/**************************************************************************** - * This Baud Rate configuration is based on idea suggested at LPCWare: - * www.lpcware.com/content/blog/lpc17xx-uart-simpler-way-calculate-baudrate-timming - * - * The original code is for LPC17xx but with few modifications it worked - * fine in the LPC11xx as well. - * - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_lowputc - * - * Description: - * Output one byte on the serial console - * - ****************************************************************************/ - -void up_lowputc(char ch) -{ -#if defined HAVE_UART && defined HAVE_SERIAL_CONSOLE - /* Wait for the transmitter to be available */ - - while ((getreg32(CONSOLE_BASE+LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) == 0); - - /* Send the character */ - - putreg32((uint32_t)ch, CONSOLE_BASE+LPC11_UART_THR_OFFSET); -#endif -} - -/**************************************************************************** - * Name: lpc11_lowsetup - * - * Description: - * This performs basic initialization of the UART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - * The UART peripheral is configured using the following registers: - * 1. Pins: For the LPC111x/101/201/301 parts, the UART pins must be - * configured in the IOCONFIG register block before the UART clocks can - * be enabled in the SYSAHBCLKCTRL register. For all other parts, no - * special enabling sequence is required. - * 2. Power: In the SYSAHBCLKCTRL register, set bit 12. - * On reset, UART is disabled. - * 3. Peripheral clock: Enable the UART peripheral clock by writing to the - * UARTCLKDIV register. - * - ****************************************************************************/ - -void lpc11_lowsetup(void) -{ -#ifdef HAVE_UART - uint32_t regval; - uint32_t coreclk = LPC11_MCLK; - uint32_t rate16 = 16 * CONSOLE_BAUD; - uint32_t dval; - uint32_t mval; - uint32_t dl; - - /* Enable clock for GPIO and I/O block */ - - regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); - regval |= (SYSCON_SYSAHBCLKCTRL_GPIO | SYSCON_SYSAHBCLKCTRL_IOCON); - putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) - /* Step 1: Pins configuration */ - - lpc11_configgpio(GPIO_UART0_TXD); - lpc11_configgpio(GPIO_UART0_RXD); -#endif - - /* Step 2: Enable power for all console UART and disable power for - * other UARTs. - */ - - regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); -#if defined(CONFIG_UART0_SERIAL_CONSOLE) - regval |= SYSCON_SYSAHBCLKCTRL_UART; -#endif - putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); - - /* Step 3: Enable peripheral clocking for the console UART and disable - * clocking for all other UARTs - */ - - /* Don't divide the UART Clock it is be equal to Peripheral Clock */ - - putreg32(1, LPC11_SYSCON_UARTCLKDIV); - - /* Configure the console (only) */ - -#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - - /* Clear fifos */ - - putreg32(UART_FCR_RXRST | UART_FCR_TXRST, - CONSOLE_BASE + LPC11_UART_FCR_OFFSET); - - /* Set trigger */ - - putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8, - CONSOLE_BASE + LPC11_UART_FCR_OFFSET); - - /* Set up the LCR and set DLAB=1 */ - - putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB, - CONSOLE_BASE + LPC11_UART_LCR_OFFSET); - - /* Configure the Baud rate - * - * The fractional is calculated as - * (PCLK % (16 * Baudrate)) / (16 * Baudrate) - */ - - dval = coreclk % rate16; - - /* The PCLK / (16 * Baudrate) is fractional - * dval = pclk % rate16 - * mval = rate16 - * now normalize the ratio - * dval / mval = 1 / new_mval - * new_mval = mval / dval; - * new_dval = 1 - */ - - if (dval > 0) - { - mval = rate16 / dval; - dval = 1; - - if (mval > 12) - { - dval = 0; - } - } - - dval &= 0xf; - mval &= 0xf; - - dl = coreclk / (rate16 + rate16 * dval / mval); - - /* Set the BAUD divisor */ - - putreg32(dl & 0xff, CONSOLE_BASE + LPC11_UART_DLL_OFFSET); - putreg32(dl >> 8, CONSOLE_BASE + LPC11_UART_DLM_OFFSET); - - /* Set the BAUD fractional */ - - putreg32((mval << UART_FDR_MULVAL_SHIFT) | - (dval << UART_FDR_DIVADDVAL_SHIFT), - CONSOLE_BASE + LPC11_UART_FDR_OFFSET); - - /* Clear DLAB */ - - putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC11_UART_LCR_OFFSET); - - /* Configure the FIFOs */ - - putreg32(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | - UART_FCR_FIFOEN, - CONSOLE_BASE + LPC11_UART_FCR_OFFSET); -#endif -#endif /* HAVE_UART */ -} diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c deleted file mode 100644 index 00ec359fb2f..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_serial.c +++ /dev/null @@ -1,1033 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_serial.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TERMIOS -# include -#endif - -#include -#include -#include -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "chip.h" -#include "hardware/lpc11_uart.h" -#include "lpc11_gpio.h" -#include "lpc11_serial.h" - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/* If we are not using the serial driver for the console, then we still must - * provide some minimal implementation of up_putc. - */ - -#if defined(USE_SERIALDRIVER) && defined(HAVE_UART) - -/* Configuration ************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - uint32_t uartbase; /* Base address of UART registers */ - uint32_t baud; /* Configured baud */ - uint32_t ier; /* Saved IER value */ - uint8_t irq; /* IRQ associated with this UART */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ -#ifdef LPC111x - uint8_t cclkdiv; /* Divisor needed to get PCLK from CCLK */ -#endif - bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context, void *arg); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/* I/O buffers */ - -#ifdef CONFIG_LPC11_UART0 -static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; -#endif - -/* This describes the state of the LPC11xx uart0 port. */ - -#ifdef CONFIG_LPC11_UART0 -static struct up_dev_s g_uart0priv = -{ - .uartbase = LPC11_UART0_BASE, - .baud = CONFIG_UART0_BAUD, - .irq = LPC11_IRQ_UART, - .parity = CONFIG_UART0_PARITY, - .bits = CONFIG_UART0_BITS, - .stopbits2 = CONFIG_UART0_2STOP, -}; - -static uart_dev_t g_uart0port = -{ - .recv = - { - .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart0priv, -}; -#endif - -/* Which UART with be tty0/console and which tty1? tty2? tty3? */ - -#ifdef HAVE_SERIAL_CONSOLE -# if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0port /* UART0=console */ -# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ -# endif -#else /* No console */ -# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ -#endif /* HAVE_SERIAL_CONSOLE */ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialin - ****************************************************************************/ - -static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) -{ - return getreg32(priv->uartbase + offset); -} - -/**************************************************************************** - * Name: up_serialout - ****************************************************************************/ - -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) -{ - putreg32(value, priv->uartbase + offset); -} - -/**************************************************************************** - * Name: up_disableuartint - ****************************************************************************/ - -static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier) -{ - if (ier) - { - *ier = priv->ier & UART_IER_ALLIE; - } - - priv->ier &= ~UART_IER_ALLIE; - up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); -} - -/**************************************************************************** - * Name: up_restoreuartint - ****************************************************************************/ - -static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier) -{ - priv->ier |= ier & UART_IER_ALLIE; - up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); -} - -/**************************************************************************** - * Name: up_enablebreaks - ****************************************************************************/ - -static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) -{ - uint32_t lcr = up_serialin(priv, LPC11_UART_LCR_OFFSET); - - if (enable) - { - lcr |= UART_LCR_BRK; - } - else - { - lcr &= ~UART_LCR_BRK; - } - - up_serialout(priv, LPC11_UART_LCR_OFFSET, lcr); -} - -/************************************************************************************ - * Name: lpc11_uartcclkdiv - * - * Description: - * Select a CCLK divider to produce the UART PCLK. The strategy is to select the - * smallest divisor that results in an solution within range of the 16-bit - * DLM and DLL divisor: - * - * PCLK = MCLK / divisor - * BAUD = PCLK / (16 * DL) - * - * Ignoring the fractional divider for now. (If you want to extend this driver - * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses - * the same peripheral and that logic could easily leveraged here). - * - * For the LPC111x the PCLK is determined by the UART-specific divisor in - * PCLKSEL0 or PCLKSEL1: - * - * PCLK = MCLK / divisor - * - * For the LPC111x, the PCLK is determined by the global divisor setting in - * the PLKSEL register (and, in that case, this function is not needed). - * - * NOTE: This is an inline function. If a typical optimization level is used and - * a constant is provided for the desired frequency, then most of the following - * logic will be optimized away. - * - ************************************************************************************/ - -#ifdef LPC111x -static inline uint32_t lpc11_uartcclkdiv(uint32_t baud) -{ - /* Ignoring the fractional divider, the BAUD is given by: - * - * BAUD = PCLK / (16 * DL), or - * DL = PCLK / BAUD / 16 - * - * Where for the LPC111x the PCLK is determined by the UART-specific divisor in - * : - * - * UART_PCLK = MAIN_CLOCK / divisor - * - */ - - /* Calculate and optimal PCLKSEL0/1 divisor. - * First, check divisor == 1. This works if the upper limit is met: - * - * DL < 0xffff, or - * PCLK / BAUD / 16 < 0xffff, or - * MCLK / BAUD / 16 < 0xffff, or - * MCLK < BAUD * 0xffff * 16 - * BAUD > MCLK / 0xffff / 16 - * - * And the lower limit is met (we can't allow DL to get very close to one). - * - * DL >= MinDL - * MCLK / BAUD / 16 >= MinDL, or - * BAUD <= CCLK / 16 / MinDL - */ - - return 1; -} -#endif /* LPC111x */ - -/************************************************************************************ - * Name: lpc11_uart0config - * - * Description: - * Configure the UART. UART0 peripherals are configured using the following - * registers: - * - * 1. Power: In the PCONP register, set bits PCUART0. - * On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1) - * and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0). - * 2. Peripheral clock: In the PCLKSEL0 register, select PCLK_UART0 and - * PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and PCLK_UART3. - * 3. Pins: Select UART pins through the PINSEL registers and pin modes - * through the PINMODE registers. UART receive pins should not have - * pull-down resistors enabled. - * - ************************************************************************************/ - -#ifdef CONFIG_LPC11_UART0 -static inline void lpc11_uart0config(void) -{ - uint32_t regval; - irqstate_t flags; - - /* Step 1: Pins configuration */ - - flags = enter_critical_section(); - lpc11_configgpio(GPIO_UART0_TXD); - lpc11_configgpio(GPIO_UART0_RXD); - - /* Step 2: Enable power on UART0 */ - - regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); - regval |= SYSCON_SYSAHBCLKCTRL_UART; - putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); - - /* Step 3: Enable clocking UART */ - - putreg32(1, LPC11_SYSCON_UARTCLKDIV); - leave_critical_section(flags); -}; -#endif - -/************************************************************************************ - * Name: lpc11_uartdl - * - * Description: - * Select a divider to produce the BAUD from the UART PCLK. - * - * BAUD = PCLK / (16 * DL), or - * DL = PCLK / BAUD / 16 - * - * Ignoring the fractional divider for now. (If you want to extend this driver - * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses - * the same peripheral and that logic could easily leveraged here). - * - ************************************************************************************/ - -#ifdef LPC111x -static inline uint32_t lpc11_uartdl(uint32_t baud, uint8_t divcode) -{ - /* TODO: Calculate DL automatically */ - - uint32_t num = 312; - - return num; -} -#else -static inline uint32_t lpc11_uartdl(uint32_t baud) -{ - return (uint32_t)BOARD_PCLK_FREQUENCY / (baud << 4); -} -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This method is - * called the first time that the serial port is opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ -#ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint16_t dl; - uint32_t lcr; - - /* Clear fifos */ - - up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST)); - - /* Set trigger */ - - up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8)); - - /* Set up the IER */ - - priv->ier = up_serialin(priv, LPC11_UART_IER_OFFSET); - - /* Set up the LCR */ - - lcr = 0; - - if (priv->bits == 7) - { - lcr |= UART_LCR_WLS_7BIT; - } - else - { - lcr |= UART_LCR_WLS_8BIT; - } - - if (priv->stopbits2) - { - lcr |= UART_LCR_STOP; - } - - if (priv->parity == 1) - { - lcr |= (UART_LCR_PE | UART_LCR_PS_ODD); - } - else if (priv->parity == 2) - { - lcr |= (UART_LCR_PE | UART_LCR_PS_EVEN); - } - - /* Enter DLAB=1 */ - - up_serialout(priv, LPC11_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); - - /* Set the BAUD divisor */ - -#ifdef LPC111x - dl = lpc11_uartdl(priv->baud, priv->cclkdiv); -#else - dl = lpc11_uartdl(priv->baud); -#endif - up_serialout(priv, LPC11_UART_DLM_OFFSET, dl >> 8); - up_serialout(priv, LPC11_UART_DLL_OFFSET, dl & 0xff); - - /* Clear DLAB */ - - up_serialout(priv, LPC11_UART_LCR_OFFSET, lcr); - - /* Configure the FIFOs */ - - up_serialout(priv, LPC11_UART_FCR_OFFSET, - (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | - UART_FCR_FIFOEN)); - -#endif - - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_disableuartint(priv, NULL); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method - * is called when the serial port is opened. Normally, this is just after - * the setup() method is called, however, the serial console may - * operate in a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX - * and TX interrupts are not enabled until the txint() and rxint() methods - * are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt, dev); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The - * exception is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked when an - * interrupt received on the 'irq' It should call uart_transmitchars or - * uart_receivechar to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'irq' number into the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context, void *arg) -{ - struct uart_dev_s *dev = (struct uart_dev_s *)arg; - struct up_dev_s *priv; - uint32_t status; - int passes; - - DEBUGASSERT(dev != NULL && dev->priv != NULL); - priv = (struct up_dev_s *)dev->priv; - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - for (passes = 0; passes < 256; passes++) - { - /* Get the current UART status and check for loop - * termination conditions - */ - - status = up_serialin(priv, LPC11_UART_IIR_OFFSET); - - /* The UART_IIR_INTSTATUS bit should be zero if there are pending - * interrupts - */ - - if ((status & UART_IIR_INTSTATUS) != 0) - { - /* Break out of the loop when there is no longer a - * pending interrupt - */ - - break; - } - - /* Handle the interrupt by its interrupt ID field */ - - switch (status & UART_IIR_INTID_MASK) - { - /* Handle incoming, receive bytes (with or without timeout) */ - - case UART_IIR_INTID_RDA: - case UART_IIR_INTID_CTI: - { - uart_recvchars(dev); - break; - } - - /* Handle outgoing, transmit bytes */ - - case UART_IIR_INTID_THRE: - { - uart_xmitchars(dev); - break; - } - - /* Just clear any line status interrupts */ - - case UART_IIR_INTID_RLS: - { - /* Read the line status register (LSR) to clear */ - - status = up_serialin(priv, LPC11_UART_LSR_OFFSET); - _info("LSR: %02x\n", status); - break; - } - - /* There should be no other values */ - - default: - { - _err("ERROR: Unexpected IIR: %02x\n", status); - break; - } - } - } - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret = OK; - - switch (cmd) - { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; -#endif - - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - { - irqstate_t flags = enter_critical_section(); - up_enablebreaks(priv, true); - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - { - irqstate_t flags; - flags = enter_critical_section(); - up_enablebreaks(priv, false); - leave_critical_section(flags); - } - break; - -#ifdef CONFIG_SERIAL_TERMIOS - case TCGETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - /* TODO: Other termios fields are not yet returned. - * Note that cfsetospeed is not necessary because we have - * knowledge that only one speed is supported. - * Both cfset(i|o)speed() translate to cfsetspeed. - */ - - cfsetispeed(termiosp, priv->baud); - } - break; - - case TCSETS: - { - struct termios *termiosp = (struct termios *)arg; - uint32_t lcr; /* Holds current values of line control register */ - uint16_t dl; /* Divisor latch */ - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - /* TODO: Handle other termios settings. - * Note that only cfgetispeed is used because we have knowledge - * that only one speed is supported. - */ - - /* Get the c_speed field in the termios struct */ - - priv->baud = cfgetispeed(termiosp); - - /* TODO: Re-calculate the optimal CCLK divisor for the new baud and - * and reset the divider in the CLKSEL0/1 register. - */ - -#ifdef LPC111x - priv->cclkdiv = lpc11_uartcclkdiv(priv->baud); -#endif - /* DLAB open latch */ - /* REVISIT: Shouldn't we just call up_setup() to do all of the following? */ - - lcr = getreg32(priv->uartbase + LPC11_UART_LCR_OFFSET); - up_serialout(priv, LPC11_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); - - /* Set the BAUD divisor */ - -#ifdef LPC111x - dl = lpc11_uartdl(priv->baud, priv->cclkdiv); -#else - dl = lpc11_uartdl(priv->baud); -#endif - up_serialout(priv, LPC11_UART_DLM_OFFSET, dl >> 8); - up_serialout(priv, LPC11_UART_DLL_OFFSET, dl & 0xff); - - /* Clear DLAB */ - - up_serialout(priv, LPC11_UART_LCR_OFFSET, lcr); - } - break; -#endif - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, uint32_t *status) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t rbr; - - *status = up_serialin(priv, LPC11_UART_LSR_OFFSET); - rbr = up_serialin(priv, LPC11_UART_RBR_OFFSET); - return rbr; -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - if (enable) - { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->ier |= UART_IER_RBRIE; -#endif - } - else - { - priv->ier &= ~UART_IER_RBRIE; - } - - up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_serialout(priv, LPC11_UART_THR_OFFSET, (uint32_t)ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - irqstate_t flags; - - flags = enter_critical_section(); - if (enable) - { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->ier |= UART_IER_THREIE; - up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); -#endif - } - else - { - priv->ier &= ~UART_IER_THREIE; - up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the transmit fifo is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); -} - -/**************************************************************************** - * Public Funtions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called - * before up_serialinit. - * - * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() - * very early in the boot sequence. - * - ****************************************************************************/ - -void up_earlyserialinit(void) -{ - /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */ - -#ifdef CONFIG_LPC11_UART0 -#ifdef LPC111x - g_uart0priv.cclkdiv = lpc11_uartcclkdiv(CONFIG_UART0_BAUD); -#endif -#ifndef CONFIG_UART0_SERIAL_CONSOLE - lpc11_uart0config(); -#endif - up_disableuartint(&g_uart0priv, NULL); -#endif - - /* Configuration whichever one is the console */ - -#ifdef CONSOLE_DEV - CONSOLE_DEV.isconsole = true; - up_setup(&CONSOLE_DEV); -#endif -} - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Register serial console and serial ports. This assumes that - * up_earlyserialinit was called previously. - * - ****************************************************************************/ - -void up_serialinit(void) -{ -#ifdef CONSOLE_DEV - (void)uart_register("/dev/console", &CONSOLE_DEV); -#endif -#ifdef TTYS0_DEV - (void)uart_register("/dev/ttyS0", &TTYS0_DEV); -#endif -#ifdef TTYS1_DEV - (void)uart_register("/dev/ttyS1", &TTYS1_DEV); -#endif -#ifdef TTYS2_DEV - (void)uart_register("/dev/ttyS2", &TTYS2_DEV); -#endif -#ifdef TTYS3_DEV - (void)uart_register("/dev/ttyS3", &TTYS3_DEV); -#endif -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef HAVE_SERIAL_CONSOLE - struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; - uint32_t ier; - up_disableuartint(priv, &ier); -#endif - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_lowputc('\r'); - } - - up_lowputc(ch); -#ifdef HAVE_SERIAL_CONSOLE - up_restoreuartint(priv, ier); -#endif - - return ch; -} - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef HAVE_UART - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_lowputc('\r'); - } - - up_lowputc(ch); -#endif - return ch; -} - -#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/lpc11xx/lpc11_serial.h b/arch/arm/src/lpc11xx/lpc11_serial.h deleted file mode 100644 index 82d4e59051a..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_serial.h +++ /dev/null @@ -1,98 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_serial.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "hardware/lpc11_uart.h" -#include "hardware/lpc11_syscon.h" - -#include "lpc11_gpio.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Configuration *********************************************************************/ - -/* Are any UARTs enabled? */ - -#undef HAVE_UART -#if defined(CONFIG_LPC11_UART0) -# define HAVE_UART 1 -#endif - -/* Is there a serial console? There should be at most one defined. It could be on - * any UARTn, n=0,1,2,3 - */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC11_UART0) -# define HAVE_SERIAL_CONSOLE 1 -#else -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef HAVE_SERIAL_CONSOLE -#endif - -/* We cannot allow the DLM/DLL divisor to become to small or will will lose too - * much accuracy. This following is a "fudge factor" that represents the minimum - * value of the divisor that we will permit. - */ - -#define UART_MINDL 32 - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c deleted file mode 100644 index 78b306549ba..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_spi.c +++ /dev/null @@ -1,592 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_spi.c - * - * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "hardware/lpc11_syscon.h" -#include "lpc11_gpio.h" -#include "lpc11_spi.h" - -#ifdef CONFIG_LPC11_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ -/* This driver does not support the SPI exchange method. */ - -#ifdef CONFIG_SPI_EXCHANGE -# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration" -#endif - -/* SSP Clocking *************************************************************/ -/* The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK). - * SPI_CLOCK may be further divided by 8-254 to get the SPI clock. If we - * want a usable range of 4KHz to 25MHz for the SPI, then: - * - * 1. SPICLK must be greater than (8*25MHz) = 200MHz (so we can't reach 25MHz), - * and - * 2. SPICLK must be less than (254*40Khz) = 101.6MHz. - * - * If we assume that CCLK less than or equal to 100MHz, we can just - * use the CCLK undivided to get the SPI_CLOCK. - */ - -#define SPI_PCLKSET_DIV SYSCON_PCLKSEL_CCLK -#define SPI_CLOCK LPC11_CCLK - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the SSP driver */ - -struct lpc11_spidev_s -{ - struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ - sem_t exclsem; /* Held while chip is selected for mutual exclusion */ - uint32_t frequency; /* Requested clock frequency */ - uint32_t actual; /* Actual clock frequency */ - uint8_t nbits; /* Width of word in bits (8 to 16) */ - uint8_t mode; /* Mode 0,1,2,3 */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* SPI methods */ - -static int spi_lock(FAR struct spi_dev_s *dev, bool lock); -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, - uint32_t frequency); -static void spi_setmode(FAR struct spi_dev_s *dev, - enum spi_mode_e mode); -static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); -static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); -static void spi_sndblock(FAR struct spi_dev_s *dev, - FAR const void *buffer, size_t nwords); -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, - size_t nwords); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct spi_ops_s g_spiops = -{ - .lock = spi_lock, - .select = lpc11_spiselect, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = 0, /* Not supported */ -#endif - .status = lpc11_spistatus, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc11_spicmddata, -#endif - .send = spi_send, - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc11_spiregister, /* Provided externally */ -#else - .registercallback = 0, /* Not implemented */ -#endif -}; - -static struct lpc11_spidev_s g_spidev = -{ - .spidev = { &g_spiops }, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: spi_lock - * - * Description: - * On SPI buses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the buses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int spi_lock(FAR struct spi_dev_s *dev, bool lock) -{ - FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; - int ret; - - if (lock) - { - /* Take the semaphore (perhaps waiting) */ - - do - { - ret = nxsem_wait(&priv->exclsem); - - /* The only case that an error should occur here is if the wait - * was awakened by a signal. - */ - - DEBUGASSERT(ret == OK || ret == -EINTR); - } - while (ret == -EINTR); - } - else - { - (void)nxsem_post(&priv->exclsem); - ret = 0 - } - - return ret; -} - -/**************************************************************************** - * Name: spi_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, - uint32_t frequency) -{ - FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; - uint32_t divisor; - uint32_t actual; - - /* Check if the requested frequence is the same as the frequency selection */ - - DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2); - - if (priv->frequency == frequency) - { - /* We are already at this frequency. Return the actual. */ - - return priv->actual; - } - - /* frequency = SPI_CLOCK / divisor, or divisor = SPI_CLOCK / frequency */ - - divisor = SPI_CLOCK / frequency; - - /* The SPI CCR register must contain an even number greater than or equal - * to 8. - */ - - if (divisor < 8) - { - divisor = 8; - } - else if (divisor > 254) - { - divisor = 254; - } - - divisor = (divisor + 1) & ~1; - - /* Save the new divisor value */ - - putreg32(divisor, LPC11_SPI_CCR); - - /* Calculate the new actual */ - - actual = SPI_CLOCK / divisor; - - /* Save the frequency setting */ - - priv->frequency = frequency; - priv->actual = actual; - - spiinfo("Frequency %d->%d\n", frequency, actual); - return actual; -} - -/**************************************************************************** - * Name: spi_setmode - * - * Description: - * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions - * - * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested - * - * Returned Value: - * none - * - ****************************************************************************/ - -static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) -{ - FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; - uint32_t regval; - - /* Has the mode changed? */ - - if (mode != priv->mode) - { - /* Yes... Set CR appropriately */ - - regval = getreg32(LPC11_SPI_CR); - regval &= ~(SPI_CR_CPOL | SPI_CR_CPHA); - - switch (mode) - { - case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ - break; - - case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ - regval |= SPI_CR_CPHA; - break; - - case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ - regval |= SPI_CR_CPOL; - break; - - case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SPI_CR_CPOL | SPI_CR_CPHA); - break; - - default: - DEBUGASSERT(FALSE); - return; - } - - putreg32(regval, LPC11_SPI_CR); - - /* Save the mode so that subsequent re-configurations will be faster */ - - priv->mode = mode; - } -} - -/**************************************************************************** - * Name: spi_setbits - * - * Description: - * Set the number if bits per word. - * - * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits requests - * - * Returned Value: - * none - * - ****************************************************************************/ - -static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) -{ - FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; - uint32_t regval; - - /* Has the number of bits changed? */ - - DEBUGASSERT(priv && nbits > 7 && nbits < 17); - - if (nbits != priv->nbits) - { - /* Yes... Set CR appropriately */ - - regval = getreg32(LPC11_SPI_CR); - regval &= ~SPI_CR_BITS_MASK; - regval |= (nbits << SPI_CR_BITS_SHIFT) & SPI_CR_BITS_MASK; - regval |= SPI_CR_BITENABLE; - regval = getreg32(LPC11_SPI_CR); - - /* Save the selection so the subsequence re-configurations will be faster */ - - priv->nbits = nbits; - } -} - -/**************************************************************************** - * Name: spi_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) -{ - /* Write the data to transmitted to the SPI Data Register */ - - putreg32((uint32_t)wd, LPC11_SPI_DR); - - /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The - * SPIF bit will be set after the last sampling clock edge of the SPI - * data transfer. - */ - - while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); - - /* Read the SPI Status Register again to clear the status bit */ - - (void)getreg32(LPC11_SPI_SR); - return (uint16_t)getreg32(LPC11_SPI_DR); -} - -/**************************************************************************** - * Name: spi_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, - size_t nwords) -{ - FAR uint8_t *ptr = (FAR uint8_t *)buffer; - uint8_t data; - - spiinfo("nwords: %d\n", nwords); - while (nwords) - { - /* Write the data to transmitted to the SPI Data Register */ - - data = *ptr++; - putreg32((uint32_t)data, LPC11_SPI_DR); - - /* Wait for the SPIF bit in the SPI Status Register to be set to 1. - * The SPIF bit will be set after the last sampling clock edge of - * the SPI data transfer. - */ - - while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); - - /* Read the SPI Status Register again to clear the status bit */ - - (void)getreg32(LPC11_SPI_SR); - nwords--; - } -} - -/**************************************************************************** - * Name: spi_recvblock - * - * Description: - * Revice a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer in which to receive data - * nwords - the length of data that can be received in the buffer in - * number of words. The wordsize is determined by the number of - * bits-per-word selected for the SPI interface. If nbits <= 8, - * the data is packed into uint8_t's; if nbits >8, the data is - * packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, - size_t nwords) -{ - FAR uint8_t *ptr = (FAR uint8_t *)buffer; - - spiinfo("nwords: %d\n", nwords); - while (nwords) - { - /* Write some dummy data to the SPI Data Register in order to clock the - * read data. - */ - - putreg32(0xff, LPC11_SPI_DR); - - /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The - * SPIF bit will be set after the last sampling clock edge of the SPI - * data transfer. - */ - - while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); - - /* Read the SPI Status Register again to clear the status bit */ - - (void)getreg32(LPC11_SPI_SR); - - /* Read the received data from the SPI Data Register */ - - *ptr++ = (uint8_t)getreg32(LPC11_SPI_DR); - nwords--; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_spibus_initialize - * - * Description: - * Initialize the selected SPI port. - * - * Input Parameters: - * Port number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *lpc11_spibus_initialize(int port) -{ - FAR struct lpc11_spidev_s *priv = &g_spidev; - irqstate_t flags; - uint32_t regval; - - /* Configure multiplexed pins as connected on the board. Chip select - * pins must be configured by board-specific logic. All SPI pins and - * one SPI1 pin (SCK) have multiple, alternative pin selection. - * Definitions in the board.h file must be provided to resolve the - * board-specific pin configuration like: - * - * #define GPIO_SPI_SCK GPIO_SPI_SCK_1 - */ - - flags = enter_critical_section(); - lpc11_configgpio(GPIO_SPI_SCK); - lpc11_configgpio(GPIO_SPI_MISO); - lpc11_configgpio(GPIO_SPI_MOSI); - - /* Configure clocking */ - - regval = getreg32(LPC11_SYSCON_PCLKSEL0); - regval &= ~SYSCON_PCLKSEL0_SPI_MASK; - regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT); - putreg32(regval, LPC11_SYSCON_PCLKSEL0); - - /* Enable peripheral clocking to SPI and SPI1 */ - - regval = getreg32(LPC11_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCSPI; - putreg32(regval, LPC11_SYSCON_PCONP); - leave_critical_section(flags); - - /* Configure 8-bit SPI mode and master mode */ - - putreg32(SPI_CR_BITS_8BITS | SPI_CR_BITENABLE | SPI_CR_MSTR, - LPC11_SPI_CR); - - /* Set the initial SPI configuration */ - - priv->frequency = 0; - priv->nbits = 8; - priv->mode = SPIDEV_MODE0; - - /* Select a default frequency of approx. 400KHz */ - - spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); - - /* Initialize the SPI semaphore that enforces mutually exclusive access */ - - nxsem_init(&priv->exclsem, 0, 1); - return &priv->spidev; -} - -#endif /* CONFIG_LPC11_SPI */ diff --git a/arch/arm/src/lpc11xx/lpc11_spi.h b/arch/arm/src/lpc11xx/lpc11_spi.h deleted file mode 100644 index b17f5215080..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_spi.h +++ /dev/null @@ -1,160 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_spi.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifdef CONFIG_LPC11_SPI - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc11_spibus_initialize - * - * Description: - * Initialize the selected SPI port. - * - * Input Parameters: - * Port number (for hardware that has mutiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure - * - ************************************************************************************/ - -FAR struct spi_dev_s *lpc11_spibus_initialize(int port); - -/************************************************************************************ - * Name: lpc11_spiselect, lpc11_status, and lpc11_spicmddata - * - * Description: - * These external functions must be provided by board-specific logic. They are - * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including lpc11_spibus_initialize()) are provided by common LPC11xx logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in lpc11_boardinitialize() to configure SPI chip select pins. - * 2. Provide lpc11_spiselect() and lpc11_spistatus() functions in your board- - * specific logic. These functions will perform chip selection and status - * operations using GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * lpc11_spicmddata() functions in your board-specific logic. This function - * will perform cmd/data selection operations using GPIOs in the way your - * board is configured. - * 3. Add a call to lpc11_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by lpc11_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), - * for example, will bind the SPI driver to the SPI MMC/SD driver). - * - ************************************************************************************/ - -void lpc11_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t lpc11_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); -#ifdef CONFIG_SPI_CMDDATA -int lpc11_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -/************************************************************************************ - * Name: spi_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be called - * from spiselect after a device is deselected (if you worry about such - * things). - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ************************************************************************************/ - -void spi_flush(FAR struct spi_dev_s *dev); - -/************************************************************************************ - * Name: lpc11_spiregister - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD drvier when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function must - * must be implemented. These functions implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The funtion to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ************************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -int lpc11_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); -#endif - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_LPC11_SPI */ -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.c b/arch/arm/src/lpc11xx/lpc11_ssp.c deleted file mode 100644 index 780a8945626..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_ssp.c +++ /dev/null @@ -1,1057 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_ssp.c - * - * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "hardware/lpc11_syscon.h" -#include "lpc11_gpio.h" -#include "lpc11_ssp.h" - -#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) || \ - defined(CONFIG_LPC11_SSP2) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ -/* This driver does not support the SPI exchange method. */ - -#ifdef CONFIG_SPI_EXCHANGE -# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration" -#endif - -/* SSP Clocking *************************************************************/ - -#if defined(LPC111x) -/* The CPU clock by 1, 2, 4, or 8 to get the SSP peripheral clock (SSP_CLOCK). - * SSP_CLOCK may be further divided by 2-254 to get the SSP clock. If we - * want a usable range of 4KHz to 25MHz for the SSP, then: - * - * 1. SSPCLK must be greater than (2*25MHz) = 50MHz, and - * 2. SSPCLK must be less than (254*40Khz) = 101.6MHz. - * - * If we assume that CCLK less than or equal to 100MHz, we can just - * use the CCLK undivided to get the SSP_CLOCK. - */ - -# if LPC11_CCLK > 100000000 -# error "CCLK <= 100,000,000 assumed" -# endif - -# define SSP_PCLKSET_DIV SYSCON_PCLKSEL_CCLK -# define SSP_CLOCK LPC11_CCLK - -#elif defined(LPC111x) -/* All peripherals are clocked by the same peripheral clock in the LPC111x - * family. - */ - -# define SSP_CLOCK BOARD_PCLK_FREQUENCY - -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure descibes the state of the SSP driver */ - -struct lpc11_sspdev_s -{ - struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ - uint32_t sspbase; /* SPIn base address */ -#ifdef CONFIG_LPC11_SSP_INTERRUPTS - uint8_t sspirq; /* SPI IRQ number */ -#endif - sem_t exclsem; /* Held while chip is selected for mutual exclusion */ - uint32_t frequency; /* Requested clock frequency */ - uint32_t actual; /* Actual clock frequency */ - uint8_t nbits; /* Width of word in bits (4 to 16) */ - uint8_t mode; /* Mode 0,1,2,3 */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helpers */ - -static inline uint32_t ssp_getreg(FAR struct lpc11_sspdev_s *priv, - uint8_t offset); -static inline void ssp_putreg(FAR struct lpc11_sspdev_s *priv, - uint8_t offset, uint32_t value); - -/* SPI methods */ - -static int ssp_lock(FAR struct spi_dev_s *dev, bool lock); -static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, - uint32_t frequency); -static void ssp_setmode(FAR struct spi_dev_s *dev, - enum spi_mode_e mode); -static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits); -static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t ch); -static void ssp_sndblock(FAR struct spi_dev_s *dev, - FAR const void *buffer, size_t nwords); -static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, - size_t nwords); - -/* Initialization */ - -#ifdef CONFIG_LPC11_SSP0 -static inline FAR struct lpc11_sspdev_s *lpc11_ssp0initialize(void); -#endif -#ifdef CONFIG_LPC11_SSP1 -static inline FAR struct lpc11_sspdev_s *lpc11_ssp1initialize(void); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_LPC11_SSP0 -static const struct spi_ops_s g_spi0ops = -{ - .lock = ssp_lock, - .select = lpc11_ssp0select, /* Provided externally */ - .setfrequency = ssp_setfrequency, - .setmode = ssp_setmode, - .setbits = ssp_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = 0, /* Not supported */ -#endif - .status = lpc11_ssp0status, /* Provided externally */ -#ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc11_ssp0cmddata, /* Provided externally */ -#endif - .send = ssp_send, - .sndblock = ssp_sndblock, - .recvblock = ssp_recvblock, -#ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc11_ssp0register, /* Provided externally */ -#else - .registercallback = 0, /* Not implemented */ -#endif -}; - -static struct lpc11_sspdev_s g_ssp0dev = -{ - .spidev = { &g_spi0ops }, - .sspbase = LPC11_SSP0_BASE, -#ifdef CONFIG_LPC11_SSP_INTERRUPTS - .sspirq = LPC11_IRQ_SSP0, -#endif -}; -#endif /* CONFIG_LPC11_SSP0 */ - -#ifdef CONFIG_LPC11_SSP1 -static const struct spi_ops_s g_spi1ops = -{ - .lock = ssp_lock, - .select = lpc11_ssp1select, /* Provided externally */ - .setfrequency = ssp_setfrequency, - .setmode = ssp_setmode, - .setbits = ssp_setbits, - .status = lpc11_ssp1status, /* Provided externally */ -#ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc11_ssp1cmddata, /* Provided externally */ -#endif - .send = ssp_send, - .sndblock = ssp_sndblock, - .recvblock = ssp_recvblock, -#ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc11_ssp1register, /* Provided externally */ -#else - .registercallback = 0, /* Not implemented */ -#endif -}; - -static struct lpc11_sspdev_s g_ssp1dev = -{ - .spidev = { &g_spi1ops }, - .sspbase = LPC11_SSP1_BASE, -#ifdef CONFIG_LPC11_SSP_INTERRUPTS - .sspirq = LPC11_IRQ_SSP1, -#endif -}; -#endif /* CONFIG_LPC11_SSP1 */ - -#ifdef CONFIG_LPC11_SSP2 -static const struct spi_ops_s g_spi2ops = -{ - .lock = ssp_lock, - .select = lpc11_ssp2select, /* Provided externally */ - .setfrequency = ssp_setfrequency, - .setmode = ssp_setmode, - .setbits = ssp_setbits, - .status = lpc11_ssp2status, /* Provided externally */ -#ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc11_ssp2cmddata, /* Provided externally */ -#endif - .send = ssp_send, - .sndblock = ssp_sndblock, - .recvblock = ssp_recvblock, -#ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc11_ssp2register, /* Provided externally */ -#else - .registercallback = 0, /* Not implemented */ -#endif -}; - -static struct lpc11_sspdev_s g_ssp2dev = -{ - .spidev = { &g_spi2ops }, - .sspbase = LPC11_SSP2_BASE, -#ifdef CONFIG_LPC11_SSP_INTERRUPTS - .sspirq = LPC11_IRQ_SSP2, -#endif -}; -#endif /* CONFIG_LPC11_SSP2 */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ssp_getreg - * - * Description: - * Get the contents of the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * - * Returned Value: - * The contents of the 32-bit register - * - ****************************************************************************/ - -static inline uint32_t ssp_getreg(FAR struct lpc11_sspdev_s *priv, - uint8_t offset) -{ - return getreg32(priv->sspbase + (uint32_t)offset); -} - -/**************************************************************************** - * Name: ssp_putreg - * - * Description: - * Write a 32-bit value to the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * value - the 16-bit value to be written - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void ssp_putreg(FAR struct lpc11_sspdev_s *priv, - uint8_t offset, uint32_t value) -{ - putreg32(value, priv->sspbase + (uint32_t)offset); -} - -/**************************************************************************** - * Name: ssp_lock - * - * Description: - * On SPI buses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the buses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int ssp_lock(FAR struct spi_dev_s *dev, bool lock) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - int ret - - if (lock) - { - /* Take the semaphore (perhaps waiting) */ - - do - { - ret = nxsem_wait(&priv->exclsem); - - /* The only case that an error should occur here is if the wait - * was awakened by a signal. - */ - - DEBUGASSERT(ret == OK || ret == -EINTR); - } - while (ret == -EINTR); - } - else - { - (void)nxsem_post(&priv->exclsem); - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: ssp_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - uint32_t cpsdvsr; - uint32_t scr; - uint32_t regval; - uint32_t actual; - - /* Check if the requested frequency is the same as the frequency selection */ - - DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2); - - if (priv->frequency == frequency) - { - /* We are already at this frequency. Return the actual. */ - - return priv->actual; - } - - /* The SSP bit frequency is given by: - * - * frequency = SSP_CLOCK / (CPSDVSR * (SCR+1)). - * - * Let's try for a solution with the smallest value of SCR. NOTES: - * (1) In the calculations below, the value of the variable 'scr' is - * (SCR+1) in the above equation. (2) On slower LPC11xx parts, SCR - * will probably always be zero. - */ - - for (scr = 1; scr <= 256; scr++) - { - /* CPSDVSR = SSP_CLOCK / (SCR + 1) / frequency */ - - cpsdvsr = SSP_CLOCK / (scr * frequency); - - /* Break out on the first solution we find with the smallest value - * of SCR and with CPSDVSR within the maximum range or 254. - */ - - if (cpsdvsr < 255) - { - break; - } - } - - DEBUGASSERT(scr <= 256 && cpsdvsr <= 255); - - /* "In master mode, CPSDVSRmin = 2 or larger (even numbers only)" */ - - if (cpsdvsr < 2) - { - /* Clip to the minimum value. */ - - cpsdvsr = 2; - } - else if (cpsdvsr > 254) - { - /* This should never happen */ - - cpsdvsr = 254; - } - - /* Force even */ - - cpsdvsr = (cpsdvsr + 1) & ~1; - - /* Save the new CPSDVSR and SCR values */ - - ssp_putreg(priv, LPC11_SSP_CPSR_OFFSET, cpsdvsr); - - regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET); - regval &= ~SSP_CR0_SCR_MASK; - regval |= ((scr - 1) << SSP_CR0_SCR_SHIFT); - ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, regval); - - /* Calculate the new actual */ - - actual = SSP_CLOCK / (cpsdvsr * scr); - - /* Save the frequency setting */ - - priv->frequency = frequency; - priv->actual = actual; - - spiinfo("Frequency %d->%d\n", frequency, actual); - return actual; -} - -/**************************************************************************** - * Name: ssp_setmode - * - * Description: - * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions - * - * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested - * - * Returned Value: - * none - * - ****************************************************************************/ - -static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - uint32_t regval; - - /* Has the mode changed? */ - - if (mode != priv->mode) - { - /* Yes... Set CR0 appropriately */ - - regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET); - regval &= ~(SSP_CR0_CPOL | SSP_CR0_CPHA); - - switch (mode) - { - case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ - break; - - case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ - regval |= SSP_CR0_CPHA; - break; - - case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ - regval |= SSP_CR0_CPOL; - break; - - case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SSP_CR0_CPOL | SSP_CR0_CPHA); - break; - - default: - spierr("ERROR: Bad mode: %d\n", mode); - DEBUGASSERT(FALSE); - return; - } - - ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, regval); - - /* Save the mode so that subsequent re-configurations will be faster */ - - priv->mode = mode; - } -} - -/**************************************************************************** - * Name: ssp_setbits - * - * Description: - * Set the number if bits per word. - * - * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits requests - * - * Returned Value: - * none - * - ****************************************************************************/ - -static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - uint32_t regval; - - /* Has the number of bits changed? */ - - DEBUGASSERT(priv && nbits > 3 && nbits < 17); - - if (nbits != priv->nbits) - { - /* Yes... Set CR1 appropriately */ - - regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET); - regval &= ~SSP_CR0_DSS_MASK; - regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT); - ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, regval); - - /* Save the selection so the subsequence re-configurations will be faster */ - - priv->nbits = nbits; - } -} - -/**************************************************************************** - * Name: ssp_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - register uint32_t regval; - - /* Wait while the TX FIFO is full */ - - while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF)); - - /* Write the byte to the TX FIFO */ - - ssp_putreg(priv, LPC11_SSP_DR_OFFSET, (uint32_t)wd); - - /* Wait for the RX FIFO not empty */ - - while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE)); - - /* Get the value from the RX FIFO and return it */ - - regval = ssp_getreg(priv, LPC11_SSP_DR_OFFSET); - spiinfo("%04x->%04x\n", wd, regval); - return (uint16_t)regval; -} - -/**************************************************************************** - * Name: ssp_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, - size_t nwords) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - union - { - FAR const uint8_t *p8; - FAR const uint16_t *p16; - FAR const void *pv; - } u; - uint32_t data; - uint32_t sr; - - /* Loop while thre are bytes remaining to be sent */ - - spiinfo("nwords: %d\n", nwords); - u.pv = buffer; - while (nwords > 0) - { - /* While the TX FIFO is not full and there are bytes left to send */ - - while ((ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords) - { - /* Fetch the data to send */ - - if (priv->nbits > 8) - { - data = (uint32_t)*u.p16++; - } - else - { - data = (uint32_t)*u.p8++; - } - - /* Send the data */ - - ssp_putreg(priv, LPC11_SSP_DR_OFFSET, data); - nwords--; - } - } - - /* Then discard all card responses until the RX & TX FIFOs are emptied. */ - - spiinfo("discarding\n"); - do - { - /* Is there anything in the RX fifo? */ - - sr = ssp_getreg(priv, LPC11_SSP_SR_OFFSET); - if ((sr & SSP_SR_RNE) != 0) - { - /* Yes.. Read and discard */ - - (void)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); - } - - /* There is a race condition where TFE may go true just before - * RNE goes true and this loop terminates prematurely. The nasty - * little delay in the following solves that (it could probably be - * tuned to improve performance). - */ - - else if ((sr & SSP_SR_TFE) != 0) - { - up_udelay(100); - sr = ssp_getreg(priv, LPC11_SSP_SR_OFFSET); - } - } - while ((sr & SSP_SR_RNE) != 0 || (sr & SSP_SR_TFE) == 0); -} - -/**************************************************************************** - * Name: ssp_recvblock - * - * Description: - * Receive a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer in which to recieve data - * nwords - the length of data that can be received in the buffer in - * number of words. The wordsize is determined by the number of - * bits-per-word selected for the SPI interface. If nbits <= 8, - * the data is packed into uint8_t's; if nbits >8, the data is - * packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, - size_t nwords) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - union - { - FAR uint8_t *p8; - FAR uint16_t *p16; - FAR void *pv; - } u; - uint32_t data; - uint32_t rxpending = 0; - - /* While there is remaining to be sent (and no synchronization error has - * occurred). - */ - - spiinfo("nwords: %d\n", nwords); - u.pv = buffer; - while (nwords || rxpending) - { - /* Fill the transmit FIFO with 0xffff... - * Write 0xff to the data register while (1) the TX FIFO is - * not full, (2) we have not exceeded the depth of the TX FIFO, - * and (3) there are more bytes to be sent. - */ - - spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords); - while ((ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF) && - (rxpending < LPC11_SSP_FIFOSZ) && nwords) - { - ssp_putreg(priv, LPC11_SSP_DR_OFFSET, 0xffff); - nwords--; - rxpending++; - } - - /* Now, read the RX data from the RX FIFO while the RX FIFO is not - * empty. - */ - - spiinfo("RX: rxpending: %d\n", rxpending); - while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE) - { - data = (uint8_t)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); - if (priv->nbits > 8) - { - *u.p16++ = (uint16_t)data; - } - else - { - *u.p8++ = (uint8_t)data; - } - rxpending--; - } - } -} - -/**************************************************************************** - * Name: lpc11_ssp0initialize - * - * Description: - * Initialize the SSP0 - * - * Input Parameters: - * None - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_LPC11_SSP0 -static inline FAR struct lpc11_sspdev_s *lpc11_ssp0initialize(void) -{ - irqstate_t flags; - uint32_t regval; - - /* Configure multiplexed pins as connected on the board. Chip select - * pins must be configured by board-specific logic. All SSP0 pins and - * one SSP1 pin (SCK) have multiple, alternative pin selection. - * Definitions in the board.h file must be provided to resolve the - * board-specific pin configuration like: - * - * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 - */ - - flags = enter_critical_section(); - lpc11_configgpio(GPIO_SSP0_SCK); - lpc11_configgpio(GPIO_SSP0_MISO); - lpc11_configgpio(GPIO_SSP0_MOSI); - - /* Configure clocking */ - -#ifdef LPC111x - regval = getreg32(LPC11_SYSCON_PCLKSEL1); - regval &= ~SYSCON_PCLKSEL1_SSP0_MASK; - regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT); - putreg32(regval, LPC11_SYSCON_PCLKSEL1); -#endif - - /* Enable peripheral clocking to SSP0 */ - - regval = getreg32(LPC11_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCSSP0; - putreg32(regval, LPC11_SYSCON_PCONP); - leave_critical_section(flags); - - return &g_ssp0dev; -} -#endif - -/**************************************************************************** - * Name: lpc11_ssp1initialize - * - * Description: - * Initialize the SSP1 - * - * Input Parameters: - * None - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_LPC11_SSP1 -static inline FAR struct lpc11_sspdev_s *lpc11_ssp1initialize(void) -{ - irqstate_t flags; - uint32_t regval; - - /* Configure multiplexed pins as connected on the board. Chip select - * pins must be configured by board-specific logic. All SSP0 pins and - * one SSP1 pin (SCK) have multiple, alternative pin selection. - * Definitions in the board.h file must be provided to resolve the - * board-specific pin configuration like: - * - * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 - */ - - flags = enter_critical_section(); - lpc11_configgpio(GPIO_SSP1_SCK); - lpc11_configgpio(GPIO_SSP1_MISO); - lpc11_configgpio(GPIO_SSP1_MOSI); - - /* Configure clocking */ - -#ifdef LPC111x - regval = getreg32(LPC11_SYSCON_PCLKSEL0); - regval &= ~SYSCON_PCLKSEL0_SSP1_MASK; - regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT); - putreg32(regval, LPC11_SYSCON_PCLKSEL0); -#endif - - /* Enable peripheral clocking to SSP0 and SSP1 */ - - regval = getreg32(LPC11_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCSSP1; - putreg32(regval, LPC11_SYSCON_PCONP); - leave_critical_section(flags); - - return &g_ssp1dev; -} -#endif - -/**************************************************************************** - * Name: lpc11_ssp2initialize - * - * Description: - * Initialize the SSP2 - * - * Input Parameters: - * None - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_LPC11_SSP2 -static inline FAR struct lpc11_sspdev_s *lpc11_ssp2initialize(void) -{ - irqstate_t flags; - uint32_t regval; - - /* Configure multiplexed pins as connected on the board. Chip select - * pins must be configured by board-specific logic. All SSP2 pins have - * multiple, alternative pin selection. Definitions in the board.h file - * must be provided to resolve the board-specific pin configuration like: - * - * #define GPIO_SSP2_SCK GPIO_SSP2_SCK_1 - */ - - flags = enter_critical_section(); - lpc11_configgpio(GPIO_SSP2_SCK); - lpc11_configgpio(GPIO_SSP2_MISO); - lpc11_configgpio(GPIO_SSP2_MOSI); - - /* Configure clocking */ - -#ifdef LPC111x - regval = getreg32(LPC11_SYSCON_PCLKSEL0); - regval &= ~SYSCON_PCLKSEL0_SSP2_MASK; - regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP2_SHIFT); - putreg32(regval, LPC11_SYSCON_PCLKSEL0); -#endif - - /* Enable peripheral clocking to SSP0 and SSP1 */ - - regval = getreg32(LPC11_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCSSP2; - putreg32(regval, LPC11_SYSCON_PCONP); - leave_critical_section(flags); - - return &g_ssp2dev; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_sspbus_initialize - * - * Description: - * Initialize the selected SSP port. - * - * Input Parameters: - * Port number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *lpc11_sspbus_initialize(int port) -{ - FAR struct lpc11_sspdev_s *priv; - uint32_t regval; - int i; - - /* Only the SSP0 and SSP1 interfaces are supported */ - - switch (port) - { -#ifdef CONFIG_LPC11_SSP0 - case 0: - priv = lpc11_ssp0initialize(); - break; -#endif -#ifdef CONFIG_LPC11_SSP1 - case 1: - priv = lpc11_ssp1initialize(); - break; -#endif -#ifdef CONFIG_LPC11_SSP2 - case 2: - priv = lpc11_ssp2initialize(); - break; -#endif - default: - return NULL; - } - - /* Configure 8-bit SPI mode */ - - ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT | SSP_CR0_FRF_SPI); - - /* Disable the SSP and all interrupts (we'll poll for all data) */ - - ssp_putreg(priv, LPC11_SSP_CR1_OFFSET, 0); - ssp_putreg(priv, LPC11_SSP_IMSC_OFFSET, 0); - - /* Set the initial SSP configuration */ - - priv->frequency = 0; - priv->nbits = 8; - priv->mode = SPIDEV_MODE0; - - /* Select a default frequency of approx. 400KHz */ - - ssp_setfrequency((FAR struct spi_dev_s *)priv, 400000); - - /* Initialize the SPI semaphore that enforces mutually exclusive access */ - - nxsem_init(&priv->exclsem, 0, 1); - - /* Enable the SPI */ - - regval = ssp_getreg(priv, LPC11_SSP_CR1_OFFSET); - ssp_putreg(priv, LPC11_SSP_CR1_OFFSET, regval | SSP_CR1_SSE); - for (i = 0; i < LPC11_SSP_FIFOSZ; i++) - { - (void)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); - } - - return &priv->spidev; -} - -/**************************************************************************** - * Name: ssp_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be done - * after a device is deselected if you worry about such things. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -void ssp_flush(FAR struct spi_dev_s *dev) -{ - FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; - - /* Wait for the TX FIFO not full indication */ - - while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF)); - ssp_putreg(priv, LPC11_SSP_DR_OFFSET, 0xff); - - /* Wait until TX FIFO and TX shift buffer are empty */ - - while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_BSY); - - /* Wait until RX FIFO is not empty */ - - while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE)); - - /* Then read and discard bytes until the RX FIFO is empty */ - - do - { - (void)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); - } - while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE); -} - -#endif /* CONFIG_LPC11_SSP0/1 */ diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.h b/arch/arm/src/lpc11xx/lpc11_ssp.h deleted file mode 100644 index c38b4dbdf2f..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_ssp.h +++ /dev/null @@ -1,189 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_ssp.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include "hardware/lpc11_ssp.h" - -#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc11_sspbus_initialize - * - * Description: - * Initialize the selected SSP port. - * - * Input Parameters: - * Port number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ************************************************************************************/ - -FAR struct spi_dev_s *lpc11_sspbus_initialize(int port); - -/************************************************************************************ - * Name: lpc11_ssp0/ssp1select, lpc11_ssp0/ssp1status, and lpc11_ssp0/ssp1cmddata - * - * Description: - * These external functions must be provided by board-specific logic. They are - * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including lpc11_sspbus_initialize()) are provided by common LPC11xx logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in lpc11_boardinitialize() to configure SSP chip select pins. - * 2. Provide lpc11_ssp0/ssp1select() and lpc11_ssp0/ssp1status() functions - * in your board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * lpc11_ssp0/ssp1cmddata() functions in your board-specific logic. These - * functions will perform cmd/data selection operations using GPIOs in the way - * your board is configured. - * 3. Add a call to lpc11_sspbus_initialize() in your low level application - * initialization logic - * 4. The handle returned by lpc11_sspbus_initialize() may then be used to bind the - * SSP driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), - * for example, will bind the SSP driver to the SPI MMC/SD driver). - * - ************************************************************************************/ - -#ifdef CONFIG_LPC11_SSP0 -void lpc11_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t lpc11_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid); -#ifdef CONFIG_SPI_CMDDATA -int lpc11_ssp0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif -#endif - -#ifdef CONFIG_LPC11_SSP1 -void lpc11_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t lpc11_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid); -#ifdef CONFIG_SPI_CMDDATA -int lpc11_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif -#endif - -/************************************************************************************ - * Name: ssp_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be called - * from ssp0/1select after a device is deselected (if you worry about such - * things). - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ************************************************************************************/ - -#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) -void ssp_flush(FAR struct spi_dev_s *dev); -#endif - -/************************************************************************************ - * Name: lpc11_ssp0/1register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD drvier when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) must - * must be implemented. These functiosn implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The funtion to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ************************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_LPC11_SSP0 -int lpc11_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); -#endif - -#ifdef CONFIG_LPC11_SSP1 -int lpc11_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); -#endif -#endif - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_LPC11_SSP0 || CONFIG_LPC11_SSP1 */ -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_start.c b/arch/arm/src/lpc11xx/lpc11_start.c deleted file mode 100644 index a54dfee8e26..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_start.c +++ /dev/null @@ -1,173 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_start.c - * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "nvic.h" - -#include "lpc11_clockconfig.h" -#include "lpc11_lowputc.h" -#include "lpc11_userspace.h" - -#include "lpc11_start.h" - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) -#define HEAP_BASE ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -const uint32_t g_idle_topstack = IDLE_STACK; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: showprogress - * - * Description: - * Print a character on the UART to show boot status. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -# define showprogress(c) up_lowputc(c) -#else -# define showprogress(c) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: _start - * - * Description: - * This is the reset entry point. - * - ****************************************************************************/ - -void __start(void) -{ - const uint32_t *src; - uint32_t *dest; - - /* Configure the uart so that we can get debug output as soon as possible */ - - lpc11_clockconfig(); - lpc11_lowsetup(); - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (dest = &_sbss; dest < &_ebss; ) - { - *dest++ = 0; - } - - showprogress('B'); - - /* Move the initialized data section from his temporary holding spot in - * FLASH into the correct place in SRAM. The correct place in SRAM is - * give by _sdata and _edata. The temporary location is in FLASH at the - * end of all of the other read-only data (.text, .rodata) at _eronly. - */ - - for (src = &_eronly, dest = &_sdata; dest < &_edata; ) - { - *dest++ = *src++; - } - - showprogress('C'); - - /* Perform early serial initialization */ - -#ifdef USE_EARLYSERIALINIT - up_earlyserialinit(); -#endif - showprogress('D'); - - /* For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - */ - -#ifdef CONFIG_BUILD_PROTECTED - lpc11_userspace(); - showprogress('E'); -#endif - - /* Initialize onboard resources */ - - lpc11_boardinitialize(); - showprogress('F'); - - /* Then start NuttX */ - - showprogress('\r'); - showprogress('\n'); - - nx_start(); - - /* Shouldn't get here */ - - for (; ; ); -} diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c deleted file mode 100644 index 3af6342cd58..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_timer.c +++ /dev/null @@ -1,614 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_timer.c - * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "hardware/lpc11_syscon.h" -#include "lpc11_timer.h" -#include "hardware/lpc116x_pinconfig.h" -#include "lpc11_gpio.h" -#include "lpc116x_gpio.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the TIMER upper half driver. - */ - -#if defined(CONFIG_LPC11_TMR0) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* PWM/Timer Definitions ****************************************************/ -/* The following definitions are used to identify the various time types */ - -#define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */ -#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */ -#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */ -#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */ -#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */ - -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_PWM_INFO -# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pwm_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ -/* This structure represents the state of one PWM timer */ - -struct lpc11_timer_s -{ - FAR const struct pwm_ops_s *ops; /* PWM operations */ - uint8_t timid; /* Timer ID {0,...,7} */ - uint8_t channel; /* Timer output channel: {1,..4} */ - uint8_t timtype; /* See the TIMTYPE_* definitions */ - uint32_t base; /* The base address of the timer */ - uint32_t pincfg; /* Output pin configuration */ - uint32_t pclk; /* The frequency of the peripheral clock - * that drives the timer module. */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ -/* Register access */ - -static uint32_t timer_getreg(struct lpc11_timer_s *priv, int offset); -static void timer_putreg(struct lpc11_timer_s *priv, int offset, uint32_t value); - -#ifdef CONFIG_DEBUG_PWM_INFO -static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg); -#else -# define timer_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int timer_timer(FAR struct lpc11_timer_s *priv, - FAR const struct pwm_info_s *info); - -/* PWM driver methods */ - -static int timer_setup(FAR struct pwm_lowerhalf_s *dev); -static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev); - -static int timer_start(FAR struct pwm_lowerhalf_s *dev, - FAR const struct pwm_info_s *info); - -static int timer_stop(FAR struct pwm_lowerhalf_s *dev); -static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ -/* This is the list of lower half PWM driver methods used by the upper half driver */ - -static const struct pwm_ops_s g_pwmops = -{ - .setup = timer_setup, - .shutdown = timer_shutdown, - .start = timer_start, - .stop = timer_stop, - .ioctl = timer_ioctl, -}; - -#ifdef CONFIG_LPC11_TMR0 -static struct lpc11_timer_s g_pwm1dev = -{ - .ops = &g_pwmops, - .timid = 1, - .channel = CONFIG_LPC11_MAT0_PIN, - .timtype = TIMTYPE_TIM1, - .base = LPC11_TMR1_BASE, - .pincfg = GPIO_MAT0p1_2, - .pclk = (0x1 << 12), -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: timer_getreg - * - * Description: - * Read the value of an PWM timer register. - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t timer_getreg(struct lpc11_timer_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -/**************************************************************************** - * Name: timer_putreg - * - * Description: - * Read the value of an PWM timer register. - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void timer_putreg(struct lpc11_timer_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * Name: timer_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the PWM block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_PWM_INFO -static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg) -{ - pwminfo("%s:\n", msg); - pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - timer_getreg(priv, LPC11_PWM_MR0_OFFSET), - timer_getreg(priv, LPC11_PWM_MR1_OFFSET), - timer_getreg(priv, LPC11_PWM_MR2_OFFSET), - timer_getreg(priv, LPC11_PWM_MR3_OFFSET)); -#if defined(CONFIG_LPC11_TMR0) - if (priv->timtype == TIMTYPE_ADVANCED) - { - pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - timer_getreg(priv, LPC11_PWM_MR0_OFFSET), - timer_getreg(priv, LPC11_PWM_MR1_OFFSET), - timer_getreg(priv, LPC11_PWM_MR2_OFFSET), - timer_getreg(priv, LPC11_PWM_MR3_OFFSET)); - } - else -#endif - { - pwminfo(" DCR: %04x DMAR: %04x\n", - timer_getreg(priv, LPC11_PWM_MR2_OFFSET), - timer_getreg(priv, LPC11_PWM_MR3_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: timer_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * priv - A reference to the lower half PWM driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int timer_timer(FAR struct lpc11_timer_s *priv, - FAR const struct pwm_info_s *info) -{ - irqstate_t flags; - uint32_t regval; - - flags = enter_critical_section(); - - putreg32(info->frequency, LPC11_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ - putreg32(info->frequency, LPC11_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ - - putreg32(1, LPC11_TMR0_TCR); /* Start timer0 */ - putreg32(1, LPC11_TMR1_TCR); /* Start timer1 */ - - leave_critical_section(flags); - timer_dumpregs(priv, "After starting"); - return OK; -} - -#ifdef XXXXX -/**************************************************************************** - * Name: timer_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * priv - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int timer_interrupt(struct lpc11_timer_s *priv) -{ - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = timer_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - timer_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - return OK; -} - -/**************************************************************************** - * Name: timer_tim1/8interrupt - * - * Description: - * Handle timer 1 and 8 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int timer_tim1interrupt(int irq, void *context) -{ - return timer_interrupt(&g_pwm1dev); -} - -#endif /* XXXXX */ - -/**************************************************************************** - * Name: timer_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int timer_setup(FAR struct pwm_lowerhalf_s *dev) -{ - FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; - irqstate_t flags; - uint32_t regval; - - flags = enter_critical_section(); - - /* Power on the timer peripherals */ - - regval = getreg32(LPC11_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCTIM0; - regval |= SYSCON_PCONP_PCTIM1; - regval |= SYSCON_PCONP_PCTIM2; - regval |= SYSCON_PCONP_PCTIM3; - putreg32(regval, LPC11_SYSCON_PCONP); - - /* Select clock for the timer peripheral */ - - regval = getreg32(LPC11_SYSCON_PCLKSEL0); - regval &= ~(0x3 << 2); - regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ - regval &= ~(0x3 << 4); - regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ - putreg32(regval, LPC11_SYSCON_PCLKSEL0); - regval = getreg32(LPC11_SYSCON_PCLKSEL1); - regval &= ~(0x3 << 12); - regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ - regval &= ~(0x3 << 14); - regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ - putreg32(regval, LPC11_SYSCON_PCLKSEL1); - priv->pclk = (0x1 << 12) | (0x1 << 4); - - putreg32(1000, LPC11_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ - - putreg32(1, LPC11_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC11_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC11_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */ - putreg32((2 << 3), LPC11_TMR0_MCR); /* Reset on match register MR1 */ - - /* Output bit toggle on external match event External match on MR1, Toggle - * external bit - */ - - putreg32(((1 << 1) | (3 << 6)), LPC11_TMR0_EMR); - putreg32((1 << 0), LPC11_TMR0_TCR); /* Start timer0 */ - - /* Configure the output pins GPIO3.26 */ - - lpc11_configgpio(GPIO_MAT0p1_2); - - putreg32(500, LPC11_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ - - putreg32(1, LPC11_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC11_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC11_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */ - putreg32((2 << 0), LPC11_TMR1_MCR); /* Reset on match register MR0 */ -// putreg32(((1 << 0) | (3 << 4)), LPC11_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ - putreg32((1 << 0), LPC11_TMR1_TCR); /* Start timer1 */ - - /* configure the output pins GPIO3.26 */ -// lpc11_configgpio(GPIO_MAT0p1_2); - - leave_critical_section(flags); - pwm_dumpgpio(priv->pincfg, "TIMER setup"); - return OK; -} - -/**************************************************************************** - * Name: timer_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half TIMER driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev) -{ - FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; - uint32_t pincfg; - - pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); - - /* Make sure that the output has been stopped */ - - return OK; -} - -/**************************************************************************** - * Name: timer_start - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half TIMER driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int timer_start(FAR struct pwm_lowerhalf_s *dev, - FAR const struct pwm_info_s *info) -{ - FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; - return timer_timer(priv, info); -} - -/**************************************************************************** - * Name: timer_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half TIMER driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int timer_stop(FAR struct pwm_lowerhalf_s *dev) -{ - FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; - uint32_t resetbit; - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - pwminfo("TIM%d\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Disable further interrupts and stop the timer */ - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_LPC11_TMR0 - case 1: - break; -#endif - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where timer_start() can be called. - */ - - leave_critical_section(flags); - - pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); - timer_dumpregs(priv, "After stop"); - return OK; -} - -/**************************************************************************** - * Name: timer_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half TIMER driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_PWM_INFO - FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; - - /* There are no platform-specific ioctl commands */ - - pwminfo("TIM%d\n", priv->timid); -#endif - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_timerinitialize - * - * Description: - * Initialize one timer for use with the upper_level TIMER driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,14}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half TIMER driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer) -{ - FAR struct lpc11_timer_s *lower; - - pwminfo("TIM%d\n", timer); - - switch (timer) - { -#ifdef CONFIG_LPC11_TMR0 - case 0: - lower = &g_pwm1dev; - - /* Attach but disable the TIM1 update interrupt */ - - break; -#endif - - default: - pwmerr("ERROR: No such timer configured\n"); - return NULL; - } - - return (FAR struct pwm_lowerhalf_s *)lower; -} - -#endif /* CONFIG_LPC11_TIMn_TIMER, n = 1,...,14 */ diff --git a/arch/arm/src/lpc11xx/lpc11_timerisr.c b/arch/arm/src/lpc11xx/lpc11_timerisr.c deleted file mode 100644 index 2ec0600981d..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_timerisr.c +++ /dev/null @@ -1,163 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_timerisr.c - * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include "nvic.h" -#include "clock/clock.h" -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* "The CLKSOURCE bit in SysTick Control and Status register selects either - * the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock - * (when CLKSOURCE = 0). ..." - */ - -#if defined(CONFIG_LPC11_SYSTICK_CORECLK) -# define SYSTICK_CLOCK LPC11_MCLK /* Core clock */ -#elif defined(CONFIG_LPC11_SYSTICK_CORECLK_DIV16) -# define SYSTICK_CLOCK (LPC11_MCLK / 16) /* Core clock divided by 16 */ -#endif - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * Then, for example, if the external high speed crystal is the SysTick - * clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then - * the reload value would be: - * - * SYSTICK_RELOAD = (12,000,000 / 100) - 1 - * = 119,999 - * = 0x1d4bf - * - * Which fits within the maximum 24-bit reload value. - */ - -#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lpc11_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int lpc11_timerisr(int irq, uint32_t *regs, FAR void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: arm_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void arm_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(ARMV6M_SYSCON_SHPR3); - regval &= ~SYSCON_SHPR3_PRI_15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT); - putreg32(regval, ARMV6M_SYSCON_SHPR3); - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR); - - /* Attach the timer interrupt vector */ - - (void)irq_attach(LPC11_IRQ_SYSTICK, (xcpt_t)lpc11_timerisr, NULL); - - /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and - * Status register selects either the core clock (when CLKSOURCE = 1) or - * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." - */ - -#ifdef CONFIG_LPC11_SYSTICK_CORECLK - putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), - ARMV6M_SYSTICK_CSR); -#else - putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); -#endif - - /* And enable the timer interrupt */ - - up_enable_irq(LPC11_IRQ_SYSTICK); -} diff --git a/arch/arm/src/lpc11xx/lpc11_userspace.c b/arch/arm/src/lpc11xx/lpc11_userspace.c deleted file mode 100644 index 6ee07ad6b51..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_userspace.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_userspace.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "lpc11_mpuinit.h" -#include "lpc11_userspace.h" - -#ifdef CONFIG_BUILD_PROTECTED - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc11_userspace - * - * Description: - * For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - * - ****************************************************************************/ - -void lpc11_userspace(void) -{ - uint8_t *src; - uint8_t *dest; - uint8_t *end; - - /* Clear all of user-space .bss */ - - DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && - USERSPACE->us_bssstart <= USERSPACE->us_bssend); - - dest = (uint8_t *)USERSPACE->us_bssstart; - end = (uint8_t *)USERSPACE->us_bssend; - - while (dest != end) - { - *dest++ = 0; - } - - /* Initialize all of user-space .data */ - - DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && - USERSPACE->us_datastart <= USERSPACE->us_dataend); - - src = (uint8_t *)USERSPACE->us_datasource; - dest = (uint8_t *)USERSPACE->us_datastart; - end = (uint8_t *)USERSPACE->us_dataend; - - while (dest != end) - { - *dest++ = *src++; - } - - /* Configure the MPU to permit user-space access to its FLASH and RAM */ - - lpc11_mpuinitialize(); -} - -#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/lpc11xx/lpc11_userspace.h b/arch/arm/src/lpc11xx/lpc11_userspace.h deleted file mode 100644 index a515654ce98..00000000000 --- a/arch/arm/src/lpc11xx/lpc11_userspace.h +++ /dev/null @@ -1,76 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc11_userspace.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_USERSPACE_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_USERSPACE_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/**************************************************************************** - * Name: lpc11_userspace - * - * Description: - * For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_PROTECTED -void lpc11_userspace(void); -#endif - -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_USERSPACE_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h b/arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h deleted file mode 100644 index a99f93d754d..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h +++ /dev/null @@ -1,136 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ - -#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ -#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ -#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ -#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ -# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ -# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ -#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ -#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ -# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ -# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ -# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ -#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ -#define LPC17_SCS_BASE 0xe000e000 -#define LPC17_DEBUGMCU_BASE 0xe0042000 - -/* AHB SRAM Bank sizes **************************************************************/ - -#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ -#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ - -/* APB0 Peripherals *****************************************************************/ - -#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ -#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ -#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ -#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ -#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ - /* -0x40017fff: Reserved */ -#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ -#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ -#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ -#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ -#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ -#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ -#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ -#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ -#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ -#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ -#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ -#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ -#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ - /* -0x4005bfff: Reserved */ -#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ - /* -0x4007ffff: Reserved */ - -/* APB1 Peripherals *****************************************************************/ - - /* -0x40087fff: Reserved */ -#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ -#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ -#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ -#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ -#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ -#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ -#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ - /* -0x400a7fff: Reserved */ -#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ - /* -0x400affff: Reserved */ -#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ - /* -0x400b7fff: Reserved */ -#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ -#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ - /* -0x400fbfff: Reserved */ -#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ - -/* AHB Peripherals ******************************************************************/ - -#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ -#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ -#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h b/arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h deleted file mode 100644 index fccf9e8854d..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h +++ /dev/null @@ -1,635 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONN_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONN_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ -#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ -#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ -#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ -#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ -#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ -#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ -#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ -#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ -#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ -#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ -#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ -#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ -#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ -#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ -#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ -#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ -#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ -#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ -#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ -#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ -#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ -#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ -#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) -#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) -#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) -#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) -#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) -#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) -#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) -#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) -#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) -#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) -#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) -#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) -#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) -#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) -#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) -#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) -#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) -#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) -#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) -#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) -#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) -#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) -#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) -#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ - -#define PINCONN_PINSEL_GPIO (0) -#define PINCONN_PINSEL_ALT1 (1) -#define PINCONN_PINSEL_ALT2 (2) -#define PINCONN_PINSEL_ALT3 (3) -#define PINCONN_PINSEL_MASK (3) - -#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) -#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) - -#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ -#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) -#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ -#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) -#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ -#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) -#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ -#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) -#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ -#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) -#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ -#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) -#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ -#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) -#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ -#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) -#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ -#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) -#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ -#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) -#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ -#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) -#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ -#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ -#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) - -/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ - -#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ -#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) -#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ -#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) -#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ -#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) -#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ -#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) -#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ -#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) -#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ -#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) -#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ -#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) -#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ -#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) -#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ -#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) -#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ -#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) -#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ -#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) -#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ -#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) -#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ -#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) -#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) -#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) - /* Bits 30-31: Reserved */ -/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ - -#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) -#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) -#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) -#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) -#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) - -/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ - -#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) -#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) -#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ -#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) -#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ -#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) -#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ -#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) -#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ -#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) -#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ -#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) -#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ -#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) -#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ -#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) -#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ -#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) -#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ -#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) -#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ -#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) -#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ -#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) -#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ -#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) -#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ -#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) -#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ -#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) - -/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ - -#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) -#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) -#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) -#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) -#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) -#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) -#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ -#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) -#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) -#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ -#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) -#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ -#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) -#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ -#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) -#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ -#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) -#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ -#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) -#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ -#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ - -#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-17: Reserved */ -#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ -#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) -#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ -#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ -/* No description of bits -- Does this register exist? */ - -/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ - -#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-23: Reserved */ -#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ -#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) -#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ -#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ - /* Bits 0-2: Reserved */ -#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ - /* Bits 4-31: Reserved */ -/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ - -#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ -#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ -#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ -#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ -#define PINCONN_PINMODE_MASK (3) - -#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) -#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) - -#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ -#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) -#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ -#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) -#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ -#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) -#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ -#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) -#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ -#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) -#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ -#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) -#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ -#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) -#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ -#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) -#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ -#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) -#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ -#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) -#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ -#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) -#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ -#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ -#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) - -/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ - -#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ -#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) -#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ -#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) -#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ -#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) -#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ -#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) -#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ -#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) -#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ -#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) -#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ -#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) -#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ -#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) -#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ -#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) -#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ -#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) -#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ -#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ - -#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ -#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) -#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ -#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ -#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ -#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) -#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ -#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) -#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ -#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ -#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) -#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ -#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) - -/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ - -#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ -#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) -#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ -#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) -#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ -#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) -#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ -#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) -#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ -#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) -#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ -#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) -#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ -#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) -#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ -#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) -#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ -#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) -#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ -#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) -#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ -#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) -#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ -#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) -#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ -#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) -#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ -#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) -#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ -#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) -#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ -#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) - -/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ - -#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ -#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) -#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ -#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) -#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ -#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) -#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ -#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) -#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ -#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) -#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ -#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) -#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ -#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) -#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ -#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) -#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ -#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) -#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ -#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) -#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ -#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) -#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ -#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) -#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ -#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) -#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ -#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Mode select register 5 (PINMODE5: 0x4002c054) - * Pin Mode select register 6 (PINMODE6: 0x4002c058) - * No bit definitions -- do these registers exist? - */ - -#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ - -#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-17: Reserved */ -#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ -#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) -#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ -#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ -/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ - -#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-23: Reserved */ -#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ -#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) -#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ -#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ - -#define PINCONN_ODMODE0_P0(n) (1 << (n)) - -#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ -#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ -#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ -#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ -#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ -#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ -#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ -#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ -#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ -#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ -#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ -#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ - /* Bits 12-14: Reserved */ -#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ -#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ -#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ -#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ -#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ -#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ -#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ -#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ -#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ -#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ -#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ -#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ - /* Bits 27-28: Reserved */ -#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ -#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ - /* Bit 31: Reserved */ -/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ - -#define PINCONN_ODMODE1_P1(n) (1 << (n)) - -#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ -#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ - /* Bits 2-3: Reserved */ -#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ - /* Bits 5-7: Reserved */ -#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ -#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ -#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ - /* Bits 11-13: Reserved */ -#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ -#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ -#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ -#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ -#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ -#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ -#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ -#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ -#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ -#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ -#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ -#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ -#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ -#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ -#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ -#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ -#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ -#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ - -/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ - -#define PINCONN_ODMODE2_P2(n) (1 << (n)) - -#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ -#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ -#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ -#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ -#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ -#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ -#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ -#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ -#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ -#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ -#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ -#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ -#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ -#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ - /* Bits 14-31: Reserved */ -/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ - -#define PINCONN_ODMODE3_P3(n) (1 << (n)) - /* Bits 0-24: Reserved */ -#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ -#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ - /* Bits 17-31: Reserved */ -/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ - -#define PINCONN_ODMODE4_P4(n) (1 << (n)) - /* Bits 0-27: Reserved */ -#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ -#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ - /* Bits 30-31: Reserved */ -/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ - -#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch - * filtering/slew rate control */ -#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch - * filtering/slew rate control */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONN_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h b/arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h deleted file mode 100644 index 96b75be806b..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h +++ /dev/null @@ -1,494 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ -#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ -#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ -#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ - -#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ -#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ -#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ -#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ -#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ -#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ - -#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ -#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ - -/* More clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */ -#define LPC17_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */ - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ - -/* Register addresses ***************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) -#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) -#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) -#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) - -#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) -#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) -#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) -#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) -#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) -#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) - -#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) -#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) - -/* More clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_PCLKSEL0 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL0_OFFSET) -#define LPC17_SYSCON_PCLKSEL1 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL1_OFFSET) - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Flash accelerator module */ - /* Bits 0-11: Reserved */ -#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ -#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) -# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock - * (Up to 120 Mhz for LPC1759/69 only */ -# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ - /* Bits 16-31: Reserved */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: - * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. - * 1:User mode. The on-chip Flash memory is mapped to address 0 */ - /* Bits 1-31: Reserved */ - -/* Clocking and power control -- Clock source selection */ - -#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */ -#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT) -# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ -# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ -# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */ - /* Bits 2-31: Reserved */ - -/* Clocking and power control - Phase locked loops */ -/* PLL0/1 Control register */ - -#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */ -#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */ - /* Bits 2-31: Reserved */ -/* PLL0 Configuration register */ - -#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */ -#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT) - /* Bit 15: Reserved */ -#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */ -#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT) - /* Bits 24-31: Reserved */ -/* PLL1 Configuration register */ - -#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */ -#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT) -#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */ -#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT) - /* Bits 7-31: Reserved */ -/* PLL0 Status register */ - -#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ -#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) - /* Bit 15: Reserved */ -#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ -#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) -#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ -#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ -#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ - /* Bits 27-31: Reserved */ -/* PLL1 Status register */ - -#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ -#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) -#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ -#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) - /* Bit 7: Reserved */ -#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ -#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ -#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ - /* Bits 11-31: Reserved */ -/* PLL0/1 Feed register */ - -#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ -#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) - /* Bits 8-31: Reserved */ -/* Clocking and power control -- Clock dividers */ -/* CPU Clock Configuration register */ - -#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */ -#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT) -# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ - /* Bits 8-31: Reserved */ -/* USB Clock Configuration register */ - -#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */ -#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT) -# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */ -# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */ -# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */ - /* Bits 8-31: Reserved */ -/* Peripheral Clock Selection registers 0 and 1 */ - -#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */ -#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */ -#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */ -#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ -#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */ -#define SYSCON_PCLKSEL_MASK (3) - -#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */ -#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT) -#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */ -#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT) -#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */ -#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT) -#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ -#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT) -#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ -#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) - /* Bits 10-11: Reserved */ -#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */ -#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT) -#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */ -#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT) -#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */ -#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT) - /* Bits 18-19: Reserved */ -#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */ -#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT) -#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */ -#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT) -#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */ -#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT) -#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */ -#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT) -#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */ -#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT) -#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */ -#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT) - -#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */ -#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT) -#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */ -#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT) -#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */ -#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT) -#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */ -#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT) - /* Bits 8-9: Reserved */ -#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */ -#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT) -#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */ -#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT) -#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */ -#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT) -#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ -#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) -#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ -#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) -#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */ -#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT) -#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */ -#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT) - /* Bits 24-25: Reserved */ -#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */ -#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT) -#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */ -#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT) -#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */ -#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT) - -/* Clocking and power control - Peripheral power control registers */ -/* Power Control Register */ - -#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ -#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ -#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ -#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ -#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ - /* Bits 5-7: Reserved */ -#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ -#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ -#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ -#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ - /* Bits 12-31: Reserved */ -/* Power Control for Peripherals Register */ - - /* Bit 0: Reserved */ -#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ -#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ -#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ -#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ - /* Bit 5: Reserved */ -#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ -#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ -#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ -#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ -#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ - /* Bit 11: Reserved */ -#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ -#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ -#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ -#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ -#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ -#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ -#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ -#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ - /* Bit 20: Reserved */ -#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ -#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ -#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ -#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ -#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ -#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ -#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ - /* Bit 28: Reserved */ -#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ -#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ -#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ - -/* More clocking and power control -- Utility */ - -#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ -#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) -# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ -# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ -# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ -# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ -# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ -#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ -#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) -# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ -#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ -#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ - /* Bits 10-31: Reserved */ -/* System control registers -- External Interrupts */ -/* External Interrupt Flag register */ - -#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ -#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ -#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ -#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ - /* Bits 4-31: Reserved */ -/* External Interrupt Mode register */ - -#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ -#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ -#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ -#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ - /* Bits 4-31: Reserved */ -/* External Interrupt Polarity register */ - -#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ - /* Bits 4-31: Reserved */ -/* System control registers -- Reset */ -/* Reset Source Identification Register */ - -#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ -#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ -#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ -#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ - /* Bits 4-31: Reserved */ -/* System control registers -- Syscon Miscellaneous Registers */ - - /* Bits 0-3: Reserved */ -#define SYSCON_SCS_OSCRS (1 << 4) /* Bit 4: Main oscillator range select */ -#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ -#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ - /* Bits 7-31: Reserved */ -/* Device Interrupt Registers */ -/* USB Interrupt Status register */ - -#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ -#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ -#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ -#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ -#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ -#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ -#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ - /* Bit 7: Reserved */ -#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ - /* Bits 9-30: Reserved */ -#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ - -/* DMA Request Select Register */ - -#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */ -#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */ -#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */ -#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */ -#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */ -#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */ -#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */ -#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */ - /* Bits 8-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h b/arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h deleted file mode 100644 index bb49cd13a87..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h +++ /dev/null @@ -1,375 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Rommel Marcelo - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_IOCON_PP_OFFSET(p) ((unsigned int)(p) << 2) -#define LPC17_IOCON_PP0_OFFSET (0x0000) /* IOCON Port(n) register 0 */ -#define LPC17_IOCON_PP1_OFFSET (0x0004) /* IOCON Port(n) register 1 */ -#define LPC17_IOCON_PP2_OFFSET (0x0008) /* IOCON Port(n) register 2 */ -#define LPC17_IOCON_PP3_OFFSET (0x000c) /* IOCON Port(n) register 3 */ -#define LPC17_IOCON_PP4_OFFSET (0x0010) /* IOCON Port(n) register 4 */ -#define LPC17_IOCON_PP5_OFFSET (0x0014) /* IOCON Port(n) register 5 */ -#define LPC17_IOCON_PP6_OFFSET (0x0018) /* IOCON Port(n) register 6 */ -#define LPC17_IOCON_PP7_OFFSET (0x001c) /* IOCON Port(n) register 7 */ -#define LPC17_IOCON_PP8_OFFSET (0x0020) /* IOCON Port(n) register 8 */ -#define LPC17_IOCON_PP9_OFFSET (0x0024) /* IOCON Port(n) register 9 */ -#define LPC17_IOCON_PP10_OFFSET (0x0028) /* IOCON Port(n) register 10 */ -#define LPC17_IOCON_PP11_OFFSET (0x002c) /* IOCON Port(n) register 11 */ -#define LPC17_IOCON_PP12_OFFSET (0x0030) /* IOCON Port(n) register 12 */ -#define LPC17_IOCON_PP13_OFFSET (0x0034) /* IOCON Port(n) register 13 */ -#define LPC17_IOCON_PP14_OFFSET (0x0038) /* IOCON Port(n) register 14 */ -#define LPC17_IOCON_PP15_OFFSET (0x003c) /* IOCON Port(n) register 15 */ -#define LPC17_IOCON_PP16_OFFSET (0x0040) /* IOCON Port(n) register 16 */ -#define LPC17_IOCON_PP17_OFFSET (0x0044) /* IOCON Port(n) register 17 */ -#define LPC17_IOCON_PP18_OFFSET (0x0048) /* IOCON Port(n) register 18 */ -#define LPC17_IOCON_PP19_OFFSET (0x004c) /* IOCON Port(n) register 19 */ -#define LPC17_IOCON_PP20_OFFSET (0x0050) /* IOCON Port(n) register 20 */ -#define LPC17_IOCON_PP21_OFFSET (0x0054) /* IOCON Port(n) register 21 */ -#define LPC17_IOCON_PP22_OFFSET (0x0058) /* IOCON Port(n) register 22 */ -#define LPC17_IOCON_PP23_OFFSET (0x005c) /* IOCON Port(n) register 23 */ -#define LPC17_IOCON_PP24_OFFSET (0x0060) /* IOCON Port(n) register 24 */ -#define LPC17_IOCON_PP25_OFFSET (0x0064) /* IOCON Port(n) register 25 */ -#define LPC17_IOCON_PP26_OFFSET (0x0068) /* IOCON Port(n) register 26 */ -#define LPC17_IOCON_PP27_OFFSET (0x006c) /* IOCON Port(n) register 27 */ -#define LPC17_IOCON_PP28_OFFSET (0x0070) /* IOCON Port(n) register 28 */ -#define LPC17_IOCON_PP29_OFFSET (0x0074) /* IOCON Port(n) register 29 */ -#define LPC17_IOCON_PP30_OFFSET (0x0078) /* IOCON Port(n) register 30 */ -#define LPC17_IOCON_PP31_OFFSET (0x007c) /* IOCON Port(n) register 31 */ - -/* Register addresses ***************************************************************/ - -#define LPC17_IOCON_P_BASE(b) (LPC17_IOCON_BASE + ((unsigned int)(b) << 7)) -#define LPC17_IOCON_P0_BASE (LPC17_IOCON_BASE + 0x0000) -#define LPC17_IOCON_P1_BASE (LPC17_IOCON_BASE + 0x0080) -#define LPC17_IOCON_P2_BASE (LPC17_IOCON_BASE + 0x0100) -#define LPC17_IOCON_P3_BASE (LPC17_IOCON_BASE + 0x0180) -#define LPC17_IOCON_P4_BASE (LPC17_IOCON_BASE + 0x0200) -#define LPC17_IOCON_P5_BASE (LPC17_IOCON_BASE + 0x0280) - -#define LPC17_IOCON_P(b,p) (LPC17_IOCON_P_BASE(b) + LPC17_IOCON_PP_OFFSET(p)) - -#define LPC17_IOCON_P0_0 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP0_OFFSET) -#define LPC17_IOCON_P0_1 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP1_OFFSET) -#define LPC17_IOCON_P0_2 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP2_OFFSET) -#define LPC17_IOCON_P0_3 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP3_OFFSET) -#define LPC17_IOCON_P0_4 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP4_OFFSET) -#define LPC17_IOCON_P0_5 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP5_OFFSET) -#define LPC17_IOCON_P0_6 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP6_OFFSET) -#define LPC17_IOCON_P0_7 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP7_OFFSET) -#define LPC17_IOCON_P0_8 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP8_OFFSET) -#define LPC17_IOCON_P0_9 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP9_OFFSET) -#define LPC17_IOCON_P0_10 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP10_OFFSET) -#define LPC17_IOCON_P0_11 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP11_OFFSET) -#define LPC17_IOCON_P0_12 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP12_OFFSET) -#define LPC17_IOCON_P0_13 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP13_OFFSET) -#define LPC17_IOCON_P0_14 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP14_OFFSET) -#define LPC17_IOCON_P0_15 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP15_OFFSET) -#define LPC17_IOCON_P0_16 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP16_OFFSET) -#define LPC17_IOCON_P0_17 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP17_OFFSET) -#define LPC17_IOCON_P0_18 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP18_OFFSET) -#define LPC17_IOCON_P0_19 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP19_OFFSET) -#define LPC17_IOCON_P0_20 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP20_OFFSET) -#define LPC17_IOCON_P0_21 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP21_OFFSET) -#define LPC17_IOCON_P0_22 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP22_OFFSET) -#define LPC17_IOCON_P0_23 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP23_OFFSET) -#define LPC17_IOCON_P0_24 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP24_OFFSET) -#define LPC17_IOCON_P0_25 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP25_OFFSET) -#define LPC17_IOCON_P0_26 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP26_OFFSET) -#define LPC17_IOCON_P0_27 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP27_OFFSET) -#define LPC17_IOCON_P0_28 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP28_OFFSET) -#define LPC17_IOCON_P0_29 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP29_OFFSET) -#define LPC17_IOCON_P0_30 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP30_OFFSET) -#define LPC17_IOCON_P0_31 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP31_OFFSET) - -#define LPC17_IOCON_P1_0 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP0_OFFSET) -#define LPC17_IOCON_P1_1 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP1_OFFSET) -#define LPC17_IOCON_P1_2 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP2_OFFSET) -#define LPC17_IOCON_P1_3 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP3_OFFSET) -#define LPC17_IOCON_P1_4 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP4_OFFSET) -#define LPC17_IOCON_P1_5 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP5_OFFSET) -#define LPC17_IOCON_P1_6 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP6_OFFSET) -#define LPC17_IOCON_P1_7 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP7_OFFSET) -#define LPC17_IOCON_P1_8 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP8_OFFSET) -#define LPC17_IOCON_P1_9 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP9_OFFSET) -#define LPC17_IOCON_P1_10 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP10_OFFSET) -#define LPC17_IOCON_P1_11 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP11_OFFSET) -#define LPC17_IOCON_P1_12 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP12_OFFSET) -#define LPC17_IOCON_P1_13 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP13_OFFSET) -#define LPC17_IOCON_P1_14 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP14_OFFSET) -#define LPC17_IOCON_P1_15 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP15_OFFSET) -#define LPC17_IOCON_P1_16 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP16_OFFSET) -#define LPC17_IOCON_P1_17 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP17_OFFSET) -#define LPC17_IOCON_P1_18 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP18_OFFSET) -#define LPC17_IOCON_P1_19 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP19_OFFSET) -#define LPC17_IOCON_P1_20 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP20_OFFSET) -#define LPC17_IOCON_P1_21 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP21_OFFSET) -#define LPC17_IOCON_P1_22 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP22_OFFSET) -#define LPC17_IOCON_P1_23 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP23_OFFSET) -#define LPC17_IOCON_P1_24 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP24_OFFSET) -#define LPC17_IOCON_P1_25 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP25_OFFSET) -#define LPC17_IOCON_P1_26 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP26_OFFSET) -#define LPC17_IOCON_P1_27 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP27_OFFSET) -#define LPC17_IOCON_P1_28 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP28_OFFSET) -#define LPC17_IOCON_P1_29 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP29_OFFSET) -#define LPC17_IOCON_P1_30 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP30_OFFSET) -#define LPC17_IOCON_P1_31 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP31_OFFSET) - -#define LPC17_IOCON_P2_0 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP0_OFFSET) -#define LPC17_IOCON_P2_1 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP1_OFFSET) -#define LPC17_IOCON_P2_2 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP2_OFFSET) -#define LPC17_IOCON_P2_3 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP3_OFFSET) -#define LPC17_IOCON_P2_4 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP4_OFFSET) -#define LPC17_IOCON_P2_5 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP5_OFFSET) -#define LPC17_IOCON_P2_6 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP6_OFFSET) -#define LPC17_IOCON_P2_7 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP7_OFFSET) -#define LPC17_IOCON_P2_8 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP8_OFFSET) -#define LPC17_IOCON_P2_9 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP9_OFFSET) -#define LPC17_IOCON_P2_10 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP10_OFFSET) -#define LPC17_IOCON_P2_11 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP11_OFFSET) -#define LPC17_IOCON_P2_12 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP12_OFFSET) -#define LPC17_IOCON_P2_13 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP13_OFFSET) -#define LPC17_IOCON_P2_14 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP14_OFFSET) -#define LPC17_IOCON_P2_15 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP15_OFFSET) -#define LPC17_IOCON_P2_16 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP16_OFFSET) -#define LPC17_IOCON_P2_17 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP17_OFFSET) -#define LPC17_IOCON_P2_18 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP18_OFFSET) -#define LPC17_IOCON_P2_19 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP19_OFFSET) -#define LPC17_IOCON_P2_20 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP20_OFFSET) -#define LPC17_IOCON_P2_21 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP21_OFFSET) -#define LPC17_IOCON_P2_22 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP22_OFFSET) -#define LPC17_IOCON_P2_23 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP23_OFFSET) -#define LPC17_IOCON_P2_24 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP24_OFFSET) -#define LPC17_IOCON_P2_25 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP25_OFFSET) -#define LPC17_IOCON_P2_26 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP26_OFFSET) -#define LPC17_IOCON_P2_27 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP27_OFFSET) -#define LPC17_IOCON_P2_28 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP28_OFFSET) -#define LPC17_IOCON_P2_29 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP29_OFFSET) -#define LPC17_IOCON_P2_30 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP30_OFFSET) -#define LPC17_IOCON_P2_31 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP31_OFFSET) - -#define LPC17_IOCON_P3_0 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP0_OFFSET) -#define LPC17_IOCON_P3_1 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP1_OFFSET) -#define LPC17_IOCON_P3_2 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP2_OFFSET) -#define LPC17_IOCON_P3_3 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP3_OFFSET) -#define LPC17_IOCON_P3_4 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP4_OFFSET) -#define LPC17_IOCON_P3_5 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP5_OFFSET) -#define LPC17_IOCON_P3_6 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP6_OFFSET) -#define LPC17_IOCON_P3_7 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP7_OFFSET) -#define LPC17_IOCON_P3_8 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP8_OFFSET) -#define LPC17_IOCON_P3_9 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP9_OFFSET) -#define LPC17_IOCON_P3_10 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP10_OFFSET) -#define LPC17_IOCON_P3_11 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP11_OFFSET) -#define LPC17_IOCON_P3_12 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP12_OFFSET) -#define LPC17_IOCON_P3_13 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP13_OFFSET) -#define LPC17_IOCON_P3_14 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP14_OFFSET) -#define LPC17_IOCON_P3_15 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP15_OFFSET) -#define LPC17_IOCON_P3_16 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP16_OFFSET) -#define LPC17_IOCON_P3_17 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP17_OFFSET) -#define LPC17_IOCON_P3_18 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP18_OFFSET) -#define LPC17_IOCON_P3_19 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP19_OFFSET) -#define LPC17_IOCON_P3_20 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP20_OFFSET) -#define LPC17_IOCON_P3_21 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP21_OFFSET) -#define LPC17_IOCON_P3_22 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP22_OFFSET) -#define LPC17_IOCON_P3_23 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP23_OFFSET) -#define LPC17_IOCON_P3_24 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP24_OFFSET) -#define LPC17_IOCON_P3_25 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP25_OFFSET) -#define LPC17_IOCON_P3_26 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP26_OFFSET) -#define LPC17_IOCON_P3_27 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP27_OFFSET) -#define LPC17_IOCON_P3_28 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP28_OFFSET) -#define LPC17_IOCON_P3_29 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP29_OFFSET) -#define LPC17_IOCON_P3_30 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP30_OFFSET) -#define LPC17_IOCON_P3_31 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP31_OFFSET) - -#define LPC17_IOCON_P4_0 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP0_OFFSET) -#define LPC17_IOCON_P4_1 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP1_OFFSET) -#define LPC17_IOCON_P4_2 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP2_OFFSET) -#define LPC17_IOCON_P4_3 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP3_OFFSET) -#define LPC17_IOCON_P4_4 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP4_OFFSET) -#define LPC17_IOCON_P4_5 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP5_OFFSET) -#define LPC17_IOCON_P4_6 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP6_OFFSET) -#define LPC17_IOCON_P4_7 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP7_OFFSET) -#define LPC17_IOCON_P4_8 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP8_OFFSET) -#define LPC17_IOCON_P4_9 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP9_OFFSET) -#define LPC17_IOCON_P4_10 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP10_OFFSET) -#define LPC17_IOCON_P4_11 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP11_OFFSET) -#define LPC17_IOCON_P4_12 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP12_OFFSET) -#define LPC17_IOCON_P4_13 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP13_OFFSET) -#define LPC17_IOCON_P4_14 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP14_OFFSET) -#define LPC17_IOCON_P4_15 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP15_OFFSET) -#define LPC17_IOCON_P4_16 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP16_OFFSET) -#define LPC17_IOCON_P4_17 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP17_OFFSET) -#define LPC17_IOCON_P4_18 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP18_OFFSET) -#define LPC17_IOCON_P4_19 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP19_OFFSET) -#define LPC17_IOCON_P4_20 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP20_OFFSET) -#define LPC17_IOCON_P4_21 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP21_OFFSET) -#define LPC17_IOCON_P4_22 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP22_OFFSET) -#define LPC17_IOCON_P4_23 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP23_OFFSET) -#define LPC17_IOCON_P4_24 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP24_OFFSET) -#define LPC17_IOCON_P4_25 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP25_OFFSET) -#define LPC17_IOCON_P4_26 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP26_OFFSET) -#define LPC17_IOCON_P4_27 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP27_OFFSET) -#define LPC17_IOCON_P4_28 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP28_OFFSET) -#define LPC17_IOCON_P4_29 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP29_OFFSET) -#define LPC17_IOCON_P4_30 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP30_OFFSET) -#define LPC17_IOCON_P4_31 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP31_OFFSET) - -#define LPC17_IOCON_P5_0 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP0_OFFSET) -#define LPC17_IOCON_P5_1 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP1_OFFSET) -#define LPC17_IOCON_P5_2 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP2_OFFSET) -#define LPC17_IOCON_P5_3 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP3_OFFSET) -#define LPC17_IOCON_P5_4 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP4_OFFSET) -#define LPC17_IOCON_P5_5 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP5_OFFSET) -#define LPC17_IOCON_P5_6 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP6_OFFSET) -#define LPC17_IOCON_P5_7 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP7_OFFSET) -#define LPC17_IOCON_P5_8 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP8_OFFSET) -#define LPC17_IOCON_P5_9 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP9_OFFSET) -#define LPC17_IOCON_P5_10 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP10_OFFSET) -#define LPC17_IOCON_P5_11 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP11_OFFSET) -#define LPC17_IOCON_P5_12 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP12_OFFSET) -#define LPC17_IOCON_P5_13 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP13_OFFSET) -#define LPC17_IOCON_P5_14 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP14_OFFSET) -#define LPC17_IOCON_P5_15 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP15_OFFSET) -#define LPC17_IOCON_P5_16 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP16_OFFSET) -#define LPC17_IOCON_P5_17 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP17_OFFSET) -#define LPC17_IOCON_P5_18 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP18_OFFSET) -#define LPC17_IOCON_P5_19 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP19_OFFSET) -#define LPC17_IOCON_P5_20 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP20_OFFSET) -#define LPC17_IOCON_P5_21 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP21_OFFSET) -#define LPC17_IOCON_P5_22 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP22_OFFSET) -#define LPC17_IOCON_P5_23 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP23_OFFSET) -#define LPC17_IOCON_P5_24 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP24_OFFSET) -#define LPC17_IOCON_P5_25 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP25_OFFSET) -#define LPC17_IOCON_P5_26 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP26_OFFSET) -#define LPC17_IOCON_P5_27 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP27_OFFSET) -#define LPC17_IOCON_P5_28 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP28_OFFSET) -#define LPC17_IOCON_P5_29 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP29_OFFSET) -#define LPC17_IOCON_P5_30 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP30_OFFSET) -#define LPC17_IOCON_P5_31 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP31_OFFSET) - -/* Register bit definitions *********************************************************/ -/* IOCON pin function select */ - -#define IOCON_FUNC_GPIO (0) -#define IOCON_FUNC_ALT1 (1) -#define IOCON_FUNC_ALT2 (2) -#define IOCON_FUNC_ALT3 (3) -#define IOCON_FUNC_ALT4 (4) -#define IOCON_FUNC_ALT5 (5) -#define IOCON_FUNC_ALT6 (6) -#define IOCON_FUNC_ALT7 (7) - -#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ -#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT) -#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ -#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT ) -#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */ -#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT) -#define IOCON_INV_SHIFT (6) /* Bit 6: Type D,A,I,W */ -#define IOCON_INV_MASK (1 << IOCON_INV_SHIFT) -#define IOCON_ADMODE_SHIFT (7) /* Bit 7: Type A */ -#define IOCON_ADMODE_MASK (1 << IOCON_ADMODE_SHIFT) -#define IOCON_FILTER_SHIFT (8) /* Bit 8: Type A */ -#define IOCON_FILTER_MASK (1 << IOCON_FILTER_SHIFT) -#define IOCON_I2CHS_SHIFT (8) /* Bit 8: Type I */ -#define IOCON_I2CHS_MASK (1 << IOCON_I2CHS_SHIFT) -#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W */ -#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT) -#define IOCON_HIDRIVE_SHIFT (9) /* Bit 9: Type I */ -#define IOCON_HIDRIVE_MASK (1 << IOCON_HIDRIVE_SHIFT) -#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */ -#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) -#define IOCON_DACEN_SHIFT (16) /* Bit 16: Type A */ -#define IOCON_DACEN_MASK (1 << IOCON_DACEN_SHIFT) - -/* Pin modes */ - -#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ -#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */ -#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */ -#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */ - -/* Pin types */ - -#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */ -#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */ -#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */ -#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */ -#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */ - -/* Slew rate modes */ - -#define IOCON_SLEWMODE_NORMAL (0 << IOCON_SLEW_SHIFT) -#define IOCON_SLEWMODE_FAST (1 << IOCON_SLEW_SHIFT) - -/* I2C modes */ - -#define IOCON_I2CMODE_SHIFT (IOCON_I2CHS_SHIFT) -#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT) -# define IOCON_I2CMODE_FAST (0 << IOCON_I2CMODE_SHIFT) -# define IOCON_I2CMODE_FASTPLUS (1 << IOCON_I2CMODE_SHIFT)/* */ -# define IOCON_I2CMODE_HIOPENDRAIN (2 << IOCON_I2CMODE_SHIFT)/* */ -# define IOCON_I2CMODE_OPENDRAIN (3 << IOCON_I2CMODE_SHIFT)/* */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h b/arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h deleted file mode 100644 index 76a87f182ca..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h +++ /dev/null @@ -1,158 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Memory Map ***********************************************************************/ - -#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ -#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ -#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ -#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip Peripheral SRAM (devices >32Kb) */ -# define LPC17_SRAM_BANK0 0x20000000 /* -0x20003fff: On-chip Peripheral SRAM Bank0 (devices >=32Kb) */ -# define LPC17_SRAM_BANK1 0x20004000 /* -0x20007fff: On-chip Peripheral SRAM Bank1 (devices 64Kb) */ -#define LPC17_AHB_BASE 0x20080000 /* -0x2008ffff: DMA Controller, Ethernet, and USB */ -#define LPC17_SPIFI_BASE 0x28000000 -#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ -# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ -# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ - -/* Off chip Memory via External Memory Interface */ - -#define LPC17_EXTRAM_BASE 0x80000000 /* */ -# define LPC17_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */ -# define LPC17_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */ -# define LPC17_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */ -# define LPC17_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */ - -# define LPC17_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */ -# define LPC17_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */ -# define LPC17_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */ -# define LPC17_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */ - -#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ -#define LPC17_SCS_BASE 0xe000e000 -#define LPC17_DEBUGMCU_BASE 0xe0042000 - -/* AHB SRAM Bank sizes **************************************************************/ - -#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ -#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ - -/* APB0 Peripherals *****************************************************************/ - -#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ -#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ -#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ -#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ -#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ -#define LPC17_PWM0_BASE 0x40014000 /* -0x40017fff: PWM 0 */ -#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ -#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ - /* -0x40023fff: Reserved */ -#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ -#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ -#define LPC17_IOCON_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ -#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ -#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ -#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ -#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ -#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ -#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ -#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ - /* -0x4005bfff: Reserved */ -#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ - /* -0x4007ffff: Reserved */ - -/* APB1 Peripherals *****************************************************************/ - - /* -0x40087fff: Reserved */ -#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ -#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ -#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ -#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ -#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ -#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ -#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ -#define LPC17_UART4_BASE 0x400a4000 /* -0x400a7fff: UART4 */ -#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ -#define LPC17_SSP2_BASE 0x400ac000 /* -0x400affff: SSP2 */ - /* -0x400b3fff: Reserved */ - /* -0x400b7fff: Reserved */ -#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ -#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ -#define LPC17_MCI_BASE 0x400c0000 /* -0x400fbfff: SD interface */ -#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ - -/* AHB Peripherals ******************************************************************/ - -#define LPC17_GPDMA_BASE 0x20080000 /* GPDMA controller */ -#define LPC17_ETH_BASE 0x20084000 /* Ethernet controller */ -#define LPC17_LCD_BASE 0x20088000 /* LCD controller */ -#define LPC17_USB_BASE 0x2008c000 /* USB controller */ -#define LPC17_CRC_BASE 0x20090000 /* CRC engine */ -#define LPC17_GPIO_BASE 0x20098000 /* GPIO */ -#define LPC17_EMC_BASE 0x2009c000 /* External Memory Controller */ - -/* EEPROM */ - -#define LPC17_EEPROM_BASE 0x00200000 /* EEPROM controller */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h b/arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h deleted file mode 100644 index b6701ce6c2c..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_SYSCON_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_SYSCON_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -/* Register offsets *********************************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control Register */ - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ -#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ -#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ -#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ - -#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ -#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ -#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ -#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ -#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_EMCCLKSEL_OFFSET 0x0100 /* EMC Clock Selection Register */ -#define LPC17_SYSCON_CCLKSEL_OFFSET 0x0104 /* CPU Clock Selection Register */ -#define LPC17_SYSCON_USBCLKSEL_OFFSET 0x0108 /* USB Clock Selection Register */ - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ -#define LPC17_SYSCON_CANSLEEPCLR_OFFSET 0x0110 /* CAN Channel Sleep State Register */ -#define LPC17_SYSCON_CANWAKEFLAGS_OFFSET 0x0114 /* CAN Channel Wake-Up State Register */ - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ -#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ -#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_MATRIXARB_OFFSET 0x0188 /* Matrix Arbitration Register */ -#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ -#define LPC17_SYSCON_PCLKSEL_OFFSET 0x01a8 /* Peripheral Clock Selection Register */ -#define LPC17_SYSCON_PBOOST_OFFSET 0x01b0 /* Power Boost Register */ -#define LPC17_SYSCON_SPIFICLKSEL_OFFSET 0x01b4 /* SPIFI Clock Selection Register */ -#define LPC17_SYSCON_LCDCFG_OFFSET 0x01b8 /* LCD Clock Configuration Register */ - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ - -/* Peripheral Reset Control */ - -#define LPC17_SYSCON_RSTCON0_OFFSET 0x01cc /* Individual Peripheral Reset Control Bits */ -#define LPC17_SYSCON_RSTCON1_OFFSET 0x01d0 /* Individual Peripheral Reset Control Bits */ - -/* EMC Clock Control and Calibration */ - -#define LPC17_SYSCON_EMCDLYCTL_OFFSET 0x01dc /* Programmable Delays for SDRAM Operation */ -#define LPC17_SYSCON_EMCCAL_OFFSET 0x01e0 /* Calibration Counter for EMCDLYCTL */ - - -/* Register addresses *******************************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) -#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) -#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) -#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) - -#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) -#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) -#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) -#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) -#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_EMCCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCLKSEL_OFFSET) -#define LPC17_SYSCON_CCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKSEL_OFFSET) -#define LPC17_SYSCON_USBCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKSEL_OFFSET) - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) -#define LPC17_SYSCON_CANSLEEPCLR (LPC17_SYSCON_BASE+LPC17_SYSCON_CANSLEEPCLR_OFFSET) -#define LPC17_SYSCON_CANWAKEFLAGS (LPC17_SYSCON_BASE+LPC17_SYSCON_CANWAKEFLAGS_OFFSET) - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) - -#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) -#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_MATRIXARB (LPC17_SYSCON_BASE+LPC17_SYSCON_MATRIXARB_OFFSET) -#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) -#define LPC17_SYSCON_PCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL_OFFSET) -#define LPC17_SYSCON_PBOOST (LPC17_SYSCON_BASE+LPC17_SYSCON_PBOOST_OFFSET) -#define LPC17_SYSCON_SPIFICLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_SPIFICLKSEL_OFFSET) -#define LPC17_SYSCON_LCDCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_LCDCFG_OFFSET) - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) - - -/* Peripheral Reset Control */ - -#define LPC17_SYSCON_RSTCON0 (LPC17_SYSCON_BASE+LPC17_SYSCON_RSTCON0_OFFSET) -#define LPC17_SYSCON_RSTCON1 (LPC17_SYSCON_BASE+LPC17_SYSCON_RSTCON1_OFFSET) - -/* EMC Clock Control and Calibration */ - -#define LPC17_SYSCON_EMCDLYCTL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCDLYCTL_OFFSET) -#define LPC17_SYSCON_EMCCAL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCAL_OFFSET) - -/* Register bit definitions *************************************************************************/ -/* Flash accelerator module */ - /* Bits 0-11: Reserved */ -#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ -#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) -# define SYSCON_FLASHCFG_TIM_0 (0) /* 1 CPU clock <= 20 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_1 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_2 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_3 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_4 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock - * (Up to 120 Mhz for LPC1788x) */ -# define SYSCON_FLASHCFG_TIM_5 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ - /* Bits 16-31: Reserved */ -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: - * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. - * 1:User mode. The on-chip Flash memory is mapped to address 0 */ - /* Bits 1-31: Reserved */ -/* Clocking and power control -- Clock source selection */ - -#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0: Clock selection */ -#define SYSCON_CLKSRCSEL_MASK (1 << SYSCON_CLKSRCSEL_SHIFT) -# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ -# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ - /* Bits 1-31: Reserved */ -/* Clocking and power control - Phase locked loops */ -/* PLL0/1 Control register */ - -#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL Enable */ - /* Bits 1-31: Reserved */ -/* PLL0/1 Configuration register */ - -#define SYSCON_PLLCFG_MSEL_SHIFT (0) /* Bit 0-4: PLL Multiplier value */ -#define SYSCON_PLLCFG_MSEL_MASK (0x1f << SYSCON_PLLCFG_MSEL_SHIFT) -#define SYSCON_PLLCFG_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value */ -#define SYSCON_PLLCFG_PSEL_MASK (3 << SYSCON_PLLCFG_PSEL_SHIFT) - -/* PLL0/1 Status register */ - -#define SYSCON_PLLSTAT_MSEL_SHIFT (0) /* Bit 0-4: PLLMultiplier value readback */ -#define SYSCON_PLLSTAT_MSEL_MASK (0x1f << SYSCON_PLLSTAT_MSEL_SHIFT) -#define SYSCON_PLLSTAT_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value readback */ -#define SYSCON_PLLSTAT_PSEL_MASK (3 << SYSCON_PLLSTAT_PSEL_SHIFT) - /* Bit 7: Reserved */ -#define SYSCON_PLLSTAT_PLLE (1 << 8) /* Bit 8: PLL enable readback */ -#define SYSCON_PLLSTAT_PLLC (1 << 9) /* Bit 9: PLL connect readback */ -#define SYSCON_PLLSTAT_PLOCK (1 << 10) /* Bit 10: PLL lock status */ - /* Bits 11-31: Reserved */ -/* PLL0/1 Feed register */ - -#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ -#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) - /* Bits 8-31: Reserved */ -/* Clocking and power control -- Clock dividers */ - -/* EMC Clock Selection Register */ - -#define SYSCON_EMCDIV (1 << 0) /* Bit 0: EMC Clock rate relative to CPU */ - /* 0: EMC uses same clock as CPU */ - /* 1: EMC uses half the rate of CPU */ - /* Bits 1-31: Reserved */ -/* EMC Clock Selection Register */ - -#define SYSCON_EMCCLKSEL_CCLK_DIV2 (1 << 0) /* Bit 0: 1=EMC used CPU clock / 2 */ -#define SYSCON_EMCCLKSEL_CCLK_DIV1 (0) /* 0=EMC used CPU clock */ - -/* CPU Clock Selection Register */ - -#define SYSCON_CCLKSEL_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */ -#define SYSCON_CCLKSEL_CCLKDIV_MASK (0x1f << SYSCON_CCLKSEL_CCLKDIV_SHIFT) -# define SYSCON_CCLKSEL_CCLKDIV(n) ((n-1) << SYSCON_CCLKSEL_CCLKDIV_SHIFT) /* n = 2 - 31 */ - /* Bits 5-7: Reserved */ -#define SYSCON_CCLKSEL_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */ - /* 0: Sysclk used as input to CCLKDIV */ - /* 1: Main PLL used as input to CCLKDIV */ - /* Bits 9-31: Reserved */ -/* USB Clock Selection register */ - -#define SYSCON_USBCLKSEL_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */ -#define SYSCON_USBCLKSEL_USBDIV_MASK (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT) -# define SYSCON_USBCLKSEL_USBDIV_DIV1 (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */ -# define SYSCON_USBCLKSEL_USBDIV_DIV2 (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */ -# define SYSCON_USBCLKSEL_USBDIV_DIV3 (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */ - /* Bits 5-7: Reserved */ -#define SYSCON_USBCLKSEL_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */ -#define SYSCON_USBCLKSEL_USBSEL_MASK (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT) -#define SYSCON_USBCLKSEL_USBSEL_PLL0 (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */ -#define SYSCON_USBCLKSEL_USBSEL_PLL1 (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */ - /* 11: unused */ - /* Bits 10-31: Reserved */ -/* CAN0/1 Sleep Clear Register */ - /* Bit 0: Reserved */ -#define SYSCON_CANSLEEPCLR_SHIFT (1) /* Bits 1-2: CAN0/1 Sleep Status and Control */ -#define SYSCON_CANSLEEPCLR_MASK (3 << SYSCON_CANSLEEPCLR_SHIFT) /* */ -#define SYSCON_CANSLEEPCLR_CAN1 (1 << SYSCON_CANSLEEPCLR_SHIFT) /* CAN1 Sleep Status */ -#define SYSCON_CANSLEEPCLR_CAN2 (2 << SYSCON_CANSLEEPCLR_SHIFT) /* CAN2 Sleep Status */ - /* Read 1: CAN channel in sleep mode */ - /* Write 1: CAN channel clocks restored */ - /* Bits 3-31: Reserved */ -/* CAN0/1 WakeUp Flags Register */ - /* Bit 0: Reserved */ -#define SYSCON_CANWAKEFLAGS_SHIFT (1) /* Bits 1-2: CAN0/1 WakeUp Status */ -#define SYSCON_CANWAKEFLAGS_MASK (3 << SYSCON_CANWAKEFLAGS_SHIFT) /* */ -#define SYSCON_CANWAKEFLAGS_CAN1 (1 << SYSCON_CANWAKEFLAGS_SHIFT) /* CAN1 WakeUp Status */ -#define SYSCON_CANWAKEFLAGS_CAN2 (2 << SYSCON_CANWAKEFLAGS_SHIFT) /* CAN2 WakeUp Status */ - /* Read 1: CAN channel falling edge occur on receive line */ - /* Write 1: CAN channel clears wakeup flag bit */ - /* Bits 3-31: Reserved */ -/* Peripheral Clock Selection register */ -/* PCLK is common to all peripheral */ - -#define SYSCON_PCLKSEL_PCLKDIV_SHIFT (0) /* Bits 0-4: Clock divide value for all APB peripherals */ -#define SYSCON_PCLKSEL_PCLKDIV_MASK (0x1f << SYSCON_PCLKSEL_PCLKDIV_SHIFT) -# define SYSCON_PCLKSEL_PCLKDIV(n) ((n) & SYSCON_PCLKSEL_PCLKDIV_MASK) /* n = 1 - 31 */ - /* Bits 5-31: Reserved */ -/* Power Boost Control Register */ - -#define SYSCON_PBOOST_BOOST_SHIFT (0) /* Bits 0-1: Boost control bits */ -#define SYSCON_PBOOST_BOOST_MASK (3 << SYSCON_PBOOST_BOOST_SHIFT) -#define SYSCON_PBOOST_BOOST_OFF (0) /* Boost OFF, operation must be below 100MHz */ -#define SYSCON_PBOOST_BOOST_ON (3) /* Boost ON, operation upto 120MHz allowed */ - /* Bits 2-31: Reserved */ -/* SPIFI Clock Selection Register */ - -#define SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT (0) /* Bits 0-4: divide value for SPIFI clock */ -#define SYSCON_SPIFICLKSEL_SPIFIDIV_MASK (0x1f << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) -# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */ - /* Bits 5-7: Reserved */ -#define SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT (8) /* Bits 8-9: Selects input clock for SPIFI clock divider */ -#define SYSCON_SPIFICLKSEL_SPIFISEL_MASK (3 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) -#define SYSCON_SPIFICLKSEL_SPIFISEL_SYSCLK (0) /* Sysclk used as input to SPIFIDIV */ -#define SYSCON_SPIFICLKSEL_SPIFISEL_PLL0 (1 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) /* Main PLL used as input to SPIFIDIV */ -#define SYSCON_SPIFICLKSEL_SPIFISEL_PLL1 (2 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) /* Alt PLL used as input to SPIFIDIV */ - /* Bits 10-31: Reserved */ -/* LCD Configuration Register */ - -#define SYSCON_LCDCFG_CLKDIV_SHIFT (0) /* Bits 0-4: LCD Panel clock prescaler */ -#define SYSCON_LCDCFG_CLKDIV_MASK (0x1f << SYSCON_LCDCFG_CLKDIV_SHIFT) -#define SYSCON_LCDCFG_CLKDIV(n) ((n-1) << SYSCON_LCDCFG_CLKDIV_SHIFT) /* n = 1 - 32 */ - /* Bits 5-31: Reserved */ -/* Clocking and power control - Peripheral power control registers */ -/* Power Control Register */ - -#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ -#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ -#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ -#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ -#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ - /* Bits 5-7: Reserved */ -#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ -#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ -#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ -#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ - /* Bits 12-31: Reserved */ -/* Power Control for Peripherals Register */ - -#define SYSCON_PCONP_PCLCD (1 << 0) /* Bit 0: LCD power/clock control */ -#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ -#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ -#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ -#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ -#define SYSCON_PCONP_PCPWM0 (1 << 5) /* Bit 5: PWM0 power/clock control */ -#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ -#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ -#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ -#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ -#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ -#define SYSCON_PCONP_PCEMC (1 << 11) /* Bit 11: External Memory */ -#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ -#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ -#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ -#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ -#define SYSCON_PCONP_PCSPIFI (1 << 16) /* Bit 16: SPI Flash Interface power/clock control */ -#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ -#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ -#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ -#define SYSCON_PCONP_PCSSP2 (1 << 20) /* Bit 20: SSP2 power/clock control */ -#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ -#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ -#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ -#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ -#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ -#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ -#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ -#define SYSCON_PCONP_PCSDC (1 << 28) /* Bit 28: SD Card power/clock control */ -#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ -#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ -#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ - -/* More clocking and power control -- Utility */ - -#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ -#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) -# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ -# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ -# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ -# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ -# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ -# define SYSCON_CLKOUTCFG_SEL_SPIFI (5 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=SPIFI osc */ -#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ -#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) -# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ -#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ -#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ - /* Bits 10-31: Reserved */ -/* System control registers -- External Interrupts */ -/* External Interrupt Flag register */ - -#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ -#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ -#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ -#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ - /* Bits 4-31: Reserved */ -/* External Interrupt Mode register */ - -#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ -#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ -#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ -#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ - /* Bits 4-31: Reserved */ -/* External Interrupt Polarity register */ - -#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ - /* Bits 4-31: Reserved */ -/* System control registers -- Reset */ -/* Reset Source Identification Register */ - -#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ -#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ -#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ -#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ -#define SYSCON_RSID_SYSRESET (1 << 4) /* Bit 4: System Reset */ -#define SYSCON_RSID_LOCKUP (1 << 5) /* Bit 5: Lockup Reset */ - /* Bits 6-31: Reserved */ -/* System control registers -- Matrix Arbitration Priorities */ - -# define SYSCON_MATRIXARB_PRI_LOWEST (0) -# define SYSCON_MATRIXARB_PRI_LOW (1) -# define SYSCON_MATRIXARB_PRI_HIGH (2) -# define SYSCON_MATRIXARB_PRI_HIGHEST (3) - -#define SYSCON_MATRIXARB_PRI_ICODE_SHIFT (0) /* Bits 0-1: I-Code bus priority (should be lower than D-Code) */ -#define SYSCON_MATRIXARB_PRI_ICODE_MASK (3 << SYSCON_MATRIXARB_PRI_ICODE_SHIFT) -# define SYSCON_MATRIXARB_PRI_ICODE(n) ((n) << SYSCON_MATRIXARB_PRI_ICODE_SHIFT) -#define SYSCON_MATRIXARB_PRI_DCODE_SHIFT (2) /* Bits 2-3: D-Code bus priority */ -#define SYSCON_MATRIXARB_PRI_DCODE_MASK (3 << SYSCON_MATRIXARB_PRI_DCODE_SHIFT) -# define SYSCON_MATRIXARB_PRI_DCODE(n) ((n) << SYSCON_MATRIXARB_PRI_DCODE_SHIFT) -#define SYSCON_MATRIXARB_PRI_SYS_SHIFT (4) /* Bits 4-5: System bus priority */ -#define SYSCON_MATRIXARB_PRI_SYS_MASK (3 << SYSCON_MATRIXARB_PRI_SYS_SHIFT) -# define SYSCON_MATRIXARB_PRI_SYS(n) ((n) << SYSCON_MATRIXARB_PRI_SYS_SHIFT) -#define SYSCON_MATRIXARB_PRI_GPDMA_SHIFT (6) /* Bits 6-7: General Purpose DMA priority */ -#define SYSCON_MATRIXARB_PRI_GPDMA_MASK (3 << SYSCON_MATRIXARB_PRI_GPDMA_SHIFT) -# define SYSCON_MATRIXARB_PRI_GPDMA(n) ((n) << SYSCON_MATRIXARB_PRI_GPDMA_SHIFT) -#define SYSCON_MATRIXARB_PRI_ETH_SHIFT (8) /* Bits 8-9: Ethernet DMA priority */ -#define SYSCON_MATRIXARB_PRI_ETH_MASK (3 << SYSCON_MATRIXARB_PRI_ETH_SHIFT) -# define SYSCON_MATRIXARB_PRI_ETH(n) ((n) << SYSCON_MATRIXARB_PRI_ETH_SHIFT) -#define SYSCON_MATRIXARB_PRI_LCD_SHIFT (10) /* Bits 10-11: LCD DMA priority */ -#define SYSCON_MATRIXARB_PRI_LCD_MASK (3 << SYSCON_MATRIXARB_PRI_LCD_SHIFT) -# define SYSCON_MATRIXARB_PRI_LCD(n) ((n) << SYSCON_MATRIXARB_PRI_LCD_SHIFT) -#define SYSCON_MATRIXARB_PRI_USB_SHIFT (12) /* Bits 12-13: USB DMA priority */ -#define SYSCON_MATRIXARB_PRI_USB_MASK (3 << SYSCON_MATRIXARB_PRI_USB_SHIFT) -# define SYSCON_MATRIXARB_PRI_USB(n) ((n) << SYSCON_MATRIXARB_PRI_USB_SHIFT) - /* Bits 14-15: Reserved */ -#define SYSCON_MATRIXARB_ROM_LAT_SHIFT (16) /* Bit 16: ROM Latency select (should always be zero) */ -#define SYSCON_MATRIXARB_ROM_LAT (1 << SYSCON_MATRIXARB_ROM_LAT_SHIFT) - /* Bits 17-31: Reserved */ - -#define SYSCON_MATRIXARB_PRI_MASK (0x00013fff) - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define SYSCON_SCS_EMCSC (1 << 0) /* Bit 0: EMC shift control */ -#define SYSCON_SCS_EMCRD (1 << 1) /* Bit 1: EMC reset disable */ -#define SYSCON_SCS_EMCBC (1 << 2) /* Bit 2: EMC burst control */ -#define SYSCON_SCS_MCIPWRAL (1 << 3) /* Bit 3: MCI power active level */ -#define SYSCON_SCS_OSCRS (1 << 4) /* Bit 4: Main oscillator range select */ -#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ -#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ - /* Bits 7-31: Reserved */ -/* Device Interrupt Registers */ -/* USB Interrupt Status register */ - -#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ -#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ -#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ -#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ -#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ -#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ -#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ - /* Bit 7: Reserved */ -#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ - /* Bits 9-30: Reserved */ -#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ - -/* DMA Request Select Register */ - -#define SYSCON_DMAREQSEL_INP0 (1 << 0) /* Bit 0: Input 0 0=unused 1=Timer 0 match 0 */ -#define SYSCON_DMAREQSEL_INP1 (1 << 1) /* Bit 1: Input 1 0=SD 1=Timer 0 match 1 */ -#define SYSCON_DMAREQSEL_INP2 (1 << 2) /* Bit 2: Input 2 0=SSP0 TX 1=Timer 1 match 0 */ -#define SYSCON_DMAREQSEL_INP3 (1 << 3) /* Bit 3: Input 3 0=SSP0 RX 1=Timer 1 match 1 */ -#define SYSCON_DMAREQSEL_INP4 (1 << 4) /* Bit 4: Input 4 0=SSP1 TX 1=Timer 2 match 0 */ -#define SYSCON_DMAREQSEL_INP5 (1 << 5) /* Bit 5: Input 5 0=SSP1 RX 1=Timer 2 match 1 */ -#define SYSCON_DMAREQSEL_INP6 (1 << 6) /* Bit 6: Input 6 0=SSP2 TX 1=I2S0 */ -#define SYSCON_DMAREQSEL_INP7 (1 << 7) /* Bit 7: Input 7 0=SSP2 RX 1=I2S1 */ - /* Bits 8-9: Reserved */ -#define SYSCON_DMAREQSEL_INP10 (1 << 10) /* Bit 10: Input 10 0=UART0 TX 1=UART3 TX */ -#define SYSCON_DMAREQSEL_INP11 (1 << 11) /* Bit 11: Input 11 0=UART0 RX 1=UART3 RX */ -#define SYSCON_DMAREQSEL_INP12 (1 << 12) /* Bit 12: Input 12 0=UART1 TX 1=UART4 TX */ -#define SYSCON_DMAREQSEL_INP13 (1 << 13) /* Bit 13: Input 13 0=UART1 RX 1=UART4 RX */ -#define SYSCON_DMAREQSEL_INP14 (1 << 14) /* Bit 14: Input 14 0=UART2 TX 1=Timer 3 match 0 */ -#define SYSCON_DMAREQSEL_INP15 (1 << 15) /* Bit 15: Input 15 0=UART2 RX 1=Timer 3 match 1 */ - /* Bits 16-31: Reserved */ -/* Reset Control Register 0 */ - -#define SYSCON_RSTCON0_RSTLCD (1 << 0) /* LCD controller reset control bit */ -#define SYSCON_RSTCON0_RSTTIM0 (1 << 1) /* Timer/Counter 0 reset control bit */ -#define SYSCON_RSTCON0_RSTTIM1 (1 << 2) /* Timer/Counter 1 reset control bit */ -#define SYSCON_RSTCON0_RSTUART0 (1 << 3) /* UART0 reset control bit */ -#define SYSCON_RSTCON0_RSTUART1 (1 << 4) /* UART1 reset control bit */ -#define SYSCON_RSTCON0_RSTPWM0 (1 << 5) /* PWM0 reset control bit */ -#define SYSCON_RSTCON0_RSTPWM1 (1 << 6) /* PWM1 reset control bit */ -#define SYSCON_RSTCON0_RSTI2C0 (1 << 7) /* The I2C0 interface reset control bit */ -#define SYSCON_RSTCON0_RSTUART4 (1 << 8) /* UART4 reset control bit */ -#define SYSCON_RSTCON0_RSTRTC (1 << 9) /* RTC and Event Monitor/Recorder reset control bit. RTC reset is limited */ -#define SYSCON_RSTCON0_RSTSSP1 (1 << 10) /* The SSP 1 interface reset control bit */ -#define SYSCON_RSTCON0_RSTEMC (1 << 11) /* External Memory Controller reset control bit */ -#define SYSCON_RSTCON0_RSTADC (1 << 12) /* A/D converter (ADC) reset control bit */ -#define SYSCON_RSTCON0_RSTCAN1 (1 << 13) /* CAN Controller 1 reset control bit */ - /* Note: The CAN acceptance filter may be reset by 0 - * a separate bit in the RSTCON1 register. */ -#define SYSCON_RSTCON0_RSTCAN2 (1 << 14) /* CAN Controller 2 reset control bit */ - /* Note: The CAN acceptance filter may be reset by 0 - * a separate bit in the RSTCON1 register */ -#define SYSCON_RSTCON0_RSTGPIO (1 << 15) /* Reset control bit for GPIO, and GPIO interrupts */ - /* Note: IOCON may be reset by a 0 - * separate bit in the RSTCON1 register */ -#define SYSCON_RSTCON0_RSTSPIFI (1 << 16) /* SPI Flash Interface reset control bit (LPC1773 only) */ -#define SYSCON_RSTCON0_RSTMCPWM (1 << 17) /* Motor Control PWM reset control bit */ -#define SYSCON_RSTCON0_RSTQEI (1 << 18) /* Quadrature Encoder Interface reset control bit */ -#define SYSCON_RSTCON0_RSTI2C1 (1 << 19) /* The I2C1 interface reset control bit */ -#define SYSCON_RSTCON0_RSTSSP2 (1 << 20) /* The SSP2 interface reset control bit */ -#define SYSCON_RSTCON0_RSTSSP0 (1 << 21) /* The SSP0 interface reset control bit */ -#define SYSCON_RSTCON0_RSTTIM2 (1 << 22) /* Timer 2 reset control bit */ -#define SYSCON_RSTCON0_RSTTIM3 (1 << 23) /* Timer 3 reset control bit */ -#define SYSCON_RSTCON0_RSTUART2 (1 << 24) /* UART 2 reset control bit */ -#define SYSCON_RSTCON0_RSTUART3 (1 << 25) /* UART 3 reset control bit */ -#define SYSCON_RSTCON0_RSTI2C2 (1 << 26) /* I2C2 interface reset control bit.*/ -#define SYSCON_RSTCON0_RSTI2S (1 << 27) /* I2S interface reset control bit */ -#define SYSCON_RSTCON0_RSTSDC (1 << 28) /* SD Card interface reset control bit */ -#define SYSCON_RSTCON0_RSTGPDMA (1 << 29) /* GPDMA function reset control bit */ - -#define SYSCON_RSTCON0_RSTENET (1 << 30) /* Ethernet block reset control bit */ -#define SYSCON_RSTCON0_RSTUSB (1 << 31) /* USB interface reset control bit */ - -/* Reset Control Register 1 */ - -#define SYSCON_RSTCON1_RSTIOCON (1 << 0) /* Reset control bit for the IOCON registers */ -#define SYSCON_RSTCON1_RSTDAC (1 << 1) /* D/A converter (DAC) reset control bit */ -#define SYSCON_RSTCON1_RSTCANACC (1 << 2) /* CAN acceptance filter reset control bit */ - /* Bits 3-31: Reserved */ -/* Delay Control Register - EMC */ - /* Delay values multiplied by 250 picoseconds */ -#define SYSCON_EMCDLYCTL_CMDDLY_SHIFT (0) /* Bits 0-4: Delay value for EMC outputs in command delayed mode */ -#define SYSCON_EMCDLYCTL_CMDDLY_MASK (0x1f << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) -# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n-1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 3 - 32 */ - /* Bits 5-7: Reserved */ -#define SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT (8) /* Bits 8-12: Delay value for the feedback clock that controls input data sampling */ -#define SYSCON_EMCDLYCTL_FBCLKDLY_MASK (0x1f << SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT) -#define SYSCON_EMCDLYCTL_FBCLKDLY(n) ((n-1)<< SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT) /* n = 3 - 32 */ - /* Bits 13-15: Reserved */ -#define SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT (16) /* Bits 16-20: Delay value for the CLKOUT0 output */ -#define SYSCON_EMCDLYCTL_CLKOUT0DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) -# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 3 - 32 */ - /* Bits 21-23: Reserved */ -#define SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT (24) /* Bits 24-28: Delay value for the CLKOUT1 output */ -#define SYSCON_EMCDLYCTL_CLKOUT1DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) -# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 3 - 32 */ - /* Bits 29-31: Reserved */ -/* Calibration Register - EMC */ - -#define SYSCON_EMCCAL_CALVALUE_SHIFT (0) /* Bits 0-7: Ring oscillator count during 32 clocks of Internal RC */ -#define SYSCON_EMCCAL_CALVALUE_MASK (0xff << SYSCON_EMCCAL_CALVALUE_SHIFT) - /* Bits 8-13: Reserved */ -#define SYSCON_EMCCAL_START_SHIFT (14) /* Bit 14: Start control bit for EMC calibration counter */ -#define SYSCON_EMCCAL_START_MASK (1 << SYSCON_EMCCAL_START_SHIFT) -# define SYSCON_EMCCAL_START (1) /* Automatically cleared when measurement is done */ -#define SYSCON_EMCCAL_DONE_SHIFT (15) /* Bit 15: Measurement completetion flag bit */ -#define SYSCON_EMCCAL_DONE_MASK (1 << SYSCON_EMCCAL_DONE_SHIFT) - /* Automatically cleared when START bit is set */ - /* Bits 16-31: Reserved */ - -/* Compatibility Definitions ************************************************************************/ -/* Need in lpc17_clockconfig.h for compatibility with the LPC176x family: */ - -#define SYSCON_PLLCON_PLLC (0) /* Bit does not exist in LPC178x family */ -#define SYSCON_PLL0STAT_PLLE SYSCON_PLLSTAT_PLLE /* PLL enable readback */ -#define SYSCON_PLL0STAT_PLLC SYSCON_PLLSTAT_PLLC /* PLL connect readback */ -#define SYSCON_PLL0STAT_PLOCK SYSCON_PLLSTAT_PLOCK /* PLL lock status */ -#define SYSCON_PLL1STAT_PLLE SYSCON_PLLSTAT_PLLE /* PLL enable readback */ -#define SYSCON_PLL1STAT_PLLC SYSCON_PLLSTAT_PLLC /* PLL connect readback */ -#define SYSCON_PLL1STAT_PLOCK SYSCON_PLLSTAT_PLOCK /* PLL lock status */ - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_SYSCON_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_can.h b/arch/arm/src/lpc17xx/hardware/lpc17_can.h deleted file mode 100644 index 2a9172ada94..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_can.h +++ /dev/null @@ -1,510 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_can.h - * - * Copyright (C) 2010-2012, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_CAN_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_CAN_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* CAN acceptance filter registers */ - -#define LPC17_CANAF_AFMR_OFFSET 0x0000 /* Acceptance Filter Register */ -#define LPC17_CANAF_SFFSA_OFFSET 0x0004 /* Standard Frame Individual Start Address Register */ -#define LPC17_CANAF_SFFGRPSA_OFFSET 0x0008 /* Standard Frame Group Start Address Register */ -#define LPC17_CANAF_EFFSA_OFFSET 0x000c /* Extended Frame Start Address Register */ -#define LPC17_CANAF_EFFGRPSA_OFFSET 0x0010 /* Extended Frame Group Start Address Register */ -#define LPC17_CANAF_EOT_OFFSET 0x0014 /* End of AF Tables register */ -#define LPC17_CANAF_LUTERRAD_OFFSET 0x0018 /* LUT Error Address register */ -#define LPC17_CANAF_LUTERR_OFFSET 0x001c /* LUT Error Register */ -#define LPC17_CANAF_FCANIE_OFFSET 0x0020 /* FullCAN interrupt enable register */ -#define LPC17_CANAF_FCANIC0_OFFSET 0x0024 /* FullCAN interrupt and capture register 0 */ -#define LPC17_CANAF_FCANIC1_OFFSET 0x0028 /* FullCAN interrupt and capture register 1 */ - -/* Central CAN registers */ - -#define LPC17_CAN_TXSR_OFFSET 0x0000 /* CAN Central Transmit Status Register */ -#define LPC17_CAN_RXSR_OFFSET 0x0004 /* CAN Central Receive Status Register */ -#define LPC17_CAN_MSR_OFFSET 0x0008 /* CAN Central Miscellaneous Register */ - -/* CAN1/2 registers */ - -#define LPC17_CAN_MOD_OFFSET 0x0000 /* CAN operating mode */ -#define LPC17_CAN_CMR_OFFSET 0x0004 /* Command bits */ -#define LPC17_CAN_GSR_OFFSET 0x0008 /* Controller Status and Error Counters */ -#define LPC17_CAN_ICR_OFFSET 0x000c /* Interrupt and capure register */ -#define LPC17_CAN_IER_OFFSET 0x0010 /* Interrupt Enable */ -#define LPC17_CAN_BTR_OFFSET 0x0014 /* Bus Timing */ -#define LPC17_CAN_EWL_OFFSET 0x0018 /* Error Warning Limit */ -#define LPC17_CAN_SR_OFFSET 0x001c /* Status Register */ -#define LPC17_CAN_RFS_OFFSET 0x0020 /* Receive frame status */ -#define LPC17_CAN_RID_OFFSET 0x0024 /* Received Identifier */ -#define LPC17_CAN_RDA_OFFSET 0x0028 /* Received data bytes 1-4 */ -#define LPC17_CAN_RDB_OFFSET 0x002c /* Received data bytes 5-8 */ -#define LPC17_CAN_TFI1_OFFSET 0x0030 /* Transmit frame info (Tx Buffer 1) */ -#define LPC17_CAN_TID1_OFFSET 0x0034 /* Transmit Identifier (Tx Buffer 1) */ -#define LPC17_CAN_TDA1_OFFSET 0x0038 /* Transmit data bytes 1-4 (Tx Buffer 1) */ -#define LPC17_CAN_TDB1_OFFSET 0x003c /* Transmit data bytes 5-8 (Tx Buffer 1) */ -#define LPC17_CAN_TFI2_OFFSET 0x0040 /* Transmit frame info (Tx Buffer 2) */ -#define LPC17_CAN_TID2_OFFSET 0x0044 /* Transmit Identifier (Tx Buffer 2) */ -#define LPC17_CAN_TDA2_OFFSET 0x0048 /* Transmit data bytes 1-4 (Tx Buffer 2) */ -#define LPC17_CAN_TDB2_OFFSET 0x004c /* Transmit data bytes 5-8 (Tx Buffer 2) */ -#define LPC17_CAN_TFI3_OFFSET 0x0050 /* Transmit frame info (Tx Buffer 3) */ -#define LPC17_CAN_TID3_OFFSET 0x0054 /* Transmit Identifier (Tx Buffer 3) */ -#define LPC17_CAN_TDA3_OFFSET 0x0058 /* Transmit data bytes 1-4 (Tx Buffer 3) */ -#define LPC17_CAN_TDB3_OFFSET 0x005c /* Transmit data bytes 5-8 (Tx Buffer 3) */ - -/* Register addresses ***************************************************************/ -/* CAN acceptance filter registers */ - -#define LPC17_CANAF_AFMR (LPC17_CANAF_BASE+LPC17_CANAF_AFMR_OFFSET) -#define LPC17_CANAF_SFFSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFSA_OFFSET) -#define LPC17_CANAF_SFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFGRPSA_OFFSET) -#define LPC17_CANAF_EFFSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFSA_OFFSET) -#define LPC17_CANAF_EFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFGRPSA_OFFSET) -#define LPC17_CANAF_EOT (LPC17_CANAF_BASE+LPC17_CANAF_EOT_OFFSET) -#define LPC17_CANAF_LUTERRAD (LPC17_CANAF_BASE+LPC17_CANAF_LUTERRAD_OFFSET) -#define LPC17_CANAF_LUTERR (LPC17_CANAF_BASE+LPC17_CANAF_LUTERR_OFFSET) -#define LPC17_CANAF_FCANIE (LPC17_CANAF_BASE+LPC17_CANAF_FCANIE_OFFSET) -#define LPC17_CANAF_FCANIC0 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC0_OFFSET) -#define LPC17_CANAF_FCANIC1 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC1_OFFSET) - -/* Central CAN registers */ - -#define LPC17_CAN_TXSR (LPC17_CAN_BASE+LPC17_CAN_TXSR_OFFSET) -#define LPC17_CAN_RXSR (LPC17_CAN_BASE+LPC17_CAN_RXSR_OFFSET) -#define LPC17_CAN_MSR (LPC17_CAN_BASE+LPC17_CAN_MSR_OFFSET) - -/* CAN1/2 registers */ - -#define LPC17_CAN1_MOD (LPC17_CAN1_BASE+LPC17_CAN_MOD_OFFSET) -#define LPC17_CAN1_CMR (LPC17_CAN1_BASE+LPC17_CAN_CMR_OFFSET) -#define LPC17_CAN1_GSR (LPC17_CAN1_BASE+LPC17_CAN_GSR_OFFSET) -#define LPC17_CAN1_ICR (LPC17_CAN1_BASE+LPC17_CAN_ICR_OFFSET) -#define LPC17_CAN1_IER (LPC17_CAN1_BASE+LPC17_CAN_IER_OFFSET) -#define LPC17_CAN1_BTR (LPC17_CAN1_BASE+LPC17_CAN_BTR_OFFSET) -#define LPC17_CAN1_EWL (LPC17_CAN1_BASE+LPC17_CAN_EWL_OFFSET) -#define LPC17_CAN1_SR (LPC17_CAN1_BASE+LPC17_CAN_SR_OFFSET) -#define LPC17_CAN1_RFS (LPC17_CAN1_BASE+LPC17_CAN_RFS_OFFSET) -#define LPC17_CAN1_RID (LPC17_CAN1_BASE+LPC17_CAN_RID_OFFSET) -#define LPC17_CAN1_RDA (LPC17_CAN1_BASE+LPC17_CAN_RDA_OFFSET) -#define LPC17_CAN1_RDB (LPC17_CAN1_BASE+LPC17_CAN_RDB_OFFSET) -#define LPC17_CAN1_TFI1 (LPC17_CAN1_BASE+LPC17_CAN_TFI1_OFFSET) -#define LPC17_CAN1_TID1 (LPC17_CAN1_BASE+LPC17_CAN_TID1_OFFSET) -#define LPC17_CAN1_TDA1 (LPC17_CAN1_BASE+LPC17_CAN_TDA1_OFFSET) -#define LPC17_CAN1_TDB1 (LPC17_CAN1_BASE+LPC17_CAN_TDB1_OFFSET) -#define LPC17_CAN1_TFI2 (LPC17_CAN1_BASE+LPC17_CAN_TFI2_OFFSET) -#define LPC17_CAN1_TID2 (LPC17_CAN1_BASE+LPC17_CAN_TID2_OFFSET) -#define LPC17_CAN1_TDA2 (LPC17_CAN1_BASE+LPC17_CAN_TDA2_OFFSET) -#define LPC17_CAN1_TDB2 (LPC17_CAN1_BASE+LPC17_CAN_TDB2_OFFSET) -#define LPC17_CAN1_TFI3 (LPC17_CAN1_BASE+LPC17_CAN_TFI3_OFFSET) -#define LPC17_CAN1_TID3 (LPC17_CAN1_BASE+LPC17_CAN_TID3_OFFSET) -#define LPC17_CAN1_TDA3 (LPC17_CAN1_BASE+LPC17_CAN_TDA3_OFFSET) -#define LPC17_CAN1_TDB3 (LPC17_CAN1_BASE+LPC17_CAN_TDB3_OFFSET) - -#define LPC17_CAN2_MOD (LPC17_CAN2_BASE+LPC17_CAN_MOD_OFFSET) -#define LPC17_CAN2_CMR (LPC17_CAN2_BASE+LPC17_CAN_CMR_OFFSET) -#define LPC17_CAN2_GSR (LPC17_CAN2_BASE+LPC17_CAN_GSR_OFFSET) -#define LPC17_CAN2_ICR (LPC17_CAN2_BASE+LPC17_CAN_ICR_OFFSET) -#define LPC17_CAN2_IER (LPC17_CAN2_BASE+LPC17_CAN_IER_OFFSET) -#define LPC17_CAN2_BTR (LPC17_CAN2_BASE+LPC17_CAN_BTR_OFFSET) -#define LPC17_CAN2_EWL (LPC17_CAN2_BASE+LPC17_CAN_EWL_OFFSET) -#define LPC17_CAN2_SR (LPC17_CAN2_BASE+LPC17_CAN_SR_OFFSET) -#define LPC17_CAN2_RFS (LPC17_CAN2_BASE+LPC17_CAN_RFS_OFFSET) -#define LPC17_CAN2_RID (LPC17_CAN2_BASE+LPC17_CAN_RID_OFFSET) -#define LPC17_CAN2_RDA (LPC17_CAN2_BASE+LPC17_CAN_RDA_OFFSET) -#define LPC17_CAN2_RDB (LPC17_CAN2_BASE+LPC17_CAN_RDB_OFFSET) -#define LPC17_CAN2_TFI1 (LPC17_CAN2_BASE+LPC17_CAN_TFI1_OFFSET) -#define LPC17_CAN2_TID1 (LPC17_CAN2_BASE+LPC17_CAN_TID1_OFFSET) -#define LPC17_CAN2_TDA1 (LPC17_CAN2_BASE+LPC17_CAN_TDA1_OFFSET) -#define LPC17_CAN2_TDB1 (LPC17_CAN2_BASE+LPC17_CAN_TDB1_OFFSET) -#define LPC17_CAN2_TFI2 (LPC17_CAN2_BASE+LPC17_CAN_TFI2_OFFSET) -#define LPC17_CAN2_TID2 (LPC17_CAN2_BASE+LPC17_CAN_TID2_OFFSET) -#define LPC17_CAN2_TDA2 (LPC17_CAN2_BASE+LPC17_CAN_TDA2_OFFSET) -#define LPC17_CAN2_TDB2 (LPC17_CAN2_BASE+LPC17_CAN_TDB2_OFFSET) -#define LPC17_CAN2_TFI3 (LPC17_CAN2_BASE+LPC17_CAN_TFI3_OFFSET) -#define LPC17_CAN2_TID3 (LPC17_CAN2_BASE+LPC17_CAN_TID3_OFFSET) -#define LPC17_CAN2_TDA3 (LPC17_CAN2_BASE+LPC17_CAN_TDA3_OFFSET) -#define LPC17_CAN2_TDB3 (LPC17_CAN2_BASE+LPC17_CAN_TDB3_OFFSET) - -/* Register bit definitions *********************************************************/ -/* CAN acceptance filter registers */ -/* Acceptance Filter Register */ - -#define CANAF_AFMR_ACCOFF (1 << 0) /* Bit 0: AF non-operational; All RX messages ignored */ -#define CANAF_AFMR_ACCBP (1 << 1) /* Bit 1: AF bypass: All RX messages accepted */ -#define CANAF_AFMR_EFCAN (1 << 2) /* Bit 2: Enable Full CAN mode */ - /* Bits 3-31: Reserved */ -/* Standard Frame Individual Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_SFFSA_SHIFT (2) /* Bits 2-10: Address of Standard Identifiers in AF Lookup RAM */ -#define CANAF_SFFSA_MASK (0x01ff << CANAF_SFFSA_SHIFT) - /* Bits 11-31: Reserved */ -/* Standard Frame Group Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_SFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Standard Identifiers in AF Lookup RAM */ -#define CANAF_SFFGRPSA_MASK (0x01ff << CANAF_SFFGRPSA_SHIFT) - /* Bits 11-31: Reserved */ -/* Extended Frame Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_EFFSA_SHIFT (2) /* Bits 2-10: Address of Extended Identifiers in AF Lookup RAM */ -#define CANAF_EFFSA_MASK (0x01ff << CANAF_EFFSA_SHIFT) - /* Bits 11-31: Reserved */ -/* Extended Frame Group Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_EFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Extended Identifiers in AF Lookup RAM */ -#define CANAF_EFFGRPSA_MASK (0x01ff << CANAF_EFFGRPSA_SHIFT) - /* Bits 11-31: Reserved */ -/* End of AF Tables register */ - /* Bits 0-1: Reserved */ -#define CANAF_EOT_SHIFT (2) /* Bits 2-10: Last active address in last active AF table */ -#define CANAF_EOT_MASK (0x01ff << CANAF_EOT_SHIFT) - /* Bits 11-31: Reserved */ -/* LUT Error Address register */ - /* Bits 0-1: Reserved */ -#define CANAF_LUTERRAD_SHIFT (2) /* Bits 2-10: Address in AF Lookup RAM of error */ -#define CANAF_LUTERRAD_MASK (0x01ff << CANAF_EOT_SHIFT) - /* Bits 11-31: Reserved */ -/* LUT Error Register */ - -#define CANAF_LUTERR_LUTERR (1 << 0) /* Bit 0: AF error in AF RAM tables */ - /* Bits 1-31: Reserved */ -/* FullCAN interrupt enable register */ - -#define CANAF_FCANIE_FCANIE (1 << 0) /* Bit 0: Global FullCAN Interrupt Enable */ - /* Bits 1-31: Reserved */ - -/* FullCAN interrupt and capture register 0 */ - -#define CANAF_FCANIC0_INTPND(n) (1 << (n)) /* n=0,1,2,... 31 */ - -/* FullCAN interrupt and capture register 1 */ - -#define CANAF_FCANIC1_INTPND(n) (1 << ((n)-32)) /* n=32,33,...63 */ - -/* Central CAN registers */ -/* CAN Central Transmit Status Register */ - -#define CAN_TXSR_TS1 (1 << 0) /* Bit 0: CAN1 sending */ -#define CAN_TXSR_TS2 (1 << 1) /* Bit 1: CAN2 sending */ - /* Bits 2-7: Reserved */ -#define CAN_TXSR_TBS1 (1 << 8) /* Bit 8: All 3 CAN1 TX buffers available */ -#define CAN_TXSR_TBS2 (1 << 9) /* Bit 9: All 3 CAN2 TX buffers available */ - /* Bits 10-15: Reserved */ -#define CAN_TXSR_TCS1 (1 << 16) /* Bit 16: All CAN1 xmissions completed */ -#define CAN_TXSR_TCS2 (1 << 17) /* Bit 17: All CAN2 xmissions completed */ - /* Bits 18-31: Reserved */ -/* CAN Central Receive Status Register */ - -#define CAN_RXSR_RS1 (1 << 0) /* Bit 0: CAN1 receiving */ -#define CAN_RXSR_RS2 (1 << 1) /* Bit 1: CAN2 receiving */ - /* Bits 2-7: Reserved */ -#define CAN_RXSR_RB1 (1 << 8) /* Bit 8: CAN1 received message available */ -#define CAN_RXSR_RB2 (1 << 9) /* Bit 9: CAN2 received message available */ - /* Bits 10-15: Reserved */ -#define CAN_RXSR_DOS1 (1 << 16) /* Bit 16: All CAN1 message lost */ -#define CAN_RXSR_DOS2 (1 << 17) /* Bit 17: All CAN2 message lost */ - /* Bits 18-31: Reserved */ -/* CAN Central Miscellaneous Register */ - -#define CAN_MSR_E1 (1 << 0) /* Bit 0: CAN1 error counters at limit */ -#define CAN_MSR_E2 (1 << 1) /* Bit 1: CAN2 error counters at limit */ - /* Bits 2-7: Reserved */ -#define CAN_MSR_BS1 (1 << 8) /* Bit 8: CAN1 busy */ -#define CAN_MSR_BS2 (1 << 9) /* Bit 7: CAN2 busy */ - /* Bits 10-31: Reserved */ -/* CAN1/2 registers */ -/* CAN operating mode */ - -#define CAN_MOD_RM (1 << 0) /* Bit 0: Reset Mode */ -#define CAN_MOD_LOM (1 << 1) /* Bit 1: Listen Only Mode */ -#define CAN_MOD_STM (1 << 2) /* Bit 2: Self Test Mode */ -#define CAN_MOD_TPM (1 << 3) /* Bit 3: Transmit Priority Mode */ -#define CAN_MOD_SM (1 << 4) /* Bit 4: Sleep Mode */ -#define CAN_MOD_RPM (1 << 5) /* Bit 5: Receive Polarity Mode */ - /* Bit 6: Reserved */ -#define CAN_MOD_TM (1 << 7) /* Bit 7: Test Mode */ - /* Bits 8-31: Reserved */ -/* Command bits */ - -#define CAN_CMR_TR (1 << 0) /* Bit 0: Transmission Request */ -#define CAN_CMR_AT (1 << 1) /* Bit 1: Abort Transmission */ -#define CAN_CMR_RRB (1 << 2) /* Bit 2: Release Receive Buffer */ -#define CAN_CMR_CDO (1 << 3) /* Bit 3: Clear Data Overrun */ -#define CAN_CMR_SRR (1 << 4) /* Bit 4: Self Reception Request */ -#define CAN_CMR_STB1 (1 << 5) /* Bit 5: Select Tx Buffer 1 */ -#define CAN_CMR_STB2 (1 << 6) /* Bit 6: Select Tx Buffer 2 */ -#define CAN_CMR_STB3 (1 << 7) /* Bit 7: Select Tx Buffer 3 */ - /* Bits 8-31: Reserved */ -/* Controller Status and Error Counters */ - -#define CAN_GSR_RBS (1 << 0) /* Bit 0: Receive Buffer Status */ -#define CAN_GSR_DOS (1 << 1) /* Bit 1: Data Overrun Status */ -#define CAN_GSR_TBS (1 << 2) /* Bit 2: Transmit Buffer Status */ -#define CAN_GSR_TCS (1 << 3) /* Bit 3: Transmit Complete Status */ -#define CAN_GSR_RS (1 << 4) /* Bit 4: Receive Status */ -#define CAN_GSR_TS (1 << 5) /* Bit 5: Transmit Status */ -#define CAN_GSR_ES (1 << 6) /* Bit 6: Error Status */ -#define CAN_GSR_BS (1 << 7) /* Bit 7: Bus Status */ - /* Bits 8-15: Reserved */ -#define CAN_GSR_RXERR_SHIFT (16) /* Bits 16-23: Rx Error Counter */ -#define CAN_GSR_RXERR_MASK (0xff << CAN_GSR_RXERR_SHIFT) -#define CAN_GSR_TXERR_SHIFT (24) /* Bits 24-31: Tx Error Counter */ -#define CAN_GSR_TXERR_MASK (0xff << CAN_GSR_TXERR_SHIFT) - -/* Interrupt and capture register */ - -#define CAN_ICR_RI (1 << 0) /* Bit 0: Receive Interrupt */ -#define CAN_ICR_TI1 (1 << 1) /* Bit 1: Transmit Interrupt 1 */ -#define CAN_ICR_EI (1 << 2) /* Bit 2: Error Warning Interrupt */ -#define CAN_ICR_DOI (1 << 3) /* Bit 3: Data Overrun Interrupt */ -#define CAN_ICR_WUI (1 << 4) /* Bit 4: Wake-Up Interrupt */ -#define CAN_ICR_EPI (1 << 5) /* Bit 5: Error Passive Interrupt */ -#define CAN_ICR_ALI (1 << 6) /* Bit 6: Arbitration Lost Interrupt */ -#define CAN_ICR_BEI (1 << 7) /* Bit 7: Bus Error Interrupt */ -#define CAN_ICR_IDI (1 << 8) /* Bit 8: ID Ready Interrupt */ -#define CAN_ICR_TI2 (1 << 9) /* Bit 9: Transmit Interrupt 2 */ -#define CAN_ICR_TI3 (1 << 10) /* Bit 10: Transmit Interrupt 3 */ - /* Bits 11-15: Reserved */ -#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */ -#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT) -# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ -# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ -# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ -# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ -# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ -# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ -# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ -# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ -# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ -# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ -# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ -# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ -# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ -# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ -# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ -# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ -# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ -# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ -# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ -# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ -# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ -# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ -#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */ -#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */ -#define CAN_ICR_ERRC_MASK (3 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_BIT (0 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_FORM (1 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_STUFF (2 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_OTHER (3 << CAN_ICR_ERRC_SHIFT) -#define CAN_ICR_ALCBIT_SHIFT (24) /* Bits 24-31: Bit number within frame */ -#define CAN_ICR_ALCBIT_MASK (0xff << CAN_ICR_ALCBIT_SHIFT) - -/* Interrupt Enable */ - -#define CAN_IER_RIE (1 << 0) /* Bit 0: Receiver Interrupt Enable */ -#define CAN_IER_TIE1 (1 << 1) /* Bit 1: Transmit Interrupt Enable for Buffer1 */ -#define CAN_IER_EIE (1 << 2) /* Bit 2: Error Warning Interrupt Enable */ -#define CAN_IER_DOIE (1 << 3) /* Bit 3: Data Overrun Interrupt Enable */ -#define CAN_IER_WUIE (1 << 4) /* Bit 4: Wake-Up Interrupt Enable */ -#define CAN_IER_EPIE (1 << 5) /* Bit 5: Error Passive Interrupt Enable */ -#define CAN_IER_ALIE (1 << 6) /* Bit 6: Arbitration Lost Interrupt Enable */ -#define CAN_IER_BEIE (1 << 7) /* Bit 7: Bus Error Interrupt */ -#define CAN_IER_IDIE (1 << 8) /* Bit 8: ID Ready Interrupt Enable */ -#define CAN_IER_TIE2 (1 << 9) /* Bit 9: Transmit Interrupt Enable for Buffer2 */ -#define CAN_IER_TIE3 (1 << 10) /* Bit 10: Transmit Interrupt Enable for Buffer3 */ - /* Bits 11-31: Reserved */ -/* Bus Timing */ - -#define CAN_BTR_BRP_SHIFT (0) /* Bits 0-9: Baud Rate Prescaler */ -#define CAN_BTR_BRP_MASK (0x3ff << CAN_BTR_BRP_SHIFT) - /* Bits 10-13: Reserved */ -#define CAN_BTR_SJW_SHIFT (14) /* Bits 14-15: Synchronization Jump Width */ -#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) -#define CAN_BTR_TSEG1_SHIFT (16) /* Bits 16-19: Sync to sample delay */ -#define CAN_BTR_TSEG1_MASK (15 << CAN_BTR_TSEG1_SHIFT) -#define CAN_BTR_TSEG2_SHIFT (20) /* Bits 20-22: smaple to next delay */ -#define CAN_BTR_TSEG2_MASK (7 << CAN_BTR_TSEG2_SHIFT) -#define CAN_BTR_SAM (1 << 23) /* Bit 23: Sampling */ - /* Bits 24-31: Reserved */ - -#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ -#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ -#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ - -/* Error Warning Limit */ - -#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ -#define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT) - /* Bits 8-31: Reserved */ -/* Status Register */ - -#define CAN_SR_RBS1 (1 << 0) /* Bit 0: Receive Buffer Status */ -#define CAN_SR_DOS1 (1 << 1) /* Bit 1: Data Overrun Status */ -#define CAN_SR_TBS1 (1 << 2) /* Bit 2: Transmit Buffer Status 1 */ -#define CAN_SR_TCS1 (1 << 3) /* Bit 3: Transmission Complete Status */ -#define CAN_SR_RS1 (1 << 4) /* Bit 4: Receive Status */ -#define CAN_SR_TS1 (1 << 5) /* Bit 5: Transmit Status 1 */ -#define CAN_SR_ES1 (1 << 6) /* Bit 6: Error Status */ -#define CAN_SR_BS1 (1 << 7) /* Bit 7: Bus Status */ -#define CAN_SR_RBS2 (1 << 8) /* Bit 8: Receive Buffer Status */ -#define CAN_SR_DOS2 (1 << 9) /* Bit 9: Data Overrun Status */ -#define CAN_SR_TBS2 (1 << 10) /* Bit 10: Transmit Buffer Status 2 */ -#define CAN_SR_TCS2 (1 << 11) /* Bit 11: Transmission Complete Status */ -#define CAN_SR_RS2 (1 << 12) /* Bit 12: Receive Status */ -#define CAN_SR_TS2 (1 << 13) /* Bit 13: Transmit Status 2 */ -#define CAN_SR_ES2 (1 << 14) /* Bit 14: Error Status */ -#define CAN_SR_BS2 (1 << 15) /* Bit 15: Bus Status */ -#define CAN_SR_RBS3 (1 << 16) /* Bit 16: Receive Buffer Status */ -#define CAN_SR_DOS3 (1 << 17) /* Bit 17: Data Overrun Status */ -#define CAN_SR_TBS3 (1 << 18) /* Bit 18: Transmit Buffer Status 3 */ -#define CAN_SR_TCS3 (1 << 19) /* Bit 19: Transmission Complete Status */ -#define CAN_SR_RS3 (1 << 20) /* Bit 20: Receive Status */ -#define CAN_SR_TS3 (1 << 21) /* Bit 21: Transmit Status 3 */ -#define CAN_SR_ES3 (1 << 22) /* Bit 22: Error Status */ -#define CAN_SR_BS3 (1 << 23) /* Bit 23: Bus Status */ - /* Bits 24-31: Reserved */ -/* Receive frame status */ - -#define CAN_RFS_ID_SHIFT (0) /* Bits 0-9: ID Index */ -#define CAN_RFS_ID_MASK (0x03ff << CAN_RFS_ID_SHIFT) -#define CAN_RFS_BP (1 << 10) /* Bit 10: Received in AF Bypass mode */ - /* Bits 11-15: Reserved */ -#define CAN_RFS_DLC_SHIFT (16) /* Bits 16-19: Message Data Length Code (DLC) */ -#define CAN_RFS_DLC_MASK (15 << CAN_RFS_DLC_SHIFT) - /* Bits 20-29: Reserved */ -#define CAN_RFS_RTR (1 << 30) /* Bit 30: Message Remote Transmission Request */ -#define CAN_RFS_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ - -/* Received Identifier */ - -#define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ - /* Bits 11-31: Reserved */ -#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ - /* Bits 29-31: Reserved */ -/* Received data bytes 1-4 */ - -#define CAN_RDA_DATA1_SHIFT (0) /* Bits 0-7: If CANRFS >= 1 */ -#define CAN_RDA_DATA1_MASK (0x0ff << CAN_RDA_DATA1_SHIFT) -#define CAN_RDA_DATA2_SHIFT (8) /* Bits 8-15: If CANRFS >= 2 */ -#define CAN_RDA_DATA2_MASK (0x0ff << CAN_RDA_DATA2_SHIFT) -#define CAN_RDA_DATA3_SHIFT (16) /* Bits 16-23: If CANRFS >= 3 */ -#define CAN_RDA_DATA3_MASK (0x0ff << CAN_RDA_DATA3_SHIFT) -#define CAN_RDA_DATA4_SHIFT (24) /* Bits 24-31: If CANRFS >= 4 */ -#define CAN_RDA_DATA4_MASK (0x0ff << CAN_RDA_DATA4_SHIFT) - -/* Received data bytes 5-8 */ - -#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: If CANRFS >= 5 */ -#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) -#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: If CANRFS >= 6 */ -#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) -#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: If CANRFS >= 7 */ -#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) -#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: If CANRFS >= 8 */ -#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) - -/* Transmit frame info (Tx Buffer 1), Transmit frame info (Tx Buffer 2), and - * Transmit frame info (Tx Buffer 3) common bit field definitions - */ - -#define CAN_TFI_PRIO_SHIFT (0) /* Bits 0-7: TX buffer priority */ -#define CAN_TFI_PRIO_MASK (0xff << CAN_TFI_PRIO_SHIFT) - /* Bits 8-15: Reserved */ -#define CAN_TFI_DLC_SHIFT (16) /* Bits 16-19: TX Data Length Code */ -#define CAN_TFI_DLC_MASK (15 << CAN_TFI_DLC_SHIFT) - /* Bits 20-29: Reserved */ -#define CAN_TFI_RTR (1 << 30) /* Bit 30: TX RTR bit */ -#define CAN_TFI_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ - -/* Transmit Identifier (Tx Buffer 1), Transmit Identifier (Tx Buffer 2), and - * Transmit Identifier (Tx Buffer 3) common bit field definitions. - */ - -#define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ - /* Bits 11-31: Reserved */ -#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ - /* Bits 29-31: Reserved */ - -/* Transmit data bytes 1-4 (Tx Buffer 1), Transmit data bytes 1-4 (Tx Buffer 2), and - * Transmit data bytes 1-4 (Tx Buffer 3) common bit field definitions. - */ - -#define CAN_TDA_DATA1_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 1 */ -#define CAN_TDA_DATA1_MASK (0x0ff << CAN_TDA_DATA1_SHIFT) -#define CAN_TDA_DATA2_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 2 */ -#define CAN_TDA_DATA2_MASK (0x0ff << CAN_TDA_DATA2_SHIFT) -#define CAN_TDA_DATA3_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 3 */ -#define CAN_TDA_DATA3_MASK (0x0ff << CAN_TDA_DATA3_SHIFT) -#define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */ -#define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT) - -/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and - * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions. - */ - -#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 5 */ -#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) -#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 6 */ -#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) -#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 7 */ -#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) -#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 8 */ -#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_CAN_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h b/arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h deleted file mode 100644 index d202cb73175..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h +++ /dev/null @@ -1,186 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_EEPROM_EECMD_OFFSET 0x0080 /* Command register */ -#define LPC17_EEPROM_EEADDR_OFFSET 0x0084 /* Address register */ -#define LPC17_EEPROM_EEWDATA_OFFSET 0x0088 /* Write Data register */ -#define LPC17_EEPROM_EERDATA_OFFSET 0x008c /* Read Data register */ -#define LPC17_EEPROM_EEWSTATE_OFFSET 0x0090 /* Wait state register */ -#define LPC17_EEPROM_EECLKDIV_OFFSET 0x0094 /* Clock divider register */ -#define LPC17_EEPROM_EEPWRDWN_OFFSET 0x0098 /* Power down register */ - -#define LPC17_EEPROM_INTSTAT_OFFSET 0x0fe0 /* Interrupt status */ -#define LPC17_EEPROM_INTEN_OFFSET 0x0fe4 /* Interrupt enable */ -#define LPC17_EEPROM_INTSTATCLR_OFFSET 0x0fe8 /* Interrupt status clear */ -#define LPC17_EEPROM_INTENCLR_OFFSET 0x0fd8 /* Interrupt enable clear */ -#define LPC17_EEPROM_INTENSET_OFFSET 0x0fdc /* Interrupt enable set */ -#define LPC17_EEPROM_INTSTATSET_OFFSET 0x0fec /* Interrupt status set */ - -#define LPC17_EEPROM_EECMD (LPC17_EEPROM_BASE+LPC17_EEPROM_EECMD_OFFSET) -#define LPC17_EEPROM_EEADDR (LPC17_EEPROM_BASE+LPC17_EEPROM_EEADDR_OFFSET) -#define LPC17_EEPROM_EEWDATA (LPC17_EEPROM_BASE+LPC17_EEPROM_EEWDATA_OFFSET) -#define LPC17_EEPROM_EERDATA (LPC17_EEPROM_BASE+LPC17_EEPROM_EERDATA_OFFSET) -#define LPC17_EEPROM_EEWSTATE (LPC17_EEPROM_BASE+LPC17_EEPROM_EEWSTATE_OFFSET) -#define LPC17_EEPROM_EECLKDIV (LPC17_EEPROM_BASE+LPC17_EEPROM_EECLKDIV_OFFSET) -#define LPC17_EEPROM_EEPWRDWN (LPC17_EEPROM_BASE+LPC17_EEPROM_EEPWRDWN_OFFSET) - -#define LPC17_EEPROM_INTSTAT (LPC17_EEPROM_BASE+LPC17_EEPROM_INTSTAT_OFFSET) -#define LPC17_EEPROM_INTEN (LPC17_EEPROM_BASE+LPC17_EEPROM_INTEN_OFFSET) -#define LPC17_EEPROM_INTSTATCLR (LPC17_EEPROM_BASE+LPC17_EEPROM_INTSTATCLR_OFFSET) -#define LPC17_EEPROM_INTENCLR (LPC17_EEPROM_BASE+LPC17_EEPROM_INTENCLR_OFFSET) -#define LPC17_EEPROM_INTENSET (LPC17_EEPROM_BASE+LPC17_EEPROM_INTENSET_OFFSET) -#define LPC17_EEPROM_INTSTATSET (LPC17_EEPROM_BASE+LPC17_EEPROM_INTSTATSET_OFFSET) - -/* EECMD - EEPROM Command Register */ - -#define EEPROM_CMD_SHIFT (0) /* Bit 0-2: Command */ -#define EEPROM_CMD_MASK (7 << EEPROM_CMD_SHIFT) -# define EECMD_READ8 (0) /* 000: 8bit read */ -# define EECMD_READ16 (1) /* 001: 16bit read */ -# define EECMD_READ32 (2) /* 010: 32bit read */ -# define EECMD_WRITE8 (3) /* 011: 8bit write */ -# define EECMD_WRITE16 (4) /* 100: 16bit write */ -# define EECMD_WRITE32 (5) /* 101: 32bit write */ -# define EEMCD_ERASE (6) /* 110: erase/program page */ - /* 111: Reserved */ -#define EEPROM_RDPREFETCH (1 << 3) /* Bit 3: Read data prefetch bit */ - /* Bits 4-31: Reserved */ -/* EEADDR - EEPROM Address Register */ - -#define EEPROM_ADDR_SHIFT (0) /* Bits 0-11: Address */ -#define EEPROM_ADDR_MASK (0x7ff << EEPROM_EEADDR_ADDR_SHIFT) - /* Bits 12-31: Reserved */ -/* EEPROM Read/Write Data Registers */ -/* R/W registers has no bitfields, data read/write - * must conforms to the expected sizes - */ - -/* EEWSTATE - EEPROM Wait State Register */ - -#define EEPROM_WSTATE_PHASE3_SHIFT (0) /* Bits 0-7: Wait states 3 (minus 1 encoded) */ -#define EEPROM_WSTATE_PHASE3_MASK (0xff << EEWSTATE_PHASE3_SHIFT) -#define EEPROM_WSTATE_PHASE2_SHIFT (8) /* Bits 8-15: Wait states 2 (minus 1 encoded) */ -#define EEPROM_WSTATE_PHASE2_MASK (0xff << EEWSTATE_PHASE2_SHIFT) -#define EEPROM_WSTATE_PHASE1_SHIFT (16) /* Bits 16-23: Wait states 1 (minus 1 encoded) */ -#define EEPROM_WSTATE_PHASE1_MASK (0xff << EEWSTATE_PHASE1_SHIFT) - /* Bits 24-31: Reserved */ - -/* EECLKDIV - EEPROM Clock Divider Register */ - -#define EEPROM_CLKDIV_SHIFT (0) /* Bits 0-15: Division factor (minus 1 encoded) */ -#define EEPROM_CLKDIV_MASK (0xffff << EECLKDIV_CLKDIV_SHIFT) - /* Bits 16-31: Reserved */ - -/* EEPWRDWN - EEPROM Power Down Register */ - -#define EEPROM_PWRDWN (1) /* Bit 0: Power down mode bit */ - /* Bits 1-31: Reserved */ - -/* EEPROM Interrupt Registers ******************************************/ - -/* INTEN - Interrupt Enable Register */ - - /* Bits 0-25: Reserved */ -#define EEPROM_INTEN_RW_DONE (1 << 26) /* Bit 26: Read/Write finished interrupt bit */ - /* Bit 27: Reserved */ -#define EEPROM_INTEN_PROG_DONE (1 << 28) /* Bit 28: Program finished interrupt bit */ - /* Bits 29-31: Reserved */ - -/* INTENCLR - Interrupt Enable Clear Register */ - /* Bits 0-25: Reserved */ -#define EEPROM_INTENCLR_RWCLR_EN (1 << 26) /* Bit 26: Clear R/W interrupt enable bit */ - /* Bits27: Reserved */ -#define EEPROM_INTENCLR_PROG1CLR_EN (1 << 28) /* Bit 28: Clear program interrupt bit */ - /* Bits 29-31: Reserved */ - -/* INTENSET - Interrupt Enable Set Register */ - /* Bits 0-25: Reserved */ -#define EEPROM_INTENSET_RWSET_EN (1 << 26) /* Bit 26: Set Read/Write finished interrupt bit */ - /* Bit 27: Reserved */ -#define EEPROM_INTENSET_PROG1SET_EN (1 << 28) /* Bit 28: Set program interrupt bit */ - /* Bits 29-31: Reserved */ - -/* INTSTAT - Interrupt Status Register */ - /* Bits 0-25: Reserved */ -#define EEPROM_INTSTAT_RW_END (1 << 26) /* Bit 26: Read/Write done status bit */ - /* Bit 27: Reserved */ -#define EEPROM_INTSTAT_PROG1_END (1 << 28) /* Bit 28: Program done status bit */ - /* Bits 29-31: Reserved */ - -/* INTSTATCLR - Interrupt Status Clear Register */ - /* Bits 0-25: Reserved */ -#define EEPROM_INTSTATCLR_RW_CLR (1 << 26) /* Bit 26: Set Read/Write finished interrupt bit */ - /* Bit 27: Reserved */ -#define EEPROM_INTSTATCLR_PROG_1CLR (1 << 28) /* Bit 28: Set program interrupt bit */ - /* Bits 29-31: Reserved */ - -/* INTSTATSET - Interrupt Status Set Register */ - /* Bits 0-25: Reserved */ -#define EEPROM_INTSTATSET_RW_SET (1 << 26) /* Bit 26: Read/Write done status bit */ - /* Bit 27: Reserved */ -#define EEPROM_INTSTATSET_PROG1_SET (1 << 28) /* Bit 28: Program done status bit */ - /* Bits 29-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_emc.h b/arch/arm/src/lpc17xx/hardware/lpc17_emc.h deleted file mode 100644 index 11e30a0cf4b..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_emc.h +++ /dev/null @@ -1,350 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/lpc17xx/hardware/lpc17_emc - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ -/* Register Offsets */ - -#define LPC17_EMC_CONTROL_OFFSET 0x0000 /* EMC Control register */ -#define LPC17_EMC_STATUS_OFFSET 0x0004 /* EMC Status register */ -#define LPC17_EMC_CONFIG_OFFSET 0x0008 /* EMC Configuration register */ -#define LPC17_EMC_DYNAMICCONTROL_OFFSET 0x0020 /* Dynamic Memory Control register */ -#define LPC17_EMC_DYNAMICREFRESH_OFFSET 0x0024 /* Dynamic Memory Refresh Timer register */ -#define LPC17_EMC_DYNAMICREADCONFIG_OFFSET 0x0028 /* Dynamic Memory Read Configuration register */ -#define LPC17_EMC_DYNAMICRP_OFFSET 0x0030 /* Dynamic Memory Precharge Command Period register */ -#define LPC17_EMC_DYNAMICRAS_OFFSET 0x0034 /* Dynamic Memory Active to Precharge Command Period register */ -#define LPC17_EMC_DYNAMICSREX_OFFSET 0x0038 /* Dynamic Memory Self-refresh Exit Time register */ -#define LPC17_EMC_DYNAMICAPR_OFFSET 0x003c /* Dynamic Memory Last Data Out to Active Time register */ -#define LPC17_EMC_DYNAMICDAL_OFFSET 0x0040 /* Dynamic Memory Data-in to Active Command Time register */ -#define LPC17_EMC_DYNAMICWR_OFFSET 0x0044 /* Dynamic Memory Write Recovery Time register */ -#define LPC17_EMC_DYNAMICRC_OFFSET 0x0048 /* Dynamic Memory Active to Active Command Period register */ -#define LPC17_EMC_DYNAMICRFC_OFFSET 0x004c /* Dynamic Memory Auto-refresh Period register */ -#define LPC17_EMC_DYNAMICXSR_OFFSET 0x0050 /* Dynamic Memory Exit Self-refresh register */ -#define LPC17_EMC_DYNAMICRRD_OFFSET 0x0054 /* Dynamic Memory Active Bank A to Active Bank B Time register */ -#define LPC17_EMC_DYNAMICMRD_OFFSET 0x0058 /* Dynamic Memory Load Mode register to Active Command Time */ -#define LPC17_EMC_STATICEXTENDEDWAIT_OFFSET 0x0080 /* Static Memory Extended Wait register */ - -#define LPC17_EMC_DYNAMICCONFIG0_OFFSET 0x0100 /* Dynamic Memory Configuration register 0 */ -#define LPC17_EMC_DYNAMICRASCAS0_OFFSET 0x0104 /* Dynamic Memory RAS & CAS Delay register 0 */ - -#define LPC17_EMC_DYNAMICCONFIG1_OFFSET 0x0120 /* Dynamic Memory Configuration register 1 */ -#define LPC17_EMC_DYNAMICRASCAS1_OFFSET 0x0124 /* Dynamic Memory RAS & CAS Delay register 1 */ - -#define LPC17_EMC_DYNAMICCONFIG2_OFFSET 0x0140 /* Dynamic Memory Configuration register 2 */ -#define LPC17_EMC_DYNAMICRASCAS2_OFFSET 0x0144 /* Dynamic Memory RAS & CAS Delay register 2 */ - -#define LPC17_EMC_DYNAMICCONFIG3_OFFSET 0x0160 /* Dynamic Memory Configuration register 3 */ -#define LPC17_EMC_DYNAMICRASCAS3_OFFSET 0x0164 /* Dynamic Memory RAS & CAS Delay register 3 */ - -#define LPC17_EMC_STATICCONFIG0_OFFSET 0x0200 /* Static Memory Configuration register 0 */ -#define LPC17_EMC_STATICWAITWEN0_OFFSET 0x0204 /* Static Memory Write Enable Delay register 0 */ -#define LPC17_EMC_STATICWAITOEN0_OFFSET 0x0208 /* Static Memory Output Enable Delay registers 0 */ -#define LPC17_EMC_STATICWAITRD0_OFFSET 0x020c /* Static Memory Read Delay register 0 */ -#define LPC17_EMC_STATICWAITPAGE0_OFFSET 0x0210 /* Static Memory Page Mode Read Delay register 0*/ -#define LPC17_EMC_STATICWAITWR0_OFFSET 0x0214 /* Static Memory Write Delay register 0 */ -#define LPC17_EMC_STATICWAITTURN0_OFFSET 0x0218 /* Static Memory Turn Round Delay register 0 */ - -#define LPC17_EMC_STATICCONFIG1_OFFSET 0x0220 /* Static Memory Configuration register 1 */ -#define LPC17_EMC_STATICWAITWEN1_OFFSET 0x0224 /* Static Memory Write Enable Delay register 1 */ -#define LPC17_EMC_STATICWAITOEN1_OFFSET 0x0228 /* Static Memory Output Enable Delay register 1 */ -#define LPC17_EMC_STATICWAITRD1_OFFSET 0x022c /* Static Memory Read Delay register 1 */ -#define LPC17_EMC_STATICWAITPAGE1_OFFSET 0x0230 /* Static Memory Page Mode Read Delay register 1 */ -#define LPC17_EMC_STATICWAITWR1_OFFSET 0x0234 /* Static Memory Write Delay register 1 */ -#define LPC17_EMC_STATICWAITTURN1_OFFSET 0x0238 /* Static Memory Turn Round Delay register 1 */ - -#define LPC17_EMC_STATICCONFIG2_OFFSET 0x0240 /* Static Memory Configuration register 2 */ -#define LPC17_EMC_STATICWAITWEN2_OFFSET 0x0244 /* Static Memory Write Enable Delay register 2 */ -#define LPC17_EMC_STATICWAITOEN2_OFFSET 0x0248 /* Static Memory Output Enable Delay register 2 */ -#define LPC17_EMC_STATICWAITRD2_OFFSET 0x024c /* Static Memory Read Delay register 2 */ -#define LPC17_EMC_STATICWAITPAGE2_OFFSET 0x0250 /* Static Memory Page Mode Read Delay registers 3 */ -#define LPC17_EMC_STATICWAITWR2_OFFSET 0x0254 /* Static Memory Write Delay register 2 */ -#define LPC17_EMC_EMCSTATICWAITTURN2_OFFSET 0x0258 /* Static Memory Turn Round Delay register 2 */ - -#define LPC17_EMC_STATICCONFIG3_OFFSET 0x0260 /* Static Memory Configuration register 3 */ -#define LPC17_EMC_STATICWAITWEN3_OFFSET 0x0264 /* Static Memory Write Enable Delay register 3 */ -#define LPC17_EMC_STATICWAITOEN3_OFFSET 0x0268 /* Static Memory Output Enable Delay register 3 */ -#define LPC17_EMC_STATICWAITRD3_OFFSET 0x026c /* Static Memory Read Delay register 3 */ -#define LPC17_EMC_STATICWAITPAGE3_OFFSET 0x0270 /* Static Memory Page Mode Read Delay register 4 */ -#define LPC17_EMC_STATICWAITWR3_OFFSET 0x0274 /* Static Memory Write Delay register 3 */ -#define LPC17_EMC_STATICWAITTURN3_OFFSET 0x0278 /* Static Memory Turn Round Delay register 3 */ - -/* Register Addresses */ - -#define LPC17_EMC_CONTROL (LPC17_EMC_BASE+LPC17_EMC_CONTROL_OFFSET) -#define LPC17_EMC_STATUS (LPC17_EMC_BASE+LPC17_EMC_STATUS_OFFSET) -#define LPC17_EMC_CONFIG (LPC17_EMC_BASE+LPC17_EMC_CONFIG_OFFSET) -#define LPC17_EMC_DYNAMICCONTROL (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONTROL_OFFSET) -#define LPC17_EMC_DYNAMICREFRESH (LPC17_EMC_BASE+LPC17_EMC_DYNAMICREFRESH_OFFSET) -#define LPC17_EMC_DYNAMICREADCONFIG (LPC17_EMC_BASE+LPC17_EMC_DYNAMICREADCONFIG_OFFSET) -#define LPC17_EMC_DYNAMICRP (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRP_OFFSET) -#define LPC17_EMC_DYNAMICRAS (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRAS_OFFSET) -#define LPC17_EMC_DYNAMICSREX (LPC17_EMC_BASE+LPC17_EMC_DYNAMICSREX_OFFSET) -#define LPC17_EMC_DYNAMICAPR (LPC17_EMC_BASE+LPC17_EMC_DYNAMICAPR_OFFSET) -#define LPC17_EMC_DYNAMICDAL (LPC17_EMC_BASE+LPC17_EMC_DYNAMICDAL_OFFSET) -#define LPC17_EMC_DYNAMICWR (LPC17_EMC_BASE+LPC17_EMC_DYNAMICWR_OFFSET) -#define LPC17_EMC_DYNAMICRC (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRC_OFFSET) -#define LPC17_EMC_DYNAMICRFC (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRFC_OFFSET) -#define LPC17_EMC_DYNAMICXSR (LPC17_EMC_BASE+LPC17_EMC_DYNAMICXSR_OFFSET) -#define LPC17_EMC_DYNAMICRRD (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRRD_OFFSET) -#define LPC17_EMC_DYNAMICMRD (LPC17_EMC_BASE+LPC17_EMC_DYNAMICMRD_OFFSET) -#define LPC17_EMC_STATICEXTENDEDWAIT (LPC17_EMC_BASE+LPC17_EMC_STATICEXTENDEDWAIT_OFFSET) - -#define LPC17_EMC_DYNAMICCONFIG0 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG0_OFFSET) -#define LPC17_EMC_DYNAMICRASCAS0 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS0_OFFSET) - -#define LPC17_EMC_DYNAMICCONFIG1 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG1_OFFSET) -#define LPC17_EMC_DYNAMICRASCAS1 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS1_OFFSET) - -#define LPC17_EMC_DYNAMICCONFIG2 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG2_OFFSET) -#define LPC17_EMC_DYNAMICRASCAS2 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS2_OFFSET) - -#define LPC17_EMC_DYNAMICCONFIG3 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG3_OFFSET) -#define LPC17_EMC_DYNAMICRASCAS3 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS3_OFFSET) - -#define LPC17_EMC_STATICCONFIG0 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG0_OFFSET) -#define LPC17_EMC_STATICWAITWEN0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN0_OFFSET) -#define LPC17_EMC_STATICWAITOEN0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN0_OFFSET) -#define LPC17_EMC_STATICWAITRD0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD0_OFFSET) -#define LPC17_EMC_STATICWAITPAGE0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE0_OFFSET) -#define LPC17_EMC_STATICWAITWR0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR0_OFFSET) -#define LPC17_EMC_STATICWAITTURN0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITTURN0_OFFSET) - -#define LPC17_EMC_STATICCONFIG1 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG1_OFFSET) -#define LPC17_EMC_STATICWAITWEN1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN1_OFFSET) -#define LPC17_EMC_STATICWAITOEN1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN1_OFFSET) -#define LPC17_EMC_STATICWAITRD (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD1_OFFSET) -#define LPC17_EMC_STATICWAITPAGE1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE1_OFFSET) -#define LPC17_EMC_STATICWAITWR1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR1_OFFSET) -#define LPC17_EMC_STATICWAITTURN1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITTURN1_OFFSET) - -#define LPC17_EMC_STATICCONFIG2 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG2_OFFSET) -#define LPC17_EMC_STATICWAITWEN2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN2_OFFSET) -#define LPC17_EMC_STATICWAITOEN2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN2_OFFSET) -#define LPC17_EMC_STATICWAITRD2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD2_OFFSET) -#define LPC17_EMC_STATICWAITPAGE2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE2_OFFSET) -#define LPC17_EMC_STATICWAITWR2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR2_OFFSET) -#define LPC17_EMC_EMCSTATICWAITTURN2 (LPC17_EMC_BASE+LPC17_EMC_EMCSTATICWAITTURN2_OFFSET) - -#define LPC17_EMC_STATICCONFIG3 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG3_OFFSET) -#define LPC17_EMC_STATICWAITWEN3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN3_OFFSET) -#define LPC17_EMC_STATICWAITOEN3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN3_OFFSET) -#define LPC17_EMC_STATICWAITRD3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD3_OFFSET) -#define LPC17_EMC_STATICWAITPAGE3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE3_OFFSET) -#define LPC17_EMC_STATICWAITWR3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR3_OFFSET) -#define LPC17_EMC_STATICWAITTURN3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITTURN3_OFFSET) - -/* Register Bitfield Definitions */ - -/* EMC Control register */ - -#define EMC_CONTROL_E (1 << 0) /* Bit 0: EMC Enable */ -#define EMC_CONTROL_M (1 << 1) /* Bit 1: Address mirror */ -#define EMC_CONTROL_L (1 << 2) /* Bit 2: Low-power mode */ - -/* EMC Status register */ - -#define EMC_STATUS_B (1 << 0) /* Bit 0: Busy */ -#define EMC_STATUS_S (1 << 1) /* Bit 1: Write buffer status */ -#define EMC_STATUS_SA (1 << 2) /* Bit 2: Self-refresh acknowledge */ - -/* EMC Configuration register */ - -#define EMC_CONFIG_EM (1 << 0) /* Bit 0: Endian mode */ -#define EMC_CONFIG_CLKR (1 << 8) /* Bit 8: CCLK:CLKOUT ratio */ - -/* Dynamic Memory Control register */ - -#define EMC_DYNAMICCONTROL_CE (1 << 0) /* Bit 0: Dynamic memory clock enable */ -#define EMC_DYNAMICCONTROL_CS (1 << 1) /* Bit 1: Dynamic memory clock control */ -#define EMC_DYNAMICCONTROL_SR (1 << 2) /* Bit 2: Self-refresh request */ -#define EMC_DYNAMICCONTROL_MMC (1 << 5) /* Bit 5: Memory clock control */ -#define EMC_DYNAMICCONTROL_I_SHIFT (7) /* Bits 7-8: SDRAM initialization */ -#define EMC_DYNAMICCONTROL_I_MASK (3 << EMC_DYNAMICCONTROL_I_SHIFT) -# define EMC_DYNAMICCONTROL_I_NORMAL (0 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM NORMAL operation command */ -# define EMC_DYNAMICCONTROL_I_MODE (1 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM MODE command */ -# define EMC_DYNAMICCONTROL_I_PALL (2 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM PALL (precharge all) command */ -# define EMC_DYNAMICCONTROL_I_NOP (3 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM NOP (no operation) command) */ - -/* Dynamic Memory Refresh Timer register */ - -#define EMC_DYNAMICREFRESH_MASK (0x000007ff) /* Bits 0-10: REFRESH Refresh timer */ - -/* Dynamic Memory Read Configuration register */ - -#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0) /* Bits 0-1: Read data strategy */ -#define EMC_DYNAMICREADCONFIG_RD_MASK (3 << EMC_DYNAMICREADCONFIG_RD_SHIFT) -# define EMC_DYNAMICREADCONFIG_RD_CLKOUT (0 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Clock out delayed strategy */ -# define EMC_DYNAMICREADCONFIG_RD_CMD (1 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy */ -# define EMC_DYNAMICREADCONFIG_RD_CMD1 (2 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy + 1 cycle */ -# define EMC_DYNAMICREADCONFIG_RD_CMD2 (3 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy + 2 cycles */ - -/* Dynamic Memory Precharge Command Period register */ - -#define EMC_DYNAMICRP_TRP_MASK (0x0000000f) /* Bits 0-3: Precharge command period */ - -/* Dynamic Memory Active to Precharge Command Period register */ - -#define EMC_DYNAMICRAS_TRAS_MASK (0x0000000f) /* Bits 0-3: Active to precharge command period */ - -/* Dynamic Memory Self-refresh Exit Time register */ - -#define EMC_DYNAMICSREX_TSREX_MASK (0x0000000f) /* Bits 0-3: Self-refresh exit time */ - -/* Dynamic Memory Last Data Out to Active Time register */ - -#define EMC_DYNAMICAPR_TAPR_MASK (0x0000000f) /* Bits 0-3: Last-data-out to active command time */ - -/* Dynamic Memory Data-in to Active Command Time register */ - -#define EMC_DYNAMICDAL_TDAL_MASK (0x0000000f) /* Bits 0-3: Data-in to active command */ - -/* Dynamic Memory Write Recovery Time register */ - -#define EMC_DYNAMICWR_TWR_MASK (0x0000000f) /* Bits 0-3: Write recovery time */ - -/* Dynamic Memory Active to Active Command Period register */ - -#define EMC_DYNAMICRC_TRC_MASK (0x0000001f) /* Bits 0-4: Active to active command period */ - -/* Dynamic Memory Auto-refresh Period register */ - -#define EMC_DYNAMICRFC_TRFC_MASK (0x0000001f) /* Bits 0-4: Auto-refresh period and auto-refresh to active command period */ - -/* Dynamic Memory Exit Self-refresh register */ - -#define EMC_DYNAMICXSR_TXSR_MASK (0x0000001f) /* Bits 0-4: Exit self-refresh to active command time */ - -/* Dynamic Memory Active Bank A to Active Bank B Time register */ - -#define EMC_DYNAMICRRD_TRRD_MASK (0x0000000f) /* Bits 0-3: Active bank A to active bank B latency */ - -/* Dynamic Memory Load Mode register to Active Command Time */ - -#define EMC_DYNAMICMRD_TMRD_MASK (0x0000000f) /* Bits 0-3: Load mode register to active command time */ - -/* Static Memory Extended Wait register */ - -#define EMC_STATICEXTENDEDWAIT_MASK (0x000003ff) /* Bits 0-9: Extended wait time out */ - -/* Dynamic Memory Configuration registers (0-3) */ - -#define EMC_DYNAMICCONFIG_MD_SHIFT (3) /* Bits 3-4: Memory device */ -#define EMC_DYNAMICCONFIG_MD_MASK (3 << EMC_DYNAMICCONFIG_MD_SHIFT) -# define EMC_DYNAMICCONFIG_MD_SDRAM (0 << EMC_DYNAMICCONFIG_MD_SHIFT) /* SDRAM */ -# define EMC_DYNAMICCONFIG_MD_LOWPOWER (1 << EMC_DYNAMICCONFIG_MD_SHIFT) /* Low-power SDRAM */ -#define EMC_DYNAMICCONFIG_AM0_SHIFT (7) /* Bits 7-12: */ -#define EMC_DYNAMICCONFIG_AM0_MASK (63 << EMC_DYNAMICCONFIG_AM0_SHIFT) -# define EMC_DYNAMICCONFIG_AM0(n) ((n) << EMC_DYNAMICCONFIG_AM0_SHIFT) -#define EMC_DYNAMICCONFIG_AM1 (1 << 14) /* Bit 14: */ -#define EMC_DYNAMICCONFIG_B (1 << 19) /* Bit 19: Buffer enable */ -#define EMC_DYNAMICCONFIG_P (1 << 20) /* Bit 20: Write protect */ - -/* Dynamic Memory RAS & CAS Delay registers (0-3) */ - -#define EMC_DYNAMICRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency (active to read/write delay) */ -#define EMC_DYNAMICRASCAS_RAS_MASK (3 << EMC_DYNAMICRASCAS_RAS_SHIFT) -# define EMC_DYNAMICRASCAS_RAS_1CCLK (1 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* One CCLK cycle */ -# define EMC_DYNAMICRASCAS_RAS_2CCLK (2 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* Two CCLK cycles */ -# define EMC_DYNAMICRASCAS_RAS_3CCLK (3 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* Three CCLK cycles */ -#define EMC_DYNAMICRASCAS_CAS_SHIFT (8) /* Bits 8-9: CAS latency */ -#define EMC_DYNAMICRASCAS_CAS_MASK (3 << EMC_DYNAMICRASCAS_CAS_SHIFT) -# define EMC_DYNAMICRASCAS_CAS_1CCLK (1 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* One CCLK cycle */ -# define EMC_DYNAMICRASCAS_CAS_2CCLK (2 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* Two CCLK cycles */ -# define EMC_DYNAMICRASCAS_CAS_3CCLK (3 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* Three CCLK cycles */ - -/* Static Memory Configuration registers (0-3) */ - -#define EMC_STATICCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */ -#define EMC_STATICCONFIG_MW_MASK (3 << EMC_STATICCONFIG_MW_SHIFT) -# define EMC_STATICCONFIG_MW_8BIT (0 << EMC_STATICCONFIG_MW_SHIFT) -# define EMC_STATICCONFIG_MW_16BIT (1 << EMC_STATICCONFIG_MW_SHIFT) -# define EMC_STATICCONFIG_MW_32BIT (2 << EMC_STATICCONFIG_MW_SHIFT) -#define EMC_STATICCONFIG_PM (1 << 3) /* Bit 3: Page mode */ -#define EMC_STATICCONFIG_PC (1 << 6) /* Bit 6: Chip select polarity */ -#define EMC_STATICCONFIG_PB (1 << 7) /* Bit 7: Byte lane state */ -#define EMC_STATICCONFIG_EW (1 << 8) /* Bit 8: Extended wait */ -#define EMC_STATICCONFIG_B (1 << 19) /* Bit 19: Buffer enable */ -#define EMC_STATICCONFIG_P (1 << 20) /* Bit 20: Write protect */ - -/* Static Memory Write Enable Delay registers (0-3) */ - -#define EMC_STATICWAITWEN_MASK (0x0000000f) /* Bits 0-3: Wait write enable */ - -/* Static Memory Output Enable Delay registers (0-3) */ - -#define EMC_STATICWAITOEN_MASK (0x0000000f) /* Bits 0-3: Wait output enable */ - -/* Static Memory Read Delay registers (0-3) */ - -#define EMC_STATICWAITRD_MASK (0x0000001f) /* Bits 0-4: Exit self-refresh to active command time */ - -/* Static Memory Page Mode Read Delay registers (0-3) */ - -#define EMC_STATICWAITPAGE_MASK (0x0000001f) /* Bits 0-4: Asynchronous page mode read after the first read wait states */ - -/* Static Memory Write Delay registers (0-3) */ - -#define EMC_STATICWAITWR_MASK (0x0000001f) /* Bits 0-4: Write wait states */ - -/* Static Memory Turn Round Delay registers (0-3) */ - -#define EMC_STATICWAITTURN_MASK (0x0000000f) /* Bits 0-3: Bus turn-around cycles */ - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h b/arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h deleted file mode 100644 index f60e5530f8b..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h +++ /dev/null @@ -1,597 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_ETHERNET_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_ETHERNET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* MAC registers */ - -#define LPC17_ETH_MAC1_OFFSET 0x0000 /* MAC configuration register 1 */ -#define LPC17_ETH_MAC2_OFFSET 0x0004 /* MAC configuration register 2 */ -#define LPC17_ETH_IPGT_OFFSET 0x0008 /* Back-to-Back Inter-Packet-Gap register */ -#define LPC17_ETH_IPGR_OFFSET 0x000c /* Non Back-to-Back Inter-Packet-Gap register */ -#define LPC17_ETH_CLRT_OFFSET 0x0010 /* Collision window / Retry register */ -#define LPC17_ETH_MAXF_OFFSET 0x0014 /* Maximum Frame register */ -#define LPC17_ETH_SUPP_OFFSET 0x0018 /* PHY Support register */ -#define LPC17_ETH_TEST_OFFSET 0x001c /* Test register */ -#define LPC17_ETH_MCFG_OFFSET 0x0020 /* MII Mgmt Configuration register */ -#define LPC17_ETH_MCMD_OFFSET 0x0024 /* MII Mgmt Command register */ -#define LPC17_ETH_MADR_OFFSET 0x0028 /* MII Mgmt Address register */ -#define LPC17_ETH_MWTD_OFFSET 0x002c /* MII Mgmt Write Data register */ -#define LPC17_ETH_MRDD_OFFSET 0x0030 /* MII Mgmt Read Data register */ -#define LPC17_ETH_MIND_OFFSET 0x0034 /* MII Mgmt Indicators register */ -#define LPC17_ETH_SA0_OFFSET 0x0040 /* Station Address 0 register */ -#define LPC17_ETH_SA1_OFFSET 0x0044 /* Station Address 1 register */ -#define LPC17_ETH_SA2_OFFSET 0x0048 /* Station Address 2 register */ - -/* Control registers */ - -#define LPC17_ETH_CMD_OFFSET 0x0100 /* Command register */ -#define LPC17_ETH_STAT_OFFSET 0x0104 /* Status register */ -#define LPC17_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */ -#define LPC17_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */ -#define LPC17_ETH_RXDESCNO_OFFSET 0x0110 /* Receive number of descriptors register */ -#define LPC17_ETH_RXPRODIDX_OFFSET 0x0114 /* Receive produce index register */ -#define LPC17_ETH_RXCONSIDX_OFFSET 0x0118 /* Receive consume index register */ -#define LPC17_ETH_TXDESC_OFFSET 0x011c /* Transmit descriptor base address register */ -#define LPC17_ETH_TXSTAT_OFFSET 0x0120 /* Transmit status base address register */ -#define LPC17_ETH_TXDESCRNO_OFFSET 0x0124 /* Transmit number of descriptors register */ -#define LPC17_ETH_TXPRODIDX_OFFSET 0x0128 /* Transmit produce index register */ -#define LPC17_ETH_TXCONSIDX_OFFSET 0x012c /* Transmit consume index register */ -#define LPC17_ETH_TSV0_OFFSET 0x0158 /* Transmit status vector 0 register */ -#define LPC17_ETH_TSV1_OFFSET 0x015c /* Transmit status vector 1 register */ -#define LPC17_ETH_RSV_OFFSET 0x0160 /* Receive status vector register */ -#define LPC17_ETH_FCCNTR_OFFSET 0x0170 /* Flow control counter register */ -#define LPC17_ETH_FCSTAT_OFFSET 0x0174 /* Flow control status register */ - -/* Rx filter registers */ - -#define LPC17_ETH_RXFLCTRL_OFFSET 0x0200 /* Receive filter control register */ -#define LPC17_ETH_RXFLWOLST_OFFSET 0x0204 /* Receive filter WoL status register */ -#define LPC17_ETH_RXFLWOLCLR_OFFSET 0x0208 /* Receive filter WoL clear register */ -#define LPC17_ETH_HASHFLL_OFFSET 0x0210 /* Hash filter table LSBs register */ -#define LPC17_ETH_HASHFLH_OFFSET 0x0214 /* Hash filter table MSBs register */ - -/* Module control registers */ - -#define LPC17_ETH_INTST_OFFSET 0x0fe0 /* Interrupt status register */ -#define LPC17_ETH_INTEN_OFFSET 0x0fe4 /* Interrupt enable register */ -#define LPC17_ETH_INTCLR_OFFSET 0x0fe8 /* Interrupt clear register */ -#define LPC17_ETH_INTSET_OFFSET 0x0fec /* Interrupt set register */ -#define LPC17_ETH_PWRDOWN_OFFSET 0x0ff4 /* Power-down register */ - -/* Register addresses ***************************************************************/ -/* MAC registers */ - -#define LPC17_ETH_MAC1 (LPC17_ETH_BASE+LPC17_ETH_MAC1_OFFSET) -#define LPC17_ETH_MAC2 (LPC17_ETH_BASE+LPC17_ETH_MAC2_OFFSET) -#define LPC17_ETH_IPGT (LPC17_ETH_BASE+LPC17_ETH_IPGT_OFFSET) -#define LPC17_ETH_IPGR (LPC17_ETH_BASE+LPC17_ETH_IPGR_OFFSET) -#define LPC17_ETH_CLRT (LPC17_ETH_BASE+LPC17_ETH_CLRT_OFFSET) -#define LPC17_ETH_MAXF (LPC17_ETH_BASE+LPC17_ETH_MAXF_OFFSET) -#define LPC17_ETH_SUPP (LPC17_ETH_BASE+LPC17_ETH_SUPP_OFFSET) -#define LPC17_ETH_TEST (LPC17_ETH_BASE+LPC17_ETH_TEST_OFFSET) -#define LPC17_ETH_MCFG (LPC17_ETH_BASE+LPC17_ETH_MCFG_OFFSET) -#define LPC17_ETH_MCMD (LPC17_ETH_BASE+LPC17_ETH_MCMD_OFFSET) -#define LPC17_ETH_MADR (LPC17_ETH_BASE+LPC17_ETH_MADR_OFFSET) -#define LPC17_ETH_MWTD (LPC17_ETH_BASE+LPC17_ETH_MWTD_OFFSET) -#define LPC17_ETH_MRDD (LPC17_ETH_BASE+LPC17_ETH_MRDD_OFFSET) -#define LPC17_ETH_MIND (LPC17_ETH_BASE+LPC17_ETH_MIND_OFFSET) -#define LPC17_ETH_SA0 (LPC17_ETH_BASE+LPC17_ETH_SA0_OFFSET) -#define LPC17_ETH_SA1 (LPC17_ETH_BASE+LPC17_ETH_SA1_OFFSET) -#define LPC17_ETH_SA2 (LPC17_ETH_BASE+LPC17_ETH_SA2_OFFSET) - -/* Control registers */ - -#define LPC17_ETH_CMD (LPC17_ETH_BASE+LPC17_ETH_CMD_OFFSET) -#define LPC17_ETH_STAT (LPC17_ETH_BASE+LPC17_ETH_STAT_OFFSET) -#define LPC17_ETH_RXDESC (LPC17_ETH_BASE+LPC17_ETH_RXDESC_OFFSET) -#define LPC17_ETH_RXSTAT (LPC17_ETH_BASE+LPC17_ETH_RXSTAT_OFFSET) -#define LPC17_ETH_RXDESCNO (LPC17_ETH_BASE+LPC17_ETH_RXDESCNO_OFFSET) -#define LPC17_ETH_RXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_RXPRODIDX_OFFSET) -#define LPC17_ETH_RXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_RXCONSIDX_OFFSET) -#define LPC17_ETH_TXDESC (LPC17_ETH_BASE+LPC17_ETH_TXDESC_OFFSET) -#define LPC17_ETH_TXSTAT (LPC17_ETH_BASE+LPC17_ETH_TXSTAT_OFFSET) -#define LPC17_ETH_TXDESCRNO (LPC17_ETH_BASE+LPC17_ETH_TXDESCRNO_OFFSET) -#define LPC17_ETH_TXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_TXPRODIDX_OFFSET) -#define LPC17_ETH_TXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_TXCONSIDX_OFFSET) -#define LPC17_ETH_TSV0 (LPC17_ETH_BASE+LPC17_ETH_TSV0_OFFSET) -#define LPC17_ETH_TSV1 (LPC17_ETH_BASE+LPC17_ETH_TSV1_OFFSET) -#define LPC17_ETH_RSV (LPC17_ETH_BASE+LPC17_ETH_RSV_OFFSET) -#define LPC17_ETH_FCCNTR (LPC17_ETH_BASE+LPC17_ETH_FCCNTR_OFFSET) -#define LPC17_ETH_FCSTAT (LPC17_ETH_BASE+LPC17_ETH_FCSTAT_OFFSET) - -/* Rx filter registers */ - -#define LPC17_ETH_RXFLCTRL (LPC17_ETH_BASE+LPC17_ETH_RXFLCTRL_OFFSET) -#define LPC17_ETH_RXFLWOLST (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLST_OFFSET) -#define LPC17_ETH_RXFLWOLCLR (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLCLR_OFFSET) -#define LPC17_ETH_HASHFLL (LPC17_ETH_BASE+LPC17_ETH_HASHFLL_OFFSET) -#define LPC17_ETH_HASHFLH (LPC17_ETH_BASE+LPC17_ETH_HASHFLH_OFFSET) - -/* Module control registers */ - -#define LPC17_ETH_INTST (LPC17_ETH_BASE+LPC17_ETH_INTST_OFFSET) -#define LPC17_ETH_INTEN (LPC17_ETH_BASE+LPC17_ETH_INTEN_OFFSET) -#define LPC17_ETH_INTCLR (LPC17_ETH_BASE+LPC17_ETH_INTCLR_OFFSET) -#define LPC17_ETH_INTSET (LPC17_ETH_BASE+LPC17_ETH_INTSET_OFFSET) -#define LPC17_ETH_PWRDOWN (LPC17_ETH_BASE+LPC17_ETH_PWRDOWN_OFFSET) - -/* Register bit definitions *********************************************************/ -/* MAC registers */ -/* MAC configuration register 1 (MAC1) */ - -#define ETH_MAC1_RE (1 << 0) /* Bit 0: Receive enable */ -#define ETH_MAC1_PARF (1 << 1) /* Bit 1: Passall all receive frames */ -#define ETH_MAC1_RFC (1 << 2) /* Bit 2: RX flow control */ -#define ETH_MAC1_TFC (1 << 3) /* Bit 3: TX flow control */ -#define ETH_MAC1_LPBK (1 << 4) /* Bit 4: Loopback */ - /* Bits 5-7: Reserved */ -#define ETH_MAC1_TXRST (1 << 8) /* Bit 8: Reset TX */ -#define ETH_MAC1_MCSTXRST (1 << 9) /* Bit 9: Reset MCS/TX */ -#define ETH_MAC1_RXRST (1 << 10) /* Bit 10: Reset RX */ -#define ETH_MAC1_MCSRXRST (1 << 11) /* Bit 11: Reset MCS/RX */ - /* Bits 12-13: Reserved */ -#define ETH_MAC1_SIMRST (1 << 14) /* Bit 14: Simulation reset */ -#define ETH_MAC1_SOFTRST (1 << 15) /* Bit 15: Soft reset */ - /* Bits 16-31: Reserved */ -/* MAC configuration register 2 (MAC2) */ - -#define ETH_MAC2_FD (1 << 0) /* Bit 0: Full duplex */ -#define ETH_MAC2_FLC (1 << 1) /* Bit 1: Frame length checking */ -#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge frame enable */ -#define ETH_MAC2_DCRC (1 << 3) /* Bit 3: Delayed CRC */ -#define ETH_MAC2_CRCEN (1 << 4) /* Bit 4: CRC enable */ -#define ETH_MAC2_PADCRCEN (1 << 5) /* Bit 5: Pad/CRC enable */ -#define ETH_MAC2_VLANPADEN (1 << 6) /* Bit 6: VLAN pad enable */ -#define ETH_MAC2_AUTOPADEN (1 << 7) /* Bit 7: Auto detect pad enable */ -#define ETH_MAC2_PPE (1 << 8) /* Bit 8: Pure preamble enforcement */ -#define ETH_MAC2_LPE (1 << 9) /* Bit 9: Long preamble enforcement */ - /* Bits 10-11: Reserved */ -#define ETH_MAC2_NBKOFF (1 << 12) /* Bit 12: No backoff */ -#define ETH_MAC2_BPNBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */ -#define ETH_MAC2_EXDEF (1 << 14) /* Bit 14: Excess defer */ - /* Bits 15-31: Reserved */ -/* Back-to-Back Inter-Packet-Gap register (IPGT) */ - -#define ETH_IPGT_SHIFT (0) /* Bits 0-6 */ -#define ETH_IPGT_MASK (0x7f << ETH_IPGT_SHIFT) - /* Bits 7-31: Reserved */ -/* Non Back-to-Back Inter-Packet-Gap register (IPGR) */ - -#define ETH_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */ -#define ETH_IPGR_GAP2_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) - /* Bit 7: Reserved */ -#define ETH_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */ -#define ETH_IPGR_GAP1_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) - /* Bits 15-31: Reserved */ -/* Collision window / Retry register (CLRT) */ - -#define ETH_CLRT_RMAX_SHIFT (0) /* Bits 0-3: Retransmission maximum */ -#define ETH_CLRT_RMAX_MASK (15 << ETH_CLRT_RMAX_SHIFT) - /* Bits 4-7: Reserved */ -#define ETH_CLRT_COLWIN_SHIFT (8) /* Bits 8-13: Collision window */ -#define ETH_CLRT_COLWIN_MASK (0x3f << ETH_CLRT_COLWIN_SHIFT) - /* Bits 14-31: Reserved */ -/* Maximum Frame register (MAXF) */ - -#define ETH_MAXF_SHIFT (0) /* Bits 0-15 */ -#define ETH_MAXF_MASK (0xffff << ETH_MAXF_SHIFT) - /* Bits 16-31: Reserved */ -/* PHY Support register (SUPP) */ - /* Bits 0-7: Reserved */ -#define ETH_SUPP_SPEED (1 << 8) /* Bit 8: 0=10Bps 1=100Bps */ - /* Bits 9-31: Reserved */ -/* Test register (TEST) */ - -#define ETH_TEST_SPQ (1 << 0) /* Bit 0: Shortcut pause quanta */ -#define ETH_TEST_TP (1 << 1) /* Bit 1: Test pause */ -#define ETH_TEST_TBP (1 << 2) /* Bit 2: Test packpressure */ - /* Bits 3-31: Reserved */ -/* MII Mgmt Configuration register (MCFG) */ - -#define ETH_MCFG_SCANINC (1 << 0) /* Bit 0: Scan increment */ -#define ETH_MCFG_SUPPRE (1 << 1) /* Bit 1: Suppress preamble */ -#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5: Clock select */ -#define ETH_MCFG_CLKSEL_MASK (15 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV4 (0 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV6 (2 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV8 (3 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV10 (4 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV14 (5 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV20 (6 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV28 (7 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV36 (8 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV40 (9 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV44 (10 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV48 (11 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV52 (12 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV56 (13 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV60 (14 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV64 (15 << ETH_MCFG_CLKSEL_SHIFT) - /* Bits 6-14: Reserved */ -#define ETH_MCFG_MIIRST (1 << 15) /* Bit 15: Reset MII mgmt */ - /* Bits 16-31: Reserved */ -/* MII Mgmt Command register (MCMD) */ - -#define ETH_MCMD_READ (1 << 0) /* Bit 0: Single read cycle */ -#define ETH_MCMD_SCAN (1 << 1) /* Bit 1: Continuous read cycles */ - /* Bits 2-31: Reserved */ -#define ETH_MCMD_WRITE (0) - -/* MII Mgmt Address register (MADR) */ - -#define ETH_MADR_REGADDR_SHIFT (0) /* Bits 0-4: Register address */ -#define ETH_MADR_REGADDR_MASK (31 << ETH_MADR_REGADDR_SHIFT) - /* Bits 7-5: Reserved */ -#define ETH_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */ -#define ETH_MADR_PHYADDR_MASK (31 << ETH_MADR_PHYADDR_SHIFT) - /* Bits 13-31: Reserved */ -/* MII Mgmt Write Data register (MWTD) */ - -#define ETH_MWTD_SHIFT (0) /* Bits 0-15 */ -#define ETH_MWTD_MASK (0xffff << ETH_MWTD_SHIFT) - /* Bits 16-31: Reserved */ -/* MII Mgmt Read Data register (MRDD) */ - -#define ETH_MRDD_SHIFT (0) /* Bits 0-15 */ -#define ETH_MRDD_MASK (0xffff << ETH_MRDD_SHIFT) - /* Bits 16-31: Reserved */ -/* MII Mgmt Indicators register (MIND) */ - -#define ETH_MIND_BUSY (1 << 0) /* Bit 0: Busy */ -#define ETH_MIND_SCANNING (1 << 1) /* Bit 1: Scanning */ -#define ETH_MIND_NVALID (1 << 2) /* Bit 2: Not valid */ -#define ETH_MIND_MIIFAIL (1 << 3) /* Bit 3: MII link fail */ - /* Bits 4-31: Reserved */ -/* Station Address 0 register (SA0) */ - -#define ETH_SA0_OCTET2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */ -#define ETH_SA0_OCTET2_MASK (0xff << ETH_SA0_OCTET2_SHIFT) -#define ETH_SA0_OCTET1_SHIFT (8) /* Bits 8-15: Station address 1st octet */ -#define ETH_SA0_OCTET1_MASK (0xff << ETH_SA0_OCTET1_SHIFT) - /* Bits 16-31: Reserved */ -/* Station Address 1 register (SA1) */ - -#define ETH_SA1_OCTET4_SHIFT (0) /* Bits 0-7: Station address 4th octet */ -#define ETH_SA1_OCTET4_MASK (0xff << ETH_SA0_OCTET4_SHIFT) -#define ETH_SA1_OCTET3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */ -#define ETH_SA1_OCTET3_MASK (0xff << ETH_SA0_OCTET3_SHIFT) - /* Bits 16-31: Reserved */ -/* Station Address 2 register (SA2) */ - -#define ETH_SA2_OCTET6_SHIFT (0) /* Bits 0-7: Station address 5th octet */ -#define ETH_SA2_OCTET6_MASK (0xff << ETH_SA0_OCTET6_SHIFT) -#define ETH_SA2_OCTET5_SHIFT (8) /* Bits 8-15: Station address 6th octet */ -#define ETH_SA2_OCTET5_MASK (0xff << ETH_SA0_OCTET5_SHIFT) - /* Bits 16-31: Reserved */ -/* Control registers */ -/* Command register (CMD) */ - -#define ETH_CMD_RXEN (1 << 0) /* Bit 0: Receive enable */ -#define ETH_CMD_TXEN (1 << 1) /* Bit 1: Transmit enable */ - /* Bit 2: Reserved */ -#define ETH_CMD_REGRST (1 << 3) /* Bit 3: Reset host registers */ -#define ETH_CMD_TXRST (1 << 4) /* Bit 4: Reset transmit datapath */ -#define ETH_CMD_RXRST (1 << 5) /* Bit 5: Reset receive datapath */ -#define ETH_CMD_PRFRAME (1 << 6) /* Bit 6: Pass run frame */ -#define ETH_CMD_PRFILTER (1 << 7) /* Bit 7: Pass RX filter */ -#define ETH_CMD_TXFC (1 << 8) /* Bit 8: TX flow control */ -#define ETH_CMD_RMII (1 << 9) /* Bit 9: RMII mode */ -#define ETH_CMD_FD (1 << 10) /* Bit 10: Full duplex */ - /* Bits 11-31: Reserved */ -/* Status register */ - -#define ETH_STAT_RX (1 << 0) /* Bit 0: RX status */ -#define ETH_STAT_TX (1 << 1) /* Bit 1: TX status */ - /* Bits 2-31: Reserved */ -/* Receive descriptor base address register (RXDESC) - * - * The receive descriptor base address is a byte address aligned to a word - * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest - * address in the array of descriptors. - */ - -/* Receive status base address register (RXSTAT) - * - * The receive status base address is a byte address aligned to a double word - * boundary i.e. LSB 2:0 are fixed to 000. - */ - -/* Receive number of descriptors register (RXDESCNO) */ - -#define ETH_RXDESCNO_SHIFT (0) /* Bits 0-15 */ -#define ETH_RXDESCNO_MASK (0xffff << ETH_RXDESCNO_SHIFT) - /* Bits 16-31: Reserved */ -/* Receive produce index register (RXPRODIDX) */ - -#define ETH_RXPRODIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_RXPRODIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Receive consume index register (RXCONSIDX) */ - -#define ETH_RXCONSIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_RXCONSIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit descriptor base address register (TXDESC) - * - * The transmit descriptor base address is a byte address aligned to a word - * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest - * address in the array of descriptors. - */ - -/* Transmit status base address register (TXSTAT) - * - * The transmit status base address is a byte address aligned to a word - * boundary i.e. LSB1:0 are fixed to 00. The register contains the lowest - * address in the array of statuses. - */ - -/* Transmit number of descriptors register (TXDESCRNO) */ - -#define ETH_TXDESCRNO_SHIFT (0) /* Bits 0-15 */ -#define ETH_TXDESCRNO_MASK (0xffff << ETH_TXDESCRNO_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit produce index register (TXPRODIDX) */ - -#define ETH_TXPRODIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_TXPRODIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit consume index register (TXCONSIDX) */ - -#define ETH_TXCONSIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_TXCONSIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit status vector 0 register (TSV0) */ - -#define ETH_TSV0_CRCERR (1 << 0) /* Bit 0: CRC error */ -#define ETH_TSV0_LENCHKERR (1 << 1) /* Bit 1: Length check error */ -#define ETH_TSV0_LENOOR (1 << 2) /* Bit 2: Length out of range */ -#define ETH_TSV0_DONE (1 << 3) /* Bit 3: Done */ -#define ETH_TSV0_MCAST (1 << 4) /* Bit 4: Multicast */ -#define ETH_TSV0_BCAST (1 << 5) /* Bit 5: Broadcast */ -#define ETH_TSV0_PKTDEFER (1 << 6) /* Bit 6: Packet Defer */ -#define ETH_TSV0_EXCDEFER (1 << 7) /* Bit 7: Excessive Defer */ -#define ETH_TSV0_EXCCOL (1 << 8) /* Bit 8: Excessive Collision */ -#define ETH_TSV0_LATECOL (1 << 9) /* Bit 9: Late Collision */ -#define ETH_TSV0_GIANT (1 << 10) /* Bit 10: Giant */ -#define ETH_TSV0_UNDRUN (1 << 11) /* Bit 11: Underrun */ -#define ETH_TSV0_TOTBYTES_SHIFT (12) /* Bits 12-27:Total bytes */ -#define ETH_TSV0_TOTBYTES_MASK (0xffff << ETH_TSV0_TOTBYTES_SHIFT) -#define ETH_TSV0_CTLFRAME (1 << 28) /* Bit 28: Control frame */ -#define ETH_TSV0_PAUSE (1 << 29) /* Bit 29: Pause */ -#define ETH_TSV0_BP (1 << 30) /* Bit 30: Backpressure */ -#define ETH_TSV0_VLAN (1 << 31) /* Bit 31: VLAN */ - -/* Transmit status vector 1 register (TSV1) */ - -#define ETH_TSV1_TXCNT_SHIFT (0) /* Bits 0-15: Transmit byte count */ -#define ETH_TSV1_TXCNT_MASK (0xffff << ETH_TSV1_TXCNT_SHIFT) -#define ETH_TSV1_COLCNT_SHIFT (16) /* Bits 16-19: Transmit collision count */ -#define ETH_TSV1_COLCNT_MASK (15 << ETH_TSV1_COLCNT_SHIFT) - /* Bits 20-31: Reserved */ -/* Receive status vector register (RSV) */ - -#define ETH_RSV_RXCNT_SHIFT (0) /* Bits 0-15: Received byte count */ -#define ETH_RSV_RXCNT_MASK (0xffff << ETH_RSV_RXCNT_SHIFT) -#define ETH_RSV_PKTPI (1 << 16) /* Bit 16: Packet previously ignored */ -#define ETH_RSV_RXEPS (1 << 17) /* Bit 17: RXDV event previously seen */ -#define ETH_RSV_CEPS (1 << 18) /* Bit 18: Carrier event previously seen */ -#define ETH_RSV_RXCV (1 << 19) /* Bit 19: Receive code violation */ -#define ETH_RSV_CRCERR (1 << 20) /* Bit 20: CRC error */ -#define ETH_RSV_LENCHKERR (1 << 21) /* Bit 21: Length check error */ -#define ETH_RSV_LENOOR (1 << 22) /* Bit 22: Length out of range */ -#define ETH_RSV_RXOK (1 << 23) /* Bit 23: Receive OK */ -#define ETH_RSV_MCAST (1 << 24) /* Bit 24: Multicast */ -#define ETH_RSV_BCAST (1 << 25) /* Bit 25: Broadcast */ -#define ETH_RSV_DRIBNIB (1 << 26) /* Bit 26: Dribble Nibble */ -#define ETH_RSV_CTLFRAME (1 << 27) /* Bit 27: Control frame */ -#define ETH_RSV_PAUSE (1 << 28) /* Bit 28: Pause */ -#define ETH_RSV_UNSUPOP (1 << 29) /* Bit 29: Unsupported Opcode */ -#define ETH_RSV_VLAN (1 << 30) /* Bit 30: VLAN */ - /* Bit 31: Reserved */ -/* Flow control counter register (FCCNTR) */ - -#define ETH_FCCNTR_MCOUNT_SHIFT (0) /* Bits 0-15: Mirror count */ -#define ETH_FCCNTR_MCOUNT_MASK (0xffff << ETH_FCCNTR_MCOUNT_SHIFT) -#define ETH_FCCNTR_PTMR_SHIFT (16) /* Bits 16-31: Pause timer */ -#define ETH_FCCNTR_PTMR_MASK (0xffff << ETH_FCCNTR_PTMR_SHIFT) - -/* Flow control status register (FCSTAT) */ - -#define ETH_FCSTAT_MCOUNT_SHIFT (0) /* Bits 0-15: Current mirror count */ -#define ETH_FCSTAT_MCOUNT_MASK (0xffff << ETH_FCSTAT_MCOUNT_SHIFT) - /* Bits 16-31: Reserved */ -/* Rx filter registers */ -/* Receive filter control register (RXFLCTRL) */ - -#define ETH_RXFLCTRL_UCASTEN (1 << 0) /* Bit 0: Accept all unicast frames */ -#define ETH_RXFLCTRL_BCASTEN (1 << 1) /* Bit 1: Accept all broadcast frames */ -#define ETH_RXFLCTRL_MCASTEN (1 << 2) /* Bit 2: Accept all multicast frames */ -#define ETH_RXFLCTRL_UCASTHASHEN (1 << 3) /* Bit 3: Accept hashed unicast */ -#define ETH_RXFLCTRL_MCASTHASHEN (1 << 4) /* Bit 4: Accect hashed multicast */ -#define ETH_RXFLCTRL_PERFEN (1 << 5) /* Bit 5: Accept perfect dest match */ - /* Bits 6-11: Reserved */ -#define ETH_RXFLCTRL_MPKTEN (1 << 12) /* Bit 12: Magic pkt filter WoL int */ -#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect match WoL interrupt */ - /* Bits 14-31: Reserved */ -/* Receive filter WoL status register (RXFLWOLST) AND - * Receive filter WoL clear register (RXFLWOLCLR) - */ - -#define ETH_RXFLWOL_UCAST (1 << 0) /* Bit 0: Unicast frame WoL */ -#define ETH_RXFLWOL_BCAST (1 << 1) /* Bit 1: Broadcast frame WoL */ -#define ETH_RXFLWOL_MCAST (1 << 2) /* Bit 2: Multicast frame WoL */ -#define ETH_RXFLWOL_UCASTHASH (1 << 3) /* Bit 3: Unicast hash filter WoL */ -#define ETH_RXFLWOL_MCASTHASH (1 << 4) /* Bit 4: Multiicast hash filter WoL */ -#define ETH_RXFLWOL_PERF (1 << 5) /* Bit 5: Perfect addr match WoL */ - /* Bit 6: Reserved */ -#define ETH_RXFLWOL_RXFIL (1 << 7) /* Bit 7: Receive filter WoL */ -#define ETH_RXFLWOL_MPKT (1 << 8) /* Bit 8: Magic pkt filter WoL */ - /* Bits 9-31: Reserved */ -/* Hash filter table LSBs register (HASHFLL) AND Hash filter table MSBs register -* (HASHFLH) Are registers containing a 32-bit value with no bitfield. - */ - -/* Module control registers */ -/* Interrupt status register (INTST), Interrupt enable register (INTEN), Interrupt - * clear register (INTCLR), and Interrupt set register (INTSET) common bit field - * definition: - */ - -#define ETH_INT_RXOVR (1 << 0) /* Bit 0: RX overrun interrupt */ -#define ETH_INT_RXERR (1 << 1) /* Bit 1: RX error interrupt */ -#define ETH_INT_RXFIN (1 << 2) /* Bit 2: RX finished interrupt */ -#define ETH_INT_RXDONE (1 << 3) /* Bit 3: RX done interrupt */ -#define ETH_INT_TXUNR (1 << 4) /* Bit 4: TX underrun interrupt */ -#define ETH_INT_TXERR (1 << 5) /* Bit 5: TX error interrupt */ -#define ETH_INT_TXFIN (1 << 6) /* Bit 6: TX finished interrupt */ -#define ETH_INT_TXDONE (1 << 7) /* Bit 7: TX done interrupt */ - /* Bits 8-11: Reserved */ -#define ETH_INT_SOFT (1 << 12) /* Bit 12: Soft interrupt */ -#define ETH_INT_WKUP (1 << 13) /* Bit 13: Wakeup interrupt */ - /* Bits 14-31: Reserved */ -/* Power-down register */ - /* Bits 0-30: Reserved */ -#define ETH_PWRDOWN_MACAHB (1 << 31) /* Power down MAC/AHB */ - -/* Descriptors Offsets **************************************************************/ - -/* Tx descriptor offsets */ - -#define LPC17_TXDESC_PACKET 0x00 /* Base address of the Tx data buffer */ -#define LPC17_TXDESC_CONTROL 0x04 /* Control Information */ -#define LPC17_TXDESC_SIZE 0x08 /* Size in bytes of one Tx descriptor */ - -/* Tx status offsets */ - -#define LPC17_TXSTAT_INFO 0x00 /* Transmit status return flags */ -#define LPC17_TXSTAT_SIZE 0x04 /* Size in bytes of one Tx status */ - -/* Rx descriptor offsets */ - -#define LPC17_RXDESC_PACKET 0x00 /* Base address of the Rx data buffer */ -#define LPC17_RXDESC_CONTROL 0x04 /* Control Information */ -#define LPC17_RXDESC_SIZE 0x08 /* Size in bytes of one Rx descriptor */ - -/* Rx status offsets */ - -#define LPC17_RXSTAT_INFO 0x00 /* Receive status return flags */ -#define LPC17_RXSTAT_HASHCRC 0x04 /* Dest and source hash CRC */ -#define LPC17_RXSTAT_SIZE 0x08 /* Size in bytes of one Rx status */ - -/* Descriptor Bit Definitions *******************************************************/ - -/* Tx descriptor bit definitions */ - -#define TXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ -#define TXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) - -#define TXDESC_CONTROL_OVERRIDE (1 << 26 /* Bit 26: Per-frame override */ -#define TXDESC_CONTROL_HUGE (1 << 27) /* Bit 27: Enable huge frame size */ -#define TXDESC_CONTROL_PAD (1 << 28) /* Bit 28: Pad short frames */ -#define TXDESC_CONTROL_CRC (1 << 29) /* Bit 29: Append CRC */ -#define TXDESC_CONTROL_LAST (1 << 30) /* Bit 30: Last descriptor of a fragment */ -#define TXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate TxDone interrupt */ - -/* Tx status bit definitions */ - -#define TXSTAT_INFO_COLCNT_SHIFT (21) /* Bits 21-24: Number of collisions */ -#define TXSTAT_INFO_COLCNT_MASK (15 << TXSTAT_INFO_COLCNT_SHIFT) -#define TXSTAT_INFO_DEFER (1 << 25) /* Bit 25: Packet deffered */ -#define TXSTAT_INFO_EXCESSDEFER (1 << 26) /* Bit 26: Excessive packet defferals */ -#define TXSTAT_INFO_EXCESSCOL (1 << 27) /* Bit 27: Excessive packet collisions */ -#define TXSTAT_INFO_LATECOL (1 << 28) /* Bit 28: Out of window collision */ -#define TXSTAT_INFO_UNDERRUN (1 << 29) /* Bit 29: Tx underrun */ -#define TXSTAT_INFO_NODESC (1 << 30) /* Bit 29: No Tx descriptor available */ -#define TXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ - -/* Rx descriptor bit definitions */ - -#define RXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ -#define RXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) -#define RXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate RxDone interrupt */ - -/* Rx status bit definitions */ - -#define RXSTAT_SAHASHCRC_SHIFT (0) /* Bits 0-8: Hash CRC calculated from the source address */ -#define RXSTAT_SAHASHCRC_MASK (0x1ff << RXSTAT_SAHASHCRC_SHIFT) -#define RXSTAT_DAHASHCRC_SHIFT (16) /* Bits 16-24: Hash CRC calculated from the dest address */ -#define RXSTAT_DAHASHCRC_MASK (0x1ff << RXSTAT_DAHASHCRC_SHIFT) - -#define RXSTAT_INFO_RXSIZE_SHIFT (0) /* Bits 0-10: Size of actual data transferred */ -#define RXSTAT_INFO_RXSIZE_MASK (0x7ff << RXSTAT_INFO_RXSIZE_SHIFT) -#define RXSTAT_INFO_CONTROL (1 << 18) /* Bit 18: This is a control frame */ -#define RXSTAT_INFO_VLAN (1 << 19) /* Bit 19: This is a VLAN frame */ -#define RXSTAT_INFO_FAILFILTER (1 << 20) /* Bit 20: Frame failed Rx filter */ -#define RXSTAT_INFO_MULTICAST (1 << 21) /* Bit 21: This is a multicast frame */ -#define RXSTAT_INFO_BROADCAST (1 << 22) /* Bit 22: This is a broadcast frame */ -#define RXSTAT_INFO_CRCERROR (1 << 23) /* Bit 23: Received frame had a CRC error */ -#define RXSTAT_INFO_SYMBOLERROR (1 << 24) /* Bit 24: PHY reported bit error */ -#define RXSTAT_INFO_LENGTHERROR (1 << 25) /* Bit 25: Invalid frame length */ -#define RXSTAT_INFO_RANGEERROR (1 << 26) /* Bit 26: Exceeds maximum packet size */ -#define RXSTAT_INFO_ALIGNERROR (1 << 27) /* Bit 27: Alignment error */ -#define RXSTAT_INFO_OVERRUN (1 << 28) /* Bit 28: Receive overrun error */ -#define RXSTAT_INFO_NODESC (1 << 29) /* Bit 29: No Rx descriptor available */ -#define RXSTAT_INFO_LASTFLAG (1 << 30) /* Bit 30: Last fragment of a frame */ -#define RXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_ETHERNET_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h b/arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h deleted file mode 100644 index 4a1f25bf91c..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h +++ /dev/null @@ -1,597 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_GPDMA_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_GPDMA_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Register offsets *****************************************************************/ - -/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */ - -#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ -#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ -#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ -#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ -#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ -#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ -#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ -#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ -#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ -#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ -#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ -#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ -#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ -#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ - -/* Channel Registers */ - -#define LPC17_NDMACH 8 /* Eight DMA channels */ -#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...,(LPC17_NDMACH-1) */ - -#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ -#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ -#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ -#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ -#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ - -#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET) - -/* Register addresses ***************************************************************/ -/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ - -#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET) -#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET) -#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET) -#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET) -#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET) -#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET) -#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET) -#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET) -#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET) -#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET) -#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET) -#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET) -#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET) -#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET) - -/* Channel Registers */ - -#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n)) - -#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET) -#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET) -#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET) -#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET) -#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET) - -#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET) -#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET) -#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET) -#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET) -#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET) - -#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET) -#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET) -#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET) -#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET) -#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET) - -#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET) -#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET) -#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET) -#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET) -#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET) - -#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET) -#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET) -#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET) -#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET) -#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET) - -#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET) -#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET) -#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET) -#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET) -#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET) - -#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET) -#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET) -#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET) -#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET) -#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET) - -#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET) -#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET) -#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET) -#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET) -#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* DMA Request Connections **********************************************************/ - -#define LPC17_NDMAREQ (16) /* The number of DMA requests */ -#if defined(LPC176x) -/* Request Numbers */ - -# define DMA_REQ_SSP0TX (0) -# define DMA_REQ_SSP0RX (1) -# define DMA_REQ_SSP1TX (2) -# define DMA_REQ_SSP1RX (3) - -# define DMA_REQ_ADC (4) - -# define DMA_REQ_I2SCH0 (5) -# define DMA_REQ_I2SCH1 (6) - -# define DMA_REQ_DAC (7) - -# define DMA_REQ_UART0TX (8) /* DMASEL08=0*/ -# define DMA_REQ_UART0RX (9) /* DMASEL09=0*/ -# define DMA_REQ_UART1TX (10) /* DMASEL010=0*/ -# define DMA_REQ_UART1RX (11) /* DMASEL011=0*/ -# define DMA_REQ_UART2TX (12) /* DMASEL012=0*/ -# define DMA_REQ_UART2RX (13) /* DMASEL013=0*/ -# define DMA_REQ_UART3TX (14) /* DMASEL014=0*/ -# define DMA_REQ_UART3RX (15) /* DMASEL015=0*/ - -# define DMA_REQ_MAT0p0 (8) /* DMASEL08=1 */ -# define DMA_REQ_MAT0p1 (9) /* DMASEL09=1 */ -# define DMA_REQ_MAT1p0 (10) /* DMASEL010=1 */ -# define DMA_REQ_MAT1p1 (11) /* DMASEL011=1 */ -# define DMA_REQ_MAT2p0 (12) /* DMASEL012=1 */ -# define DMA_REQ_MAT2p1 (13) /* DMASEL013=1 */ -# define DMA_REQ_MAT3p0 (14) /* DMASEL014=1 */ -# define DMA_REQ_MAT3p1 (15) /* DMASEL015=1 */ - -/* DMASEL values. For the LPC176x family, only request numbers 8-15 have - * DMASEL bits. - */ - -# define DMA_DMASEL_SSP0TX (0) /* Not applicable */ -# define DMA_DMASEL_SSP0RX (0) /* Not applicable */ -# define DMA_DMASEL_SSP1TX (0) /* Not applicable */ -# define DMA_DMASEL_SSP1RX (0) /* Not applicable */ - -# define DMA_DMASEL_ADC (0) /* Not applicable */ - -# define DMA_DMASEL_I2SCH0 (0) /* Not applicable */ -# define DMA_DMASEL_I2SCH1 (0) /* Not applicable */ - -# define DMA_DMASEL_DAC (0) /* Not applicable */ - -# define DMA_DMASEL_UART0TX (0) -# define DMA_DMASEL_UART0RX (0) -# define DMA_DMASEL_UART1TX (0) -# define DMA_DMASEL_UART1RX (0) -# define DMA_DMASEL_UART2TX (0) -# define DMA_DMASEL_UART2RX (0) -# define DMA_DMASEL_UART3TX (0) -# define DMA_DMASEL_UART3RX (0) - -# define DMA_DMASEL_MAT0p0 (1) -# define DMA_DMASEL_MAT0p1 (1) -# define DMA_DMASEL_MAT1p0 (1) -# define DMA_DMASEL_MAT1p1 (1) -# define DMA_DMASEL_MAT2p0 (1) -# define DMA_DMASEL_MAT2p1 (1) -# define DMA_DMASEL_MAT3p0 (1) -# define DMA_DMASEL_MAT3p1 (1) - -#elif defined(LPC178x) -/* Request Numbers */ - -# define DMA_REQ_SDCARD (1) /* DMASEL01=0 */ - -# define DMA_REQ_SSP0TX (2) /* DMASEL02=0 */ -# define DMA_REQ_SSP0RX (3) /* DMASEL03=0 */ -# define DMA_REQ_SSP1TX (4) /* DMASEL04=0 */ -# define DMA_REQ_SSP1RX (5) /* DMASEL05=0 */ -# define DMA_REQ_SSP2TX (6) /* DMASEL06=0 */ -# define DMA_REQ_SSP2RX (7) /* DMASEL07=0 */ - -# define DMA_REQ_MAT0p0 (0) /* DMASEL00=1 */ -# define DMA_REQ_MAT0p1 (1) /* DMASEL01=1 */ -# define DMA_REQ_MAT1p0 (2) /* DMASEL02=1 */ -# define DMA_REQ_MAT1p1 (3) /* DMASEL03=1 */ -# define DMA_REQ_MAT2p0 (4) /* DMASEL04=1 */ -# define DMA_REQ_MAT2p1 (5) /* DMASEL05=1 */ -# define DMA_REQ_MAT3p0 (14) /* DMASEL14=1 */ -# define DMA_REQ_MAT3p1 (15) /* DMASEL15=1 */ - -# define DMA_REQ_I2SCH0 (6) /* DMASEL06=1 */ -# define DMA_REQ_I2SCH1 (7) /* DMASEL07=1 */ - -# define DMA_REQ_ADC (8) /* Not applicable */ -# define DMA_REQ_DAC (9) /* Not applicable */ - -# define DMA_REQ_UART0TX (10) /* DMASEL10=0 */ -# define DMA_REQ_UART0RX (11) /* DMASEL11=0 */ -# define DMA_REQ_UART1TX (12) /* DMASEL12=0 */ -# define DMA_REQ_UART1RX (13) /* DMASEL13=0 */ -# define DMA_REQ_UART2TX (14) /* DMASEL14=0 */ -# define DMA_REQ_UART2RX (15) /* DMASEL15=0 */ -# define DMA_REQ_UART3TX (10) /* DMASEL10=1 */ -# define DMA_REQ_UART3RX (11) /* DMASEL11=1 */ -# define DMA_REQ_UART4TX (12) /* DMASEL12=1 */ -# define DMA_REQ_UART4RX (13) /* DMASEL13=1 */ - -/* DMASEL values */ - -# define DMA_DMASEL_SDCARD (0) - -# define DMA_DMASEL_SSP0TX (0) -# define DMA_DMASEL_SSP0RX (0) -# define DMA_DMASEL_SSP1TX (0) -# define DMA_DMASEL_SSP1RX (0) -# define DMA_DMASEL_SSP2TX (0) -# define DMA_DMASEL_SSP2RX (0) - -# define DMA_DMASEL_MAT0p0 (1) -# define DMA_DMASEL_MAT0p1 (1) -# define DMA_DMASEL_MAT1p0 (1) -# define DMA_DMASEL_MAT1p1 (1) -# define DMA_DMASEL_MAT2p0 (1) -# define DMA_DMASEL_MAT2p1 (1) -# define DMA_DMASEL_MAT3p0 (1) -# define DMA_DMASEL_MAT3p1 (1) - -# define DMA_DMASEL_I2SCH0 (1) -# define DMA_DMASEL_I2SCH1 (1) - -# define DMA_DMASEL_ADC (0) /* Not applicable */ -# define DMA_DMASEL_DAC (0) /* Not applicable */ - -# define DMA_DMASEL_UART0TX (0) -# define DMA_DMASEL_UART0RX (0) -# define DMA_DMASEL_UART1TX (0) -# define DMA_DMASEL_UART1RX (0) -# define DMA_DMASEL_UART2TX (0) -# define DMA_DMASEL_UART2RX (0) -# define DMA_DMASEL_UART3TX (1) -# define DMA_DMASEL_UART3RX (1) -# define DMA_DMASEL_UART4TX (1) -# define DMA_DMASEL_UART4RX (1) -#endif - -/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ -/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, - * respectively. Bits 8-31 are reserved. - * - * DMA Interrupt Status Register - * DMA Interrupt Terminal Count Request Status Register - * DMA Interrupt Terminal Count Request Clear Register - * DMA Interrupt Error Status Register - * DMA Interrupt Error Clear Register - * DMA Raw Interrupt Terminal Count Status Register - * DMA Raw Error Interrupt Status Register - * DMA Enabled Channel Register - */ - -#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ -#define DMACH_ALL (0xff) - -/* For each of the following registers, bits 0-15 represent a set of encoded - * DMA sources. Bits 16-31 are reserved in each case. - * - * DMA Software Burst Request Register - * DMA Software Single Request Register - * DMA Software Last Burst Request Register - * DMA Software Last Single Request Register - * DMA Synchronization Register - */ - -#if defined(LPC176x) -# define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) -# define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) -# define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) -# define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) -# define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) -# define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) -# define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) -# define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) - -# define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) -# define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) -# define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) -# define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) -# define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) -# define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) -# define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) -# define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) - -# define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) -# define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) -# define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) -# define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) -# define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) -# define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) -# define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) -# define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) -#elif defined(LPC178x) -# define DMA_REQ_SDCARD_BIT (1 << DMA_REQ_SDCARD) - -# define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) -# define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) -# define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) -# define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP1RX) -# define DMA_REQ_SSP2TX_BIT (1 << DMA_REQ_SSP2TX) -# define DMA_REQ_SSP2RX_BIT (1 << DMA_REQ_SSP2RX) - -# define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) -# define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) -# define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) -# define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) -# define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) -# define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) -# define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) -# define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) - -# define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) -# define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) - -# define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) -# define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) - -# define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) -# define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) -# define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) -# define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) -# define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) -# define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) -# define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) -# define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) -# define DMA_REQ_UART4TX_BIT (1 << DMA_REQ_UART4TX) -# define DMA_REQ_UART4RX_BIT (1 << DMA_REQ_UART4RX) -#endif - -/* DMA Configuration Register */ - -#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ -#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ - /* Bits 2-31: Reserved */ -/* Channel Registers */ - -/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ -/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ -/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list - * item. Bits 0-1 must be zero. - */ - -/* DMA Channel Control Register */ - -#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ -#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) -# define DMACH_CONTROL_XFRSIZE(n) ((n) << DMACH_CONTROL_XFRSIZE_SHIFT) -#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ -#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) -#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ -#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) -#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ -#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) -# define DMACH_CONTROL_SWIDTH_8BIT (0 << DMACH_CONTROL_SWIDTH_SHIFT) /* Byte (8-bit) */ -# define DMACH_CONTROL_SWIDTH_16BIT (1 << DMACH_CONTROL_SWIDTH_SHIFT) /* Halfword (16-bit) */ -# define DMACH_CONTROL_SWIDTH_32BIT (2 << DMACH_CONTROL_SWIDTH_SHIFT) /* Word (32-bit) */ -#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ -#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) -# define DMACH_CONTROL_DWIDTH_8BIT (0 << DMACH_CONTROL_DWIDTH_SHIFT) /* Byte (8-bit) */ -# define DMACH_CONTROL_DWIDTH_16BIT (1 << DMACH_CONTROL_DWIDTH_SHIFT) /* Halfword (16-bit) */ -# define DMACH_CONTROL_DWIDTH_32BIT (2 << DMACH_CONTROL_DWIDTH_SHIFT) /* Word (32-bit) */ -#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ -#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ -#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ -#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ -#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ -#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ - -/* DMA Channel Configuration Register */ - -#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ -#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ -#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SDCARD (DMA_REQ_SDCARD << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP1RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP2TX (DMA_REQ_SSP2TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP2RX (DMA_REQ_SSP2RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART4TX (DMA_REQ_UART4TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART4RX (DMA_REQ_UART4RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) -#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Destination peripheral */ -#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SDCARD (DMA_REQ_SDCARD << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP1RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP2TX (DMA_REQ_SSP2TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP2RX (DMA_REQ_SSP2RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART4TX (DMA_REQ_UART4TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART4RX (DMA_REQ_UART4RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) -#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ -#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) - /* Flow controller = DMA controller */ -# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory */ -# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral */ -# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory */ -# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral */ -#ifdef LPC178x - /* Flow controller = Dest peripheral */ -# define DMACH_CONFIG_XFRTYPE_M2M_DC (4 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory */ -# define DMACH_CONFIG_XFRTYPE_M2P_DC (5 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral */ - /* Flow controller = Source peripheral */ -# define DMACH_CONFIG_XFRTYPE_P2M_SC (6 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory */ -# define DMACH_CONFIG_XFRTYPE_P2P_SC (7 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral */ -#endif -#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ -#define DMACH_CONFIG_ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ -#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ -#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ -#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ - /* Bits 19-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_GPDMA_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_gpio.h b/arch/arm/src/lpc17xx/hardware/lpc17_gpio.h deleted file mode 100644 index 2e9891058b1..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_gpio.h +++ /dev/null @@ -1,210 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_gpio.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* GPIO block register offsets ******************************************************/ - -#define LPC17_FIO0_OFFSET 0x0000 -#define LPC17_FIO1_OFFSET 0x0020 -#define LPC17_FIO2_OFFSET 0x0040 -#define LPC17_FIO3_OFFSET 0x0060 -#define LPC17_FIO4_OFFSET 0x0080 -#ifdef LPC178x -# define LPC17_FIO5_OFFSET 0x00a0 -#endif - -#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ -#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ -#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ -#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ -#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ - -/* GPIO interrupt block register offsets ********************************************/ - -#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) -#define LPC17_GPIOINT0_OFFSET 0x0080 -#define LPC17_GPIOINT2_OFFSET 0x00a0 - -#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ -#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ -#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ -#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ -#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ -#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ - -/* Register addresses ***************************************************************/ -/* GPIO block register addresses ****************************************************/ - -#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) -#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) -#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) -#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) -#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) -#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) -#ifdef LPC178x -# define LPC17_FIO5_BASE (LPC17_GPIO_BASE+LPC17_FIO5_OFFSET) -#endif - -#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) - -#ifdef LPC178x -# define LPC17_FIO5_DIR (LPC17_FIO5_BASE+LPC17_FIO_DIR_OFFSET) -# define LPC17_FIO5_MASK (LPC17_FIO5_BASE+LPC17_FIO_MASK_OFFSET) -# define LPC17_FIO5_PIN (LPC17_FIO5_BASE+LPC17_FIO_PIN_OFFSET) -# define LPC17_FIO5_SET (LPC17_FIO5_BASE+LPC17_FIO_SET_OFFSET) -# define LPC17_FIO5_CLR (LPC17_FIO5_BASE+LPC17_FIO_CLR_OFFSET) -#endif - -/* GPIO interrupt block register addresses ******************************************/ - -#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) -#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) -#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) - -#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) - -#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) - -/* Pins P0.0-31 */ - -#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) - -/* Pins P2.0-31 */ - -#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) - -/* Register bit definitions *********************************************************/ -/* GPIO block register bit definitions **********************************************/ - -/* Fast GPIO Port Direction control registers (FIODIR) */ -/* Fast Mask register for ports (FIOMASK) */ -/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ -/* Fast Port Output Set registers using FIOMASK (FIOSET) */ -/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ - -#define FIO(n) (1 << (n)) /* n=0,1,..31 */ - -/* GPIO interrupt block register bit definitions ************************************/ - -/* GPIO overall Interrupt Status (IOINTSTATUS) */ -#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ - /* Bit 1: Reserved */ -#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ - /* Bits 3-31: Reserved */ - -/* GPIO Interrupt Status for Rising edge (INTSTATR) - * GPIO Interrupt Status for Falling edge (INTSTATF) - * GPIO Interrupt Clear (INTCLR) - * GPIO Interrupt Enable for Rising edge (INTENR) - * GPIO Interrupt Enable for Falling edge (INTENF) - */ - -#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_i2c.h b/arch/arm/src/lpc17xx/hardware/lpc17_i2c.h deleted file mode 100644 index eb370fdd5dc..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_i2c.h +++ /dev/null @@ -1,208 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_i2c.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ -#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ -#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ -#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ -#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ -#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ -#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ -#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ -#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ -#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ -#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ -#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ -#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ -#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ -#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ -#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET) - -#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET) - -#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET) - -/* Register bit definitions *********************************************************/ -/* I2C Control Set Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ - /* Bits 7-31: Reserved */ -/* I2C Control Clear Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ -#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ - /* Bit 4: Reserved */ -#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ -#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ - /* Bits 7-31: Reserved */ -/* I2C Status Register - * - * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January - * 2010, NXP for definitions of status codes. - */ - -#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status - * Bits 0-1 always zero */ - /* Bits 8-31: Reserved */ -/* I2C Data Register */ - -#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ - /* Bits 8-31: Reserved */ -/* Monitor mode control register */ - -#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ -#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ -#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ - /* Bits 3-31: Reserved */ -/* Data buffer register */ - -#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ - /* Bits 8-31: Reserved */ -/* I2C Slave address registers: - * - * I2C Slave Address Register 0 - * I2C Slave Address Register 1 - * I2C Slave Address Register 2 - * I2C Slave Address Register 3 - */ - -#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ -#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ -#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Slave address mask registers: - * - * I2C Slave address mask register 0 - * I2C Slave address mask register 1 - * I2C Slave address mask register 2 - * I2C Slave address mask register 3 - */ - /* Bit 0: Reserved */ -#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ -#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* SCH Duty Cycle Register High Half Word */ - -#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ - /* Bits 16-31: Reserved */ -/* SCL Duty Cycle Register Low Half Word */ - -#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ - /* Bits 16-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_i2s.h b/arch/arm/src/lpc17xx/hardware/lpc17_i2s.h deleted file mode 100644 index bb0f9ca4427..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_i2s.h +++ /dev/null @@ -1,190 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_i2s - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */ -#define LPC17_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */ -#define LPC17_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */ -#define LPC17_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */ -#define LPC17_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */ -#define LPC17_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */ -#define LPC17_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */ -#define LPC17_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */ -#define LPC17_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */ -#define LPC17_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */ -#define LPC17_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */ -#define LPC17_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */ -#define LPC17_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */ -#define LPC17_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */ - -/* Register addresses ***************************************************************/ - -#define LPC17_I2S_DAO (LPC17_I2S_BASE+LPC17_I2S_DAO_OFFSET) -#define LPC17_I2S_DAI (LPC17_I2S_BASE+LPC17_I2S_DAI_OFFSET) -#define LPC17_I2S_TXFIFO (LPC17_I2S_BASE+LPC17_I2S_TXFIFO_OFFSET) -#define LPC17_I2S_RXFIFO (LPC17_I2S_BASE+LPC17_I2S_RXFIFO_OFFSET) -#define LPC17_I2S_STATE (LPC17_I2S_BASE+LPC17_I2S_STATE_OFFSET) -#define LPC17_I2S_DMA1 (LPC17_I2S_BASE+LPC17_I2S_DMA1_OFFSET) -#define LPC17_I2S_DMA2 (LPC17_I2S_BASE+LPC17_I2S_DMA2_OFFSET) -#define LPC17_I2S_IRQ (LPC17_I2S_BASE+LPC17_I2S_IRQ_OFFSET) -#define LPC17_I2S_TXRATE (LPC17_I2S_BASE+LPC17_I2S_TXRATE_OFFSET) -#define LPC17_I2S_RXRATE (LPC17_I2S_BASE+LPC17_I2S_RXRATE_OFFSET) -#define LPC17_I2S_TXBITRATE (LPC17_I2S_BASE+LPC17_I2S_TXBITRATE_OFFSET) -#define LPC17_I2S_RXBITRATE (LPC17_I2S_BASE+LPC17_I2S_RXBITRATE_OFFSET) -#define LPC17_I2S_TXMODE (LPC17_I2S_BASE+LPC17_I2S_TXMODE_OFFSET) -#define LPC17_I2S_RXMODE (LPC17_I2S_BASE+LPC17_I2S_RXMODE_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Digital Audio Output Register */ - -#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ -#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT) -#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */ -#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ -#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ -#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */ -#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ -#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT) -#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */ - /* Bits 16-31: Reserved */ -/* Digital Audio Input Register */ - -#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ -#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT) -#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */ -#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ -#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ -#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */ -#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ -#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT) - /* Bits 15-31: Reserved */ -/* Transmit FIFO: 8 × 32-bit transmit FIFO */ -/* Receive FIFO: 8 × 32-bit receive FIFO */ - -/* Status Feedback Register */ - -#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */ -#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */ -#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */ - /* Bits 3-7: Reserved */ -#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */ -#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT) - /* Bits 12-15: Reserved */ -#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */ -#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT) - /* Bits 20-31: Reserved */ -/* DMA Configuration Register 1 and 2 */ - -#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */ -#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */ - /* Bits 2-7: Reserved */ -#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */ -#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT) - /* Bits 12-15: Reserved */ -#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */ -#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT) - /* Bits 20-31: Reserved */ -/* Interrupt Request Control Register */ - -#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */ -#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */ - /* Bits 2-7: Reserved */ -#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */ -#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT) - /* Bits 12-15: Reserved */ -#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */ -#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT) - /* Bits 20-31: Reserved */ -/* Transmit and Receive MCLK divider */ - -#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */ -#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT) -#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */ -#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT) - /* Bits 16-31: Reserved */ - -/* Transmit and received bit rate divider */ - -#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */ -#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT) - /* Bits 6-31: Reserved */ -/* Transmit and Receive mode control */ - -#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */ -#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT) -# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */ -# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */ -# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */ -#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */ -#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_lcd.h b/arch/arm/src/lpc17xx/hardware/lpc17_lcd.h deleted file mode 100644 index af47bbd8a7e..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_lcd.h +++ /dev/null @@ -1,346 +0,0 @@ -/************************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_lcd.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -/* Register offsets *****************************************************************************/ - -#define LPC17_LCD_TIMH_OFFSET (0x0000) /* Horizontal Timing Control register */ -#define LPC17_LCD_TIMV_OFFSET (0x0004) /* Vertical Timing Control register */ -#define LPC17_LCD_POL_OFFSET (0x0008) /* Clock & Signal Polarity Control register */ -#define LPC17_LCD_LE_OFFSET (0x000c) /* Line End Control register */ -#define LPC17_LCD_UPBASE_OFFSET (0x0010) /* Upper Panel Frame Base Address register */ -#define LPC17_LCD_LPBASE_OFFSET (0x0014) /* Lower Panel Frame Base Address register */ -#define LPC17_LCD_CTRL_OFFSET (0x0018) /* LCD Control register */ -#define LPC17_LCD_INTMSK_OFFSET (0x001c) /* Interrupt Mask register */ -#define LPC17_LCD_INTRAW_OFFSET (0x0020) /* Raw Interrupt Status register */ -#define LPC17_LCD_INTSTAT_OFFSET (0x0024) /* Masked Interrupt Status register */ -#define LPC17_LCD_INTCLR_OFFSET (0x0028) /* Interrupt Clear register */ -#define LPC17_LCD_UPCURR_OFFSET (0x002c) /* Upper Panel Current Address Value register */ -#define LPC17_LCD_LPCURR_OFFSET (0x0030) /* Lower Panel Current Address Value register */ - -/* 256x16-bit Color Palette registers, n=0-127 */ - -#define LPC17_LCD_PAL_OFFSET(n) (0x0200 + ((n) << 2)) - -/* Cursor Image registers, n=0-255 */ - -#define LPC17_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2)) - -#define LPC17_LCD_CRSR_CRTL_OFFSET (0x0c00) /* Cursor Control register */ -#define LPC17_LCD_CRSR_CFG_OFFSET (0x0c04) /* Cursor Configuration register */ -#define LPC17_LCD_CRSR_PAL0_OFFSET (0x0c08) /* Cursor Palette register 0 */ -#define LPC17_LCD_CRSR_PAL1_OFFSET (0x0c0c) /* Cursor Palette register 1 */ -#define LPC17_LCD_CRSR_XY_OFFSET (0x0c10) /* Cursor XY Position register */ -#define LPC17_LCD_CRSR_CLIP_OFFSET (0x0c14) /* Cursor Clip Position register */ -#define LPC17_LCD_CRSR_INTMSK_OFFSET (0x0c20) /* Cursor Interrupt Mask regsiter */ -#define LPC17_LCD_CRSR_INTCLR_OFFSET (0x0c24) /* Cursor Interrupt Clear register */ -#define LPC17_LCD_CRSR_INTRAW_OFFSET (0x0c28) /* Cursor Raw Interrupt Status register */ -#define LPC17_LCD_CRSR_INTSTAT_OFFSET (0x0c2c) /* Cursor Masked Interrupt Status register */ - -/* Register Addresses ***************************************************************************/ - -#define LPC17_LCD_TIMH (LPC17_LCD_BASE+LPC17_LCD_TIMH_OFFSET) -#define LPC17_LCD_TIMV (LPC17_LCD_BASE+LPC17_LCD_TIMV_OFFSET) -#define LPC17_LCD_POL (LPC17_LCD_BASE+LPC17_LCD_POL_OFFSET) -#define LPC17_LCD_LE (LPC17_LCD_BASE+LPC17_LCD_LE_OFFSET) -#define LPC17_LCD_UPBASE (LPC17_LCD_BASE+LPC17_LCD_UPBASE_OFFSET) -#define LPC17_LCD_LPBASE (LPC17_LCD_BASE+LPC17_LCD_LPBASE_OFFSET) -#define LPC17_LCD_CTRL (LPC17_LCD_BASE+LPC17_LCD_CTRL_OFFSET) -#define LPC17_LCD_INTMSK (LPC17_LCD_BASE+LPC17_LCD_INTMSK_OFFSET) -#define LPC17_LCD_INTRAW (LPC17_LCD_BASE+LPC17_LCD_INTRAW_OFFSET) -#define LPC17_LCD_INTSTAT (LPC17_LCD_BASE+LPC17_LCD_INTSTAT_OFFSET) -#define LPC17_LCD_INTCLR (LPC17_LCD_BASE+ LPC17_LCD_INTCLR_OFFSET) -#define LPC17_LCD_UPCURR (LPC17_LCD_BASE+LPC17_LCD_UPCURR_OFFSET) -#define LPC17_LCD_LPCURR (LPC17_LCD_BASE+LPC17_LCD_LPCURR_OFFSET) - -#define LPC17_LCD_PAL(n) (LPC17_LCD_BASE+LPC17_LCD_PAL_OFFSET(n)) -#define LPC17_LCD_CRSR_IMG(n) (LPC17_LCD_BASE+LPC17_LCD_CRSR_IMG_OFFSET(n)) - -#define LPC17_LCD_CRSR_CRTL (LPC17_LCD_BASE+LPC17_LCD_CRSR_CRTL_OFFSET) -#define LPC17_LCD_CRSR_CFG (LPC17_LCD_BASE+LPC17_LCD_CRSR_CFG_OFFSET) -#define LPC17_LCD_CRSR_PAL0 (LPC17_LCD_BASE+LPC17_LCD_CRSR_PAL0_OFFSET) -#define LPC17_LCD_CRSR_PAL1 (LPC17_LCD_BASE+LPC17_LCD_CRSR_PAL1_OFFSET) -#define LPC17_LCD_CRSR_XY (LPC17_LCD_BASE+LPC17_LCD_CRSR_XY_OFFSET) -#define LPC17_LCD_CRSR_CLIP (LPC17_LCD_BASE+LPC17_LCD_CRSR_CLIP_OFFSET) -#define LPC17_LCD_CRSR_INTMSK (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTMSK_OFFSET) -#define LPC17_LCD_CRSR_INTCLR (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTCLR_OFFSET) -#define LPC17_LCD_CRSR_INTRAW (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTRAW_OFFSET) -#define LPC17_LCD_CRSR_INTSTAT (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTSTAT_OFFSET) - -/* Register Bitfield Definitions ****************************************************************/ - -/* LCD_TIMH - Horizontal Timing Register */ - /* Bits 0-1: Reserved */ -#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */ -#define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT) -#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */ -#define LCD_TIMH_HWS_MASK (0xff << LCD_TIMH_HSW_SHIFT) -#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */ -#define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT) -#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */ -#define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT) - -/* LCD_TIMV - Vertical Timing Register */ - -#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/ -#define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT) -#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */ -#define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT) -#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */ -#define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT) -#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */ -#define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT) - -/* LCD_POL - Clock and Signal Polarity Register */ - -#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */ -#define LCD_POL_PCDLO_MASK (0x1f << LCD_POL_PCDLO_SHIFT) -#define LCD_POL_CLKSEL (1 << 5) /* Bit 5: Clock select- 0=PCLK, 1=LCD_CLKIN */ -#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ -#define LCD_POL_ACB_MASK (0x1f << LCD_POL_ACB_SHIFT) -#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical sync */ -#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal sync */ -#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */ -#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */ - /* Bit 15: Reserved */ -#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */ -#define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT) -#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */ -#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */ -#define LCD_POL_PCDHI_MASK (0x1f << LCD_POL_PCDHI_SHIFT) - -/* LCD_LE - Line End Control Register */ - -#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */ -#define LCD_LE_LED_MASK (0x7f << LCD_LE_LED_SHIFT) - /* Bits 7-15: Reserved */ -#define LCD_LE_LEE (1 << 16) /* Bit 16: LCD line end enable */ - /* Bit 17-31: Reserved */ -/* LCD_UPBASE - Upper Panel Frame Base Address Register */ - /* Bits 0-2: Reserved */ -#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */ -#define LCD_UPBASE_LCDUPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) - -/* LCD_UPBASE - Lower Panel Frame Base Address Register */ - /* Bits 0-2: Reserved */ -#define LCD_UPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */ -#define LCD_UPBASE_LCDLPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) - -/* LCD_CTRL - Controle Register */ - -#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */ -#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ -#define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT) -# define LCD_CTRL_LCDBPP_1 (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */ -# define LCD_CTRL_LCDBPP_2 (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */ -# define LCD_CTRL_LCDBPP_4 (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */ -# define LCD_CTRL_LCDBPP_8 (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */ -# define LCD_CTRL_LCDBPP_16 (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */ -# define LCD_CTRL_LCDBPP_24 (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */ -# define LCD_CTRL_LCDBPP_565 (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */ -# define LCD_CTRL_LCDBPP_444 (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */ -#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */ -#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD TFT type selection */ -#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface bit */ -#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */ -#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format */ -#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-Endian Byte Order */ -#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */ -#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD Power enable */ -#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */ -#define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT) - /* Bits 14-15: Reserved */ -#define LCD_CTRL_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */ - /* Bits 17-31: Reserved */ -/* LCD_INTMSK - Interrupt Mask Register */ - /* Bits 0: Reserved */ -#define LCD_INTMSK_FUFIM (1 << 1) /* Bit 1: FIFO underflow interrupt enable */ -#define LCD_INTMSK_LNBUIM (1 << 2) /* Bit 2: LCD next base address interrupt enable */ -#define LCD_INTMSK_VCOMPIM (1 << 3) /* Bit 3: Vertical compare interrupt enable */ -#define LCD_INTMSK_BERIM (1 << 4) /* Bit 4: AHB Master error interrupt enable */ - /* Bits 5-31: Reserved */ -#define LCD_INTMSK_ALL (0x1e) - -/* LCD_INTRAW - Raw Interrupt Status Register */ - /* Bits 0: Reserved */ -#define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ -#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ -#define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ -#define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ - /* Bits 5-31: Reserved */ -#define LCD_INTRAW_ALL (0x1e) - -/* LCD_INTSTAT - Masked Interrupt Status Register */ - /* Bits 0: Reserved */ -#define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ -#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ -#define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ -#define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ - /* Bits 15-31: Reserved */ -#define LCD_INTSTAT_ALL (0x1e) - -/* LCD_INTCLR - Interrupt Clear Register */ - /* Bits 0: Reserved */ -#define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt clear */ -#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ -#define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ -#define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ - /* Bits 15-31: Reserved */ -#define LCD_INTCLR_ALL (0x1e) - -/* Upper and Lower Panel Address register has no bitfields */ -/* - * Upper Panel Current Address register (LCDUPCURR) - * Lower Panel Current Address register (LCDLPCURR) - */ - -/* LCD_PAL - Color Palette Registers */ - -#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */ -#define LCD_PAL_R0_MASK (0x1f << LCD_PAL_R0_SHIFT) -#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */ -#define LCD_PAL_G0_MASK (0x1f << LCD_PAL_G0_SHIFT) -#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue paletted data */ -#define LCD_PAL_B0_MASK (0x1f << LCD_PAL_B0_SHIFT) -#define LCD_PAL_I0 (1 << 15) /* Bit 15: Intensity/Unused bit */ -#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */ -#define LCD_PAL_R1_MASK (0x1f << LCD_PAL_R1_SHIFT) -#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */ -#define LCD_PAL_G1_MASK (0x1f << LCD_PAL_G1_SHIFT) -#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */ -#define LCD_PAL_B1_MASK (0x1f << LCD_PAL_B1_SHIFT) -#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity/Unused bit */ - -/* LCD_CRSR_IMG - Cursor Image Register - has no bitfields */ -/* The 256 words of the cursor image register defines the appearance - * of either one 64x64 cursor, or 4 32x32 cursors. - */ - -/* LCD CRSR_CTRL - Cursor Control Register */ - -#define LCD_CRSR_CTRL_CRSON (1 << 0) /* Bit 0: Cursor enable */ - /* Bits 1-3: Reserved */ -#define LCD_CRSR_CTRL_CRSRNUM_SHIFT (4) /* Bits 4-5: Cursor image number */ -#define LCD_CRSR_CTRL_CRSRNUM_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT) - /* Bits 6-31: Reserved */ -/* If the selected cursor is 32x32 */ - -#define LCD_CURSOR0 (0) -#define LCD_CURSOR1 (1) -#define LCD_CURSOR2 (2) -#define LCD_CURSOR3 (3) - -/* LCD CRSR_CFG - Cursor Configuration Register */ - -#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */ -#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame sync type */ - /* Bits 2-31: Reserved */ - -#define LCD_CURSOR_SIZE32 (0) /* 32x32 */ -#define LCD_CURSOR_SIZE64 (1) /* 64x64 */ -#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */ -#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */ - -/* LCD CRSR_PAL0/1 - Cursor Palette Registers */ - -#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ -#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) -#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ -#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) -#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ -#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT) - /* Bits 24-31: Reserved */ -/* LCD CRSR_XY - Cursor XY Position Register */ - -#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */ -#define LCD_CRSR_CRSRX_MASK (0x3ff << LCD_CRSR_CRSRX_SHIFT) - /* Bits 10-15: Reserved */ -#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */ -#define LCD_CRSR_CRSRY_MASK (0x3ff << LCD_CRSR_CRSRY_SHIFT) - /* Bits 26-31: Reserved */ -/* LCD CRSR_CLIP - Cursor Clip Position Register */ - -#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */ -#define LCD_CRSR_CRSRCLIPX_MASK (0x3f << LCD_CRSR_CRSRCLIPX_SHIFT) - /* Bits 6-7: Reserved */ -#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */ -#define LCD_CRSR_CRSRCLIPY_MASK (0x3f << LCD_CRSR_CRSRCLIPY_SHIFT) - /* Bits 14-31: Reserved */ -/* LCD CRSR_INTMSK - Cursor Interrrupt Mask Register */ - -#define LCD_CRSR_INTMSK_CRSRIM (1 << 0) /* Bit 0: Cursor interrupt mask */ - /* Bits 1-31: Reserved */ -/* LCD CRSR_INTCLR - Cursor Interrrupt Clear Register */ - -#define LCD_CRSR_INTCLR_CRSRIC (1 << 0) /* Bit 0: Cursor interrupt clear */ - /* Bits 1-31: Reserved */ - -/* LCD CRSR_INTRAW - Cursor Raw Interrrupt Status Register */ - -#define LCD_CRSR_INTRAW_CRSRRIS (1 << 0) /* Bit 0: Cursor raw interrupt status */ - /* Bits 1-31: Reserved */ -/* LCD CRSR_INTSTAT - Mask Interrrupt Status Register */ - -#define LCD_CRSR_INTSTAT_CRSRMIS (1 << 0) /* Bit 0: Cursor mask interrupt status */ - /* Bits 1-31: Reserved */ - -/************************************************************************************************ - * Public Types - ************************************************************************************************/ - -/************************************************************************************************ - * Public Data - ************************************************************************************************/ - -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h b/arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h deleted file mode 100644 index fc04e68ab9a..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h +++ /dev/null @@ -1,280 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ -#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ -#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ -#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ -#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ -#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ -#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ -#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ -#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ -#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ -#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ -#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ -#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ -#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ -#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ -#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */ -#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ -#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ -#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ -#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ -#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ -#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ -#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ -#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ -#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ -#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ -#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ -#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ -#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ -#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ - -/* Register addresses ***************************************************************/ - -#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET) -#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET) -#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET) -#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET) -#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET) -#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET) -#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET) -#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET) -#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET) -#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET) -#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET) -#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET) -#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET) -#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET) -#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET) -#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET) -#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET) -#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET) -#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET) -#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET) -#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET) -#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET) -#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET) -#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET) -#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET) -#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET) -#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET) -#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET) -#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET) -#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* There are no bit field definitions for the following registers because they support - * 32-bit values: - * - * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), - * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for - * channels 0, 1, 2 (no bit field definitions) - * - * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit - * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field - * definitions) - * - * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match - * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field - * definitions). - * - * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and - * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for - * channels 0, 1, 2 (no bit field definitions) - */ - -/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control - * clear address (CONCLR) common regiser bit definitions. - */ - -#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ -#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ -#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ -#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ -#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ - /* Bits 5-7: Reserved */ -#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ -#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ -#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ -#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ -#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ - /* Bits 13-15: Reserved */ -#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ -#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ -#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ -#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ -#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ - /* Bits 21-28: Reserved */ -#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ -#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ -#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ - -/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), - * and Event Control clear address (CAPCONCLR) common register bit defintions - */ - -#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ -#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ -#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ -#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ -#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ -#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ -#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ -#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ -#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ - /* Bits 24-31: Reserved */ -/* Dead time register */ - -#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ -#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) -#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ -#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) -#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ -#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) - /* Bits 30-31: reserved */ -/* Commutation Pattern register */ - -#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ -#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ -#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ -#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ -#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ -#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ - /* Bits 6-31: reserved */ - -/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), - * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), - * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) - * common bit field definitions - */ - -#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ -#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ -#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ - /* Bit 3: Reserved */ -#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ -#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ -#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ - /* Bit 7: Reserved */ -#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ -#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ -#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ - /* Bits 11-14: Reserved */ -#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ - /* Bits 16-31: Reserved */ - -/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and - * Count Control clear address (CNTCONCLR) common register bit definitions. - */ - -#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ -#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ -#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ -#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ -#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ -#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ - /* Bits 28-28: Reserved */ -#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ -#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ -#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ - -/* Capture clear address */ - -#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ -#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ -#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_pwm.h b/arch/arm/src/lpc17xx/hardware/lpc17_pwm.h deleted file mode 100644 index 4c158c9d0cf..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_pwm.h +++ /dev/null @@ -1,223 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_pwm.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_PWM_IR_OFFSET 0x0000 /* Interrupt Register */ -#define LPC17_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */ -#define LPC17_PWM_TC_OFFSET 0x0008 /* Timer Counter */ -#define LPC17_PWM_PR_OFFSET 0x000c /* Prescale Register */ -#define LPC17_PWM_PC_OFFSET 0x0010 /* Prescale Counter */ -#define LPC17_PWM_MCR_OFFSET 0x0014 /* Match Control Register */ -#define LPC17_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */ -#define LPC17_PWM_MR1_OFFSET 0x001c /* Match Register 1 */ -#define LPC17_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */ -#define LPC17_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */ -#define LPC17_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */ -#define LPC17_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */ -#define LPC17_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */ -#define LPC17_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */ -#define LPC17_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */ -#define LPC17_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */ -#define LPC17_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */ -#define LPC17_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */ -#define LPC17_PWM_PCR_OFFSET 0x004c /* PWM Control Register */ -#define LPC17_PWM_LER_OFFSET 0x0050 /* Load Enable Register */ -#define LPC17_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_PWM1_IR (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET) -#define LPC17_PWM1_TCR (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET) -#define LPC17_PWM1_TC (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET) -#define LPC17_PWM1_PR (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET) -#define LPC17_PWM1_PC (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET) -#define LPC17_PWM1_MCR (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET) -#define LPC17_PWM1_MR0 (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET) -#define LPC17_PWM1_MR1 (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET) -#define LPC17_PWM1_MR2 (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET) -#define LPC17_PWM1_MR3 (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET) -#define LPC17_PWM1_MR4 (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET) -#define LPC17_PWM1_MR5 (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET) -#define LPC17_PWM1_MR6 (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET) -#define LPC17_PWM1_CCR (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET) -#define LPC17_PWM1_CR0 (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET) -#define LPC17_PWM1_CR1 (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET) -#define LPC17_PWM1_CR2 (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET) -#define LPC17_PWM1_CR3 (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET) -#define LPC17_PWM1_PCR (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET) -#define LPC17_PWM1_LER (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET) -#define LPC17_PWM1_CTCR (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Registers holding 32-bit numeric values (no bit field definitions): - * - * Timer Counter (TC) - * Prescale Register (PR) - * Prescale Counter (PC) - * Match Register 0 (MR0) - * Match Register 1 (MR1) - * Match Register 2 (MR2) - * Match Register 3 (MR3) - * Match Register 4 (MR3) - * Match Register 5 (MR3) - * Match Register 6 (MR3) - * Capture Register 0 (CR0) - * Capture Register 1 (CR1) - * Capture Register 1 (CR2) - * Capture Register 1 (CR3) - */ - -/* Interrupt Register */ - -#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrupt */ -#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrupt */ -#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrupt */ -#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrupt */ -#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrupt */ -#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrupt */ - /* Bits 6-7: Reserved */ -#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrupt */ -#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrupt */ -#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrupt */ - /* Bits 11-31: Reserved */ -/* Timer Control Register */ - -#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */ -#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */ - /* Bit 2: Reserved */ -#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */ - /* Bits 4-31: Reserved */ -/* Match Control Register */ - -#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ -#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ -#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ -#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ -#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ -#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ -#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ -#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ -#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ -#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ -#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ -#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ -#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */ -#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */ -#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */ -#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */ -#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/ -#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */ -#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */ -#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */ -#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */ - /* Bits 21-31: Reserved */ -/* Capture Control Register (Where are CAP2 and 3?) */ - -#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ -#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */ -#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ -#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ -#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */ -#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ - /* Bits 6-31: Reserved */ -/* PWM Control Register */ - /* Bits 0-1: Reserved */ -#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */ -#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */ -#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */ -#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */ -#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */ - /* Bits 7-8: Reserved */ -#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */ -#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */ -#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */ -#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */ -#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */ -#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */ - /* Bits 15-31: Reserved */ -/* Load Enable Register */ - -#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */ -#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */ -#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */ -#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */ -#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */ -#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */ -#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */ - /* Bits 7-31: Reserved */ -/* Counter/Timer Control Register */ - -#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ -#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT) -# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */ -# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ -# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ -# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ -#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ -#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT) -# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ -# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_qei.h b/arch/arm/src/lpc17xx/hardware/lpc17_qei.h deleted file mode 100644 index ab3e3fb98ac..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_qei.h +++ /dev/null @@ -1,214 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/lpc17xx/hardware/lpc17_qei.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ -/* Control registers */ - -#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */ -#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ -#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */ - -/* Position, index, and timer registers */ - -#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */ -#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ -#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ -#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ -#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ -#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ -#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ -#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ -#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ -#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ -#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ -#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ -#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ - -#ifdef LPC178 -# define LPC17_QEI_INXCMP0_OFFSET 0x0024 /* Index compare0 register */ -# define LPC17_QEI_INXCMP1_OFFSET 0x004c /* Index compare1 register */ -# define LPC17_QEI_INXCMP2_OFFSET 0x0050 /* Index compare2 register */ -# define LPC17_QEI_FILTER_PHA_OFFSET 0x003c /* Digital filter register */ -# define LPC17_QEI_FILTER_PHB_OFFSET 0x0040 /* Digital filter register */ -# define LPC17_QEI_FILTER_INX_OFFSET 0x0044 /* Digital filter register */ -# define LPC17_QEI_WINDOW_OFFSET 0x0048 /* Index acceptance register */ -#endif - -/* Interrupt registers */ - -#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ -#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ -#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ -#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ -#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ -#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ - -/* Register addresses ***********************************************************************/ -/* Control registers */ - -#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET) -#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET) -#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET) - -/* Position, index, and timer registers */ - -#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET) -#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET) -#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET) -#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET) -#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET) -#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET) -#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET) -#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET) -#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET) -#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET) -#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET) -#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET) -#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET) - -/* Interrupt registers */ - -#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET) -#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET) -#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET) -#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET) -#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET) -#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET) - -/* Register bit definitions *****************************************************************/ -/* The following registers hold 32-bit integer values and have no bit fields defined - * in this section: - * - * Position register (POS) - * Maximum position register (MAXPOS) - * Position compare register 0 (CMPOS0) - * Position compare register 1 (CMPOS) - * Position compare register 2 (CMPOS2) - * Index count register (INXCNT) - * Index compare register (INXCMP) - * Velocity timer reload register (LOAD) - * Velocity timer register (TIME) - * Velocity counter register (VEL) - * Velocity capture register (CAP) - * Velocity compare register (VELCOMP) - * Digital filter register (FILTER) - */ - -/* Control registers */ -/* Control register */ - -#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ -#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ -#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ -#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ - /* Bits 4-31: reserved */ -/* Encoder status register */ - -#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ - /* Bits 1-31: reserved */ -/* Configuration register */ - -#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ -#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ -#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ -#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ - -#ifdef LPC178x -# define QEI_CONF_CRESPI (1 << 4) /* Bit 4: Continuous Index reset */ - /* Bits 5-15: reserved */ -# define QEI_CONF_INXGATE_SHIFT (16) /* Bit 16:19 Index Gating */ -# define QEI_CONF_INXGATE_MASK (15 << QEI_CONF_INXGATE_SHIFT) -#endif - /* Bits 20-31: reserved */ - -/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ - -/* Interrupt registers */ -/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), - * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt - * status clear register (CLR), and Interrupt status set register (SET) common - * bit definitions. - */ - -#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ -#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ -#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ -#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ -#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ -#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ -#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ -#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ -#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ -#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ -#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ -#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ -#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ - -#ifdef LPC178x -# define QEI_INT_REV1 (1 << 13) /* Bit 13: Index compare1 value to current index interrupt */ -# define QEI_INT_REV2 (1 << 14) /* Bit 14: Index compare2 value to current index interrupt */ -# define QEI_INT_MAXPOS (1 << 15) /* Bit 15: Current position count interrupt */ -#endif - /* Bits 16-31: reserved */ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -/******************************************************************************************** - * Public Data - ********************************************************************************************/ - -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_rtc.h b/arch/arm/src/lpc17xx/hardware/lpc17_rtc.h deleted file mode 100644 index 08975f2e99c..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_rtc.h +++ /dev/null @@ -1,277 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_rtc.h - * - * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* Miscellaneous registers */ - -#define LPC17_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */ -#define LPC17_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */ -#define LPC17_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */ -#define LPC17_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */ -#define LPC17_RTC_AUXEN_OFFSET 0x0058 /* RTC Auxiliary Enable register */ -#define LPC17_RTC_AUX_OFFSET 0x005c /* RTC Auxiliary control register */ - -/* Consolidated time registers */ - -#define LPC17_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */ -#define LPC17_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */ -#define LPC17_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */ - -/* Time counter registers */ - -#define LPC17_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */ -#define LPC17_RTC_MIN_OFFSET 0x0024 /* Minutes Register */ -#define LPC17_RTC_HOUR_OFFSET 0x0028 /* Hours Register */ -#define LPC17_RTC_DOM_OFFSET 0x002c /* Day of Month Register */ -#define LPC17_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */ -#define LPC17_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */ -#define LPC17_RTC_MONTH_OFFSET 0x0038 /* Months Register */ -#define LPC17_RTC_YEAR_OFFSET 0x003c /* Years Register */ -#define LPC17_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */ - -/* General purpose registers */ - -#define LPC17_RTC_GPREG0_OFFSET 0x0044 /* General Purpose Register 0 */ -#define LPC17_RTC_GPREG1_OFFSET 0x0048 /* General Purpose Register 1 */ -#define LPC17_RTC_GPREG2_OFFSET 0x004c /* General Purpose Register 2 */ -#define LPC17_RTC_GPREG3_OFFSET 0x0050 /* General Purpose Register 3 */ -#define LPC17_RTC_GPREG4_OFFSET 0x0054 /* General Purpose Register 4 */ - -/* Alarm register group */ - -#define LPC17_RTC_ALSEC_OFFSET 0x0060 /* Alarm value for Seconds */ -#define LPC17_RTC_ALMIN_OFFSET 0x0064 /* Alarm value for Minutes */ -#define LPC17_RTC_ALHOUR_OFFSET 0x0068 /* Alarm value for Hours */ -#define LPC17_RTC_ALDOM_OFFSET 0x006c /* Alarm value for Day of Month */ -#define LPC17_RTC_ALDOW_OFFSET 0x0070 /* Alarm value for Day of Week */ -#define LPC17_RTC_ALDOY_OFFSET 0x0074 /* Alarm value for Day of Year */ -#define LPC17_RTC_ALMON_OFFSET 0x0078 /* Alarm value for Months */ -#define LPC17_RTC_ALYEAR_OFFSET 0x007c /* Alarm value for Year */ - -/* Register addresses ***************************************************************/ -/* Miscellaneous registers */ - -#define LPC17_RTC_ILR (LPC17_RTC_BASE+LPC17_RTC_ILR_OFFSET) -#define LPC17_RTC_CCR (LPC17_RTC_BASE+LPC17_RTC_CCR_OFFSET) -#define LPC17_RTC_CIIR (LPC17_RTC_BASE+LPC17_RTC_CIIR_OFFSET) -#define LPC17_RTC_AMR (LPC17_RTC_BASE+LPC17_RTC_AMR_OFFSET) -#define LPC17_RTC_AUXEN (LPC17_RTC_BASE+LPC17_RTC_AUXEN_OFFSET) -#define LPC17_RTC_AUX (LPC17_RTC_BASE+LPC17_RTC_AUX_OFFSET) - -/* Consolidated time registers */ - -#define LPC17_RTC_CTIME0 (LPC17_RTC_BASE+LPC17_RTC_CTIME0_OFFSET) -#define LPC17_RTC_CTIME1 (LPC17_RTC_BASE+LPC17_RTC_CTIME1_OFFSET) -#define LPC17_RTC_CTIME2 (LPC17_RTC_BASE+LPC17_RTC_CTIME2_OFFSET) - -/* Time counter registers */ - -#define LPC17_RTC_SEC (LPC17_RTC_BASE+LPC17_RTC_SEC_OFFSET) -#define LPC17_RTC_MIN (LPC17_RTC_BASE+LPC17_RTC_MIN_OFFSET) -#define LPC17_RTC_HOUR (LPC17_RTC_BASE+LPC17_RTC_HOUR_OFFSET) -#define LPC17_RTC_DOM (LPC17_RTC_BASE+LPC17_RTC_DOM_OFFSET) -#define LPC17_RTC_DOW (LPC17_RTC_BASE+LPC17_RTC_DOW_OFFSET) -#define LPC17_RTC_DOY (LPC17_RTC_BASE+LPC17_RTC_DOY_OFFSET) -#define LPC17_RTC_MONTH (LPC17_RTC_BASE+LPC17_RTC_MONTH_OFFSET) -#define LPC17_RTC_YEAR (LPC17_RTC_BASE+LPC17_RTC_YEAR_OFFSET) -#define LPC17_RTC_CALIB (LPC17_RTC_BASE+LPC17_RTC_CALIB_OFFSET) - -/* General purpose registers */ - -#define LPC17_RTC_GPREG0 (LPC17_RTC_BASE+LPC17_RTC_GPREG0_OFFSET) -#define LPC17_RTC_GPREG1 (LPC17_RTC_BASE+LPC17_RTC_GPREG1_OFFSET) -#define LPC17_RTC_GPREG2 (LPC17_RTC_BASE+LPC17_RTC_GPREG2_OFFSET) -#define LPC17_RTC_GPREG3 (LPC17_RTC_BASE+LPC17_RTC_GPREG3_OFFSET) -#define LPC17_RTC_GPREG4 (LPC17_RTC_BASE+LPC17_RTC_GPREG4_OFFSET) - -/* Alarm register group */ - -#define LPC17_RTC_ALSEC (LPC17_RTC_BASE+LPC17_RTC_ALSEC_OFFSET) -#define LPC17_RTC_ALMIN (LPC17_RTC_BASE+LPC17_RTC_ALMIN_OFFSET) -#define LPC17_RTC_ALHOUR (LPC17_RTC_BASE+LPC17_RTC_ALHOUR_OFFSET) -#define LPC17_RTC_ALDOM (LPC17_RTC_BASE+LPC17_RTC_ALDOM_OFFSET) -#define LPC17_RTC_ALDOW (LPC17_RTC_BASE+LPC17_RTC_ALDOW_OFFSET) -#define LPC17_RTC_ALDOY (LPC17_RTC_BASE+LPC17_RTC_ALDOY_OFFSET) -#define LPC17_RTC_ALMON (LPC17_RTC_BASE+LPC17_RTC_ALMON_OFFSET) -#define LPC17_RTC_ALYEAR (LPC17_RTC_BASE+LPC17_RTC_ALYEAR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* The following registers hold 32-bit values and have no bit fields to be defined: - * - * General Purpose Register 0 - * General Purpose Register 1 - * General Purpose Register 2 - * General Purpose Register 3 - * General Purpose Register 4 - */ - -/* Miscellaneous registers */ -/* Interrupt Location Register */ - -#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */ -#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */ - /* Bits 2-31: Reserved */ -/* Clock Control Register */ - -#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */ -#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */ - /* Bits 2-3: Internal test mode controls */ -#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */ - /* Bits 5-31: Reserved */ -/* Counter Increment Interrupt Register */ - -#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */ -#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */ -#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */ -#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */ -#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */ -#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */ -#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */ -#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */ - /* Bits 8-31: Reserved */ -/* Alarm Mask Register */ - -#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */ -#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */ -#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */ -#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */ -#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */ -#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */ -#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */ -#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */ - /* Bits 8-31: Reserved */ - -/* RTC Auxiliary Control Register */ - /* Bits 0-3: Reserved */ -#define RTC_AUXEN_RTCOSCF (1 << 4) /* Bit 4: RTC Oscillator Fail detect flag */ -#ifdef LPC178x - /* Bit 5: Reserved */ -# define RTC_AUXEN_RTCPDOUT (1 << 6) /* Bit 6: RTC power down mode flag */ - /* Bits 7-31: Reserved */ -#endif - -/* RTC Auxiliary Enable Register */ - /* Bits 0-3: Reserved */ -#define RTC_AUX_OSCFEN (1 << 4) /* Bit 4: Oscillator Fail Detect interrupt enable */ - /* Bits 5-31: Reserved */ - -/* Consolidated Time Registers */ -/* Consolidated Time Register 0 */ - -#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */ -#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT) - /* Bits 6-7: Reserved */ -#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */ -#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT) - /* Bits 14-15: Reserved */ -#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */ -#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT) - /* Bits 21-23: Reserved */ -#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */ -#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT) - /* Bits 27-31: Reserved */ -/* Consolidated Time Register 1 */ - -#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */ -#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT) - /* Bits 5-7: Reserved */ -#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */ -#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT) - /* Bits 12-15: Reserved */ -#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */ -#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT) - /* Bits 28-31: Reserved */ -/* Consolidated Time Register 2 */ - -#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */ -#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT) - /* Bits 12-31: Reserved */ -/* Time counter registers */ - -#define RTC_SEC_MASK (0x003f) -#define RTC_MIN_MASK (0x003f) -#define RTC_HOUR_MASK (0x001f) -#define RTC_DOM_MASK (0x001f) -#define RTC_DOW_MASK (0x0007) -#define RTC_DOY_MASK (0x01ff) -#define RTC_MONTH_MASK (0x000f) -#define RTC_YEAR_MASK (0x0fff) - -/* Calibration Value Register */ - -#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */ -#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT) -#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */ - /* Bits 18-31: Reserved */ -/* Alarm register group */ - -#define RTC_ALSEC_MASK (0x003f) -#define RTC_ALMIN_MASK (0x003f) -#define RTC_ALHOUR_MASK (0x001f) -#define RTC_ALDOM_MASK (0x001f) -#define RTC_ALDOW_MASK (0x0007) -#define RTC_ALDOY_MASK (0x01ff) -#define RTC_ALMON_MASK (0x000f) -#define RTC_ALYEAR_MASK (0x0fff) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h b/arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h deleted file mode 100644 index 5448a3b7cf5..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h +++ /dev/null @@ -1,143 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_RTCEV_ERCONTROL_OFFSET 0x0084 /* Monitor/Recorder Control register */ -#define LPC17_RTCEV_ERSTATUS_OFFSET 0x0080 /* Status register */ -#define LPC17_RTCEV_ERCOUNTERS_OFFSET 0x0088 /* Counters register */ -#define LPC17_RTCEV_ERFIRSTSTAMP0_OFFSET 0x0090 /* Channel 0 first Stamp register */ -#define LPC17_RTCEV_ERFIRSTSTAMP1_OFFSET 0x0090 /* Channel 1 first Stamp register */ -#define LPC17_RTCEV_ERFIRSTSTAMP2_OFFSET 0x0090 /* Channel 2 first Stamp register */ -#define LPC17_RTCEV_ERLASTSTAMP0_OFFSET 0x0098 /* Channel 0 last stamp register */ -#define LPC17_RTCEV_ERLASTSTAMP1_OFFSET 0x00a0 /* Channel 1 last stamp register */ -#define LPC17_RTCEV_ERLASTSTAMP2_OFFSET 0x00a8 /* Channel 2 last stamp register */ - -#define LPC17_RTCEV_ERCONTROL (LPC17_RTC_BASE+LPC17_RTCEV_ERCONTROL_OFFSET) -#define LPC17_RTCEV_ERSTATUS (LPC17_RTC_BASE+LPC17_RTCEV_ERSTATUS_OFFSET) -#define LPC17_RTCEV_ERCOUNTERS (LPC17_RTC_BASE+LPC17_RTCEV_ERCOUNTERS_OFFSET) -#define LPC17_RTCEV_ERFIRSTSTAMP0 (LPC17_RTC_BASE+LPC17_RTCEV_ERFIRSTSTAMP0_OFFSET) -#define LPC17_RTCEV_ERFIRSTSTAMP1 (LPC17_RTC_BASE+LPC17_RTCEV_ERFIRSTSTAMP1_OFFSET) -#define LPC17_RTCEV_ERFIRSTSTAMP2 (LPC17_RTC_BASE+LPC17_RTCEV_ERFIRSTSTAMP2_OFFSET) -#define LPC17_RTCEV_ERLASTSTAMP0 (LPC17_RTC_BASE+LPC17_RTCEV_ERLASTSTAMP0_OFFSET) -#define LPC17_RTCEV_ERLASTSTAMP1 (LPC17_RTC_BASE+LPC17_RTCEV_ERLASTSTAMP1_OFFSET) -#define LPC17_RTCEV_ERLASTSTAMP2 (LPC17_RTC_BASE+LPC17_RTCEV_ERLASTSTAMP2_OFFSET) - -/* RTCEV ERCONTROL Event Monitor/Recorder Control Register */ - -#define RTCEV_ERCONTROL_INTWAKE_EN0 (1) /* Bit 0: Interrupt/wakeup enable channel 0 */ -#define RTCEV_ERCONTROL_GPCLEAR_EN0 (1 << 1) /* Bit 1: Automatic clearing of RTC - channel 0 */ -#define RTCEV_ERCONTROL_POL0 (1 << 2) /* Bit 2: Edge polarity on RTC_EV0 pins */ -#define RTCEV_ERCONTROL_EV0_INPUT_EN (1 << 3) /* Bit 3: Event enable for channel 0 */ - /* Bits 4-9: Reserved */ -#define RTCEV_ERCONTROL_INTWAKE_EN1 (1 << 10) /* Bit 10: Interrupt/wakeup enable - channel 1 */ -#define RTCEV_ERCONTROL_GPCLEAR_EN1 (1 << 11) /* Bit 11: Automatic clearing of RTC - channel 1 */ -#define RTCEV_ERCONTROL_POL1 (1 << 12) /* Bit 12: Edge polarity on RTC_EV1 pins */ -#define RTCEV_ERCONTROL_EV1_INPUT_EN (1 << 13) /* Bit 13: Event enable for channel 1 */ - /* Bits 14-19: Reserved */ -#define RTCEV_ERCONTROL_INTWAKE_EN2 (1 << 20) /* Bit 20: Interrupt/wakeup enable - channel 2 */ -#define RTCEV_ERCONTROL_GPCLEAR_EN2 (1 << 21) /* Bit 21: Automatic clearing of RTC - channel 2 */ -#define RTCEV_ERCONTROL_POL2 (1 << 22) /* Bit 22: Edge polarity on RTC_EV2 pins */ -#define RTCEV_ERCONTROL_EV2_INPUT_EN (1 << 23) /* Bit 23: Event enable for channel 1 */ - /* Bits 24-29: Reserved */ -#define RTCEV_ERCONTROL_ERMODE_SHIFT (30) /* Bits 30-31: Event monitoring mode */ -#define RTCEV_ERCONTROL_ERMODE_MASK (3 << RTCEV_ERCONTROL_ERMODE_SHIFT) -# define ERMODE0 (0) /* monitor/clocks disabled */ -# define ERMODE1 (1) /* 16Hz sample clock */ -# define ERMODE2 (2) /* 64Hz sample clock */ -# define ERMODE3 (3) /* 1000Hz sample clock */ - -/* RTCEV ERSTATUS - Monitor/Recorder Status Register */ - -#define RTCEV_ERSTATUS_EV0 (1) /* Bit 0: Event flag - channel 0 */ -#define RTCEV_ERSTATUS_EV1 (1 << 1) /* Bit 1: Event flag - channel 1 */ -#define RTCEV_ERSTATUS_EV2 (1 << 2) /* Bit 2: Event flag - channel 2 */ -#define RTCEV_ERSTATUS_EV2 (1 << 3) /* Bit 3: GPReg async clear flag */ - /* Bits 4-30: Reserved */ -#define RTCEV_ERSTATUS_WAKEUP (1 << 31) /* Bit 31: Interrupt/Wakeup request flag */ - -/* RTCEV ERCOUNTERS - Monitor/Recorder Counters Register */ - -#define RTCEV_ERCOUNTER_COUNTER0_SHIFT (0) /* Bits 0-2: Value for event 0 */ -#define RTCEV_ERCOUNTER_COUNTER0_MASK (7 << RTCEV_ERCOUNTER_COUNTER0_SHIFT) - /* Bits 3-7: Reserved */ -#define RTCEV_ERCOUNTER_COUNTER1_SHIFT (8) i /* Bits 8-10: Value for event 1 */ -#define RTCEV_ERCOUNTER_COUNTER1_MASK (7 << RTCEV_ERCOUNTER_COUNTER1_SHIFT) - /* Bits 11-15: Reserved */ -#define RTCEV_ERCOUNTER_COUNTER2_SHIFT (16) /* Bits 16-18: Value for event 2 */ -#define RTCEV_ERCOUNTER_COUNTER2_MASK (7 << RTCEV_ERCOUNTER_COUNTER2_SHIFT) - /* Bits 19-31: Reserved */ - -/* RTCEV ERFIRSTSTAMP[0-2] - Monitor/Recorder First Stamp Registers */ -/* RTCEV ERLASTSTAMP[0-2] - Monitor/Recorder Last Stamp Registers */ - -#define RTCEV_TIMESTAMP_SEC_SHIFT (0) /* Bits 0-5: Seconds value 0-59 */ -#define RTCEV_TIMESTAMP_SEC_MASK (0x3f << RTCEV_TIMESTAMP_SEC_SHIFT) -#define RTCEV_TIMESTAMP_MIN_SHIFT (6) /* Bits 6-11: Minutes value 0-59 */ -#define RTCEV_TIMESTAMP_MIN_MASK (0x3f << RTCEV_TIMESTAMP_MIN_SHIFT) -#define RTCEV_TIMESTAMP_HOUR_SHIFT (12) /* Bits 12-16: Hours value 0-23 */ -#define RTCEV_TIMESTAMP_HOUR_MASK (0x1f << RTCEV_TIMESTAMP_HOUR_SHIFT) -#define RTCEV_TIMESTAMP_DOY_SHIFT (17) /* Bits 17-25: Day of the year value 1-366 */ -#define RTCEV_TIMESTAMP_DOY_MASK (0x1ff << RTCEV_TIMESTAMP_DOY_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h b/arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h deleted file mode 100644 index 7140d186cf3..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h +++ /dev/null @@ -1,272 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define LPC17_SDCARD_PWR_OFFSET 0x0000 /* SD card power control register */ -#define LPC17_SDCARD_CLOCK_OFFSET 0x0004 /* SD card clock control register */ -#define LPC17_SDCARD_ARG_OFFSET 0x0008 /* SD card argument register */ -#define LPC17_SDCARD_CMD_OFFSET 0x000c /* SD card command register */ -#define LPC17_SDCARD_RESPCMD_OFFSET 0x0010 /* SD card command response register */ -#define LPC17_SDCARD_RESP_OFFSET(n) (0x0010+4*(n)) -# define LPC17_SDCARD_RESP0_OFFSET 0x0014 /* SD card response 1 register */ -# define LPC17_SDCARD_RESP1_OFFSET 0x0018 /* SD card response 2 register */ -# define LPC17_SDCARD_RESP2_OFFSET 0x001c /* SD card response 3 register */ -# define LPC17_SDCARD_RESP3_OFFSET 0x0020 /* SD card response 4 register */ -#define LPC17_SDCARD_DTIMER_OFFSET 0x0024 /* SD card data timer register */ -#define LPC17_SDCARD_DLEN_OFFSET 0x0028 /* SD card data length register */ -#define LPC17_SDCARD_DCTRL_OFFSET 0x002c /* SD card data control register */ -#define LPC17_SDCARD_DCOUNT_OFFSET 0x0030 /* SD card data counter register */ -#define LPC17_SDCARD_STATUS_OFFSET 0x0034 /* SD card status register */ -#define LPC17_SDCARD_CLEAR_OFFSET 0x0038 /* SD card interrupt clear register */ -#define LPC17_SDCARD_MASK0_OFFSET 0x003c /* SD card mask register */ -#define LPC17_SDCARD_FIFOCNT_OFFSET 0x0048 /* SD card FIFO counter register */ -#define LPC17_SDCARD_FIFO_OFFSET 0x0080 /* SD card data FIFO register */ - -/* Register Addresses ***************************************************************/ - -#define LPC17_SDCARD_PWR (LPC17_MCI_BASE+LPC17_SDCARD_PWR_OFFSET) -#define LPC17_SDCARD_CLOCK (LPC17_MCI_BASE+LPC17_SDCARD_CLOCK_OFFSET) -#define LPC17_SDCARD_ARG (LPC17_MCI_BASE+LPC17_SDCARD_ARG_OFFSET) -#define LPC17_SDCARD_CMD (LPC17_MCI_BASE+LPC17_SDCARD_CMD_OFFSET) -#define LPC17_SDCARD_RESPCMD (LPC17_MCI_BASE+LPC17_SDCARD_RESPCMD_OFFSET) -#define LPC17_SDCARD_RESP(n) (LPC17_MCI_BASE+LPC17_SDCARD_RESP_OFFSET(n)) -#define LPC17_SDCARD_RESP0 (LPC17_MCI_BASE+LPC17_SDCARD_RESP0_OFFSET) -#define LPC17_SDCARD_RESP1 (LPC17_MCI_BASE+LPC17_SDCARD_RESP1_OFFSET) -#define LPC17_SDCARD_RESP2 (LPC17_MCI_BASE+LPC17_SDCARD_RESP2_OFFSET) -#define LPC17_SDCARD_RESP3 (LPC17_MCI_BASE+LPC17_SDCARD_RESP3_OFFSET) -#define LPC17_SDCARD_DTIMER (LPC17_MCI_BASE+LPC17_SDCARD_DTIMER_OFFSET) -#define LPC17_SDCARD_DLEN (LPC17_MCI_BASE+LPC17_SDCARD_DLEN_OFFSET) -#define LPC17_SDCARD_DCTRL (LPC17_MCI_BASE+LPC17_SDCARD_DCTRL_OFFSET) -#define LPC17_SDCARD_DCOUNT (LPC17_MCI_BASE+LPC17_SDCARD_DCOUNT_OFFSET) -#define LPC17_SDCARD_STATUS (LPC17_MCI_BASE+LPC17_SDCARD_STATUS_OFFSET) -#define LPC17_SDCARD_CLEAR (LPC17_MCI_BASE+LPC17_SDCARD_CLEAR_OFFSET) -#define LPC17_SDCARD_MASK0 (LPC17_MCI_BASE+LPC17_SDCARD_MASK0_OFFSET) -#define LPC17_SDCARD_FIFOCNT (LPC17_MCI_BASE+LPC17_SDCARD_FIFOCNT_OFFSET) -#define LPC17_SDCARD_FIFO (LPC17_MCI_BASE+LPC17_SDCARD_FIFO_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* MCI Power Control Registers - PWR - 0x400c 0000*/ - -#define SDCARD_PWR_CTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define SDCARD_PWR_CTRL_MASK (3 << SDCARD_PWR_CTRL_SHIFT) -# define SDCARD_PWR_CTRL_OFF (0 << SDCARD_PWR_CTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define SDCARD_PWR_CTRL_PWRUP (2 << SDCARD_PWR_CTRL_SHIFT) /* 10: Reserved power-up */ -# define SDCARD_PWR_CTRL_ON (3 << SDCARD_PWR_CTRL_SHIFT) /* 11: Power-on: card is clocked */ - /* Bits 2-5 Reserved */ -#define SDCARD_PWR_OPENDRAIN (1 << 6) /* SD_CMD Output Control */ -#define SDCARD_PWR_ROD (1 << 7) /* Rod Control */ - /* Bits 8-31: Reserved */ -#define SDCARD_PWR_RESET (0) /* Reset value */ - -/* MCI Clock Control Register - CLOCK - 0x400c 0004 */ - -#define SDCARD_CLOCK_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define SDCARD_CLOCK_CLKDIV_MASK (0xff << SDCARD_CLOCK_CLKDIV_SHIFT) -#define SDCARD_CLOCK_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define SDCARD_CLOCK_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define SDCARD_CLOCK_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define SDCARD_CLOCK_WIDBUS (1 << 11) /* Bit 11: Wide bus mode enable bit */ -# define SDCARD_CLOCK_WIDBUS_D1 (0) /* 0: Default (SDIO_D0) */ -# define SDCARD_CLOCK_WIDBUS_D4 (SDCARD_CLOCK_WIDBUS) /* 1: 4-wide (SDIO_D[3:0]) */ - /* Bits 12-31: Reserved */ - -#define SDCARD_CLOCK_RESET (0) /* Reset value */ - -/* MCI Argument Register - ARGUMENT - 0x400c 0008 has no bitfields */ - -#define SDCARD_ARG_RESET (0) /* Reset value */ - -/* MCI Command Register - COMMAND - 0x400c 000c */ - -#define SDCARD_CMD_INDEX_SHIFT (0) /* Bits 0-5: Command Index */ -#define SDCARD_CMD_INDEX_MASK (0x3f << SDCARD_CMD_INDEX_SHIFT) -#define SDCARD_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define SDCARD_CMD_WAITRESP_MASK (3 << SDCARD_CMD_WAITRESP_SHIFT) -# define SDCARD_CMD_NORESPONSE (0 << SDCARD_CMD_WAITRESP_SHIFT) /* 00/01: No response */ -# define SDCARD_CMD_SHORTRESPONSE (1 << SDCARD_CMD_WAITRESP_SHIFT) /* 10: Short response */ -# define SDCARD_CMD_LONGRESPONSE (3 << SDCARD_CMD_WAITRESP_SHIFT) /* 11: Long response */ -#define SDCARD_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define SDCARD_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define SDCARD_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ - /* Bits 11-31: Reserved */ - -#define SDCARD_CMD_RESET (0) /* Reset value */ - -/* MCI Command Response Register - RESPCOMMAND - 0x400c 0010 */ - -#define SDCARD_RESPCMD_SHIFT (0) /* Bits 0-5: Resopnse Command index */ -#define SDCARD_RESPCMD_MASK (0x3f << SDCARD_RESPCMD_SHIFT) - /* Bits 6-31: Reserved */ - -/* MCI Response Registers RESPONSE0-3 - 0x400c 0014, 0x400c 0018, - No bitfields 0x400c 001c, 0x400c 0020 */ - - -/* MCI - Data Timer Register DATATIMER - 0x400c 0024 */ -/* No bitfields */ - -#define SDCARD_DTIMER_RESET (0) /* Reset value */ - -/* MCI - Data Length Register DATALENGTH - 0x400C 0028 */ - -#define SDCARD_DATALENGTH_SHIFT (0) /* Bits 0-15: Data length value */ -#define SDCARD_DATALENGTH_MASK (0xffff << SDCARD_DATALENGTH_SHIFT) - /* Bits 16-31: Reserved */ - -#define SDCARD_DLEN_RESET (0) /* Reset value */ - -/* MCI - Data Control Register - DATACTRL - 0x400c 002c */ - -#define SDCARD_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define SDCARD_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define SDCARD_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define SDCARD_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define SDCARD_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 4-7: Data block size */ -#define SDCARD_DCTRL_DBLOCKSIZE_MASK (15 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_1BYTE (0 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_2BYTES (1 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_4BYTES (2 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_8BYTES (3 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_16BYTES (4 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_32BYTES (5 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_64BYTES (6 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_128BYTES (7 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_256BYTES (8 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_512BYTES (9 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_1KBYTE (10 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) -# define SDCARD_DCTRL_2KBYTES (11 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) - /* Bits 8-31: Reserved */ - -#define SDCARD_DCTRL_RESET (0) /* Reset value */ - -/* MCI - Data Length Register DATALENGTH - 0x400c 0028 */ - -#define SDCARD_DATACOUNT_SHIFT (0) /* Bits 0-15: Remaining data */ -#define SDCARD_DATACOUNT_MASK (0xffff << SDCARD_DATACOUNT_SHIFT) - /* Bits 16-31: Reserved */ - -/* MCI - Status Register -Status - 0x400c 0034 */ - -#define SDCARD_STATUS_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define SDCARD_STATUS_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define SDCARD_STATUS_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define SDCARD_STATUS_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define SDCARD_STATUS_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define SDCARD_STATUS_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define SDCARD_STATUS_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define SDCARD_STATUS_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define SDCARD_STATUS_DATAEND (1 << 8) /* Bit 8: Data end */ -#define SDCARD_STATUS_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define SDCARD_STATUS_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define SDCARD_STATUS_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define SDCARD_STATUS_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define SDCARD_STATUS_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define SDCARD_STATUS_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define SDCARD_STATUS_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define SDCARD_STATUS_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define SDCARD_STATUS_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define SDCARD_STATUS_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define SDCARD_STATUS_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define SDCARD_STATUS_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define SDCARD_STATUS_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ - /* Bits 22-31: Reserved */ - -/* MCI - Clear Register CLEAR - 0x400c 0038 */ - -#define SDCARD_CLEAR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define SDCARD_CLEAR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define SDCARD_CLEAR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define SDCARD_CLEAR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define SDCARD_CLEAR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define SDCARD_CLEAR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define SDCARD_CLEAR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define SDCARD_CLEAR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define SDCARD_CLEAR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define SDCARD_CLEAR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define SDCARD_CLEAR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ - /* Bits 11-31: Reserved */ - -#define SDCARD_CLEAR_RESET 0x000007ff -#define SDCARD_CLEAR_STATICFLAGS 0x000005ff - -/* MCI - Interrupt Mask Registers - MASK0 - 0x400c 003c */ - -#define SDCARD_MASK0_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define SDCARD_MASK0_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define SDCARD_MASK0_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define SDCARD_MASK0_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define SDCARD_MASK0_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define SDCARD_MASK0_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define SDCARD_MASK0_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define SDCARD_MASK0_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define SDCARD_MASK0_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define SDCARD_MASK0_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define SDCARD_MASK0_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define SDCARD_MASK0_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define SDCARD_MASK0_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define SDCARD_MASK0_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define SDCARD_MASK0_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define SDCARD_MASK0_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define SDCARD_MASK0_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define SDCARD_MASK0_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define SDCARD_MASK0_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define SDCARD_MASK0_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define SDCARD_MASK0_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define SDCARD_MASK0_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ - /* Bits 22-31: Reserved */ -#define SDCARD_MASK0_RESET (0) - -/* MCI - FIFO Counter Register (FIFOCNT - 0x400c 0048 */ - -#define SDCARD_FIFOCNT_SHIFT (0) /* Bits 0-14: Remaining data */ -#define SDCARD_FIFOCNT_MASK (0x7fff << SDCARD_FIFOCNT_SHIFT) - /* Bits 15-31: Reserved */ - -/* MCI - Data FIFO Register - FIFO - 0x400c 0080 to 0x400c 00bc */ -/* The receive and transmit FIFOs can be read or written as 32 bit wide registers. - * The FIFOs contain 16 entries on 16 sequential addresses. - */ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H */ - diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_spi.h b/arch/arm/src/lpc17xx/hardware/lpc17_spi.h deleted file mode 100644 index dc9dce94385..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_spi.h +++ /dev/null @@ -1,141 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_spi.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */ -#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ -#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ -#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ -#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ -#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ -#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET) -#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET) -#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET) -#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET) -#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET) -#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET) -#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Control Register */ - /* Bits 0-1: Reserved */ -#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ -#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ -#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ -#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ -#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ -#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ -#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ -#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) -# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ -# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ -# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ -# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ -# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ -# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ -# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ -# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ -# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ - /* Bits 12-31: Reserved */ -/* SPI Status Register */ - /* Bits 0-2: Reserved */ -#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ -#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ -#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ -#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ -#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ - /* Bits 8-31: Reserved */ -/* SPI Data Register */ - -#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ -#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ - /* Bits 8-31: Reserved */ -/* SPI Clock Counter Register */ - -#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ - /* Bits 8-31: Reserved */ -/* SPI Test Control Register */ - /* Bit 0: Reserved */ -#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ -#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) - /* Bits 8-31: Reserved */ -/* SPI Test Status Register */ - /* Bits 0-2: Reserved */ -#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ -#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ -#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ -#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ -#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ - /* Bits 8-31: Reserved */ -/* SPI Interrupt Register */ - -#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ - /* Bits 1-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_ssp.h b/arch/arm/src/lpc17xx/hardware/lpc17_ssp.h deleted file mode 100644 index c1d40a211f5..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_ssp.h +++ /dev/null @@ -1,185 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_ssp.h - * - * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* 8 frame FIFOs for both transmit and receive */ - -#define LPC17_SSP_FIFOSZ 8 - -/* Register offsets *****************************************************************/ - -#define LPC17_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */ -#define LPC17_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */ -#define LPC17_SSP_DR_OFFSET 0x0008 /* Data Register */ -#define LPC17_SSP_SR_OFFSET 0x000c /* Status Register */ -#define LPC17_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */ -#define LPC17_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */ -#define LPC17_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */ -#define LPC17_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */ -#define LPC17_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */ -#define LPC17_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_SSP0_CR0 (LPC17_SSP0_BASE+LPC17_SSP_CR0_OFFSET) -#define LPC17_SSP0_CR1 (LPC17_SSP0_BASE+LPC17_SSP_CR1_OFFSET) -#define LPC17_SSP0_DR (LPC17_SSP0_BASE+LPC17_SSP_DR_OFFSET) -#define LPC17_SSP0_SR (LPC17_SSP0_BASE+LPC17_SSP_SR_OFFSET) -#define LPC17_SSP0_CPSR (LPC17_SSP0_BASE+LPC17_SSP_CPSR_OFFSET) -#define LPC17_SSP0_IMSC (LPC17_SSP0_BASE+LPC17_SSP_IMSC_OFFSET) -#define LPC17_SSP0_RIS (LPC17_SSP0_BASE+LPC17_SSP_RIS_OFFSET) -#define LPC17_SSP0_MIS (LPC17_SSP0_BASE+LPC17_SSP_MIS_OFFSET) -#define LPC17_SSP0_ICR (LPC17_SSP0_BASE+LPC17_SSP_ICR_OFFSET) -#define LPC17_SSP0_DMACR (LPC17_SSP0_BASE+LPC17_SSP_DMACR_OFFSET) - -#define LPC17_SSP1_CR0 (LPC17_SSP1_BASE+LPC17_SSP_CR0_OFFSET) -#define LPC17_SSP1_CR1 (LPC17_SSP1_BASE+LPC17_SSP_CR1_OFFSET) -#define LPC17_SSP1_DR (LPC17_SSP1_BASE+LPC17_SSP_DR_OFFSET) -#define LPC17_SSP1_SR (LPC17_SSP1_BASE+LPC17_SSP_SR_OFFSET) -#define LPC17_SSP1_CPSR (LPC17_SSP1_BASE+LPC17_SSP_CPSR_OFFSET) -#define LPC17_SSP1_IMSC (LPC17_SSP1_BASE+LPC17_SSP_IMSC_OFFSET) -#define LPC17_SSP1_RIS (LPC17_SSP1_BASE+LPC17_SSP_RIS_OFFSET) -#define LPC17_SSP1_MIS (LPC17_SSP1_BASE+LPC17_SSP_MIS_OFFSET) -#define LPC17_SSP1_ICR (LPC17_SSP1_BASE+LPC17_SSP_ICR_OFFSET) -#define LPC17_SSP1_DMACR (LPC17_SSP1_BASE+LPC17_SSP_DMACR_OFFSET) - -#define LPC17_SSP2_CR0 (LPC17_SSP2_BASE+LPC17_SSP_CR0_OFFSET) -#define LPC17_SSP2_CR1 (LPC17_SSP2_BASE+LPC17_SSP_CR1_OFFSET) -#define LPC17_SSP2_DR (LPC17_SSP2_BASE+LPC17_SSP_DR_OFFSET) -#define LPC17_SSP2_SR (LPC17_SSP2_BASE+LPC17_SSP_SR_OFFSET) -#define LPC17_SSP2_CPSR (LPC17_SSP2_BASE+LPC17_SSP_CPSR_OFFSET) -#define LPC17_SSP2_IMSC (LPC17_SSP2_BASE+LPC17_SSP_IMSC_OFFSET) -#define LPC17_SSP2_RIS (LPC17_SSP2_BASE+LPC17_SSP_RIS_OFFSET) -#define LPC17_SSP2_MIS (LPC17_SSP2_BASE+LPC17_SSP_MIS_OFFSET) -#define LPC17_SSP2_ICR (LPC17_SSP2_BASE+LPC17_SSP_ICR_OFFSET) -#define LPC17_SSP2_DMACR (LPC17_SSP2_BASE+LPC17_SSP_DMACR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Control Register 0 */ - -#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */ -#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT) -#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */ -#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT) -#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */ -#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */ -#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */ -#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT) - /* Bits 8-31: Reserved */ -/* Control Register 1 */ - -#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */ -#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */ -#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */ -#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */ - /* Bits 4-31: Reserved */ -/* Data Register */ - -#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */ - /* Bits 16-31: Reserved */ -/* Status Register */ - -#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */ -#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ -#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */ -#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */ -#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */ - /* Bits 5-31: Reserved */ -/* Clock Prescale Register */ - -#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */ - /* Bits 8-31: Reserved */ -/* Common format for interrupt control registers: - * - * Interrupt Mask Set and Clear Register (IMSC) - * Raw Interrupt Status Register (RIS) - * Masked Interrupt Status Register (MIS) - * Interrupt Clear Register (ICR) - */ - -#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */ -#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */ -#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */ -#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */ - /* Bits 4-31: Reserved */ -/* DMA Control Register */ - -#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */ -#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_timer.h b/arch/arm/src/lpc17xx/hardware/lpc17_timer.h deleted file mode 100644 index b66b3921ada..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_timer.h +++ /dev/null @@ -1,250 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_timer.h - * - * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ -#define LPC17_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */ -#define LPC17_TMR_TC_OFFSET 0x0008 /* Timer Counter */ -#define LPC17_TMR_PR_OFFSET 0x000c /* Prescale Register */ -#define LPC17_TMR_PC_OFFSET 0x0010 /* Prescale Counter */ -#define LPC17_TMR_MCR_OFFSET 0x0014 /* Match Control Register */ -#define LPC17_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */ -#define LPC17_TMR_MR1_OFFSET 0x001c /* Match Register 1 */ -#define LPC17_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */ -#define LPC17_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */ -#define LPC17_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */ -#define LPC17_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */ -#define LPC17_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */ -#define LPC17_TMR_EMR_OFFSET 0x003c /* External Match Register */ -#define LPC17_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_TMR0_IR (LPC17_TMR0_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR0_TCR (LPC17_TMR0_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR0_TC (LPC17_TMR0_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR0_PR (LPC17_TMR0_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR0_PC (LPC17_TMR0_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR0_MCR (LPC17_TMR0_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR0_MR0 (LPC17_TMR0_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR0_MR1 (LPC17_TMR0_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR0_MR2 (LPC17_TMR0_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR0_MR3 (LPC17_TMR0_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR0_CCR (LPC17_TMR0_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR0_CR0 (LPC17_TMR0_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR0_CR1 (LPC17_TMR0_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR0_EMR (LPC17_TMR0_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR0_CTCR (LPC17_TMR0_BASE+LPC17_TMR_CTCR_OFFSET) - -#define LPC17_TMR1_IR (LPC17_TMR1_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR1_TCR (LPC17_TMR1_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR1_TC (LPC17_TMR1_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR1_PR (LPC17_TMR1_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR1_PC (LPC17_TMR1_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR1_MCR (LPC17_TMR1_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR1_MR0 (LPC17_TMR1_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR1_MR1 (LPC17_TMR1_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR1_MR2 (LPC17_TMR1_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR1_MR3 (LPC17_TMR1_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR1_CCR (LPC17_TMR1_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR1_CR0 (LPC17_TMR1_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR1_CR1 (LPC17_TMR1_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR1_EMR (LPC17_TMR1_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR1_CTCR (LPC17_TMR1_BASE+LPC17_TMR_CTCR_OFFSET) - -#define LPC17_TMR2_IR (LPC17_TMR2_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR2_TCR (LPC17_TMR2_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR2_TC (LPC17_TMR2_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR2_PR (LPC17_TMR2_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR2_PC (LPC17_TMR2_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR2_MCR (LPC17_TMR2_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR2_MR0 (LPC17_TMR2_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR2_MR1 (LPC17_TMR2_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR2_MR2 (LPC17_TMR2_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR2_MR3 (LPC17_TMR2_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR2_CCR (LPC17_TMR2_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR2_CR0 (LPC17_TMR2_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR2_CR1 (LPC17_TMR2_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR2_EMR (LPC17_TMR2_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR2_CTCR (LPC17_TMR2_BASE+LPC17_TMR_CTCR_OFFSET) - -#define LPC17_TMR3_IR (LPC17_TMR3_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR3_TCR (LPC17_TMR3_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR3_TC (LPC17_TMR3_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR3_PR (LPC17_TMR3_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR3_PC (LPC17_TMR3_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR3_MCR (LPC17_TMR3_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR3_MR0 (LPC17_TMR3_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR3_MR1 (LPC17_TMR3_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR3_MR2 (LPC17_TMR3_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR3_MR3 (LPC17_TMR3_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR3_CCR (LPC17_TMR3_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR3_CR0 (LPC17_TMR3_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR3_CR1 (LPC17_TMR3_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR3_EMR (LPC17_TMR3_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR3_CTCR (LPC17_TMR3_BASE+LPC17_TMR_CTCR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Registers holding 32-bit numeric values (no bit field definitions): - * - * Timer Counter (TC) - * Prescale Register (PR) - * Prescale Counter (PC) - * Match Register 0 (MR0) - * Match Register 1 (MR1) - * Match Register 2 (MR2) - * Match Register 3 (MR3) - * Capture Register 0 (CR0) - * Capture Register 1 (CR1) - */ - -/* Interrupt Register */ - -#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */ -#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */ -#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */ -#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */ -#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */ -#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */ - /* Bits 6-31: Reserved */ -/* Timer Control Register */ - -#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */ -#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */ - /* Bits 2-31: Reserved */ -/* Match Control Register */ - -#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ -#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ -#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ -#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ -#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ -#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ -#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ -#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ -#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ -#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ -#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ -#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ - /* Bits 12-31: Reserved */ -/* Capture Control Register */ - -#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ -#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */ -#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ -#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ -#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */ -#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ - /* Bits 6-31: Reserved */ -/* External Match Register */ - -#define TMR_EMR_NOTHING (0) /* Do Nothing */ -#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */ -#define TMR_EMR_SET (2) /* Set external match bit MATn.m */ -#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */ - -#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */ -#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */ -#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */ -#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */ -#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */ -#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy) -# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT) -#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */ -#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT) -#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */ -#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT) -#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */ -#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT) - /* Bits 12-31: Reserved */ -/* Count Control Register */ - -#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ -#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT) -# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */ -# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ -# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ -# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ -#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ -#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT) -# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ -# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_uart.h b/arch/arm/src/lpc17xx/hardware/lpc17_uart.h deleted file mode 100644 index 175fedacfa6..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_uart.h +++ /dev/null @@ -1,414 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_uart.h - * - * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */ -#define LPC17_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */ -#define LPC17_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */ -#define LPC17_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */ -#define LPC17_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */ -#define LPC17_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */ -#define LPC17_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */ -#define LPC17_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */ -#define LPC17_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */ -#define LPC17_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */ -#define LPC17_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */ -#define LPC17_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */ -#define LPC17_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */ -#define LPC17_UART_ICR_OFFSET 0x0024 /* IrDA Control Register (UART0,2,3 only) */ -#define LPC17_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */ -#define LPC17_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */ -#define LPC17_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */ -#define LPC17_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */ -#define LPC17_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */ -#define LPC17_UART_FIFOLVL_OFFSET 0x0058 /* FIFO Level register (all) */ - -#ifdef LPC178x -# define LPC17_UART_OSR_OFFSET 0x002c /* Oversampling Register (UART4 only) */ -# define LPC17_UART_SCICTRL_OFFSET 0x0048 /* Smart Card Interface Register (UART4 only) */ -# define LPC17_UART_SYNCCTRL_OFFSET 0x0058 /* Synchronous Mode Register (UART4 only) */ -#endif - -/* Register addresses ***************************************************************/ - -#define LPC17_UART0_RBR (LPC17_UART0_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART0_THR (LPC17_UART0_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART0_DLL (LPC17_UART0_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART0_DLM (LPC17_UART0_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART0_IER (LPC17_UART0_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART0_IIR (LPC17_UART0_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART0_FCR (LPC17_UART0_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART0_LCR (LPC17_UART0_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART0_LSR (LPC17_UART0_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART0_SCR (LPC17_UART0_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART0_ACR (LPC17_UART0_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART0_ICR (LPC17_UART0_BASE+LPC17_UART_ICR_OFFSET) -#define LPC17_UART0_FDR (LPC17_UART0_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART0_TER (LPC17_UART0_BASE+LPC17_UART_TER_OFFSET) - -#ifdef LPC178x -# define LPC17_UART0_RS485CTRL (LPC17_UART0_BASE+LPC17_UART_RS485CTRL_OFFSET) -# define LPC17_UART0_ADRMATCH (LPC17_UART0_BASE+LPC17_UART_ADRMATCH_OFFSET) -# define LPC17_UART0_RS485DLY (LPC17_UART0_BASE+LPC17_UART_RS485DLY_OFFSET) -#endif - -#define LPC17_UART0_FIFOLVL (LPC17_UART0_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#define LPC17_UART1_RBR (LPC17_UART1_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART1_THR (LPC17_UART1_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART1_DLL (LPC17_UART1_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART1_DLM (LPC17_UART1_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART1_IER (LPC17_UART1_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART1_IIR (LPC17_UART1_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART1_FCR (LPC17_UART1_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART1_LCR (LPC17_UART1_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART1_MCR (LPC17_UART1_BASE+LPC17_UART_MCR_OFFSET) -#define LPC17_UART1_LSR (LPC17_UART1_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART1_MSR (LPC17_UART1_BASE+LPC17_UART_MSR_OFFSET) -#define LPC17_UART1_SCR (LPC17_UART1_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART1_ACR (LPC17_UART1_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART1_FDR (LPC17_UART1_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART1_TER (LPC17_UART1_BASE+LPC17_UART_TER_OFFSET) -#define LPC17_UART1_RS485CTRL (LPC17_UART1_BASE+LPC17_UART_RS485CTRL_OFFSET) -#define LPC17_UART1_ADRMATCH (LPC17_UART1_BASE+LPC17_UART_ADRMATCH_OFFSET) -#define LPC17_UART1_RS485DLY (LPC17_UART1_BASE+LPC17_UART_RS485DLY_OFFSET) -#define LPC17_UART1_FIFOLVL (LPC17_UART1_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#define LPC17_UART2_RBR (LPC17_UART2_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART2_THR (LPC17_UART2_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART2_DLL (LPC17_UART2_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART2_DLM (LPC17_UART2_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART2_IER (LPC17_UART2_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART2_IIR (LPC17_UART2_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART2_FCR (LPC17_UART2_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART2_LCR (LPC17_UART2_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART2_LSR (LPC17_UART2_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART2_SCR (LPC17_UART2_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART2_ACR (LPC17_UART2_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART2_ICR (LPC17_UART2_BASE+LPC17_UART_ICR_OFFSET) -#define LPC17_UART2_FDR (LPC17_UART2_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART2_TER (LPC17_UART2_BASE+LPC17_UART_TER_OFFSET) - -#ifdef LPC178x -# define LPC17_UART2_RS485CTRL (LPC17_UART2_BASE+LPC17_UART_RS485CTRL_OFFSET) -# define LPC17_UART2_ADRMATCH (LPC17_UART2_BASE+LPC17_UART_ADRMATCH_OFFSET) -# define LPC17_UART2_RS485DLY (LPC17_UART2_BASE+LPC17_UART_RS485DLY_OFFSET) -#endif - -#define LPC17_UART2_FIFOLVL (LPC17_UART2_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#define LPC17_UART3_RBR (LPC17_UART3_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART3_THR (LPC17_UART3_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART3_DLL (LPC17_UART3_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART3_DLM (LPC17_UART3_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART3_IER (LPC17_UART3_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART3_IIR (LPC17_UART3_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART3_FCR (LPC17_UART3_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART3_LCR (LPC17_UART3_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART3_LSR (LPC17_UART3_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART3_SCR (LPC17_UART3_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART3_ACR (LPC17_UART3_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART3_ICR (LPC17_UART3_BASE+LPC17_UART_ICR_OFFSET) -#define LPC17_UART3_FDR (LPC17_UART3_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART3_TER (LPC17_UART3_BASE+LPC17_UART_TER_OFFSET) - -#ifdef LPC178x -# define LPC17_UART3_RS485CTRL (LPC17_UART3_BASE+LPC17_UART_RS485CTRL_OFFSET) -# define LPC17_UART3_ADRMATCH (LPC17_UART3_BASE+LPC17_UART_ADRMATCH_OFFSET) -# define LPC17_UART3_RS485DLY (LPC17_UART3_BASE+LPC17_UART_RS485DLY_OFFSET) -#endif - -#define LPC17_UART3_FIFOLVL (LPC17_UART3_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#ifdef LPC178x -# define LPC17_UART4_RBR (LPC17_UART4_BASE+LPC17_UART_RBR_OFFSET) -# define LPC17_UART4_THR (LPC17_UART4_BASE+LPC17_UART_THR_OFFSET) -# define LPC17_UART4_DLL (LPC17_UART4_BASE+LPC17_UART_DLL_OFFSET) -# define LPC17_UART4_DLM (LPC17_UART4_BASE+LPC17_UART_DLM_OFFSET) -# define LPC17_UART4_IER (LPC17_UART4_BASE+LPC17_UART_IER_OFFSET) -# define LPC17_UART4_IIR (LPC17_UART4_BASE+LPC17_UART_IIR_OFFSET) -# define LPC17_UART4_FCR (LPC17_UART4_BASE+LPC17_UART_FCR_OFFSET) -# define LPC17_UART4_LCR (LPC17_UART4_BASE+LPC17_UART_LCR_OFFSET) -# define LPC17_UART4_LSR (LPC17_UART4_BASE+LPC17_UART_LSR_OFFSET) -# define LPC17_UART4_SCR (LPC17_UART4_BASE+LPC17_UART_SCR_OFFSET) -# define LPC17_UART4_ACR (LPC17_UART4_BASE+LPC17_UART_ACR_OFFSET) -# define LPC17_UART4_ICR (LPC17_UART4_BASE+LPC17_UART_ICR_OFFSET) -# define LPC17_UART4_FDR (LPC17_UART4_BASE+LPC17_UART_FDR_OFFSET) -# define LPC17_UART4_TER (LPC17_UART4_BASE+LPC17_UART_TER_OFFSET) -# define LPC17_UART4_RS485CTRL (LPC17_UART4_BASE+LPC17_UART_RS485CTRL_OFFSET) -# define LPC17_UART4_ADRMATCH (LPC17_UART4_BASE+LPC17_UART_ADRMATCH_OFFSET) -# define LPC17_UART4_RS485DLY (LPC17_UART4_BASE+LPC17_UART_RS485DLY_OFFSET) -# define LPC17_UART4_FIFOLVL (LPC17_UART4_BASE+LPC17_UART_FIFOLVL_OFFSET) -# define LPC17_UART4_OSR (LPC17_UART4_BASE+LPC17_UART4_OSR_OFFSET) -# define LPC17_UART4_SCICTRL (LPC17_UART4_BASE+LPC17_UART4_SCICTRL_OFFSET) -# define LPC17_UART4_SYNCCTRL (LPC17_UART4_BASE+LPC17_UART4_SYNCCTRL_OFFSET) -#endif - -/* Register bit definitions *********************************************************/ - -/* RBR (DLAB =0) Receiver Buffer Register (all) */ - -#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ - /* Bits 8-31: Reserved */ - -/* THR (DLAB =0) Transmit Holding Register (all) */ - -#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ - /* Bits 8-31: Reserved */ - -/* DLL (DLAB =1) Divisor Latch LSB (all) */ - -#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ - /* Bits 8-31: Reserved */ - -/* DLM (DLAB =1) Divisor Latch MSB (all) */ - -#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ - /* Bits 8-31: Reserved */ - -/* IER (DLAB =0) Interrupt Enable Register (all) */ - -#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */ -#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */ -#define UART_IER_RLSIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */ -#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART1 only) */ - /* Bits 4-6: Reserved */ -#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART1 only) */ -#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ -#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ - /* Bits 10-31: Reserved */ -#define UART_IER_ALLIE (0x038f) - -/* IIR Interrupt ID Register (all) */ - -#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ -#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ -#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) -# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */ -# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ -# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */ -# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ -# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ - /* Bits 4-5: Reserved */ -#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ -#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) -#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ -#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ - /* Bits 10-31: Reserved */ -/* FCR FIFO Control Register (all) */ - -#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ -#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ -#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ -#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */ - /* Bits 4-5: Reserved */ -#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ -#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) -# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ -# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ -# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ -# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ - /* Bits 8-31: Reserved */ -/* LCR Line Control Register (all) */ - -#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ -#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) -#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */ -#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */ -#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */ -#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT) -# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */ -# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */ -# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */ -# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */ -#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ -#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ - /* Bits 8-31: Reserved */ -/* MCR Modem Control Register (UART1 only) */ - -#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ -#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ - /* Bits 2-3: Reserved */ -#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ - /* Bit 5: Reserved */ -#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */ -#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */ - /* Bits 8-31: Reserved */ -/* LSR Line Status Register (all) */ - -#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */ -#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ -#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ -#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ -#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ -#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ -#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ -#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ - /* Bits 8-31: Reserved */ -/* MSR Modem Status Register (UART1 only) */ - -#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */ -#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */ -#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */ -#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */ -#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */ -#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */ -#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */ -#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */ - /* Bits 8-31: Reserved */ -/* SCR Scratch Pad Register (all) */ - -#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ - /* Bits 8-31: Reserved */ -/* ACR Auto-baud Control Register (all) */ - -#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/ -#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/ -#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/ - /* Bits 3-7: Reserved */ -#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ -#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ - /* Bits 10-31: Reserved */ -/* ICA IrDA Control Register (UART0,2,3 only) */ - -#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */ -#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */ -#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */ -#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT) -# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */ -# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */ -# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */ -# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */ -# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */ -# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */ -# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */ -# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 246 x TPCLK */ - /* Bits 6-31: Reserved */ -/* FDR Fractional Divider Register (all) */ - -#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */ -#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT) -#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT) - /* Bits 8-31: Reserved */ -/* TER Transmit Enable Register (all) */ - /* Bits 0-6: Reserved */ -#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */ - /* Bits 8-31: Reserved */ -/* RS-485/EIA-485 Control (UART1 only) */ - -#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */ -#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */ -#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */ -#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */ -#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */ -#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */ - /* Bits 6-31: Reserved */ -/* RS-485/EIA-485 address match (UART1 only) */ - -#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */ - /* Bits 8-31: Reserved */ -/* RS-485/EIA-485 direction control delay (UART1 only) */ - -#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */ - /* Bits 8-31: Reserved */ -/* FIFOLVL FIFO Level register (all) */ - -#define UART_FIFOLVL_RX_SHIFT (0) /* Bits 0-3: Current level of the UART RX FIFO */ -#define UART_FIFOLVL_RX_MASK (15 << UART_FIFOLVL_RX_SHIFT) - /* Bits 4-7: Reserved */ -#define UART_FIFOLVL_TX_SHIFT (8) /* Bits 8-11: Current level of the UART TX FIFO */ -#define UART_FIFOLVL_TX_MASK (15 << UART_FIFOLVL_TX_SHIFT) - /* Bits 12-31: Reserved */ - -/* SCICTL Smart Card Interface (UART4 only) */ - -#ifdef LPC178x -# define UART_SCIEN (1 << 0) /* Bit 0: Smart Card Interface enable */ -# define UART_NACKDIS (1 << 1) /* Bit 1: NACK response disable.Applicable if PROTSEL=0 */ -# define UART_PROTSEL (1 << 2) /* Bit 2: Protocol Selection ISO7816-3 */ -# define UART_TXRETRY (7 << 5) /* Bits 5-7: Maximum number of Re-Transmission */ -# define UART_GUARDTIME_SHIFT (8) /* Bits 8-15: Extra guard time */ -# define UART_GUARDTIME_MASK (0xff << UART_GUARDTIME_SHIFT) - /* Bits 16-31: Reserved */ -#endif - -/* OSR Oversampling Register (UART4 only) */ - -#ifdef LPC178x - /* Bit 0: Reserved */ -# define UART_OSFRAC (7 << 1) /* Bits 1-3: Fractional part of Oversampling Ratio */ -# define UART_OSINT_SHIFT (4) /* Bits 4-7: Integer part of (Oversampling Ratio -1) */ -# define UART_OSINT_MASK (0x0f << UART_OSINT_SHIFT) -# define UART_FDINT_SHIFT (8) /* Bits 8-14: OSINT extension in Smart Card mode */ -# define UART_FDINT_MASK (0x7f << UART_FDINT_SHIFT) - /* Bits 15-31: Reserved */ -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_usb.h b/arch/arm/src/lpc17xx/hardware/lpc17_usb.h deleted file mode 100644 index 56b38e55a09..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_usb.h +++ /dev/null @@ -1,778 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_usb.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_USB_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_USB_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* See include/nuttx/usb/ohci.h */ - -#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ - -/* USB OTG Controller ***************************************************************/ -/* OTG registers */ - -#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ -#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ -#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ -#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ -#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ -#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ - -#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ -#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ -#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ -#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ - -/* SIE Command registers */ - -#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ -#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ - -/* USB transfer registers */ - -#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ -#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ -#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ -#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ -#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ - -/* More Device interrupt registers */ - -#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ - -/* Endpoint interrupt registers */ - -#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ -#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ -#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ -#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ -#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ - -/* Endpoint realization registers */ - -#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ -#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ -#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ - -/* DMA registers */ - -#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ -#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ -#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ -#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ -#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ -#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ -#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ -#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ -#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ -#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ -#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ -#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ -#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ -#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ -#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ -#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ -#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ -#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ - -/* OTG I2C registers ****************************************************************/ - -#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ -#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ -#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ -#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ -#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ -#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ - -/* Clock control registers ***********************************************************/ - -#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ -#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ - -#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ -#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ - -/* Register addresses ***************************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* Control and status registers (section 7.1) */ - -#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) -#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) -#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) -#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) -#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) -#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) - -/* Memory pointers (section 7.2) */ - -#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) -#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) -#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) -#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) -#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) -#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) -#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) - -/* Frame counters (section 7.3) */ - -#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) -#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) -#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) -#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) - -/* Root hub ports (section 7.4) */ - -#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) -#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) -#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) -#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) -#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) -#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) -#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) - -/* USB OTG Controller ***************************************************************/ -/* OTG registers */ - -#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET) -#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET) -#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET) -#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET) -#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET) -#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET) - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ - -#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET) -#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET) -#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET) -#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET) - -/* SIE Command registers */ - -#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) -#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) - -/* USB transfer registers */ - -#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET) -#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET) -#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET) -#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET) -#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET) - -/* More Device interrupt registers */ - -#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET) - -/* Endpoint interrupt registers */ - -#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET) -#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET) -#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET) -#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET) -#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET) - -/* Endpoint realization registers */ - -#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET) -#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET) -#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET) - -/* DMA registers */ - -#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET) -#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET) -#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET) -#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET) -#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET) -#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET) -#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET) -#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET) -#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET) -#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET) -#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET) -#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET) -#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET) -#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET) -#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET) -#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET) -#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET) -#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET) - -/* OTG I2C registers ****************************************************************/ - -#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET) -#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET) -#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET) -#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET) -#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET) -#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET) - -/* Clock control registers ***********************************************************/ - -#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET) -#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET) - -#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET) -#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET) - -/* Register bit definitions *********************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* See include/nuttx/usb/ohci.h */ - -/* Module ID/Revision ID */ - -#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ -#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) -#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ -#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) -#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ -#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) -# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) - -/* USB OTG Controller ***************************************************************/ -/* OTG registers: - * - * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt - * Clear - */ - -#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ -#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ -#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ -#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ - /* Bits 4-31: Reserved */ -/* OTG Status and Control */ - -#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ -#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) -# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ -#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ -#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) -# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ -# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ -# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ -#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ -#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ -#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ - /* Bit 7: Reserved */ -#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ -#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ -#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ - /* Bits 11-15: Reserved */ -#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ -#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) - -/* OTG Timer */ - -#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ -#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) - /* Bits 16-31: Reserved */ - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ -/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt - * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority - */ - -#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ -#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ -#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ -#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ -#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ -#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ -#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ -#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ -#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ -#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ - /* Bits 10-31: Reserved */ -/* SIE Command registers: - * - * USB Command Code - */ - /* Bits 0-7: Reserved */ -#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ -#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) -#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ -#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) -#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ -#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) - /* Bits 24-31: Reserved */ -/* USB Command Data */ - -#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ -#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) - /* Bits 8-31: Reserved */ -/* USB transfer registers: - * - * USB Receive Data (Bits 0-31: Received data) - */ - -/* USB Receive Packet Length */ - -#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ -#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) -#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ -#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ - /* Bits 12-31: Reserved */ -/* USB Transmit Data (Bits 0-31: Transmit data) */ - -/* USB Transmit Packet Length */ - -#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ -#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) - /* Bits 10-31: Reserved */ -/* USB Control */ - -#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ -#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ -#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ -#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) - /* Bits 6-31: Reserved */ -/* Endpoint interrupt registers: - * - * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt - * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond - * to on RX or TX value for any of 15 logical endpoints). - */ - -#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) -#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) -#define USBDEV_LOGEPRX0 (1 << 0) -#define USBDEV_LOGEPTX0 (1 << 1) -#define USBDEV_LOGEPRX1 (1 << 2) -#define USBDEV_LOGEPTX1 (1 << 3) -#define USBDEV_LOGEPRX2 (1 << 4) -#define USBDEV_LOGEPTX2 (1 << 5) -#define USBDEV_LOGEPRX3 (1 << 6) -#define USBDEV_LOGEPTX3 (1 << 7) -#define USBDEV_LOGEPRX4 (1 << 8) -#define USBDEV_LOGEPTX4 (1 << 9) -#define USBDEV_LOGEPRX5 (1 << 10) -#define USBDEV_LOGEPTX5 (1 << 11) -#define USBDEV_LOGEPRX6 (1 << 12) -#define USBDEV_LOGEPTX6 (1 << 13) -#define USBDEV_LOGEPRX7 (1 << 14) -#define USBDEV_LOGEPTX7 (1 << 15) -#define USBDEV_LOGEPRX8 (1 << 16) -#define USBDEV_LOGEPTX8 (1 << 17) -#define USBDEV_LOGEPRX9 (1 << 18) -#define USBDEV_LOGEPTX9 (1 << 19) -#define USBDEV_LOGEPRX10 (1 << 20) -#define USBDEV_LOGEPTX10 (1 << 21) -#define USBDEV_LOGEPRX11 (1 << 22) -#define USBDEV_LOGEPTX11 (1 << 23) -#define USBDEV_LOGEPRX12 (1 << 24) -#define USBDEV_LOGEPTX12 (1 << 25) -#define USBDEV_LOGEPRX13 (1 << 26) -#define USBDEV_LOGEPTX13 (1 << 27) -#define USBDEV_LOGEPRX14 (1 << 28) -#define USBDEV_LOGEPTX14 (1 << 29) -#define USBDEV_LOGEPRX15 (1 << 30) -#define USBDEV_LOGEPTX15 (1 << 31) - -/* Endpoint realization registers: - * - * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) - */ - -#define USBDEV_PHYEP(n) (1 << (n)) -#define USBDEV_PHYEP0 (1 << 0) -#define USBDEV_PHYEP1 (1 << 1) -#define USBDEV_PHYEP2 (1 << 2) -#define USBDEV_PHYEP3 (1 << 3) -#define USBDEV_PHYEP4 (1 << 4) -#define USBDEV_PHYEP5 (1 << 5) -#define USBDEV_PHYEP6 (1 << 6) -#define USBDEV_PHYEP7 (1 << 7) -#define USBDEV_PHYEP8 (1 << 8) -#define USBDEV_PHYEP9 (1 << 9) -#define USBDEV_PHYEP10 (1 << 10) -#define USBDEV_PHYEP11 (1 << 11) -#define USBDEV_PHYEP12 (1 << 12) -#define USBDEV_PHYEP13 (1 << 13) -#define USBDEV_PHYEP14 (1 << 14) -#define USBDEV_PHYEP15 (1 << 15) -#define USBDEV_PHYEP16 (1 << 16) -#define USBDEV_PHYEP17 (1 << 17) -#define USBDEV_PHYEP18 (1 << 18) -#define USBDEV_PHYEP19 (1 << 19) -#define USBDEV_PHYEP20 (1 << 20) -#define USBDEV_PHYEP21 (1 << 21) -#define USBDEV_PHYEP22 (1 << 22) -#define USBDEV_PHYEP23 (1 << 23) -#define USBDEV_PHYEP24 (1 << 24) -#define USBDEV_PHYEP25 (1 << 25) -#define USBDEV_PHYEP26 (1 << 26) -#define USBDEV_PHYEP27 (1 << 27) -#define USBDEV_PHYEP28 (1 << 28) -#define USBDEV_PHYEP29 (1 << 29) -#define USBDEV_PHYEP30 (1 << 30) -#define USBDEV_PHYEP31 (1 << 31) - -/* USB Endpoint Index */ - -#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ -#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) - /* Bits 5-31: Reserved */ -/* USB MaxPacketSize */ - -#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ -#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) - /* Bits 10-31: Reserved */ -/* DMA registers: - * - * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers - * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions - * above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB UDCA Head */ - /* Bits 0-6: Reserved */ -#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ -#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) - -/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. - * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* - * definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ - -#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ -#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ -#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ - /* Bits 3-31: Reserved */ -/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB - * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. - * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB - * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. - * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System - * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use - * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* OTG I2C registers ****************************************************************/ - -/* I2C Receive */ - -#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ -#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Transmit */ - -#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ -#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) -#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ -#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ - /* Bits 3-31: Reserved */ -/* I2C Status */ - -#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ -#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ -#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ -#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ -#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ -#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ -#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ -#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ -#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ -#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ -#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ -#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ - /* Bits 12-31: Reserved */ -/* I2C Control */ - -#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ -#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ -#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ -#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ -#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ -#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ -#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ -#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ -#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ - /* Bits 9-31: Reserved */ -/* I2C Clock High */ - -#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ -#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Clock Low */ - -#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ -#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) - /* Bits 8-31: Reserved */ -/* Clock control registers ***********************************************************/ - -/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ - -#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ -#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ -#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ -#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ -#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ -#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ - /* Bits 5-31: Reserved */ -/* Alternate naming */ - -#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK -#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK -#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK -#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK -#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK -#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK - -/* Endpoints *************************************************************************/ - -#define LPC17_EP0_OUT 0 -#define LPC17_EP0_IN 1 -#define LPC17_CTRLEP_OUT LPC17_EP0_OUT -#define LPC17_CTRLEP_IN LPC17_EP0_IN -#define LPC17_EP1_OUT 2 -#define LPC17_EP1_IN 3 -#define LPC17_EP2_OUT 4 -#define LPC17_EP2_IN 5 -#define LPC17_EP3_OUT 6 -#define LPC17_EP3_IN 7 -#define LPC17_EP4_OUT 8 -#define LPC17_EP4_IN 9 -#define LPC17_EP5_OUT 10 -#define LPC17_EP5_IN 11 -#define LPC17_EP6_OUT 12 -#define LPC17_EP6_IN 13 -#define LPC17_EP7_OUT 14 -#define LPC17_EP7_IN 15 -#define LPC17_EP8_OUT 16 -#define LPC17_EP8_IN 17 -#define LPC17_EP9_OUT 18 -#define LPC17_EP9_IN 19 -#define LPC17_EP10_OUT 20 -#define LPC17_EP10_IN 21 -#define LPC17_EP11_OUT 22 -#define LPC17_EP11_IN 23 -#define LPC17_EP12_OUT 24 -#define LPC17_EP12_IN 25 -#define LPC17_EP13_OUT 26 -#define LPC17_EP13_IN 27 -#define LPC17_EP14_OUT 28 -#define LPC17_EP14_IN 29 -#define LPC17_EP15_OUT 30 -#define LPC17_EP15_IN 31 -#define LPC17_NUMEPS 32 - -/* Commands *************************************************************************/ - -/* USB Command Code Register */ - -#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ -#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) -#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ -#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) -#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT -#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK - -/* Device Commands */ - -#define CMD_USBDEV_SETADDRESS (0x00d0) -#define CMD_USBDEV_CONFIG (0x00d8) -#define CMD_USBDEV_SETMODE (0x00f3) -#define CMD_USBDEV_READFRAMENO (0x00f5) -#define CMD_USBDEV_READTESTREG (0x00fd) -#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ -#define CMD_USBDEV_GETSTATUS (0x00fe) -#define CMD_USBDEV_GETERRORCODE (0x00ff) -#define CMD_USBDEV_READERRORSTATUS (0x00fb) - -/* Endpoint Commands */ - -#define CMD_USBDEV_EPSELECT (0x0000) -#define CMD_USBDEV_EPSELECTCLEAR (0x0040) -#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ -#define CMD_USBDEV_EPCLRBUFFER (0x00f2) -#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) - -/* Command/response bit definitions ********************************************/ -/* SETADDRESS (0xd0) command definitions */ - -#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ -#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ - -/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ - -#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ -#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ -#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ -#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ -#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ - -/* EPSELECT (0x00) endpoint status response */ - -#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ -#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ -#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ -#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ -#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ -#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ -#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ - /* Bit 7: Reserved */ -/* EPSETSTATUS (0x40) command */ - -#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ - /* Bits 1-4: Reserved */ -#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ -#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ -#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ - -/* EPCLRBUFFER (0xf2) response */ - -#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) - -/* SETMODE(0xf3) command */ - -#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ -#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ -#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ -#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ -#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ -#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ -#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ - -/* READERRORSTATUS (0xFb) command */ - -#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ -#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ -#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ -#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ -#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ -#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ -#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ -#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ -#define CMD_READERRORSTATUS_ALLERRS (0xff) - -/* DMA ******************************************************************************/ -/* The DMA descriptor */ - -#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ -#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ -#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ -#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ -#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ - -/* Bit settings for CONFIG (offset 1 )*/ - -#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ -#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) -# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ -# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ -#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ - /* Bit 3: Reserved */ -#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ -#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ -#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) -#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ -#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT - -/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ - -#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ -#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) -#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ -#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ -#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ -#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ -#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) -#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ -#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) - -/* DMA packet size format */ - -#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ -#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) -#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ -#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ -#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_USB_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_wdt.h b/arch/arm/src/lpc17xx/hardware/lpc17_wdt.h deleted file mode 100644 index f740fe167c9..00000000000 --- a/arch/arm/src/lpc17xx/hardware/lpc17_wdt.h +++ /dev/null @@ -1,156 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_wdt.h - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */ -#define LPC17_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */ -#define LPC17_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */ -#define LPC17_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */ - -#ifdef LPC176x -# define LPC17_WDT_CLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ -#endif - -#ifdef LPC178x -# define LPC17_WDT_WARNINT_OFFSET 0x0014 /* Watchdog warning interrupt */ -# define LPC17_WDT_WINDOW_OFFSET 0x0018 /* Watchdog window compare value */ -#endif - -/* Register addresses ***************************************************************/ - -#define LPC17_WDT_MOD (LPC17_WDT_BASE+LPC17_WDT_MOD_OFFSET) -#define LPC17_WDT_TC (LPC17_WDT_BASE+LPC17_WDT_TC_OFFSET) -#define LPC17_WDT_FEED (LPC17_WDT_BASE+LPC17_WDT_FEED_OFFSET) -#define LPC17_WDT_TV (LPC17_WDT_BASE+LPC17_WDT_TV_OFFSET) -#define LPC17_WDT_CLKSEL (LPC17_WDT_BASE+LPC17_WDT_CLKSEL_OFFSET) - -#ifdef LPC178x -# define LPC17_WDT_WARNINT (LPC17_WDT_BASE+LPC17_WDT_WARNINT_OFFSET) -# define LPC17_WDT_WINDOW (LPC17_WDT_BASE+LPC17_WDT_WINDOW_OFFSET) -#endif - -/* Register bit definitions *********************************************************/ - -/* Watchdog mode register */ - -#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ -#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ -#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ -#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ -#ifdef LPC178x -# define WDT_MOD_WDPROTECT (1 << 4) /* Bit 4: Watchdog interrupt */ -#endif - /* Bits 5-31: Reserved */ -/* Watchdog timer constant register */ - -#ifdef LPC176x -# define WDT_TC (0xffffffff) /* Bits 0-31: Watchdog time-out interval */ -#endif -#ifdef LPC178x -# define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */ - /* Bits 24-31: Reserved */ -#endif - -/* Watchdog feed sequence register */ - -#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa - * followed by 0x55 */ - /* Bits 14-31: Reserved */ -/* Watchdog timer value register */ - -#ifdef LPC176x -# define WDT_TVT (0xffffffff) /* Bits 0-31: Watchdog timer value */ -#endif -#ifdef LPC178x -# define WDT_TVT (0xffffff) /* Bits 0-23: Watchdog timer value */ - /* Bits 24-31: Reserved */ -#endif - -/* Watchdog clock source selection register */ - -#ifdef LPC176x -# define WDT_CLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ -# define WDT_CLKSEL_WDSEL_MASK (3 << WDT_CLKSEL_WDSEL_SHIFT) -# define WDT_CLKSEL_WDSEL_INTRC (0 << WDT_CLKSEL_WDSEL_SHIFT) /* Internal RC osc */ -# define WDT_CLKSEL_WDSEL_APB (1 << WDT_CLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ -# define WDT_CLKSEL_WDSEL_RTC (2 << WDT_CLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ - /* Bits 2-30: Reserved */ -# define WDT_CLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ -#endif - -/* Watchdog timer warning interrupt register */ - -#ifdef LPC178x -# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */ - /* Bits 10-31: Reserved */ -#endif - -/* Watchdog timer value register */ - -#ifdef LPC178x -# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */ - /* Bits 24-31: Reserved */ -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_timer.h b/arch/arm/src/lpc17xx/lpc17_timer.h deleted file mode 100644 index 3f0e8af09ac..00000000000 --- a/arch/arm/src/lpc17xx/lpc17_timer.h +++ /dev/null @@ -1,62 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_timer.h - * - * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "hardware/lpc17_timer.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H */ diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx_40xx/Kconfig similarity index 63% rename from arch/arm/src/lpc17xx/Kconfig rename to arch/arm/src/lpc17xx_40xx/Kconfig index b75adb5d529..6c1eda91ffe 100644 --- a/arch/arm/src/lpc17xx/Kconfig +++ b/arch/arm/src/lpc17xx_40xx/Kconfig @@ -3,97 +3,151 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -comment "LPC17xx Configuration Options" +comment "LPC17xx/40xx Configuration Options" choice - prompt "NXP LPC17XX Chip Selection" + prompt "NXP LPC17XX/LPC40XX Chip Selection" default ARCH_CHIP_LPC1768 - depends on ARCH_CHIP_LPC17XX + depends on ARCH_CHIP_LPC17XX_40XX config ARCH_CHIP_LPC1751 bool "LPC1751" select ARCH_FAMILY_LPC175X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1752 bool "LPC1752" select ARCH_FAMILY_LPC175X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1754 bool "LPC1754" select ARCH_FAMILY_LPC175X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1756 bool "LPC1756" select ARCH_FAMILY_LPC175X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1758 bool "LPC1758" select ARCH_FAMILY_LPC175X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1759 bool "LPC1759" select ARCH_FAMILY_LPC175X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1764 bool "LPC1764" select ARCH_FAMILY_LPC176X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1765 bool "LPC1765" select ARCH_FAMILY_LPC176X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1766 bool "LPC1766" select ARCH_FAMILY_LPC176X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1767 bool "LPC1767" select ARCH_FAMILY_LPC176X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1768 bool "LPC1768" select ARCH_FAMILY_LPC176X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1769 bool "LPC1769" select ARCH_FAMILY_LPC176X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1773 bool "LPC1773" select ARCH_FAMILY_LPC177X - select LPC17_HAVE_SPIFI + select LPC17_40_HAVE_SPIFI + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1774 bool "LPC1774" select ARCH_FAMILY_LPC177X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1776 bool "LPC1776" select ARCH_FAMILY_LPC177X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1777 bool "LPC1777" select ARCH_FAMILY_LPC177X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1778 bool "LPC1778" select ARCH_FAMILY_LPC177X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1785 bool "LPC1785" select ARCH_FAMILY_LPC178X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1786 bool "LPC1786" select ARCH_FAMILY_LPC178X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1787 bool "LPC1787" select ARCH_FAMILY_LPC178X + select ARCH_CORTEXM3 config ARCH_CHIP_LPC1788 bool "LPC1788" select ARCH_FAMILY_LPC178X + select ARCH_CORTEXM3 + +config ARCH_CHIP_LPC4072 + bool "LPC4072" + select ARCH_FAMILY_LPC407X + select LPC17_40_HAVE_SPIFI + select ARCH_CORTEXM4 + +config ARCH_CHIP_LPC4074 + bool "LPC4074" + select ARCH_FAMILY_LPC407X + select LPC17_40_HAVE_SPIFI + select ARCH_CORTEXM4 + +config ARCH_CHIP_LPC4076 + bool "LPC4076" + select ARCH_FAMILY_LPC407X + select LPC17_40_HAVE_SPIFI + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + +config ARCH_CHIP_LPC4078 + bool "LPC4078" + select ARCH_FAMILY_LPC407X + select LPC17_40_HAVE_SPIFI + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + +config ARCH_CHIP_LPC4088 + bool "LPC4088" + select ARCH_FAMILY_LPC408X + select LPC17_40_HAVE_SPIFI + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU endchoice @@ -109,285 +163,292 @@ config ARCH_FAMILY_LPC177X config ARCH_FAMILY_LPC178X bool -config LPC17_HAVE_SPIFI +config ARCH_FAMILY_LPC407X bool -menu "LPC17xx Peripheral Support" +config ARCH_FAMILY_LPC408X + bool -config LPC17_MAINOSC +config LPC17_40_HAVE_SPIFI + bool + +menu "LPC17xx/LPC40xx Peripheral Support" + +config LPC17_40_MAINOSC bool "Main oscillator" default y -config LPC17_PLL0 +config LPC17_40_PLL0 bool "PLL0" default y -config LPC17_PLL1 +config LPC17_40_PLL1 bool "PLL1" default y -config LPC17_EMC +config LPC17_40_EMC bool "EMC" default y - depends on ARCH_FAMILY_LPC178X - select LPC17_HAVE_EXTNAND - select LPC17_HAVE_EXTSRAM0 - select LPC17_HAVE_EXTDRAM - select LPC17_HAVE_EXTNOR + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X + select LPC17_40_HAVE_EXTNAND + select LPC17_40_HAVE_EXTSRAM0 + select LPC17_40_HAVE_EXTDRAM + select LPC17_40_HAVE_EXTNOR -config LPC17_ETHERNET +config LPC17_40_ETHERNET bool "Ethernet" select NETDEVICES select ARCH_HAVE_PHY select ARCH_HAVE_NETDEV_STATISTICS default n -config LPC17_LCD +config LPC17_40_LCD bool "LCD controller" default n - depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X + depends on ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC408X -config LPC17_USBHOST +config LPC17_40_USBHOST bool "USB host" select USBHOST select USBHOST_HAVE_ASYNCH default n -config LPC17_USBDEV +config LPC17_40_USBDEV bool "USB Device" select USBDEV default n -config LPC17_USBOTG +config LPC17_40_USBOTG bool "USB OTG" default n - depends on LPC17_USBHOST && LPC17_USBDEV + depends on LPC17_40_USBHOST && LPC17_40_USBDEV -config LPC17_SDCARD +config LPC17_40_SDCARD bool "SD Card Interface" - depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X select ARCH_HAVE_SDIO default n -config LPC17_UART0 +config LPC17_40_UART0 bool "UART0" default n select UART0_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS -config LPC17_UART1 +config LPC17_40_UART1 bool "UART1" default n select UART1_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS -config LPC17_UART2 +config LPC17_40_UART2 bool "UART2" default n select UART2_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS -config LPC17_UART3 +config LPC17_40_UART3 bool "UART3" default n select UART3_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS -config LPC17_UART4 +config LPC17_40_UART4 bool "UART4" + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X default n select UART4_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS -config LPC17_CAN1 +config LPC17_40_CAN1 bool "CAN1" default n select CAN -config LPC17_CAN2 +config LPC17_40_CAN2 bool "CAN2" default n select CAN -config LPC17_SPI +config LPC17_40_SPI bool "SPI" default n depends on ARCH_FAMILY_LPC175X || ARCH_FAMILY_LPC176X -config LPC17_SSP0 +config LPC17_40_SSP0 bool "SSP0" default n -config LPC17_SSP1 +config LPC17_40_SSP1 bool "SSP1" default n -config LPC17_SSP2 +config LPC17_40_SSP2 bool "SSP1" default n - depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X -config LPC17_SPIFI +config LPC17_40_SPIFI bool "SPIFI Interface" - depends on LPC17_HAVE_SPIFI + depends on LPC17_40_HAVE_SPIFI default n -config LPC17_I2C0 +config LPC17_40_I2C0 bool "I2C0" default n -config LPC17_I2C1 +config LPC17_40_I2C1 bool "I2C1" default n -config LPC17_I2C2 +config LPC17_40_I2C2 bool "I2C2" default n -config LPC17_I2S +config LPC17_40_I2S bool "I2S" default n -config LPC17_TMR0 +config LPC17_40_TMR0 bool "Timer 0" default n -config LPC17_MAT0_PIN +config LPC17_40_MAT0_PIN int "TIM1 MAT0 Output Pin" default 1 range 1 4 - depends on LPC17_TMR0 + depends on LPC17_40_TMR0 ---help--- If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config LPC17_TMR1 +config LPC17_40_TMR1 bool "Timer 1" default n -config LPC17_TMR2 +config LPC17_40_TMR2 bool "Timer 2" default n -config LPC17_TMR3 +config LPC17_40_TMR3 bool "Timer 3" default n -config LPC17_RIT +config LPC17_40_RIT bool "RIT" default n -config LPC17_PWM0 +config LPC17_40_PWM0 bool "PWM0" + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X default n -config LPC17_PWM1 +config LPC17_40_PWM1 bool "PWM1" default n - depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC176X -config LPC17_PWM1_PIN +config LPC17_40_PWM1_PIN int "TIM1 PWM Output Pin" default 1 range 1 4 - depends on LPC17_PWM1 + depends on LPC17_40_PWM1 ---help--- If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config LPC17_MCPWM +config LPC17_40_MCPWM bool "MCPWM" default n depends on ARCH_FAMILY_LPC175X || ARCH_FAMILY_LPC176X -config LPC17_MCPWM1_PIN +config LPC17_40_MCPWM1_PIN int "TIM1 MCPWM Output Pin" default 1 range 1 4 - depends on LPC17_MCPWM + depends on LPC17_40_MCPWM ---help--- If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config LPC17_QEI +config LPC17_40_QEI bool "QEI" default n -config LPC17_RTC +config LPC17_40_RTC bool "RTC" default n -config LPC17_RTCEV +config LPC17_40_RTCEV bool "RTC event monitor" default n - depends on LPC17_RTC + depends on LPC17_40_RTC -config LPC17_WDT +config LPC17_40_WDT bool "WDT" default n -config LPC17_ADC +config LPC17_40_ADC bool "ADC" default n -config LPC17_DAC +config LPC17_40_DAC bool "DAC" default n -config LPC17_GPDMA +config LPC17_40_GPDMA bool "GPDMA" default n select ARCH_DMA -config LPC17_CRC +config LPC17_40_CRC bool "CRC engine" default n - depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X -config LPC17_FLASH +config LPC17_40_FLASH bool "FLASH" default n -config LPC17_EEPROM +config LPC17_40_EEPROM bool "EEPROM" default n - depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X + depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X || ARCH_FAMILY_LPC407X || ARCH_FAMILY_LPC408X -config LPC17_PROGMEM +config LPC17_40_PROGMEM bool PROGMEM default n select ARCH_HAVE_PROGMEM ---help--- - Use a part of LPC17xx's internal flash memory as a + Use a part of LPC17xx/LPC40xx's internal flash memory as a Memory-Technology-Device (MTD). endmenu menu "External Memory Configuration" -config LPC17_HAVE_EXTNAND +config LPC17_40_HAVE_EXTNAND bool -config LPC17_HAVE_EXTNOR +config LPC17_40_HAVE_EXTNOR bool -config LPC17_HAVE_EXTDRAM +config LPC17_40_HAVE_EXTDRAM bool -config LPC17_HAVE_EXTSRAM0 +config LPC17_40_HAVE_EXTSRAM0 bool -config LPC17_EXTNAND +config LPC17_40_EXTNAND bool "Configure external NAND" default n - depends on LPC17_HAVE_EXTNAND + depends on LPC17_40_HAVE_EXTNAND ---help--- Configure external NAND memory and, if applicable, map then external NAND into the memory map. -if LPC17_EXTNAND +if LPC17_40_EXTNAND -config LPC17_EXTNANDSIZE +config LPC17_40_EXTNANDSIZE int "External NAND size" default 0 ---help--- @@ -395,17 +456,17 @@ config LPC17_EXTNANDSIZE endif -config LPC17_EXTNOR +config LPC17_40_EXTNOR bool "Configure external NOR memory" default n - depends on LPC17_HAVE_EXTNOR + depends on LPC17_40_HAVE_EXTNOR ---help--- Configure external NOR memory and, if applicable, map then external NOR into the memory map. -if LPC17_EXTNOR +if LPC17_40_EXTNOR -config LPC17_EXTNORSIZE +config LPC17_40_EXTNORSIZE int "External NOR size" default 0 ---help--- @@ -413,18 +474,18 @@ config LPC17_EXTNORSIZE endif -config LPC17_EXTDRAM +config LPC17_40_EXTDRAM bool "Configure external DRAM" default n - depends on LPC17_HAVE_EXTDRAM + depends on LPC17_40_HAVE_EXTDRAM select ARCH_HAVE_SDRAM ---help--- Configure external DRAM memory and, if applicable, map then external DRAM into the memory map. -if LPC17_EXTDRAM +if LPC17_40_EXTDRAM -config LPC17_EXTDRAMSIZE +config LPC17_40_EXTDRAMSIZE int "External SDRAM size" default 0 ---help--- @@ -432,56 +493,56 @@ config LPC17_EXTDRAMSIZE choice prompt "SDRAM Width Selection" - default LPC17_SDRAM_16BIT + default LPC17_40_SDRAM_16BIT -config LPC17_SDRAM_8BIT +config LPC17_40_SDRAM_8BIT bool "8-bit" -config LPC17_SDRAM_16BIT +config LPC17_40_SDRAM_16BIT bool "16-bit" -config LPC17_SDRAM_32BIT +config LPC17_40_SDRAM_32BIT bool "32-bit" endchoice -config LPC17_EXTDRAMHEAP +config LPC17_40_EXTDRAMHEAP bool "Add external SDRAM to the heap" default y ---help--- Add the external SDRAM into the heap. -config LPC17_EXTDRAMHEAP_OFFSET +config LPC17_40_EXTDRAMHEAP_OFFSET int "DRAM heap offset" default 0 - depends on LPC17_EXTDRAMHEAP + depends on LPC17_40_EXTDRAMHEAP ---help--- Memory may be reserved at the beginning of DRAM for other purposes (for example for video framebuffers). Memory can similar be - reserved at the end of DRAM using LPC17_EXTDRAMSIZE. The amount to - be added to the heap will be from DRAM_BASE + LPC17_EXTDRAMHEAP_OFFSET - through DRAM_BASE + LPC17_EXTDRAMSIZE where (DRAM_BASE is the base + reserved at the end of DRAM using LPC17_40_EXTDRAMSIZE. The amount to + be added to the heap will be from DRAM_BASE + LPC17_40_EXTDRAMHEAP_OFFSET + through DRAM_BASE + LPC17_40_EXTDRAMSIZE where (DRAM_BASE is the base address of CS0). endif -config LPC17_EXTSRAM0 +config LPC17_40_EXTSRAM0 bool "Configure external SRAM (Bank 0)" default n - depends on LPC17_HAVE_EXTSRAM0 + depends on LPC17_40_HAVE_EXTSRAM0 ---help--- Configure external SRAM Bank 0 memory and, if applicable, map then external SRAM Bank 0 into the memory map. -if LPC17_EXTSRAM0 +if LPC17_40_EXTSRAM0 -config LPC17_EXTSRAM0SIZE +config LPC17_40_EXTSRAM0SIZE int "External SRAM size" default 0 ---help--- Size of the external SRAM Bank 0 in bytes. -config LPC17_EXTSRAM0HEAP +config LPC17_40_EXTSRAM0HEAP bool "Add external SRAM (Bank 0) to the heap" default y ---help--- @@ -491,11 +552,11 @@ endif endmenu menu "Serial driver options" - depends on LPC17_UART0 || LPC17_UART1 || LPC17_UART2 || LPC17_UART3 || LPC17_UART4 + depends on LPC17_40_UART0 || LPC17_40_UART1 || LPC17_40_UART2 || LPC17_40_UART3 || LPC17_40_UART4 -config LPC17_UART1_RINGINDICATOR +config LPC17_40_UART1_RINGINDICATOR bool "UART1 ring indicator" - depends on LPC17_UART1 + depends on LPC17_40_UART1 default n ---help--- Enable UART1 ring indicator @@ -503,21 +564,21 @@ config LPC17_UART1_RINGINDICATOR endmenu menu "ADC driver options" - depends on LPC17_ADC + depends on LPC17_40_ADC -config LPC17_ADC0_AVERAGE +config LPC17_40_ADC0_AVERAGE int "ADC0 average" default 200 -config LPC17_ADC0_MASK +config LPC17_40_ADC0_MASK hex "ADC0 mask" default 0x01 -config LPC17_ADC0_SPS +config LPC17_40_ADC0_SPS int "ADC0 SPS" default 1000 -config LPC17_ADC_CHANLIST +config LPC17_40_ADC_CHANLIST bool "Use ADC channel list" default n ---help--- @@ -532,80 +593,80 @@ config LPC17_ADC_CHANLIST triggering interrupt from the global DONE flag). If this option is enabled, then the platform specific code must do - two things: (1) define LPC17_ADC_NCHANNELS in the configuration file + two things: (1) define LPC17_40_ADC_NCHANNELS in the configuration file and (2) provide an array g_adc_chanlist[] with the channel numbers - matching the LPC17_ADC0_MASK within the board-specific library. + matching the LPC17_40_ADC0_MASK within the board-specific library. -config LPC17_ADC_BURSTMODE +config LPC17_40_ADC_BURSTMODE bool "One interrupt at the end of all ADC conversions" default n ---help--- Select this if you want to generate only one interrupt once all selected channels has been converted by the ADC -config LPC17_ADC_NCHANNELS +config LPC17_40_ADC_NCHANNELS int "ADC0 number of channels" - depends on LPC17_ADC_CHANLIST + depends on LPC17_40_ADC_CHANLIST default 0 ---help--- - If LPC17_ADC_CHANLIST is enabled, then the platform specific code - must do two things: (1) define LPC17_ADC_NCHANNELS in the configuration + If LPC17_40_ADC_CHANLIST is enabled, then the platform specific code + must do two things: (1) define LPC17_40_ADC_NCHANNELS in the configuration file and (2) provide an array g_adc_chanlist[] with the channel - numbers matching the LPC17_ADC0_MASK within the board-specific + numbers matching the LPC17_40_ADC0_MASK within the board-specific library. endmenu menu "CAN driver options" - depends on LPC17_CAN1 || LPC17_CAN2 + depends on LPC17_40_CAN1 || LPC17_40_CAN2 -config LPC17_CAN1_BAUD +config LPC17_40_CAN1_BAUD int "CAN1 BAUD" - depends on LPC17_CAN1 + depends on LPC17_40_CAN1 ---help--- - CAN1 BAUD rate. Required if LPC17_CAN1 is defined. + CAN1 BAUD rate. Required if LPC17_40_CAN1 is defined. -config LPC17_CAN2_BAUD +config LPC17_40_CAN2_BAUD int "CAN2 BAUD" - depends on LPC17_CAN2 + depends on LPC17_40_CAN2 ---help--- - CAN2 BAUD rate. Required if LPC17_CAN2 is defined. + CAN2 BAUD rate. Required if LPC17_40_CAN2 is defined. -config LPC17_CAN1_DIVISOR +config LPC17_40_CAN1_DIVISOR int "CAN1 CCLK divisor" - depends on LPC17_CAN1 + depends on LPC17_40_CAN1 default 4 ---help--- CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. -config LPC17_CAN2_DIVISOR +config LPC17_40_CAN2_DIVISOR int "CAN2 CCLK divisor" - depends on LPC17_CAN2 + depends on LPC17_40_CAN2 default 4 ---help--- CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. -config LPC17_CAN_TSEG1 +config LPC17_40_CAN_TSEG1 int "TSEG1 quanta" default 6 ---help--- The number of CAN time quanta in segment 1. Default: 6 -config LPC17_CAN_TSEG2 +config LPC17_40_CAN_TSEG2 int "TSEG2 quanta" default 4 ---help--- The number of CAN time quanta in segment 2. Default: 7 -config LPC17_CAN_SAM +config LPC17_40_CAN_SAM bool "CAN sampling" default n ---help--- The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line). -config LPC17_CAN_REGDEBUG +config LPC17_40_CAN_REGDEBUG bool "Register level debug" depends on DEBUG_CAN_INFO default n @@ -615,47 +676,47 @@ config LPC17_CAN_REGDEBUG endmenu -config LPC17_GPIOIRQ +config LPC17_40_GPIOIRQ bool "GPIO interrupt support" default n ---help--- Enable support for GPIO interrupts menu "I2C driver options" - depends on LPC17_I2C0 || LPC17_I2C1 || LPC17_I2C2 + depends on LPC17_40_I2C0 || LPC17_40_I2C1 || LPC17_40_I2C2 -config LPC17_I2C0_FREQUENCY +config LPC17_40_I2C0_FREQUENCY int "I2C0 frequency" - depends on LPC17_I2C0 + depends on LPC17_40_I2C0 default 100000 -config LPC17_I2C1_FREQUENCY +config LPC17_40_I2C1_FREQUENCY int "I2C1 frequency" - depends on LPC17_I2C1 + depends on LPC17_40_I2C1 default 100000 -config LPC17_I2C2_FREQUENCY +config LPC17_40_I2C2_FREQUENCY int "I2C2 frequency" - depends on LPC17_I2C2 + depends on LPC17_40_I2C2 default 100000 endmenu menu "SDCARD Configuration" - depends on LPC17_SDCARD + depends on LPC17_40_SDCARD -config LPC17_SDCARD_DMA +config LPC17_40_SDCARD_DMA bool "Support DMA data transfers" - default y if LPC17_GPDMA + default y if LPC17_40_GPDMA select SDIO_DMA - depends on LPC17_GPDMA + depends on LPC17_40_GPDMA ---help--- Support DMA data transfers. Enable SD card DMA data transfers. This is marginally optional. For most usages, SD accesses will cause data overruns if used without DMA. -config LPC17_SDCARD_WIDTH_D1_ONLY +config LPC17_40_SDCARD_WIDTH_D1_ONLY bool "Use D1 only" default n ---help--- @@ -666,63 +727,63 @@ config LPC17_SDCARD_WIDTH_D1_ONLY endmenu menu "Ethernet driver options" - depends on LPC17_ETHERNET + depends on LPC17_40_ETHERNET -config LPC17_PHY_AUTONEG +config LPC17_40_PHY_AUTONEG bool "Autonegotiation" ---help--- Enable auto-negotiation -config LPC17_PHY_SPEED100 +config LPC17_40_PHY_SPEED100 bool "100Mbit/Sec" - depends on !LPC17_PHY_AUTONEG + depends on !LPC17_40_PHY_AUTONEG ---help--- Select 100Mbit vs. 10Mbit speed. -config LPC17_PHY_FDUPLEX +config LPC17_40_PHY_FDUPLEX bool "Full duplex" - depends on !LPC17_PHY_AUTONEG + depends on !LPC17_40_PHY_AUTONEG ---help--- Select full (vs. half) duplex -config LPC17_EMACRAM_SIZE +config LPC17_40_EMACRAM_SIZE int "EMAC RAM Size" default 16384 ---help--- Size of EMAC RAM. Default: 16384 bytes -config LPC17_ETH_NTXDESC +config LPC17_40_ETH_NTXDESC int "Number of Tx descriptors" default 13 ---help--- Configured number of Tx descriptors. Default: 13 -config LPC17_ETH_NRXDESC +config LPC17_40_ETH_NRXDESC int "Number of Rx descriptors" default 13 ---help--- Configured number of Rx descriptors. Default: 13 -config LPC17_NET_WOL +config LPC17_40_NET_WOL bool "Wake-up on LAN" default n ---help--- Enable Wake-up on Lan (not fully implemented). -config LPC17_NET_REGDEBUG +config LPC17_40_NET_REGDEBUG bool "Ethernet register-level debug" depends on DEBUG_NET_INFO default n ---help--- Enable low level register debug. Also needs CONFIG_DEBUG_NET_INFO. -config LPC17_ETH_HASH +config LPC17_40_ETH_HASH bool "Hashing" default n ---help--- Enable receipt of near-perfect match frames. -config LPC17_MULTICAST +config LPC17_40_MULTICAST bool "Multicast" default y if NET_MCASTGROUP default n if !NET_MCASTGROUP @@ -733,35 +794,35 @@ config LPC17_MULTICAST endmenu menu "LCD device driver options" - depends on LPC17_LCD + depends on LPC17_40_LCD -config LPC17_LCD_VRAMBASE +config LPC17_40_LCD_VRAMBASE hex "Video RAM base address" default 0xa0010000 ---help--- Base address of the video RAM frame buffer. The default is - (LPC17_EXTDRAM_CS0 + 0x00010000) + (LPC17_40_EXTDRAM_CS0 + 0x00010000) -config LPC17_LCD_REFRESH_FREQ +config LPC17_40_LCD_REFRESH_FREQ int "LCD refesh rate (Hz)" default 50 ---help--- LCD refesh rate (Hz) -config LPC17_LCD_BACKLIGHT +config LPC17_40_LCD_BACKLIGHT bool "Enable backlight" default y ---help--- - Enable backlight support. If LPC17_LCD_BACKLIGHT is selected, then - the board-specific logic must provide this lpc17_backlight() + Enable backlight support. If LPC17_40_LCD_BACKLIGHT is selected, then + the board-specific logic must provide this lpc17_40_backlight() interface so that the LCD driver can turn the backlight on and off as necessary. You should select this option and implement - lpc17_backlight() if your board provides GPIO control over the + lpc17_40_backlight() if your board provides GPIO control over the backlight. This interface provides only ON/OFF control of the backlight. If you want finer control over the backlight level (for example, using PWM), then this interface would need to be extended. -config LPC17_LCD_TFTPANEL +config LPC17_40_LCD_TFTPANEL bool "TFT Panel" default y ---help--- @@ -771,103 +832,103 @@ config LPC17_LCD_TFTPANEL display panels require the digital color value of each pixel to be applied to the display data inputs. -config LPC17_LCD_MONOCHROME +config LPC17_40_LCD_MONOCHROME bool "Monochrome LCD" default n - depends on !LPC17_LCD_TFTPANEL + depends on !LPC17_40_LCD_TFTPANEL ---help--- STN LCD monochrome/color selection. Selects monochrome LCD. This selection has no meaning for a TFT panel. choice prompt "Bits per pixel" - default LPC17_LCD_BPP24 if LPC17_LCD_TFTPANEL - default LPC17_LCD_BPP16_565 if !LPC17_LCD_TFTPANEL + default LPC17_40_LCD_BPP24 if LPC17_40_LCD_TFTPANEL + default LPC17_40_LCD_BPP16_565 if !LPC17_40_LCD_TFTPANEL -config LPC17_LCD_BPP1 +config LPC17_40_LCD_BPP1 bool "1 bit per pixel" -config LPC17_LCD_BPP2 +config LPC17_40_LCD_BPP2 bool "2 bit per pixel" -config LPC17_LCD_BPP4 +config LPC17_40_LCD_BPP4 bool "4 bit per pixel" -config LPC17_LCD_BPP8 +config LPC17_40_LCD_BPP8 bool "8 bit per pixel" -config LPC17_LCD_BPP16 +config LPC17_40_LCD_BPP16 bool "16 bit per pixel" - depends on !LPC17_LCD_MONOCHROME + depends on !LPC17_40_LCD_MONOCHROME -config LPC17_LCD_BPP24 +config LPC17_40_LCD_BPP24 bool "24 bit per pixel" - depends on LPC17_LCD_TFTPANEL + depends on LPC17_40_LCD_TFTPANEL -config LPC17_LCD_BPP16_565 +config LPC17_40_LCD_BPP16_565 bool "16 bpp, 5:6:5 mode" - depends on !LPC17_LCD_MONOCHROME + depends on !LPC17_40_LCD_MONOCHROME -config LPC17_LCD_BPP12_444 +config LPC17_40_LCD_BPP12_444 bool "12 bpp, 4:4:4 mode" - depends on !LPC17_LCD_MONOCHROME + depends on !LPC17_40_LCD_MONOCHROME endchoice -config LPC17_LCD_BACKCOLOR +config LPC17_40_LCD_BACKCOLOR hex "Initial background color" default 0x0 ---help--- Initial background color -config LPC17_LCD_HWIDTH +config LPC17_40_LCD_HWIDTH int "Display width (pixels)" default 480 ---help--- Horizontal width the display in pixels -config LPC17_LCD_HPULSE +config LPC17_40_LCD_HPULSE int "Horizontal pulse" default 2 -config LPC17_LCD_HFRONTPORCH +config LPC17_40_LCD_HFRONTPORCH int "Horizontal front porch" default 5 -config LPC17_LCD_HBACKPORCH +config LPC17_40_LCD_HBACKPORCH int "Horizontal back porch" default 40 -config LPC17_LCD_VHEIGHT +config LPC17_40_LCD_VHEIGHT int "Display height (rows)" default 272 ---help--- Vertical height of the display in rows -config LPC17_LCD_VPULSE +config LPC17_40_LCD_VPULSE int "Vertical pulse" default 2 -config LPC17_LCD_VFRONTPORCH +config LPC17_40_LCD_VFRONTPORCH int "Vertical front porch" default 8 -config LPC17_LCD_VBACKPORCH +config LPC17_40_LCD_VBACKPORCH int "Vertical back porch" default 8 endmenu menu "USB device driver options" - depends on LPC17_USBDEV + depends on LPC17_40_USBDEV -config LPC17_USBDEV_EP0_MAXSIZE +config LPC17_40_USBDEV_EP0_MAXSIZE int "EP0 Max packet size" default 64 ---help--- Endpoint 0 maximum packet size. Default: 64 -config LPC17_USBDEV_FRAME_INTERRUPT +config LPC17_40_USBDEV_FRAME_INTERRUPT bool "USB frame interrupt" default n ---help--- @@ -875,37 +936,37 @@ config LPC17_USBDEV_FRAME_INTERRUPT handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. -config LPC17_USBDEV_EPFAST_INTERRUPT +config LPC17_40_USBDEV_EPFAST_INTERRUPT bool "EP fast interrupt handling" default n ---help--- Enable high priority interrupts. I have no idea why you might want to do that -config LPC17_USBDEV_NDMADESCRIPTORS +config LPC17_40_USBDEV_NDMADESCRIPTORS int "Number of DMA descriptors" default 8 ---help--- Number of DMA descriptors to allocate in SRAM. Default: 8 -config LPC17_USBDEV_DMA +config LPC17_40_USBDEV_DMA bool "Enable USB device DMA" default n ---help--- - Enable lpc17xx-specific DMA support + Enable lpc17xx/lpc40xx-specific DMA support -config LPC17_USBDEV_NOVBUS +config LPC17_40_USBDEV_NOVBUS bool "Disable VBUS support" default n ---help--- Define if the hardware implementation does not support the VBUS signal -config LPC17_USBDEV_NOLED +config LPC17_40_USBDEV_NOLED bool "Disable USB device LCD support" default n ---help--- Define if the hardware implementation does not support the LED output -config LPC17_USBDEV_REGDEBUG +config LPC17_40_USBDEV_REGDEBUG bool "Register level debug" depends on DEBUG_USB_INFO default n @@ -916,46 +977,46 @@ config LPC17_USBDEV_REGDEBUG endmenu menu "USB host driver options" - depends on LPC17_USBHOST + depends on LPC17_40_USBHOST -config LPC17_OHCIRAM_SIZE +config LPC17_40_OHCIRAM_SIZE int "OHCI RAM Size" default 16384 ---help--- Total size of OHCI RAM (in AHB SRAM Bank 1). Default: 16384 -config LPC17_USBHOST_NEDS +config LPC17_40_USBHOST_NEDS int "Number of Endpoint Descriptors" default 2 ---help--- Number of endpoint descriptors. Default: 2 -config LPC17_USBHOST_NTDS +config LPC17_40_USBHOST_NTDS int "Number of transfer descriptors" default 3 ---help--- Number of transfer descriptors. Default: 3 -config LPC17_USBHOST_TDBUFFERS +config LPC17_40_USBHOST_TDBUFFERS int "Number of descriptor buffers" default 2 ---help--- Number of transfer descriptor buffers. Default: 2 -config LPC17_USBHOST_TDBUFSIZE +config LPC17_40_USBHOST_TDBUFSIZE int "Descriptor buffer size" default 128 ---help--- Size of one transfer descriptor buffer. Default 128 -config LPC17_USBHOST_IOBUFSIZE +config LPC17_40_USBHOST_IOBUFSIZE int "I/O buffer size" default 512 ---help--- Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. -config LPC17_USBHOST_NPREALLOC +config LPC17_40_USBHOST_NPREALLOC int "Max concurrent transfers" default 8 if USBHOST_HUB default 4 if !USBHOST_HUB @@ -964,7 +1025,7 @@ config LPC17_USBHOST_NPREALLOC concurrent data transfers. This number limits that number of concurrent asynchronous IN endpoint transfer that can be supported. -config LPC17_USBHOST_REGDEBUG +config LPC17_40_USBHOST_REGDEBUG bool "Register level debug" depends on DEBUG_USB_INFO default n @@ -975,9 +1036,9 @@ config LPC17_USBHOST_REGDEBUG endmenu menu "Memory-Technolgy-Device Options (PROGMEM)" - depends on LPC17_PROGMEM + depends on LPC17_40_PROGMEM -config LPC17_PROGMEM_NSECTORS +config LPC17_40_PROGMEM_NSECTORS int "Size in 32 kB sectors" default 2 ---help--- diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx_40xx/Make.defs similarity index 74% rename from arch/arm/src/lpc17xx/Make.defs rename to arch/arm/src/lpc17xx_40xx/Make.defs index 446330c022a..b4004d03a50 100644 --- a/arch/arm/src/lpc17xx/Make.defs +++ b/arch/arm/src/lpc17xx_40xx/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/lpc17xx/Make.defs +# arch/arm/src/lpc17xx_40xx/Make.defs # # Copyright (C) 2010-2011, 2013-2015, 2018 Gregory Nutt. All rights reserved. # Author: Gregory Nutt @@ -80,7 +80,7 @@ endif # up_initialize(). Then this stub would not be needed. ifeq ($(CONFIG_NET),y) -ifneq ($(CONFIG_LPC17_ETHERNET),y) +ifneq ($(CONFIG_LPC17_40_ETHERNET),y) CMN_CSRCS += up_etherstub.c endif endif @@ -94,90 +94,90 @@ endif CHIP_ASRCS = -CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_clrpend.c -CHIP_CSRCS += lpc17_gpio.c lpc17_i2c.c lpc17_irq.c lpc17_lowputc.c -CHIP_CSRCS += lpc17_serial.c lpc17_spi.c lpc17_ssp.c lpc17_start.c +CHIP_CSRCS = lpc17_40_allocateheap.c lpc17_40_clockconfig.c lpc17_40_clrpend.c +CHIP_CSRCS += lpc17_40_gpio.c lpc17_40_i2c.c lpc17_40_irq.c lpc17_40_lowputc.c +CHIP_CSRCS += lpc17_40_serial.c lpc17_40_spi.c lpc17_40_ssp.c lpc17_40_start.c # Configuration-dependent LPC17xx files ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += lpc17_idle.c +CHIP_CSRCS += lpc17_40_idle.c endif ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += lpc17_timerisr.c +CHIP_CSRCS += lpc17_40_timerisr.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += lpc17_userspace.c lpc17_mpuinit.c +CHIP_CSRCS += lpc17_40_userspace.c lpc17_40_mpuinit.c endif -ifeq ($(CONFIG_LPC17_EMC),y) -CHIP_CSRCS += lpc17_emc.c +ifeq ($(CONFIG_LPC17_40_EMC),y) +CHIP_CSRCS += lpc17_40_emc.c endif -ifeq ($(CONFIG_LPC17_GPIOIRQ),y) -CHIP_CSRCS += lpc17_gpioint.c +ifeq ($(CONFIG_LPC17_40_GPIOIRQ),y) +CHIP_CSRCS += lpc17_40_gpioint.c endif ifeq ($(CONFIG_DEBUG_GPIO_INFO),y) -CHIP_CSRCS += lpc17_gpiodbg.c +CHIP_CSRCS += lpc17_40_gpiodbg.c endif -ifeq ($(CONFIG_LPC17_LCD),y) -CHIP_CSRCS += lpc17_lcd.c +ifeq ($(CONFIG_LPC17_40_LCD),y) +CHIP_CSRCS += lpc17_40_lcd.c endif ifeq ($(CONFIG_USBDEV),y) -CHIP_CSRCS += lpc17_usbdev.c +CHIP_CSRCS += lpc17_40_usbdev.c endif ifeq ($(CONFIG_USBHOST),y) -CHIP_CSRCS += lpc17_usbhost.c +CHIP_CSRCS += lpc17_40_usbhost.c endif -ifeq ($(CONFIG_LPC17_GPDMA),y) -CHIP_CSRCS += lpc17_gpdma.c +ifeq ($(CONFIG_LPC17_40_GPDMA),y) +CHIP_CSRCS += lpc17_40_gpdma.c endif -ifeq ($(CONFIG_LPC17_SDCARD),y) -CHIP_CSRCS += lpc17_sdcard.c +ifeq ($(CONFIG_LPC17_40_SDCARD),y) +CHIP_CSRCS += lpc17_40_sdcard.c endif ifeq ($(CONFIG_NET),y) -ifeq ($(CONFIG_LPC17_ETHERNET),y) -CHIP_CSRCS += lpc17_ethernet.c +ifeq ($(CONFIG_LPC17_40_ETHERNET),y) +CHIP_CSRCS += lpc17_40_ethernet.c endif endif ifeq ($(CONFIG_CAN),y) -CHIP_CSRCS += lpc17_can.c +CHIP_CSRCS += lpc17_40_can.c endif -ifeq ($(CONFIG_LPC17_ADC),y) -CHIP_CSRCS += lpc17_adc.c +ifeq ($(CONFIG_LPC17_40_ADC),y) +CHIP_CSRCS += lpc17_40_adc.c endif -ifeq ($(CONFIG_LPC17_DAC),y) -CHIP_CSRCS += lpc17_dac.c +ifeq ($(CONFIG_LPC17_40_DAC),y) +CHIP_CSRCS += lpc17_40_dac.c endif -ifeq ($(CONFIG_LPC17_RTC),y) +ifeq ($(CONFIG_LPC17_40_RTC),y) CHIP_CSRCS += lpc176x_rtc.c endif -ifeq ($(CONFIG_LPC17_PWM1),y) -CHIP_CSRCS += lpc17_pwm.c +ifeq ($(CONFIG_LPC17_40_PWM1),y) +CHIP_CSRCS += lpc17_40_pwm.c endif -ifeq ($(CONFIG_LPC17_MCPWM),y) -CHIP_CSRCS += lpc17_mcpwm.c +ifeq ($(CONFIG_LPC17_40_MCPWM),y) +CHIP_CSRCS += lpc17_40_mcpwm.c endif -ifeq ($(CONFIG_LPC17_TMR0),y) -CHIP_CSRCS += lpc17_timer.c +ifeq ($(CONFIG_LPC17_40_TMR0),y) +CHIP_CSRCS += lpc17_40_timer.c endif ifeq ($(CONFIG_MTD_PROGMEM),y) -CHIP_CSRCS += lpc17_progmem.c +CHIP_CSRCS += lpc17_40_progmem.c endif diff --git a/arch/arm/src/lpc17xx/chip.h b/arch/arm/src/lpc17xx_40xx/chip.h similarity index 86% rename from arch/arm/src/lpc17xx/chip.h rename to arch/arm/src/lpc17xx_40xx/chip.h index 391901a2717..f4df7fd8c27 100644 --- a/arch/arm/src/lpc17xx/chip.h +++ b/arch/arm/src/lpc17xx_40xx/chip.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/chip.h + * arch/arm/src/lpc17xx_40xx/chip.h * * Copyright (C) 2010-2011, 2013, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_H -#define __ARCH_ARM_SRC_LPC17XX_CHIP_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H /************************************************************************************ * Included Files @@ -45,28 +45,28 @@ /* Include the chip capabilities file */ -#include +#include /* Include the chip interrupt definition file */ -#include +#include /* Include the memory map file. Other chip hardware files should then include * this file for the proper setup. */ -#include "hardware/lpc17_memorymap.h" +#include "hardware/lpc17_40_memorymap.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ /* Provide the required number of peripheral interrupt vector definitions as well. - * The definition LPC17_IRQ_NEXTINT simply comes from the chip-specific IRQ header - * file included by arch/lpc17xx/irq.h. + * The definition LPC17_40_IRQ_NEXTINT simply comes from the chip-specific IRQ header + * file included by arch/lpc17xx_40xx/irq.h. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS LPC17_IRQ_NEXTINT +#define ARMV7M_PERIPHERAL_INTERRUPTS LPC17_40_IRQ_NEXTINT /* Vector Table Offset Register (VECTAB). Redefine the mask defined in * arch/arm/src/armv7-m/nvic.h; The LPC178x/7x User manual definitions @@ -78,4 +78,4 @@ #undef NVIC_VECTAB_TBLOFF_MASK #define NVIC_VECTAB_TBLOFF_MASK (0x3fffff00) -#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h new file mode 100644 index 00000000000..14f8a4c3dcd --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h @@ -0,0 +1,136 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define LPC17_40_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC17_40_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ +#define LPC17_40_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ +#define LPC17_40_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ +# define LPC17_40_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ +# define LPC17_40_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ +#define LPC17_40_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ +#define LPC17_40_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ +# define LPC17_40_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ +# define LPC17_40_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ +# define LPC17_40_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ +#define LPC17_40_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC17_40_SCS_BASE 0xe000e000 +#define LPC17_40_DEBUGMCU_BASE 0xe0042000 + +/* AHB SRAM Bank sizes **************************************************************/ + +#define LPC17_40_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ +#define LPC17_40_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ + +/* APB0 Peripherals *****************************************************************/ + +#define LPC17_40_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ +#define LPC17_40_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ +#define LPC17_40_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ +#define LPC17_40_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ +#define LPC17_40_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ + /* -0x40017fff: Reserved */ +#define LPC17_40_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ +#define LPC17_40_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ +#define LPC17_40_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ +#define LPC17_40_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ +#define LPC17_40_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ +#define LPC17_40_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_40_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ +#define LPC17_40_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ +#define LPC17_40_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ +#define LPC17_40_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ +#define LPC17_40_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ +#define LPC17_40_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ +#define LPC17_40_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ + /* -0x4005bfff: Reserved */ +#define LPC17_40_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ + /* -0x4007ffff: Reserved */ + +/* APB1 Peripherals *****************************************************************/ + + /* -0x40087fff: Reserved */ +#define LPC17_40_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ +#define LPC17_40_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ +#define LPC17_40_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ +#define LPC17_40_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ +#define LPC17_40_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ +#define LPC17_40_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ +#define LPC17_40_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ + /* -0x400a7fff: Reserved */ +#define LPC17_40_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ + /* -0x400affff: Reserved */ +#define LPC17_40_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ + /* -0x400b7fff: Reserved */ +#define LPC17_40_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ +#define LPC17_40_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ + /* -0x400fbfff: Reserved */ +#define LPC17_40_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC17_40_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ +#define LPC17_40_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ +#define LPC17_40_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconfig.h similarity index 98% rename from arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconfig.h index 3adb293adc9..d1f7b84c4b9 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconfig.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconfig.h * * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONFIG_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONFIG_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_PINCONFIG_H /************************************************************************************ * Included Files @@ -231,4 +231,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONFIG_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_PINCONFIG_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconn.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconn.h new file mode 100644 index 00000000000..8354530a6b4 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconn.h @@ -0,0 +1,635 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc176x_pinconn.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_PINCONN_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_PINCONN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ +#define LPC17_40_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ +#define LPC17_40_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ +#define LPC17_40_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ +#define LPC17_40_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ +#define LPC17_40_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ +#define LPC17_40_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ +#define LPC17_40_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ +#define LPC17_40_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ +#define LPC17_40_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ +#define LPC17_40_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ +#define LPC17_40_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ +#define LPC17_40_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ +#define LPC17_40_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ +#define LPC17_40_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ +#define LPC17_40_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ +#define LPC17_40_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ +#define LPC17_40_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ +#define LPC17_40_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ +#define LPC17_40_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ +#define LPC17_40_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ +#define LPC17_40_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ +#define LPC17_40_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ +#define LPC17_40_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_PINCONN_PINSEL0 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL0_OFFSET) +#define LPC17_40_PINCONN_PINSEL1 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL1_OFFSET) +#define LPC17_40_PINCONN_PINSEL2 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL2_OFFSET) +#define LPC17_40_PINCONN_PINSEL3 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL3_OFFSET) +#define LPC17_40_PINCONN_PINSEL4 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL4_OFFSET) +#define LPC17_40_PINCONN_PINSEL7 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL7_OFFSET) +#define LPC17_40_PINCONN_PINSEL8 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL8_OFFSET) +#define LPC17_40_PINCONN_PINSEL9 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL9_OFFSET) +#define LPC17_40_PINCONN_PINSEL10 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINSEL10_OFFSET) +#define LPC17_40_PINCONN_PINMODE0 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE0_OFFSET) +#define LPC17_40_PINCONN_PINMODE1 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE1_OFFSET) +#define LPC17_40_PINCONN_PINMODE2 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE2_OFFSET) +#define LPC17_40_PINCONN_PINMODE3 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE3_OFFSET) +#define LPC17_40_PINCONN_PINMODE4 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE4_OFFSET) +#define LPC17_40_PINCONN_PINMODE5 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE5_OFFSET) +#define LPC17_40_PINCONN_PINMODE6 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE6_OFFSET) +#define LPC17_40_PINCONN_PINMODE7 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE7_OFFSET) +#define LPC17_40_PINCONN_PINMODE9 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_PINMODE9_OFFSET) +#define LPC17_40_PINCONN_ODMODE0 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_ODMODE0_OFFSET) +#define LPC17_40_PINCONN_ODMODE1 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_ODMODE1_OFFSET) +#define LPC17_40_PINCONN_ODMODE2 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_ODMODE2_OFFSET) +#define LPC17_40_PINCONN_ODMODE3 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_ODMODE3_OFFSET) +#define LPC17_40_PINCONN_ODMODE4 (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_ODMODE4_OFFSET) +#define LPC17_40_PINCONN_I2CPADCFG (LPC17_40_PINCONN_BASE+LPC17_40_PINCONN_I2CPADCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ + +#define PINCONN_PINSEL_GPIO (0) +#define PINCONN_PINSEL_ALT1 (1) +#define PINCONN_PINSEL_ALT2 (2) +#define PINCONN_PINSEL_ALT3 (3) +#define PINCONN_PINSEL_MASK (3) + +#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) +#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) + +#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ +#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) +#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ +#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) +#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ +#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) +#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ +#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) +#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ +#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) +#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ +#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) +#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ +#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) +#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ +#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) +#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ +#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) +#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ +#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) +#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ +#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) +#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ +#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ +#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) + +/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ + +#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ +#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) +#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ +#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) +#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ +#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) +#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ +#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) +#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ +#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) +#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ +#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) +#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ +#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) +#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ +#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) +#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ +#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) +#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ +#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) +#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ +#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) +#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ +#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) +#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ +#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) +#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) +#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) + /* Bits 30-31: Reserved */ +/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ + +#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) +#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) +#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) +#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) +#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) + +/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ + +#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) +#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) +#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ +#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) +#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ +#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) +#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ +#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) +#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ +#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) +#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ +#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) +#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ +#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) +#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ +#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) +#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ +#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) +#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ +#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) +#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ +#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) +#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ +#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) +#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ +#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) +#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ +#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) +#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ +#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) + +/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ + +#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) +#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) +#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) +#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) +#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) +#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) +#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ +#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) +#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) +#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ +#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) +#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ +#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) +#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ +#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) +#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ +#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) +#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ +#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) +#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ +#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ + +#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-17: Reserved */ +#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ +#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) +#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ +#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ +/* No description of bits -- Does this register exist? */ + +/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ + +#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-23: Reserved */ +#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ +#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) +#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ +#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ + /* Bits 0-2: Reserved */ +#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ + /* Bits 4-31: Reserved */ +/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ + +#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ +#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ +#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ +#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ +#define PINCONN_PINMODE_MASK (3) + +#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) +#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) + +#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ +#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) +#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ +#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) +#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ +#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) +#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ +#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) +#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ +#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) +#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ +#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) +#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ +#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) +#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ +#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) +#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ +#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) +#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ +#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) +#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ +#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) +#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ +#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ +#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) + +/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ + +#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ +#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) +#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ +#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) +#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ +#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) +#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ +#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) +#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ +#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) +#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ +#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) +#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ +#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) +#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ +#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) +#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ +#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) +#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ +#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) +#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ +#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ + +#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ +#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) +#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ +#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ +#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ +#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) +#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ +#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) +#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ +#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ +#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) +#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ +#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) + +/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ + +#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ +#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) +#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ +#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) +#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ +#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) +#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ +#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) +#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ +#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) +#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ +#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) +#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ +#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) +#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ +#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) +#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ +#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) +#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ +#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) +#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ +#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) +#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ +#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) +#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ +#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) +#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ +#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) +#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ +#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) +#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ +#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) + +/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ + +#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ +#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) +#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ +#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) +#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ +#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) +#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ +#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) +#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ +#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) +#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ +#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) +#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ +#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) +#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ +#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) +#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ +#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) +#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ +#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) +#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ +#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) +#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ +#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) +#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ +#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) +#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ +#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Mode select register 5 (PINMODE5: 0x4002c054) + * Pin Mode select register 6 (PINMODE6: 0x4002c058) + * No bit definitions -- do these registers exist? + */ + +#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ + +#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-17: Reserved */ +#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ +#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) +#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ +#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ +/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ + +#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-23: Reserved */ +#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ +#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) +#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ +#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ + +#define PINCONN_ODMODE0_P0(n) (1 << (n)) + +#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ +#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ +#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ +#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ +#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ +#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ +#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ +#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ +#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ +#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ +#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ +#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ + /* Bits 12-14: Reserved */ +#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ +#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ +#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ +#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ +#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ +#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ +#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ +#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ +#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ +#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ +#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ +#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ + /* Bits 27-28: Reserved */ +#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ +#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ + /* Bit 31: Reserved */ +/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ + +#define PINCONN_ODMODE1_P1(n) (1 << (n)) + +#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ +#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ + /* Bits 2-3: Reserved */ +#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ + /* Bits 5-7: Reserved */ +#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ +#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ +#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ + /* Bits 11-13: Reserved */ +#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ +#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ +#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ +#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ +#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ +#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ +#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ +#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ +#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ +#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ +#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ +#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ +#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ +#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ +#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ +#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ +#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ +#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ + +/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ + +#define PINCONN_ODMODE2_P2(n) (1 << (n)) + +#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ +#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ +#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ +#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ +#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ +#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ +#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ +#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ +#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ +#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ +#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ +#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ +#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ +#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ + /* Bits 14-31: Reserved */ +/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ + +#define PINCONN_ODMODE3_P3(n) (1 << (n)) + /* Bits 0-24: Reserved */ +#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ +#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ + /* Bits 17-31: Reserved */ +/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ + +#define PINCONN_ODMODE4_P4(n) (1 << (n)) + /* Bits 0-27: Reserved */ +#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ +#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ + /* Bits 30-31: Reserved */ +/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ + +#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch + * filtering/slew rate control */ +#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch + * filtering/slew rate control */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_PINCONN_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h new file mode 100644 index 00000000000..9bec63ef559 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h @@ -0,0 +1,494 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_SYSCON_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_SYSCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Flash accelerator module */ + +#define LPC17_40_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_40_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_40_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ +#define LPC17_40_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ +#define LPC17_40_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ +#define LPC17_40_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ + +#define LPC17_40_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ +#define LPC17_40_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ +#define LPC17_40_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ +#define LPC17_40_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_40_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ +#define LPC17_40_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_40_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ +#define LPC17_40_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_40_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ + +/* System control registers -- External Interrupts */ + +#define LPC17_40_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ + +#define LPC17_40_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ +#define LPC17_40_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ + +/* System control registers -- Reset */ + +#define LPC17_40_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_40_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ + +/* More clocking and power control -- Clock dividers */ + +#define LPC17_40_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */ +#define LPC17_40_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */ + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_40_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ + +/* DMA Request Select Register */ + +#define LPC17_40_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ + +/* More clocking and power control -- Utility */ + +#define LPC17_40_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ + +/* Register addresses ***************************************************************/ +/* Flash accelerator module */ + +#define LPC17_40_SYSCON_FLASHCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_FLASHCFG_OFFSET) + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_40_SYSCON_MEMMAP (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_MEMMAP_OFFSET) + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_40_SYSCON_PLL0CON (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0CON_OFFSET) +#define LPC17_40_SYSCON_PLL0CFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0CFG_OFFSET) +#define LPC17_40_SYSCON_PLL0STAT (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0STAT_OFFSET) +#define LPC17_40_SYSCON_PLL0FEED (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0FEED_OFFSET) + +#define LPC17_40_SYSCON_PLL1CON (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1CON_OFFSET) +#define LPC17_40_SYSCON_PLL1CFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1CFG_OFFSET) +#define LPC17_40_SYSCON_PLL1STAT (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1STAT_OFFSET) +#define LPC17_40_SYSCON_PLL1FEED (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1FEED_OFFSET) + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_40_SYSCON_PCON (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCON_OFFSET) +#define LPC17_40_SYSCON_PCONP (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCONP_OFFSET) + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_40_SYSCON_CCLKCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CCLKCFG_OFFSET) +#define LPC17_40_SYSCON_USBCLKCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_USBCLKCFG_OFFSET) + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_40_SYSCON_CLKSRCSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CLKSRCSEL_OFFSET) + +/* System control registers -- External Interrupts */ + +#define LPC17_40_SYSCON_EXTINT (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EXTINT_OFFSET) + +#define LPC17_40_SYSCON_EXTMODE (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EXTMODE_OFFSET) +#define LPC17_40_SYSCON_EXTPOLAR (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EXTPOLAR_OFFSET) + +/* System control registers -- Reset */ + +#define LPC17_40_SYSCON_RSID (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_RSID_OFFSET) + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_40_SYSCON_SCS (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_SCS_OFFSET) + +/* More clocking and power control -- Clock dividers */ + +#define LPC17_40_SYSCON_PCLKSEL0 (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCLKSEL0_OFFSET) +#define LPC17_40_SYSCON_PCLKSEL1 (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCLKSEL1_OFFSET) + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_40_SYSCON_USBINTST (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_USBINTST_OFFSET) + +/* DMA Request Select Register */ + +#define LPC17_40_SYSCON_DMAREQSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_DMAREQSEL_OFFSET) + +/* More clocking and power control -- Utility */ + +#define LPC17_40_SYSCON_CLKOUTCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CLKOUTCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Flash accelerator module */ + /* Bits 0-11: Reserved */ +#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ +#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) +# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock + * (Up to 120 Mhz for LPC1759/69 only */ +# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ + /* Bits 16-31: Reserved */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: + * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. + * 1:User mode. The on-chip Flash memory is mapped to address 0 */ + /* Bits 1-31: Reserved */ + +/* Clocking and power control -- Clock source selection */ + +#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */ +#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT) +# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ +# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ +# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */ + /* Bits 2-31: Reserved */ + +/* Clocking and power control - Phase locked loops */ +/* PLL0/1 Control register */ + +#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */ +#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */ + /* Bits 2-31: Reserved */ +/* PLL0 Configuration register */ + +#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */ +#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT) + /* Bit 15: Reserved */ +#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */ +#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT) + /* Bits 24-31: Reserved */ +/* PLL1 Configuration register */ + +#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */ +#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT) +#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */ +#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT) + /* Bits 7-31: Reserved */ +/* PLL0 Status register */ + +#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ +#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) + /* Bit 15: Reserved */ +#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ +#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) +#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ +#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ +#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ + /* Bits 27-31: Reserved */ +/* PLL1 Status register */ + +#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ +#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) +#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ +#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) + /* Bit 7: Reserved */ +#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ +#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ +#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ + /* Bits 11-31: Reserved */ +/* PLL0/1 Feed register */ + +#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ +#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) + /* Bits 8-31: Reserved */ +/* Clocking and power control -- Clock dividers */ +/* CPU Clock Configuration register */ + +#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */ +#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT) +# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ + /* Bits 8-31: Reserved */ +/* USB Clock Configuration register */ + +#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */ +#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT) +# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */ +# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */ +# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */ + /* Bits 8-31: Reserved */ +/* Peripheral Clock Selection registers 0 and 1 */ + +#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */ +#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */ +#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */ +#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ +#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */ +#define SYSCON_PCLKSEL_MASK (3) + +#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */ +#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT) +#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */ +#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT) +#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */ +#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT) +#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ +#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT) +#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ +#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) + /* Bits 10-11: Reserved */ +#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */ +#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT) +#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */ +#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT) +#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */ +#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT) + /* Bits 18-19: Reserved */ +#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */ +#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT) +#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */ +#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT) +#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */ +#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT) +#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */ +#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT) +#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */ +#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT) +#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */ +#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT) + +#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */ +#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT) +#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */ +#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT) +#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */ +#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT) +#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */ +#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT) + /* Bits 8-9: Reserved */ +#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */ +#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT) +#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */ +#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT) +#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */ +#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT) +#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ +#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) +#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ +#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) +#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */ +#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT) +#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */ +#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT) + /* Bits 24-25: Reserved */ +#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */ +#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT) +#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */ +#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT) +#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */ +#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT) + +/* Clocking and power control - Peripheral power control registers */ +/* Power Control Register */ + +#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ +#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ +#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ +#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ +#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ + /* Bits 5-7: Reserved */ +#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ +#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ +#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ +#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ + /* Bits 12-31: Reserved */ +/* Power Control for Peripherals Register */ + + /* Bit 0: Reserved */ +#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ +#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ +#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ +#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ + /* Bit 5: Reserved */ +#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ +#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ +#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ +#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ +#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ + /* Bit 11: Reserved */ +#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ +#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ +#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ +#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ +#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ +#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ +#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ +#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ + /* Bit 20: Reserved */ +#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ +#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ +#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ +#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ +#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ +#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ +#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ + /* Bit 28: Reserved */ +#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ +#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ +#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ + +/* More clocking and power control -- Utility */ + +#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ +#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) +# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ +# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ +# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ +# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ +# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ +#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ +#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) +# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ +#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ +#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ + /* Bits 10-31: Reserved */ +/* System control registers -- External Interrupts */ +/* External Interrupt Flag register */ + +#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ +#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ +#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ +#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ + /* Bits 4-31: Reserved */ +/* External Interrupt Mode register */ + +#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ +#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ +#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ +#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ + /* Bits 4-31: Reserved */ +/* External Interrupt Polarity register */ + +#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ + /* Bits 4-31: Reserved */ +/* System control registers -- Reset */ +/* Reset Source Identification Register */ + +#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ +#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ +#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ +#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ + /* Bits 4-31: Reserved */ +/* System control registers -- Syscon Miscellaneous Registers */ + + /* Bits 0-3: Reserved */ +#define SYSCON_SCS_OSCRS (1 << 4) /* Bit 4: Main oscillator range select */ +#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ +#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ + /* Bits 7-31: Reserved */ +/* Device Interrupt Registers */ +/* USB Interrupt Status register */ + +#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ +#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ +#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ +#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ +#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ +#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ +#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ + /* Bit 7: Reserved */ +#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ + /* Bits 9-30: Reserved */ +#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ + +/* DMA Request Select Register */ + +#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */ +#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */ +#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */ +#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */ +#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */ +#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */ +#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */ +#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */ + /* Bits 8-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_SYSCON_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h new file mode 100644 index 00000000000..b335b94f43a --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h @@ -0,0 +1,375 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_IOCON_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_IOCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_IOCON_PP_OFFSET(p) ((unsigned int)(p) << 2) +#define LPC17_40_IOCON_PP0_OFFSET (0x0000) /* IOCON Port(n) register 0 */ +#define LPC17_40_IOCON_PP1_OFFSET (0x0004) /* IOCON Port(n) register 1 */ +#define LPC17_40_IOCON_PP2_OFFSET (0x0008) /* IOCON Port(n) register 2 */ +#define LPC17_40_IOCON_PP3_OFFSET (0x000c) /* IOCON Port(n) register 3 */ +#define LPC17_40_IOCON_PP4_OFFSET (0x0010) /* IOCON Port(n) register 4 */ +#define LPC17_40_IOCON_PP5_OFFSET (0x0014) /* IOCON Port(n) register 5 */ +#define LPC17_40_IOCON_PP6_OFFSET (0x0018) /* IOCON Port(n) register 6 */ +#define LPC17_40_IOCON_PP7_OFFSET (0x001c) /* IOCON Port(n) register 7 */ +#define LPC17_40_IOCON_PP8_OFFSET (0x0020) /* IOCON Port(n) register 8 */ +#define LPC17_40_IOCON_PP9_OFFSET (0x0024) /* IOCON Port(n) register 9 */ +#define LPC17_40_IOCON_PP10_OFFSET (0x0028) /* IOCON Port(n) register 10 */ +#define LPC17_40_IOCON_PP11_OFFSET (0x002c) /* IOCON Port(n) register 11 */ +#define LPC17_40_IOCON_PP12_OFFSET (0x0030) /* IOCON Port(n) register 12 */ +#define LPC17_40_IOCON_PP13_OFFSET (0x0034) /* IOCON Port(n) register 13 */ +#define LPC17_40_IOCON_PP14_OFFSET (0x0038) /* IOCON Port(n) register 14 */ +#define LPC17_40_IOCON_PP15_OFFSET (0x003c) /* IOCON Port(n) register 15 */ +#define LPC17_40_IOCON_PP16_OFFSET (0x0040) /* IOCON Port(n) register 16 */ +#define LPC17_40_IOCON_PP17_OFFSET (0x0044) /* IOCON Port(n) register 17 */ +#define LPC17_40_IOCON_PP18_OFFSET (0x0048) /* IOCON Port(n) register 18 */ +#define LPC17_40_IOCON_PP19_OFFSET (0x004c) /* IOCON Port(n) register 19 */ +#define LPC17_40_IOCON_PP20_OFFSET (0x0050) /* IOCON Port(n) register 20 */ +#define LPC17_40_IOCON_PP21_OFFSET (0x0054) /* IOCON Port(n) register 21 */ +#define LPC17_40_IOCON_PP22_OFFSET (0x0058) /* IOCON Port(n) register 22 */ +#define LPC17_40_IOCON_PP23_OFFSET (0x005c) /* IOCON Port(n) register 23 */ +#define LPC17_40_IOCON_PP24_OFFSET (0x0060) /* IOCON Port(n) register 24 */ +#define LPC17_40_IOCON_PP25_OFFSET (0x0064) /* IOCON Port(n) register 25 */ +#define LPC17_40_IOCON_PP26_OFFSET (0x0068) /* IOCON Port(n) register 26 */ +#define LPC17_40_IOCON_PP27_OFFSET (0x006c) /* IOCON Port(n) register 27 */ +#define LPC17_40_IOCON_PP28_OFFSET (0x0070) /* IOCON Port(n) register 28 */ +#define LPC17_40_IOCON_PP29_OFFSET (0x0074) /* IOCON Port(n) register 29 */ +#define LPC17_40_IOCON_PP30_OFFSET (0x0078) /* IOCON Port(n) register 30 */ +#define LPC17_40_IOCON_PP31_OFFSET (0x007c) /* IOCON Port(n) register 31 */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_IOCON_P_BASE(b) (LPC17_40_IOCON_BASE + ((unsigned int)(b) << 7)) +#define LPC17_40_IOCON_P0_BASE (LPC17_40_IOCON_BASE + 0x0000) +#define LPC17_40_IOCON_P1_BASE (LPC17_40_IOCON_BASE + 0x0080) +#define LPC17_40_IOCON_P2_BASE (LPC17_40_IOCON_BASE + 0x0100) +#define LPC17_40_IOCON_P3_BASE (LPC17_40_IOCON_BASE + 0x0180) +#define LPC17_40_IOCON_P4_BASE (LPC17_40_IOCON_BASE + 0x0200) +#define LPC17_40_IOCON_P5_BASE (LPC17_40_IOCON_BASE + 0x0280) + +#define LPC17_40_IOCON_P(b,p) (LPC17_40_IOCON_P_BASE(b) + LPC17_40_IOCON_PP_OFFSET(p)) + +#define LPC17_40_IOCON_P0_0 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP0_OFFSET) +#define LPC17_40_IOCON_P0_1 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP1_OFFSET) +#define LPC17_40_IOCON_P0_2 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP2_OFFSET) +#define LPC17_40_IOCON_P0_3 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP3_OFFSET) +#define LPC17_40_IOCON_P0_4 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP4_OFFSET) +#define LPC17_40_IOCON_P0_5 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP5_OFFSET) +#define LPC17_40_IOCON_P0_6 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP6_OFFSET) +#define LPC17_40_IOCON_P0_7 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP7_OFFSET) +#define LPC17_40_IOCON_P0_8 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP8_OFFSET) +#define LPC17_40_IOCON_P0_9 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP9_OFFSET) +#define LPC17_40_IOCON_P0_10 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP10_OFFSET) +#define LPC17_40_IOCON_P0_11 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP11_OFFSET) +#define LPC17_40_IOCON_P0_12 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP12_OFFSET) +#define LPC17_40_IOCON_P0_13 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP13_OFFSET) +#define LPC17_40_IOCON_P0_14 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP14_OFFSET) +#define LPC17_40_IOCON_P0_15 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP15_OFFSET) +#define LPC17_40_IOCON_P0_16 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP16_OFFSET) +#define LPC17_40_IOCON_P0_17 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP17_OFFSET) +#define LPC17_40_IOCON_P0_18 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP18_OFFSET) +#define LPC17_40_IOCON_P0_19 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP19_OFFSET) +#define LPC17_40_IOCON_P0_20 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP20_OFFSET) +#define LPC17_40_IOCON_P0_21 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP21_OFFSET) +#define LPC17_40_IOCON_P0_22 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP22_OFFSET) +#define LPC17_40_IOCON_P0_23 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP23_OFFSET) +#define LPC17_40_IOCON_P0_24 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP24_OFFSET) +#define LPC17_40_IOCON_P0_25 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP25_OFFSET) +#define LPC17_40_IOCON_P0_26 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP26_OFFSET) +#define LPC17_40_IOCON_P0_27 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP27_OFFSET) +#define LPC17_40_IOCON_P0_28 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP28_OFFSET) +#define LPC17_40_IOCON_P0_29 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP29_OFFSET) +#define LPC17_40_IOCON_P0_30 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP30_OFFSET) +#define LPC17_40_IOCON_P0_31 (LPC17_40_IOCON_P0_BASE + LPC17_40_IOCON_PP31_OFFSET) + +#define LPC17_40_IOCON_P1_0 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP0_OFFSET) +#define LPC17_40_IOCON_P1_1 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP1_OFFSET) +#define LPC17_40_IOCON_P1_2 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP2_OFFSET) +#define LPC17_40_IOCON_P1_3 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP3_OFFSET) +#define LPC17_40_IOCON_P1_4 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP4_OFFSET) +#define LPC17_40_IOCON_P1_5 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP5_OFFSET) +#define LPC17_40_IOCON_P1_6 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP6_OFFSET) +#define LPC17_40_IOCON_P1_7 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP7_OFFSET) +#define LPC17_40_IOCON_P1_8 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP8_OFFSET) +#define LPC17_40_IOCON_P1_9 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP9_OFFSET) +#define LPC17_40_IOCON_P1_10 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP10_OFFSET) +#define LPC17_40_IOCON_P1_11 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP11_OFFSET) +#define LPC17_40_IOCON_P1_12 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP12_OFFSET) +#define LPC17_40_IOCON_P1_13 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP13_OFFSET) +#define LPC17_40_IOCON_P1_14 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP14_OFFSET) +#define LPC17_40_IOCON_P1_15 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP15_OFFSET) +#define LPC17_40_IOCON_P1_16 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP16_OFFSET) +#define LPC17_40_IOCON_P1_17 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP17_OFFSET) +#define LPC17_40_IOCON_P1_18 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP18_OFFSET) +#define LPC17_40_IOCON_P1_19 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP19_OFFSET) +#define LPC17_40_IOCON_P1_20 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP20_OFFSET) +#define LPC17_40_IOCON_P1_21 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP21_OFFSET) +#define LPC17_40_IOCON_P1_22 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP22_OFFSET) +#define LPC17_40_IOCON_P1_23 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP23_OFFSET) +#define LPC17_40_IOCON_P1_24 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP24_OFFSET) +#define LPC17_40_IOCON_P1_25 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP25_OFFSET) +#define LPC17_40_IOCON_P1_26 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP26_OFFSET) +#define LPC17_40_IOCON_P1_27 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP27_OFFSET) +#define LPC17_40_IOCON_P1_28 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP28_OFFSET) +#define LPC17_40_IOCON_P1_29 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP29_OFFSET) +#define LPC17_40_IOCON_P1_30 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP30_OFFSET) +#define LPC17_40_IOCON_P1_31 (LPC17_40_IOCON_P1_BASE + LPC17_40_IOCON_PP31_OFFSET) + +#define LPC17_40_IOCON_P2_0 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP0_OFFSET) +#define LPC17_40_IOCON_P2_1 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP1_OFFSET) +#define LPC17_40_IOCON_P2_2 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP2_OFFSET) +#define LPC17_40_IOCON_P2_3 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP3_OFFSET) +#define LPC17_40_IOCON_P2_4 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP4_OFFSET) +#define LPC17_40_IOCON_P2_5 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP5_OFFSET) +#define LPC17_40_IOCON_P2_6 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP6_OFFSET) +#define LPC17_40_IOCON_P2_7 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP7_OFFSET) +#define LPC17_40_IOCON_P2_8 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP8_OFFSET) +#define LPC17_40_IOCON_P2_9 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP9_OFFSET) +#define LPC17_40_IOCON_P2_10 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP10_OFFSET) +#define LPC17_40_IOCON_P2_11 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP11_OFFSET) +#define LPC17_40_IOCON_P2_12 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP12_OFFSET) +#define LPC17_40_IOCON_P2_13 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP13_OFFSET) +#define LPC17_40_IOCON_P2_14 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP14_OFFSET) +#define LPC17_40_IOCON_P2_15 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP15_OFFSET) +#define LPC17_40_IOCON_P2_16 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP16_OFFSET) +#define LPC17_40_IOCON_P2_17 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP17_OFFSET) +#define LPC17_40_IOCON_P2_18 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP18_OFFSET) +#define LPC17_40_IOCON_P2_19 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP19_OFFSET) +#define LPC17_40_IOCON_P2_20 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP20_OFFSET) +#define LPC17_40_IOCON_P2_21 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP21_OFFSET) +#define LPC17_40_IOCON_P2_22 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP22_OFFSET) +#define LPC17_40_IOCON_P2_23 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP23_OFFSET) +#define LPC17_40_IOCON_P2_24 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP24_OFFSET) +#define LPC17_40_IOCON_P2_25 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP25_OFFSET) +#define LPC17_40_IOCON_P2_26 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP26_OFFSET) +#define LPC17_40_IOCON_P2_27 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP27_OFFSET) +#define LPC17_40_IOCON_P2_28 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP28_OFFSET) +#define LPC17_40_IOCON_P2_29 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP29_OFFSET) +#define LPC17_40_IOCON_P2_30 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP30_OFFSET) +#define LPC17_40_IOCON_P2_31 (LPC17_40_IOCON_P2_BASE + LPC17_40_IOCON_PP31_OFFSET) + +#define LPC17_40_IOCON_P3_0 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP0_OFFSET) +#define LPC17_40_IOCON_P3_1 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP1_OFFSET) +#define LPC17_40_IOCON_P3_2 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP2_OFFSET) +#define LPC17_40_IOCON_P3_3 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP3_OFFSET) +#define LPC17_40_IOCON_P3_4 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP4_OFFSET) +#define LPC17_40_IOCON_P3_5 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP5_OFFSET) +#define LPC17_40_IOCON_P3_6 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP6_OFFSET) +#define LPC17_40_IOCON_P3_7 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP7_OFFSET) +#define LPC17_40_IOCON_P3_8 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP8_OFFSET) +#define LPC17_40_IOCON_P3_9 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP9_OFFSET) +#define LPC17_40_IOCON_P3_10 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP10_OFFSET) +#define LPC17_40_IOCON_P3_11 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP11_OFFSET) +#define LPC17_40_IOCON_P3_12 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP12_OFFSET) +#define LPC17_40_IOCON_P3_13 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP13_OFFSET) +#define LPC17_40_IOCON_P3_14 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP14_OFFSET) +#define LPC17_40_IOCON_P3_15 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP15_OFFSET) +#define LPC17_40_IOCON_P3_16 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP16_OFFSET) +#define LPC17_40_IOCON_P3_17 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP17_OFFSET) +#define LPC17_40_IOCON_P3_18 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP18_OFFSET) +#define LPC17_40_IOCON_P3_19 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP19_OFFSET) +#define LPC17_40_IOCON_P3_20 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP20_OFFSET) +#define LPC17_40_IOCON_P3_21 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP21_OFFSET) +#define LPC17_40_IOCON_P3_22 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP22_OFFSET) +#define LPC17_40_IOCON_P3_23 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP23_OFFSET) +#define LPC17_40_IOCON_P3_24 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP24_OFFSET) +#define LPC17_40_IOCON_P3_25 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP25_OFFSET) +#define LPC17_40_IOCON_P3_26 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP26_OFFSET) +#define LPC17_40_IOCON_P3_27 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP27_OFFSET) +#define LPC17_40_IOCON_P3_28 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP28_OFFSET) +#define LPC17_40_IOCON_P3_29 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP29_OFFSET) +#define LPC17_40_IOCON_P3_30 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP30_OFFSET) +#define LPC17_40_IOCON_P3_31 (LPC17_40_IOCON_P3_BASE + LPC17_40_IOCON_PP31_OFFSET) + +#define LPC17_40_IOCON_P4_0 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP0_OFFSET) +#define LPC17_40_IOCON_P4_1 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP1_OFFSET) +#define LPC17_40_IOCON_P4_2 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP2_OFFSET) +#define LPC17_40_IOCON_P4_3 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP3_OFFSET) +#define LPC17_40_IOCON_P4_4 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP4_OFFSET) +#define LPC17_40_IOCON_P4_5 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP5_OFFSET) +#define LPC17_40_IOCON_P4_6 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP6_OFFSET) +#define LPC17_40_IOCON_P4_7 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP7_OFFSET) +#define LPC17_40_IOCON_P4_8 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP8_OFFSET) +#define LPC17_40_IOCON_P4_9 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP9_OFFSET) +#define LPC17_40_IOCON_P4_10 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP10_OFFSET) +#define LPC17_40_IOCON_P4_11 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP11_OFFSET) +#define LPC17_40_IOCON_P4_12 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP12_OFFSET) +#define LPC17_40_IOCON_P4_13 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP13_OFFSET) +#define LPC17_40_IOCON_P4_14 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP14_OFFSET) +#define LPC17_40_IOCON_P4_15 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP15_OFFSET) +#define LPC17_40_IOCON_P4_16 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP16_OFFSET) +#define LPC17_40_IOCON_P4_17 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP17_OFFSET) +#define LPC17_40_IOCON_P4_18 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP18_OFFSET) +#define LPC17_40_IOCON_P4_19 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP19_OFFSET) +#define LPC17_40_IOCON_P4_20 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP20_OFFSET) +#define LPC17_40_IOCON_P4_21 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP21_OFFSET) +#define LPC17_40_IOCON_P4_22 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP22_OFFSET) +#define LPC17_40_IOCON_P4_23 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP23_OFFSET) +#define LPC17_40_IOCON_P4_24 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP24_OFFSET) +#define LPC17_40_IOCON_P4_25 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP25_OFFSET) +#define LPC17_40_IOCON_P4_26 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP26_OFFSET) +#define LPC17_40_IOCON_P4_27 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP27_OFFSET) +#define LPC17_40_IOCON_P4_28 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP28_OFFSET) +#define LPC17_40_IOCON_P4_29 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP29_OFFSET) +#define LPC17_40_IOCON_P4_30 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP30_OFFSET) +#define LPC17_40_IOCON_P4_31 (LPC17_40_IOCON_P4_BASE + LPC17_40_IOCON_PP31_OFFSET) + +#define LPC17_40_IOCON_P5_0 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP0_OFFSET) +#define LPC17_40_IOCON_P5_1 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP1_OFFSET) +#define LPC17_40_IOCON_P5_2 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP2_OFFSET) +#define LPC17_40_IOCON_P5_3 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP3_OFFSET) +#define LPC17_40_IOCON_P5_4 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP4_OFFSET) +#define LPC17_40_IOCON_P5_5 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP5_OFFSET) +#define LPC17_40_IOCON_P5_6 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP6_OFFSET) +#define LPC17_40_IOCON_P5_7 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP7_OFFSET) +#define LPC17_40_IOCON_P5_8 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP8_OFFSET) +#define LPC17_40_IOCON_P5_9 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP9_OFFSET) +#define LPC17_40_IOCON_P5_10 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP10_OFFSET) +#define LPC17_40_IOCON_P5_11 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP11_OFFSET) +#define LPC17_40_IOCON_P5_12 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP12_OFFSET) +#define LPC17_40_IOCON_P5_13 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP13_OFFSET) +#define LPC17_40_IOCON_P5_14 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP14_OFFSET) +#define LPC17_40_IOCON_P5_15 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP15_OFFSET) +#define LPC17_40_IOCON_P5_16 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP16_OFFSET) +#define LPC17_40_IOCON_P5_17 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP17_OFFSET) +#define LPC17_40_IOCON_P5_18 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP18_OFFSET) +#define LPC17_40_IOCON_P5_19 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP19_OFFSET) +#define LPC17_40_IOCON_P5_20 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP20_OFFSET) +#define LPC17_40_IOCON_P5_21 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP21_OFFSET) +#define LPC17_40_IOCON_P5_22 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP22_OFFSET) +#define LPC17_40_IOCON_P5_23 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP23_OFFSET) +#define LPC17_40_IOCON_P5_24 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP24_OFFSET) +#define LPC17_40_IOCON_P5_25 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP25_OFFSET) +#define LPC17_40_IOCON_P5_26 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP26_OFFSET) +#define LPC17_40_IOCON_P5_27 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP27_OFFSET) +#define LPC17_40_IOCON_P5_28 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP28_OFFSET) +#define LPC17_40_IOCON_P5_29 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP29_OFFSET) +#define LPC17_40_IOCON_P5_30 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP30_OFFSET) +#define LPC17_40_IOCON_P5_31 (LPC17_40_IOCON_P5_BASE + LPC17_40_IOCON_PP31_OFFSET) + +/* Register bit definitions *********************************************************/ +/* IOCON pin function select */ + +#define IOCON_FUNC_GPIO (0) +#define IOCON_FUNC_ALT1 (1) +#define IOCON_FUNC_ALT2 (2) +#define IOCON_FUNC_ALT3 (3) +#define IOCON_FUNC_ALT4 (4) +#define IOCON_FUNC_ALT5 (5) +#define IOCON_FUNC_ALT6 (6) +#define IOCON_FUNC_ALT7 (7) + +#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ +#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT) +#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ +#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT ) +#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */ +#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT) +#define IOCON_INV_SHIFT (6) /* Bit 6: Type D,A,I,W */ +#define IOCON_INV_MASK (1 << IOCON_INV_SHIFT) +#define IOCON_ADMODE_SHIFT (7) /* Bit 7: Type A */ +#define IOCON_ADMODE_MASK (1 << IOCON_ADMODE_SHIFT) +#define IOCON_FILTER_SHIFT (8) /* Bit 8: Type A */ +#define IOCON_FILTER_MASK (1 << IOCON_FILTER_SHIFT) +#define IOCON_I2CHS_SHIFT (8) /* Bit 8: Type I */ +#define IOCON_I2CHS_MASK (1 << IOCON_I2CHS_SHIFT) +#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W */ +#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT) +#define IOCON_HIDRIVE_SHIFT (9) /* Bit 9: Type I */ +#define IOCON_HIDRIVE_MASK (1 << IOCON_HIDRIVE_SHIFT) +#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */ +#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) +#define IOCON_DACEN_SHIFT (16) /* Bit 16: Type A */ +#define IOCON_DACEN_MASK (1 << IOCON_DACEN_SHIFT) + +/* Pin modes */ + +#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ +#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */ +#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */ +#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */ + +/* Pin types */ + +#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */ +#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */ +#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */ +#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */ +#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */ + +/* Slew rate modes */ + +#define IOCON_SLEWMODE_NORMAL (0 << IOCON_SLEW_SHIFT) +#define IOCON_SLEWMODE_FAST (1 << IOCON_SLEW_SHIFT) + +/* I2C modes */ + +#define IOCON_I2CMODE_SHIFT (IOCON_I2CHS_SHIFT) +#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT) +# define IOCON_I2CMODE_FAST (0 << IOCON_I2CMODE_SHIFT) +# define IOCON_I2CMODE_FASTPLUS (1 << IOCON_I2CMODE_SHIFT)/* */ +# define IOCON_I2CMODE_HIOPENDRAIN (2 << IOCON_I2CMODE_SHIFT)/* */ +# define IOCON_I2CMODE_OPENDRAIN (3 << IOCON_I2CMODE_SHIFT)/* */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_IOCON_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h new file mode 100644 index 00000000000..e91beb6740e --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h @@ -0,0 +1,159 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Memory Map ***********************************************************************/ + +#define LPC17_40_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC17_40_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ +#define LPC17_40_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ +#define LPC17_40_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip Peripheral SRAM (devices >32Kb) */ +# define LPC17_40_SRAM_BANK0 0x20000000 /* -0x20003fff: On-chip Peripheral SRAM Bank0 (devices >=32Kb) */ +# define LPC17_40_SRAM_BANK1 0x20004000 /* -0x20007fff: On-chip Peripheral SRAM Bank1 (devices 64Kb) */ +#define LPC17_40_AHB_BASE 0x20080000 /* -0x2008ffff: DMA Controller, Ethernet, and USB */ +#define LPC17_40_SPIFI_BASE 0x28000000 /* -0x28ffffff: SPIFI memory mapped region */ +#define LPC17_40_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ +# define LPC17_40_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ +# define LPC17_40_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ + +/* Off chip Memory via External Memory Interface */ + +#define LPC17_40_EXTRAM_BASE 0x80000000 /* */ +# define LPC17_40_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */ + +# define LPC17_40_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */ + +#define LPC17_40_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC17_40_SCS_BASE 0xe000e000 +#define LPC17_40_DEBUGMCU_BASE 0xe0042000 + +/* AHB SRAM Bank sizes **************************************************************/ + +#define LPC17_40_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ +#define LPC17_40_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ + +/* APB0 Peripherals *****************************************************************/ + +#define LPC17_40_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ +#define LPC17_40_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ +#define LPC17_40_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ +#define LPC17_40_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ +#define LPC17_40_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ +#define LPC17_40_PWM0_BASE 0x40014000 /* -0x40017fff: PWM 0 */ +#define LPC17_40_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ +#define LPC17_40_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ +#define LPC17_40_CMP_BASE 0x40020000 /* -0x40023fff: Analog Comparators (LPC40xx only)*/ +#define LPC17_40_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ +#define LPC17_40_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ +#define LPC17_40_IOCON_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_40_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ +#define LPC17_40_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ +#define LPC17_40_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ +#define LPC17_40_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ +#define LPC17_40_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ +#define LPC17_40_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ +#define LPC17_40_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ + /* -0x4005bfff: Reserved */ +#define LPC17_40_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ + /* -0x4007ffff: Reserved */ + +/* APB1 Peripherals *****************************************************************/ + + /* -0x40087fff: Reserved */ +#define LPC17_40_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ +#define LPC17_40_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ +#define LPC17_40_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ +#define LPC17_40_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ +#define LPC17_40_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ +#define LPC17_40_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ +#define LPC17_40_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ +#define LPC17_40_UART4_BASE 0x400a4000 /* -0x400a7fff: UART4 */ +#define LPC17_40_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ +#define LPC17_40_SSP2_BASE 0x400ac000 /* -0x400affff: SSP2 */ + /* -0x400b3fff: Reserved */ + /* -0x400b7fff: Reserved */ +#define LPC17_40_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ +#define LPC17_40_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ +#define LPC17_40_MCI_BASE 0x400c0000 /* -0x400fbfff: SD interface */ +#define LPC17_40_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC17_40_GPDMA_BASE 0x20080000 /* GPDMA controller */ +#define LPC17_40_ETH_BASE 0x20084000 /* Ethernet controller */ +#define LPC17_40_LCD_BASE 0x20088000 /* LCD controller */ +#define LPC17_40_USB_BASE 0x2008c000 /* USB controller */ +#define LPC17_40_CRC_BASE 0x20090000 /* CRC engine */ +#define LPC17_40_SPIFICFG_BASE 0x20094000 /* SPIFI configuration registers */ +#define LPC17_40_GPIO_BASE 0x20098000 /* GPIO */ +#define LPC17_40_EMC_BASE 0x2009c000 /* External Memory Controller */ + +/* EEPROM */ + +#define LPC17_40_EEPROM_BASE 0x00200000 /* EEPROM controller */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h similarity index 92% rename from arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h index acafae871ad..6ef9d848099 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Authors: Rommel Marcelo @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_PINCONFIG_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_PINCONFIG_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_PINCONFIG_H /************************************************************************************ * Included Files @@ -76,44 +76,52 @@ #define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) #define GPIO_CAN2_RD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) #define GPIO_CAP2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CMP_ROSC_1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) /* Only on LPC40xx */ #define GPIO_LCD_VD0_1 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN4) #define GPIO_I2S_RXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) #define GPIO_CAN2_TD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) #define GPIO_CAP2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CMP_RESET (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) /* Only on LPC40xx */ #define GPIO_LCD_VD1_1 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN5) #define GPIO_I2S_RXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) #define GPIO_SSP1_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) #define GPIO_MAT2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) #define GPIO_UART1_RTS_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_CMP_ROSC_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) /* Only on LPC40xx */ #define GPIO_LCD_VD8_1 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN6) #define GPIO_I2S_TXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_SSP1_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_MAT2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_RTC_EV0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_CMP_VREF (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN7) /* Only on LPC40xx */ #define GPIO_LCD_VD9_1 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN7) #define GPIO_I2S_TXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_SSP1_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_MAT2p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_RTC_EV1_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_CMP1_IN_4 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN8) /* Only on LPC40xx */ #define GPIO_LCD_VD16 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN8) #define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_SSP1_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_MAT2p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_RTC_EV2_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_CMP1_IN_3 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN9) /* Only on LPC40xx */ #define GPIO_LCD_VD17 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN9) #define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) #define GPIO_I2C2_SDA_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) #define GPIO_MAT3p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_LCD_VD5_3 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN10) /* Only on LPC40xx */ #define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) #define GPIO_I2C2_SCL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) #define GPIO_MAT3p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_LCD_VD10_4 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN11) /* Only on LPC40xx */ #define GPIO_USB_PPWR2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) #define GPIO_SSP1_MISO_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) @@ -146,14 +154,16 @@ #define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) #define GPIO_SD_CLK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) #define GPIO_I2C1_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_LCD_VD13_3 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN19) /* Only on LPC40xx */ #define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) #define GPIO_SD_CMD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) #define GPIO_I2C1_SCL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_LCD_VD14_3 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN20) /* Only on LPC40xx */ #define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) #define GPIO_SD_PWR_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) -#define GPIO_UART4_OE_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UART4_OE (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) #define GPIO_CAN1_RD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) #define GPIO_UART4_SCLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) @@ -195,11 +205,11 @@ #define GPIO_ENET_TXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN0) #define GPIO_CAP3p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_SSP2_SCK (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_SSP2_SCK_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) #define GPIO_ENET_TXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN1) #define GPIO_MAT3p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_SSP2_MOSI (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_SSP2_MOSI_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) #define GPIO_ENET_TXD2 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN2) #define GPIO_SD_CLK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) @@ -216,18 +226,22 @@ #define GPIO_ENET_TX_ER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN5) #define GPIO_SD_PWR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) #define GPIO_PWM0p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CMP1_IN_2 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN5) /* Only on LPC40xx */ #define GPIO_ENET_TX_CLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN6) #define GPIO_SD_DAT0_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) #define GPIO_PWM0p4_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_CMP0_IN_4 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN6) /* Only on LPC40xx */ #define GPIO_ENET_COL (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN7) #define GPIO_SD_DAT1_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) #define GPIO_PWM0p5_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_CMP1_IN_1 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN7) /* Only on LPC40xx */ #define GPIO_ENET_CRSDV (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_ENET_CRS (GPIO_ENET_CRSDV) /* Alternate pin name for LPC17 Ethernet driver */ #define GPIO_MAT3p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) -#define GPIO_SSP2_SSEL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SSP2_SSEL_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) #define GPIO_ENET_RXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN9) #define GPIO_MAT3p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9) @@ -242,20 +256,24 @@ #define GPIO_ENET_RXD3 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN12) #define GPIO_SD_DAT3_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) #define GPIO_PWM0CAPp0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_CMP1_OUT (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) /* Only on LPC40xx */ #define GPIO_ENET_RX_DV (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN13) #define GPIO_ENET_RXER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN14) #define GPIO_CAP2p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_CMP0_IN_1 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN14) /* Only on LPC40xx */ #define GPIO_ENET_REFCLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN15) #define GPIO_I2C2_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN15) #define GPIO_ENET_MDC_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN16) #define GPIO_I2S_TXMCLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_CMP0_IN_2 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN16) /* Only on LPC40xx */ #define GPIO_ENET_MDIO_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN17) #define GPIO_I2S_RXMCLK (GPIO_ALT2 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_CMP0_IN_3 (GPIO_ALT5 | GPIO_FLOAT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN17) /* Only on LPC40xx */ #define GPIO_USB_UPLED (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) #define GPIO_PWM1p1_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) @@ -626,21 +644,27 @@ #define GPIO_LCD_VD3_3 (GPIO_ALT7 | GPIO_FLOAT | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN29) #define GPIO_EMC_CS0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_CMP0_OUT (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN30) /* Only on LPC40xx */ + #define GPIO_EMC_CS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN31) #define GPIO_EMC_A24 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_SSP2_MOSI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) #define GPIO_MAT2p2_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) #define GPIO_EMC_A25 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_SSP2_MISO_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) #define GPIO_MAT2p3_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_SSP2_SCK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) /* Only on LPC40xx */ #define GPIO_MAT3p2_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) #define GPIO_I2C0_SDA_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_SSP2_SSEL_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) /* Only on LPC40xx */ #define GPIO_UART4_RXD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) #define GPIO_I2C0_SCL0 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) -#define GPIO_UART4_OE_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_UART0_OE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) #define GPIO_MAT3p3_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) #define GPIO_UART4_TXD_3 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) @@ -656,4 +680,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_PINCONFIG_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_PINCONFIG_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h new file mode 100644 index 00000000000..96625e79ec8 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h @@ -0,0 +1,644 @@ +/**************************************************************************************************** + * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_SYSCON_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_SYSCON_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ +/* Flash accelerator module */ + +#define LPC17_40_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_40_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control Register */ + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_40_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ +#define LPC17_40_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ +#define LPC17_40_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ +#define LPC17_40_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ + +#define LPC17_40_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ +#define LPC17_40_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ +#define LPC17_40_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ +#define LPC17_40_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_40_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ +#define LPC17_40_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ +#define LPC17_40_SYSCON_PCONP1_OFFSET 0x00c8 /* Power Control for Peripherals Register 1 */ + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_40_SYSCON_EMCCLKSEL_OFFSET 0x0100 /* EMC Clock Selection Register */ +#define LPC17_40_SYSCON_CCLKSEL_OFFSET 0x0104 /* CPU Clock Selection Register */ +#define LPC17_40_SYSCON_USBCLKSEL_OFFSET 0x0108 /* USB Clock Selection Register */ + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_40_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ +#define LPC17_40_SYSCON_CANSLEEPCLR_OFFSET 0x0110 /* CAN Channel Sleep State Register */ +#define LPC17_40_SYSCON_CANWAKEFLAGS_OFFSET 0x0114 /* CAN Channel Wake-Up State Register */ + +/* System control registers -- External Interrupts */ + +#define LPC17_40_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ +#define LPC17_40_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ +#define LPC17_40_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ + +/* System control registers -- Reset */ + +#define LPC17_40_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_40_SYSCON_MATRIXARB_OFFSET 0x0188 /* Matrix Arbitration Register */ +#define LPC17_40_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ +#define LPC17_40_SYSCON_PCLKSEL_OFFSET 0x01a8 /* Peripheral Clock Selection Register */ +#define LPC17_40_SYSCON_PBOOST_OFFSET 0x01b0 /* Power Boost Register */ +#define LPC17_40_SYSCON_SPIFICLKSEL_OFFSET 0x01b4 /* SPIFI Clock Selection Register */ +#define LPC17_40_SYSCON_LCDCFG_OFFSET 0x01b8 /* LCD Clock Configuration Register */ + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_40_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ + +/* DMA Request Select Register */ + +#define LPC17_40_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ + +/* More clocking and power control -- Utility */ + +#define LPC17_40_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ + +/* Peripheral Reset Control */ + +#define LPC17_40_SYSCON_RSTCON0_OFFSET 0x01cc /* Individual Peripheral Reset Control Bits */ +#define LPC17_40_SYSCON_RSTCON1_OFFSET 0x01d0 /* Individual Peripheral Reset Control Bits */ + +/* EMC Clock Control and Calibration */ + +#define LPC17_40_SYSCON_EMCDLYCTL_OFFSET 0x01dc /* Programmable Delays for SDRAM Operation */ +#define LPC17_40_SYSCON_EMCCAL_OFFSET 0x01e0 /* Calibration Counter for EMCDLYCTL */ + + +/* Register addresses *******************************************************************************/ +/* Flash accelerator module */ + +#define LPC17_40_SYSCON_FLASHCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_FLASHCFG_OFFSET) + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_40_SYSCON_MEMMAP (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_MEMMAP_OFFSET) + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_40_SYSCON_PLL0CON (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0CON_OFFSET) +#define LPC17_40_SYSCON_PLL0CFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0CFG_OFFSET) +#define LPC17_40_SYSCON_PLL0STAT (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0STAT_OFFSET) +#define LPC17_40_SYSCON_PLL0FEED (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL0FEED_OFFSET) + +#define LPC17_40_SYSCON_PLL1CON (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1CON_OFFSET) +#define LPC17_40_SYSCON_PLL1CFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1CFG_OFFSET) +#define LPC17_40_SYSCON_PLL1STAT (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1STAT_OFFSET) +#define LPC17_40_SYSCON_PLL1FEED (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PLL1FEED_OFFSET) + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_40_SYSCON_PCON (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCON_OFFSET) +#define LPC17_40_SYSCON_PCONP (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCONP_OFFSET) +#define LPC17_40_SYSCON_PCONP1 (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCONP1_OFFSET) + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_40_SYSCON_EMCCLKSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EMCCLKSEL_OFFSET) +#define LPC17_40_SYSCON_CCLKSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CCLKSEL_OFFSET) +#define LPC17_40_SYSCON_USBCLKSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_USBCLKSEL_OFFSET) + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_40_SYSCON_CLKSRCSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CLKSRCSEL_OFFSET) +#define LPC17_40_SYSCON_CANSLEEPCLR (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CANSLEEPCLR_OFFSET) +#define LPC17_40_SYSCON_CANWAKEFLAGS (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CANWAKEFLAGS_OFFSET) + +/* System control registers -- External Interrupts */ + +#define LPC17_40_SYSCON_EXTINT (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EXTINT_OFFSET) + +#define LPC17_40_SYSCON_EXTMODE (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EXTMODE_OFFSET) +#define LPC17_40_SYSCON_EXTPOLAR (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EXTPOLAR_OFFSET) + +/* System control registers -- Reset */ + +#define LPC17_40_SYSCON_RSID (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_RSID_OFFSET) + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_40_SYSCON_MATRIXARB (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_MATRIXARB_OFFSET) +#define LPC17_40_SYSCON_SCS (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_SCS_OFFSET) +#define LPC17_40_SYSCON_PCLKSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PCLKSEL_OFFSET) +#define LPC17_40_SYSCON_PBOOST (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_PBOOST_OFFSET) +#define LPC17_40_SYSCON_SPIFICLKSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_SPIFICLKSEL_OFFSET) +#define LPC17_40_SYSCON_LCDCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_LCDCFG_OFFSET) + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_40_SYSCON_USBINTST (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_USBINTST_OFFSET) + +/* DMA Request Select Register */ + +#define LPC17_40_SYSCON_DMAREQSEL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_DMAREQSEL_OFFSET) + +/* More clocking and power control -- Utility */ + +#define LPC17_40_SYSCON_CLKOUTCFG (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_CLKOUTCFG_OFFSET) + + +/* Peripheral Reset Control */ + +#define LPC17_40_SYSCON_RSTCON0 (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_RSTCON0_OFFSET) +#define LPC17_40_SYSCON_RSTCON1 (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_RSTCON1_OFFSET) + +/* EMC Clock Control and Calibration */ + +#define LPC17_40_SYSCON_EMCDLYCTL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EMCDLYCTL_OFFSET) +#define LPC17_40_SYSCON_EMCCAL (LPC17_40_SYSCON_BASE+LPC17_40_SYSCON_EMCCAL_OFFSET) + +/* Register bit definitions *************************************************************************/ +/* Flash accelerator module */ + /* Bits 0-11: Reserved */ +#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ +#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) +# define SYSCON_FLASHCFG_TIM_0 (0) /* 1 CPU clock <= 20 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_1 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_2 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_3 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_4 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock + * (Up to 120 Mhz for LPC1788x) */ +# define SYSCON_FLASHCFG_TIM_5 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ + /* Bits 16-31: Reserved */ +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: + * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. + * 1:User mode. The on-chip Flash memory is mapped to address 0 */ + /* Bits 1-31: Reserved */ +/* Clocking and power control -- Clock source selection */ + +#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0: Clock selection */ +#define SYSCON_CLKSRCSEL_MASK (1 << SYSCON_CLKSRCSEL_SHIFT) +# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ +# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ + /* Bits 1-31: Reserved */ +/* Clocking and power control - Phase locked loops */ +/* PLL0/1 Control register */ + +#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL Enable */ + /* Bits 1-31: Reserved */ +/* PLL0/1 Configuration register */ + +#define SYSCON_PLLCFG_MSEL_SHIFT (0) /* Bit 0-4: PLL Multiplier value */ +#define SYSCON_PLLCFG_MSEL_MASK (0x1f << SYSCON_PLLCFG_MSEL_SHIFT) +#define SYSCON_PLLCFG_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value */ +#define SYSCON_PLLCFG_PSEL_MASK (3 << SYSCON_PLLCFG_PSEL_SHIFT) + +/* PLL0/1 Status register */ + +#define SYSCON_PLLSTAT_MSEL_SHIFT (0) /* Bit 0-4: PLLMultiplier value readback */ +#define SYSCON_PLLSTAT_MSEL_MASK (0x1f << SYSCON_PLLSTAT_MSEL_SHIFT) +#define SYSCON_PLLSTAT_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value readback */ +#define SYSCON_PLLSTAT_PSEL_MASK (3 << SYSCON_PLLSTAT_PSEL_SHIFT) + /* Bit 7: Reserved */ +#define SYSCON_PLLSTAT_PLLE (1 << 8) /* Bit 8: PLL enable readback */ +#define SYSCON_PLLSTAT_PLLC (1 << 9) /* Bit 9: PLL connect readback */ +#define SYSCON_PLLSTAT_PLOCK (1 << 10) /* Bit 10: PLL lock status */ + /* Bits 11-31: Reserved */ +/* PLL0/1 Feed register */ + +#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ +#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) + /* Bits 8-31: Reserved */ +/* Clocking and power control -- Clock dividers */ + +/* EMC Clock Selection Register */ + +#define SYSCON_EMCDIV (1 << 0) /* Bit 0: EMC Clock rate relative to CPU */ + /* 0: EMC uses same clock as CPU */ + /* 1: EMC uses half the rate of CPU */ + /* Bits 1-31: Reserved */ +/* EMC Clock Selection Register */ + +#define SYSCON_EMCCLKSEL_CCLK_DIV2 (1 << 0) /* Bit 0: 1=EMC used CPU clock / 2 */ +#define SYSCON_EMCCLKSEL_CCLK_DIV1 (0) /* 0=EMC used CPU clock */ + +/* CPU Clock Selection Register */ + +#define SYSCON_CCLKSEL_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */ +#define SYSCON_CCLKSEL_CCLKDIV_MASK (0x1f << SYSCON_CCLKSEL_CCLKDIV_SHIFT) +# define SYSCON_CCLKSEL_CCLKDIV(n) ((n-1) << SYSCON_CCLKSEL_CCLKDIV_SHIFT) /* n = 2 - 31 */ + /* Bits 5-7: Reserved */ +#define SYSCON_CCLKSEL_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */ + /* 0: Sysclk used as input to CCLKDIV */ + /* 1: Main PLL used as input to CCLKDIV */ + /* Bits 9-31: Reserved */ +/* USB Clock Selection register */ + +#define SYSCON_USBCLKSEL_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */ +#define SYSCON_USBCLKSEL_USBDIV_MASK (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT) +# define SYSCON_USBCLKSEL_USBDIV_DIV1 (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */ +# define SYSCON_USBCLKSEL_USBDIV_DIV2 (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */ +# define SYSCON_USBCLKSEL_USBDIV_DIV3 (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */ + /* Bits 5-7: Reserved */ +#define SYSCON_USBCLKSEL_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */ +#define SYSCON_USBCLKSEL_USBSEL_MASK (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT) +#define SYSCON_USBCLKSEL_USBSEL_PLL0 (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */ +#define SYSCON_USBCLKSEL_USBSEL_PLL1 (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */ + /* 11: unused */ + /* Bits 10-31: Reserved */ +/* CAN0/1 Sleep Clear Register */ + /* Bit 0: Reserved */ +#define SYSCON_CANSLEEPCLR_SHIFT (1) /* Bits 1-2: CAN0/1 Sleep Status and Control */ +#define SYSCON_CANSLEEPCLR_MASK (3 << SYSCON_CANSLEEPCLR_SHIFT) /* */ +#define SYSCON_CANSLEEPCLR_CAN1 (1 << SYSCON_CANSLEEPCLR_SHIFT) /* CAN1 Sleep Status */ +#define SYSCON_CANSLEEPCLR_CAN2 (2 << SYSCON_CANSLEEPCLR_SHIFT) /* CAN2 Sleep Status */ + /* Read 1: CAN channel in sleep mode */ + /* Write 1: CAN channel clocks restored */ + /* Bits 3-31: Reserved */ +/* CAN0/1 WakeUp Flags Register */ + /* Bit 0: Reserved */ +#define SYSCON_CANWAKEFLAGS_SHIFT (1) /* Bits 1-2: CAN0/1 WakeUp Status */ +#define SYSCON_CANWAKEFLAGS_MASK (3 << SYSCON_CANWAKEFLAGS_SHIFT) /* */ +#define SYSCON_CANWAKEFLAGS_CAN1 (1 << SYSCON_CANWAKEFLAGS_SHIFT) /* CAN1 WakeUp Status */ +#define SYSCON_CANWAKEFLAGS_CAN2 (2 << SYSCON_CANWAKEFLAGS_SHIFT) /* CAN2 WakeUp Status */ + /* Read 1: CAN channel falling edge occur on receive line */ + /* Write 1: CAN channel clears wakeup flag bit */ + /* Bits 3-31: Reserved */ +/* Peripheral Clock Selection register */ +/* PCLK is common to all peripheral */ + +#define SYSCON_PCLKSEL_PCLKDIV_SHIFT (0) /* Bits 0-4: Clock divide value for all APB peripherals */ +#define SYSCON_PCLKSEL_PCLKDIV_MASK (0x1f << SYSCON_PCLKSEL_PCLKDIV_SHIFT) +# define SYSCON_PCLKSEL_PCLKDIV(n) ((n) & SYSCON_PCLKSEL_PCLKDIV_MASK) /* n = 1 - 31 */ + /* Bits 5-31: Reserved */ +/* Power Boost Control Register */ + +#define SYSCON_PBOOST_BOOST_SHIFT (0) /* Bits 0-1: Boost control bits */ +#define SYSCON_PBOOST_BOOST_MASK (3 << SYSCON_PBOOST_BOOST_SHIFT) +#define SYSCON_PBOOST_BOOST_OFF (0) /* Boost OFF, operation must be below 100MHz */ +#define SYSCON_PBOOST_BOOST_ON (3) /* Boost ON, operation upto 120MHz allowed */ + /* Bits 2-31: Reserved */ +/* SPIFI Clock Selection Register */ + +#define SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT (0) /* Bits 0-4: divide value for SPIFI clock */ +#define SYSCON_SPIFICLKSEL_SPIFIDIV_MASK (0x1f << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) +# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */ + /* Bits 5-7: Reserved */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT (8) /* Bits 8-9: Selects input clock for SPIFI clock divider */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_MASK (3 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) +#define SYSCON_SPIFICLKSEL_SPIFISEL_SYSCLK (0) /* Sysclk used as input to SPIFIDIV */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_PLL0 (1 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) /* Main PLL used as input to SPIFIDIV */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_PLL1 (2 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) /* Alt PLL used as input to SPIFIDIV */ + /* Bits 10-31: Reserved */ +/* LCD Configuration Register */ + +#define SYSCON_LCDCFG_CLKDIV_SHIFT (0) /* Bits 0-4: LCD Panel clock prescaler */ +#define SYSCON_LCDCFG_CLKDIV_MASK (0x1f << SYSCON_LCDCFG_CLKDIV_SHIFT) +#define SYSCON_LCDCFG_CLKDIV(n) ((n-1) << SYSCON_LCDCFG_CLKDIV_SHIFT) /* n = 1 - 32 */ + /* Bits 5-31: Reserved */ +/* Clocking and power control - Peripheral power control registers */ +/* Power Control Register */ + +#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ +#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ +#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ +#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ +#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ + /* Bits 5-7: Reserved */ +#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ +#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ +#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ +#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ + /* Bits 12-31: Reserved */ +/* Power Control for Peripherals Register */ + +#define SYSCON_PCONP_PCLCD (1 << 0) /* Bit 0: LCD power/clock control */ +#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ +#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ +#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ +#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ +#define SYSCON_PCONP_PCPWM0 (1 << 5) /* Bit 5: PWM0 power/clock control */ +#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ +#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ +#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ +#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ +#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ +#define SYSCON_PCONP_PCEMC (1 << 11) /* Bit 11: External Memory */ +#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ +#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ +#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ +#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ +#define SYSCON_PCONP_PCSPIFI (1 << 16) /* Bit 16: SPI Flash Interface power/clock control */ +#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ +#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ +#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ +#define SYSCON_PCONP_PCSSP2 (1 << 20) /* Bit 20: SSP2 power/clock control */ +#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ +#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ +#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ +#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ +#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ +#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ +#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ +#define SYSCON_PCONP_PCSDC (1 << 28) /* Bit 28: SD Card power/clock control */ +#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ +#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ +#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ + +/* Power Control for Peripherals Register 1 */ + + /* Bits 0-2: Reserved */ +#define SYSCON_PCONP1_PCCMP (1 << 3) /* Bit 3: Comparator power/clock control */ + /* Bits 4-31: Reserved */ + +/* More clocking and power control -- Utility */ + +#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ +#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) +# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ +# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ +# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ +# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ +# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ +# define SYSCON_CLKOUTCFG_SEL_SPIFI (5 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=SPIFI osc */ +#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ +#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) +# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ +#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ +#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ + /* Bits 10-31: Reserved */ +/* System control registers -- External Interrupts */ +/* External Interrupt Flag register */ + +#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ +#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ +#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ +#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ + /* Bits 4-31: Reserved */ +/* External Interrupt Mode register */ + +#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ +#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ +#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ +#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ + /* Bits 4-31: Reserved */ +/* External Interrupt Polarity register */ + +#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ + /* Bits 4-31: Reserved */ +/* System control registers -- Reset */ +/* Reset Source Identification Register */ + +#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ +#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ +#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ +#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ +#define SYSCON_RSID_SYSRESET (1 << 4) /* Bit 4: System Reset */ +#define SYSCON_RSID_LOCKUP (1 << 5) /* Bit 5: Lockup Reset */ + /* Bits 6-31: Reserved */ +/* System control registers -- Matrix Arbitration Priorities */ + +# define SYSCON_MATRIXARB_PRI_LOWEST (0) +# define SYSCON_MATRIXARB_PRI_LOW (1) +# define SYSCON_MATRIXARB_PRI_HIGH (2) +# define SYSCON_MATRIXARB_PRI_HIGHEST (3) + +#define SYSCON_MATRIXARB_PRI_ICODE_SHIFT (0) /* Bits 0-1: I-Code bus priority (should be lower than D-Code) */ +#define SYSCON_MATRIXARB_PRI_ICODE_MASK (3 << SYSCON_MATRIXARB_PRI_ICODE_SHIFT) +# define SYSCON_MATRIXARB_PRI_ICODE(n) ((n) << SYSCON_MATRIXARB_PRI_ICODE_SHIFT) +#define SYSCON_MATRIXARB_PRI_DCODE_SHIFT (2) /* Bits 2-3: D-Code bus priority */ +#define SYSCON_MATRIXARB_PRI_DCODE_MASK (3 << SYSCON_MATRIXARB_PRI_DCODE_SHIFT) +# define SYSCON_MATRIXARB_PRI_DCODE(n) ((n) << SYSCON_MATRIXARB_PRI_DCODE_SHIFT) +#define SYSCON_MATRIXARB_PRI_SYS_SHIFT (4) /* Bits 4-5: System bus priority */ +#define SYSCON_MATRIXARB_PRI_SYS_MASK (3 << SYSCON_MATRIXARB_PRI_SYS_SHIFT) +# define SYSCON_MATRIXARB_PRI_SYS(n) ((n) << SYSCON_MATRIXARB_PRI_SYS_SHIFT) +#define SYSCON_MATRIXARB_PRI_GPDMA_SHIFT (6) /* Bits 6-7: General Purpose DMA priority */ +#define SYSCON_MATRIXARB_PRI_GPDMA_MASK (3 << SYSCON_MATRIXARB_PRI_GPDMA_SHIFT) +# define SYSCON_MATRIXARB_PRI_GPDMA(n) ((n) << SYSCON_MATRIXARB_PRI_GPDMA_SHIFT) +#define SYSCON_MATRIXARB_PRI_ETH_SHIFT (8) /* Bits 8-9: Ethernet DMA priority */ +#define SYSCON_MATRIXARB_PRI_ETH_MASK (3 << SYSCON_MATRIXARB_PRI_ETH_SHIFT) +# define SYSCON_MATRIXARB_PRI_ETH(n) ((n) << SYSCON_MATRIXARB_PRI_ETH_SHIFT) +#define SYSCON_MATRIXARB_PRI_LCD_SHIFT (10) /* Bits 10-11: LCD DMA priority */ +#define SYSCON_MATRIXARB_PRI_LCD_MASK (3 << SYSCON_MATRIXARB_PRI_LCD_SHIFT) +# define SYSCON_MATRIXARB_PRI_LCD(n) ((n) << SYSCON_MATRIXARB_PRI_LCD_SHIFT) +#define SYSCON_MATRIXARB_PRI_USB_SHIFT (12) /* Bits 12-13: USB DMA priority */ +#define SYSCON_MATRIXARB_PRI_USB_MASK (3 << SYSCON_MATRIXARB_PRI_USB_SHIFT) +# define SYSCON_MATRIXARB_PRI_USB(n) ((n) << SYSCON_MATRIXARB_PRI_USB_SHIFT) + /* Bits 14-15: Reserved */ +#define SYSCON_MATRIXARB_ROM_LAT_SHIFT (16) /* Bit 16: ROM Latency select (should always be zero) */ +#define SYSCON_MATRIXARB_ROM_LAT (1 << SYSCON_MATRIXARB_ROM_LAT_SHIFT) + /* Bits 17-31: Reserved */ + +#define SYSCON_MATRIXARB_PRI_MASK (0x00013fff) + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define SYSCON_SCS_EMCSC (1 << 0) /* Bit 0: EMC shift control */ +#define SYSCON_SCS_EMCRD (1 << 1) /* Bit 1: EMC reset disable */ +#define SYSCON_SCS_EMCBC (1 << 2) /* Bit 2: EMC burst control */ +#define SYSCON_SCS_MCIPWRAL (1 << 3) /* Bit 3: MCI power active level */ +#define SYSCON_SCS_OSCRS (1 << 4) /* Bit 4: Main oscillator range select */ +#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ +#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ + /* Bits 7-31: Reserved */ +/* Device Interrupt Registers */ +/* USB Interrupt Status register */ + +#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ +#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ +#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ +#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ +#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ +#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ +#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ + /* Bit 7: Reserved */ +#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ + /* Bits 9-30: Reserved */ +#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ + +/* DMA Request Select Register */ + +#define SYSCON_DMAREQSEL_INP0 (1 << 0) /* Bit 0: Input 0 0=unused 1=Timer 0 match 0 */ +#define SYSCON_DMAREQSEL_INP1 (1 << 1) /* Bit 1: Input 1 0=SD 1=Timer 0 match 1 */ +#define SYSCON_DMAREQSEL_INP2 (1 << 2) /* Bit 2: Input 2 0=SSP0 TX 1=Timer 1 match 0 */ +#define SYSCON_DMAREQSEL_INP3 (1 << 3) /* Bit 3: Input 3 0=SSP0 RX 1=Timer 1 match 1 */ +#define SYSCON_DMAREQSEL_INP4 (1 << 4) /* Bit 4: Input 4 0=SSP1 TX 1=Timer 2 match 0 */ +#define SYSCON_DMAREQSEL_INP5 (1 << 5) /* Bit 5: Input 5 0=SSP1 RX 1=Timer 2 match 1 */ +#define SYSCON_DMAREQSEL_INP6 (1 << 6) /* Bit 6: Input 6 0=SSP2 TX 1=I2S0 */ +#define SYSCON_DMAREQSEL_INP7 (1 << 7) /* Bit 7: Input 7 0=SSP2 RX 1=I2S1 */ + /* Bits 8-9: Reserved */ +#define SYSCON_DMAREQSEL_INP10 (1 << 10) /* Bit 10: Input 10 0=UART0 TX 1=UART3 TX */ +#define SYSCON_DMAREQSEL_INP11 (1 << 11) /* Bit 11: Input 11 0=UART0 RX 1=UART3 RX */ +#define SYSCON_DMAREQSEL_INP12 (1 << 12) /* Bit 12: Input 12 0=UART1 TX 1=UART4 TX */ +#define SYSCON_DMAREQSEL_INP13 (1 << 13) /* Bit 13: Input 13 0=UART1 RX 1=UART4 RX */ +#define SYSCON_DMAREQSEL_INP14 (1 << 14) /* Bit 14: Input 14 0=UART2 TX 1=Timer 3 match 0 */ +#define SYSCON_DMAREQSEL_INP15 (1 << 15) /* Bit 15: Input 15 0=UART2 RX 1=Timer 3 match 1 */ + /* Bits 16-31: Reserved */ +/* Reset Control Register 0 */ + +#define SYSCON_RSTCON0_RSTLCD (1 << 0) /* LCD controller reset control bit */ +#define SYSCON_RSTCON0_RSTTIM0 (1 << 1) /* Timer/Counter 0 reset control bit */ +#define SYSCON_RSTCON0_RSTTIM1 (1 << 2) /* Timer/Counter 1 reset control bit */ +#define SYSCON_RSTCON0_RSTUART0 (1 << 3) /* UART0 reset control bit */ +#define SYSCON_RSTCON0_RSTUART1 (1 << 4) /* UART1 reset control bit */ +#define SYSCON_RSTCON0_RSTPWM0 (1 << 5) /* PWM0 reset control bit */ +#define SYSCON_RSTCON0_RSTPWM1 (1 << 6) /* PWM1 reset control bit */ +#define SYSCON_RSTCON0_RSTI2C0 (1 << 7) /* The I2C0 interface reset control bit */ +#define SYSCON_RSTCON0_RSTUART4 (1 << 8) /* UART4 reset control bit */ +#define SYSCON_RSTCON0_RSTRTC (1 << 9) /* RTC and Event Monitor/Recorder reset control bit. RTC reset is limited */ +#define SYSCON_RSTCON0_RSTSSP1 (1 << 10) /* The SSP 1 interface reset control bit */ +#define SYSCON_RSTCON0_RSTEMC (1 << 11) /* External Memory Controller reset control bit */ +#define SYSCON_RSTCON0_RSTADC (1 << 12) /* A/D converter (ADC) reset control bit */ +#define SYSCON_RSTCON0_RSTCAN1 (1 << 13) /* CAN Controller 1 reset control bit */ + /* Note: The CAN acceptance filter may be reset by 0 + * a separate bit in the RSTCON1 register. */ +#define SYSCON_RSTCON0_RSTCAN2 (1 << 14) /* CAN Controller 2 reset control bit */ + /* Note: The CAN acceptance filter may be reset by 0 + * a separate bit in the RSTCON1 register */ +#define SYSCON_RSTCON0_RSTGPIO (1 << 15) /* Reset control bit for GPIO, and GPIO interrupts */ + /* Note: IOCON may be reset by a 0 + * separate bit in the RSTCON1 register */ +#define SYSCON_RSTCON0_RSTSPIFI (1 << 16) /* SPI Flash Interface reset control bit (LPC1773 only) */ +#define SYSCON_RSTCON0_RSTMCPWM (1 << 17) /* Motor Control PWM reset control bit */ +#define SYSCON_RSTCON0_RSTQEI (1 << 18) /* Quadrature Encoder Interface reset control bit */ +#define SYSCON_RSTCON0_RSTI2C1 (1 << 19) /* The I2C1 interface reset control bit */ +#define SYSCON_RSTCON0_RSTSSP2 (1 << 20) /* The SSP2 interface reset control bit */ +#define SYSCON_RSTCON0_RSTSSP0 (1 << 21) /* The SSP0 interface reset control bit */ +#define SYSCON_RSTCON0_RSTTIM2 (1 << 22) /* Timer 2 reset control bit */ +#define SYSCON_RSTCON0_RSTTIM3 (1 << 23) /* Timer 3 reset control bit */ +#define SYSCON_RSTCON0_RSTUART2 (1 << 24) /* UART 2 reset control bit */ +#define SYSCON_RSTCON0_RSTUART3 (1 << 25) /* UART 3 reset control bit */ +#define SYSCON_RSTCON0_RSTI2C2 (1 << 26) /* I2C2 interface reset control bit.*/ +#define SYSCON_RSTCON0_RSTI2S (1 << 27) /* I2S interface reset control bit */ +#define SYSCON_RSTCON0_RSTSDC (1 << 28) /* SD Card interface reset control bit */ +#define SYSCON_RSTCON0_RSTGPDMA (1 << 29) /* GPDMA function reset control bit */ + +#define SYSCON_RSTCON0_RSTENET (1 << 30) /* Ethernet block reset control bit */ +#define SYSCON_RSTCON0_RSTUSB (1 << 31) /* USB interface reset control bit */ + +/* Reset Control Register 1 */ + +#define SYSCON_RSTCON1_RSTIOCON (1 << 0) /* Reset control bit for the IOCON registers */ +#define SYSCON_RSTCON1_RSTDAC (1 << 1) /* D/A converter (DAC) reset control bit */ +#define SYSCON_RSTCON1_RSTCANACC (1 << 2) /* CAN acceptance filter reset control bit */ + /* Bits 3-31: Reserved */ +/* Delay Control Register - EMC */ + /* Delay values multiplied by 250 picoseconds */ +#define SYSCON_EMCDLYCTL_CMDDLY_SHIFT (0) /* Bits 0-4: Delay value for EMC outputs in command delayed mode */ +#define SYSCON_EMCDLYCTL_CMDDLY_MASK (0x1f << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) +# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n-1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 3 - 32 */ + /* Bits 5-7: Reserved */ +#define SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT (8) /* Bits 8-12: Delay value for the feedback clock that controls input data sampling */ +#define SYSCON_EMCDLYCTL_FBCLKDLY_MASK (0x1f << SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT) +#define SYSCON_EMCDLYCTL_FBCLKDLY(n) ((n-1)<< SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT) /* n = 3 - 32 */ + /* Bits 13-15: Reserved */ +#define SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT (16) /* Bits 16-20: Delay value for the CLKOUT0 output */ +#define SYSCON_EMCDLYCTL_CLKOUT0DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) +# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 3 - 32 */ + /* Bits 21-23: Reserved */ +#define SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT (24) /* Bits 24-28: Delay value for the CLKOUT1 output */ +#define SYSCON_EMCDLYCTL_CLKOUT1DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) +# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 3 - 32 */ + /* Bits 29-31: Reserved */ +/* Calibration Register - EMC */ + +#define SYSCON_EMCCAL_CALVALUE_SHIFT (0) /* Bits 0-7: Ring oscillator count during 32 clocks of Internal RC */ +#define SYSCON_EMCCAL_CALVALUE_MASK (0xff << SYSCON_EMCCAL_CALVALUE_SHIFT) + /* Bits 8-13: Reserved */ +#define SYSCON_EMCCAL_START_SHIFT (14) /* Bit 14: Start control bit for EMC calibration counter */ +#define SYSCON_EMCCAL_START_MASK (1 << SYSCON_EMCCAL_START_SHIFT) +# define SYSCON_EMCCAL_START (1) /* Automatically cleared when measurement is done */ +#define SYSCON_EMCCAL_DONE_SHIFT (15) /* Bit 15: Measurement completetion flag bit */ +#define SYSCON_EMCCAL_DONE_MASK (1 << SYSCON_EMCCAL_DONE_SHIFT) + /* Automatically cleared when START bit is set */ + /* Bits 16-31: Reserved */ + +/* Compatibility Definitions ************************************************************************/ +/* Need in lpc17_40_clockconfig.h for compatibility with the LPC176x family: */ + +#define SYSCON_PLLCON_PLLC (0) /* Bit does not exist in LPC178x/40xx family */ +#define SYSCON_PLL0STAT_PLLE SYSCON_PLLSTAT_PLLE /* PLL enable readback */ +#define SYSCON_PLL0STAT_PLLC SYSCON_PLLSTAT_PLLC /* PLL connect readback */ +#define SYSCON_PLL0STAT_PLOCK SYSCON_PLLSTAT_PLOCK /* PLL lock status */ +#define SYSCON_PLL1STAT_PLLE SYSCON_PLLSTAT_PLLE /* PLL enable readback */ +#define SYSCON_PLL1STAT_PLLC SYSCON_PLLSTAT_PLLC /* PLL connect readback */ +#define SYSCON_PLL1STAT_PLOCK SYSCON_PLLSTAT_PLOCK /* PLL lock status */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC178X_SYSCON_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_adc.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_adc.h similarity index 77% rename from arch/arm/src/lpc17xx/hardware/lpc17_adc.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_adc.h index fc6fb80b000..7b46983dadd 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_adc.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_adc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_adc.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_adc.h * * Copyright (C) 2010, 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_ADC_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_ADC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_ADC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_ADC_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "hardware/lpc17_memorymap.h" +#include "hardware/lpc17_40_memorymap.h" /************************************************************************************ * Pre-processor Definitions @@ -51,41 +51,41 @@ /* Register offsets *****************************************************************/ -#define LPC17_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ -#define LPC17_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ -#define LPC17_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ +#define LPC17_40_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ +#define LPC17_40_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ +#define LPC17_40_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ -#define LPC17_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) -#define LPC17_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ -#define LPC17_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ -#define LPC17_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ -#define LPC17_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ -#define LPC17_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ -#define LPC17_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ -#define LPC17_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ -#define LPC17_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ +#define LPC17_40_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) +#define LPC17_40_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ +#define LPC17_40_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ +#define LPC17_40_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ +#define LPC17_40_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ +#define LPC17_40_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ +#define LPC17_40_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ +#define LPC17_40_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ +#define LPC17_40_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ -#define LPC17_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ -#define LPC17_ADC_TRM_OFFSET 0x0034 /* ADC trim register */ +#define LPC17_40_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ +#define LPC17_40_ADC_TRM_OFFSET 0x0034 /* ADC trim register */ /* Register addresses ***************************************************************/ -#define LPC17_ADC_CR (LPC17_ADC_BASE+LPC17_ADC_CR_OFFSET) -#define LPC17_ADC_GDR (LPC17_ADC_BASE+LPC17_ADC_GDR_OFFSET) -#define LPC17_ADC_INTEN (LPC17_ADC_BASE+LPC17_ADC_INTEN_OFFSET) +#define LPC17_40_ADC_CR (LPC17_40_ADC_BASE+LPC17_40_ADC_CR_OFFSET) +#define LPC17_40_ADC_GDR (LPC17_40_ADC_BASE+LPC17_40_ADC_GDR_OFFSET) +#define LPC17_40_ADC_INTEN (LPC17_40_ADC_BASE+LPC17_40_ADC_INTEN_OFFSET) -#define LPC17_ADC_DR(n) (LPC17_ADC_BASE+LPC17_ADC_DR_OFFSET(n)) -#define LPC17_ADC_DR0 (LPC17_ADC_BASE+LPC17_ADC_DR0_OFFSET) -#define LPC17_ADC_DR1 (LPC17_ADC_BASE+LPC17_ADC_DR1_OFFSET) -#define LPC17_ADC_DR2 (LPC17_ADC_BASE+LPC17_ADC_DR2_OFFSET) -#define LPC17_ADC_DR3 (LPC17_ADC_BASE+LPC17_ADC_DR3_OFFSET) -#define LPC17_ADC_DR4 (LPC17_ADC_BASE+LPC17_ADC_DR4_OFFSET) -#define LPC17_ADC_DR5 (LPC17_ADC_BASE+LPC17_ADC_DR5_OFFSET) -#define LPC17_ADC_DR6 (LPC17_ADC_BASE+LPC17_ADC_DR6_OFFSET) -#define LPC17_ADC_DR7 (LPC17_ADC_BASE+LPC17_ADC_DR7_OFFSET) +#define LPC17_40_ADC_DR(n) (LPC17_40_ADC_BASE+LPC17_40_ADC_DR_OFFSET(n)) +#define LPC17_40_ADC_DR0 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR0_OFFSET) +#define LPC17_40_ADC_DR1 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR1_OFFSET) +#define LPC17_40_ADC_DR2 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR2_OFFSET) +#define LPC17_40_ADC_DR3 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR3_OFFSET) +#define LPC17_40_ADC_DR4 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR4_OFFSET) +#define LPC17_40_ADC_DR5 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR5_OFFSET) +#define LPC17_40_ADC_DR6 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR6_OFFSET) +#define LPC17_40_ADC_DR7 (LPC17_40_ADC_BASE+LPC17_40_ADC_DR7_OFFSET) -#define LPC17_ADC_STAT (LPC17_ADC_BASE+LPC17_ADC_STAT_OFFSET) -#define LPC17_ADC_TRM (LPC17_ADC_BASE+LPC17_ADC_TRM_OFFSET) +#define LPC17_40_ADC_STAT (LPC17_40_ADC_BASE+LPC17_40_ADC_STAT_OFFSET) +#define LPC17_40_ADC_TRM (LPC17_40_ADC_BASE+LPC17_40_ADC_TRM_OFFSET) /* Register bit definitions *********************************************************/ @@ -177,4 +177,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_ADC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_ADC_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h new file mode 100644 index 00000000000..0195e1ac204 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h @@ -0,0 +1,510 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h + * + * Copyright (C) 2010-2012, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_CAN_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_CAN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* CAN acceptance filter registers */ + +#define LPC17_40_CANAF_AFMR_OFFSET 0x0000 /* Acceptance Filter Register */ +#define LPC17_40_CANAF_SFFSA_OFFSET 0x0004 /* Standard Frame Individual Start Address Register */ +#define LPC17_40_CANAF_SFFGRPSA_OFFSET 0x0008 /* Standard Frame Group Start Address Register */ +#define LPC17_40_CANAF_EFFSA_OFFSET 0x000c /* Extended Frame Start Address Register */ +#define LPC17_40_CANAF_EFFGRPSA_OFFSET 0x0010 /* Extended Frame Group Start Address Register */ +#define LPC17_40_CANAF_EOT_OFFSET 0x0014 /* End of AF Tables register */ +#define LPC17_40_CANAF_LUTERRAD_OFFSET 0x0018 /* LUT Error Address register */ +#define LPC17_40_CANAF_LUTERR_OFFSET 0x001c /* LUT Error Register */ +#define LPC17_40_CANAF_FCANIE_OFFSET 0x0020 /* FullCAN interrupt enable register */ +#define LPC17_40_CANAF_FCANIC0_OFFSET 0x0024 /* FullCAN interrupt and capture register 0 */ +#define LPC17_40_CANAF_FCANIC1_OFFSET 0x0028 /* FullCAN interrupt and capture register 1 */ + +/* Central CAN registers */ + +#define LPC17_40_CAN_TXSR_OFFSET 0x0000 /* CAN Central Transmit Status Register */ +#define LPC17_40_CAN_RXSR_OFFSET 0x0004 /* CAN Central Receive Status Register */ +#define LPC17_40_CAN_MSR_OFFSET 0x0008 /* CAN Central Miscellaneous Register */ + +/* CAN1/2 registers */ + +#define LPC17_40_CAN_MOD_OFFSET 0x0000 /* CAN operating mode */ +#define LPC17_40_CAN_CMR_OFFSET 0x0004 /* Command bits */ +#define LPC17_40_CAN_GSR_OFFSET 0x0008 /* Controller Status and Error Counters */ +#define LPC17_40_CAN_ICR_OFFSET 0x000c /* Interrupt and capure register */ +#define LPC17_40_CAN_IER_OFFSET 0x0010 /* Interrupt Enable */ +#define LPC17_40_CAN_BTR_OFFSET 0x0014 /* Bus Timing */ +#define LPC17_40_CAN_EWL_OFFSET 0x0018 /* Error Warning Limit */ +#define LPC17_40_CAN_SR_OFFSET 0x001c /* Status Register */ +#define LPC17_40_CAN_RFS_OFFSET 0x0020 /* Receive frame status */ +#define LPC17_40_CAN_RID_OFFSET 0x0024 /* Received Identifier */ +#define LPC17_40_CAN_RDA_OFFSET 0x0028 /* Received data bytes 1-4 */ +#define LPC17_40_CAN_RDB_OFFSET 0x002c /* Received data bytes 5-8 */ +#define LPC17_40_CAN_TFI1_OFFSET 0x0030 /* Transmit frame info (Tx Buffer 1) */ +#define LPC17_40_CAN_TID1_OFFSET 0x0034 /* Transmit Identifier (Tx Buffer 1) */ +#define LPC17_40_CAN_TDA1_OFFSET 0x0038 /* Transmit data bytes 1-4 (Tx Buffer 1) */ +#define LPC17_40_CAN_TDB1_OFFSET 0x003c /* Transmit data bytes 5-8 (Tx Buffer 1) */ +#define LPC17_40_CAN_TFI2_OFFSET 0x0040 /* Transmit frame info (Tx Buffer 2) */ +#define LPC17_40_CAN_TID2_OFFSET 0x0044 /* Transmit Identifier (Tx Buffer 2) */ +#define LPC17_40_CAN_TDA2_OFFSET 0x0048 /* Transmit data bytes 1-4 (Tx Buffer 2) */ +#define LPC17_40_CAN_TDB2_OFFSET 0x004c /* Transmit data bytes 5-8 (Tx Buffer 2) */ +#define LPC17_40_CAN_TFI3_OFFSET 0x0050 /* Transmit frame info (Tx Buffer 3) */ +#define LPC17_40_CAN_TID3_OFFSET 0x0054 /* Transmit Identifier (Tx Buffer 3) */ +#define LPC17_40_CAN_TDA3_OFFSET 0x0058 /* Transmit data bytes 1-4 (Tx Buffer 3) */ +#define LPC17_40_CAN_TDB3_OFFSET 0x005c /* Transmit data bytes 5-8 (Tx Buffer 3) */ + +/* Register addresses ***************************************************************/ +/* CAN acceptance filter registers */ + +#define LPC17_40_CANAF_AFMR (LPC17_40_CANAF_BASE+LPC17_40_CANAF_AFMR_OFFSET) +#define LPC17_40_CANAF_SFFSA (LPC17_40_CANAF_BASE+LPC17_40_CANAF_SFFSA_OFFSET) +#define LPC17_40_CANAF_SFFGRPSA (LPC17_40_CANAF_BASE+LPC17_40_CANAF_SFFGRPSA_OFFSET) +#define LPC17_40_CANAF_EFFSA (LPC17_40_CANAF_BASE+LPC17_40_CANAF_EFFSA_OFFSET) +#define LPC17_40_CANAF_EFFGRPSA (LPC17_40_CANAF_BASE+LPC17_40_CANAF_EFFGRPSA_OFFSET) +#define LPC17_40_CANAF_EOT (LPC17_40_CANAF_BASE+LPC17_40_CANAF_EOT_OFFSET) +#define LPC17_40_CANAF_LUTERRAD (LPC17_40_CANAF_BASE+LPC17_40_CANAF_LUTERRAD_OFFSET) +#define LPC17_40_CANAF_LUTERR (LPC17_40_CANAF_BASE+LPC17_40_CANAF_LUTERR_OFFSET) +#define LPC17_40_CANAF_FCANIE (LPC17_40_CANAF_BASE+LPC17_40_CANAF_FCANIE_OFFSET) +#define LPC17_40_CANAF_FCANIC0 (LPC17_40_CANAF_BASE+LPC17_40_CANAF_FCANIC0_OFFSET) +#define LPC17_40_CANAF_FCANIC1 (LPC17_40_CANAF_BASE+LPC17_40_CANAF_FCANIC1_OFFSET) + +/* Central CAN registers */ + +#define LPC17_40_CAN_TXSR (LPC17_40_CAN_BASE+LPC17_40_CAN_TXSR_OFFSET) +#define LPC17_40_CAN_RXSR (LPC17_40_CAN_BASE+LPC17_40_CAN_RXSR_OFFSET) +#define LPC17_40_CAN_MSR (LPC17_40_CAN_BASE+LPC17_40_CAN_MSR_OFFSET) + +/* CAN1/2 registers */ + +#define LPC17_40_CAN1_MOD (LPC17_40_CAN1_BASE+LPC17_40_CAN_MOD_OFFSET) +#define LPC17_40_CAN1_CMR (LPC17_40_CAN1_BASE+LPC17_40_CAN_CMR_OFFSET) +#define LPC17_40_CAN1_GSR (LPC17_40_CAN1_BASE+LPC17_40_CAN_GSR_OFFSET) +#define LPC17_40_CAN1_ICR (LPC17_40_CAN1_BASE+LPC17_40_CAN_ICR_OFFSET) +#define LPC17_40_CAN1_IER (LPC17_40_CAN1_BASE+LPC17_40_CAN_IER_OFFSET) +#define LPC17_40_CAN1_BTR (LPC17_40_CAN1_BASE+LPC17_40_CAN_BTR_OFFSET) +#define LPC17_40_CAN1_EWL (LPC17_40_CAN1_BASE+LPC17_40_CAN_EWL_OFFSET) +#define LPC17_40_CAN1_SR (LPC17_40_CAN1_BASE+LPC17_40_CAN_SR_OFFSET) +#define LPC17_40_CAN1_RFS (LPC17_40_CAN1_BASE+LPC17_40_CAN_RFS_OFFSET) +#define LPC17_40_CAN1_RID (LPC17_40_CAN1_BASE+LPC17_40_CAN_RID_OFFSET) +#define LPC17_40_CAN1_RDA (LPC17_40_CAN1_BASE+LPC17_40_CAN_RDA_OFFSET) +#define LPC17_40_CAN1_RDB (LPC17_40_CAN1_BASE+LPC17_40_CAN_RDB_OFFSET) +#define LPC17_40_CAN1_TFI1 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TFI1_OFFSET) +#define LPC17_40_CAN1_TID1 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TID1_OFFSET) +#define LPC17_40_CAN1_TDA1 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TDA1_OFFSET) +#define LPC17_40_CAN1_TDB1 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TDB1_OFFSET) +#define LPC17_40_CAN1_TFI2 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TFI2_OFFSET) +#define LPC17_40_CAN1_TID2 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TID2_OFFSET) +#define LPC17_40_CAN1_TDA2 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TDA2_OFFSET) +#define LPC17_40_CAN1_TDB2 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TDB2_OFFSET) +#define LPC17_40_CAN1_TFI3 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TFI3_OFFSET) +#define LPC17_40_CAN1_TID3 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TID3_OFFSET) +#define LPC17_40_CAN1_TDA3 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TDA3_OFFSET) +#define LPC17_40_CAN1_TDB3 (LPC17_40_CAN1_BASE+LPC17_40_CAN_TDB3_OFFSET) + +#define LPC17_40_CAN2_MOD (LPC17_40_CAN2_BASE+LPC17_40_CAN_MOD_OFFSET) +#define LPC17_40_CAN2_CMR (LPC17_40_CAN2_BASE+LPC17_40_CAN_CMR_OFFSET) +#define LPC17_40_CAN2_GSR (LPC17_40_CAN2_BASE+LPC17_40_CAN_GSR_OFFSET) +#define LPC17_40_CAN2_ICR (LPC17_40_CAN2_BASE+LPC17_40_CAN_ICR_OFFSET) +#define LPC17_40_CAN2_IER (LPC17_40_CAN2_BASE+LPC17_40_CAN_IER_OFFSET) +#define LPC17_40_CAN2_BTR (LPC17_40_CAN2_BASE+LPC17_40_CAN_BTR_OFFSET) +#define LPC17_40_CAN2_EWL (LPC17_40_CAN2_BASE+LPC17_40_CAN_EWL_OFFSET) +#define LPC17_40_CAN2_SR (LPC17_40_CAN2_BASE+LPC17_40_CAN_SR_OFFSET) +#define LPC17_40_CAN2_RFS (LPC17_40_CAN2_BASE+LPC17_40_CAN_RFS_OFFSET) +#define LPC17_40_CAN2_RID (LPC17_40_CAN2_BASE+LPC17_40_CAN_RID_OFFSET) +#define LPC17_40_CAN2_RDA (LPC17_40_CAN2_BASE+LPC17_40_CAN_RDA_OFFSET) +#define LPC17_40_CAN2_RDB (LPC17_40_CAN2_BASE+LPC17_40_CAN_RDB_OFFSET) +#define LPC17_40_CAN2_TFI1 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TFI1_OFFSET) +#define LPC17_40_CAN2_TID1 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TID1_OFFSET) +#define LPC17_40_CAN2_TDA1 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TDA1_OFFSET) +#define LPC17_40_CAN2_TDB1 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TDB1_OFFSET) +#define LPC17_40_CAN2_TFI2 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TFI2_OFFSET) +#define LPC17_40_CAN2_TID2 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TID2_OFFSET) +#define LPC17_40_CAN2_TDA2 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TDA2_OFFSET) +#define LPC17_40_CAN2_TDB2 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TDB2_OFFSET) +#define LPC17_40_CAN2_TFI3 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TFI3_OFFSET) +#define LPC17_40_CAN2_TID3 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TID3_OFFSET) +#define LPC17_40_CAN2_TDA3 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TDA3_OFFSET) +#define LPC17_40_CAN2_TDB3 (LPC17_40_CAN2_BASE+LPC17_40_CAN_TDB3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* CAN acceptance filter registers */ +/* Acceptance Filter Register */ + +#define CANAF_AFMR_ACCOFF (1 << 0) /* Bit 0: AF non-operational; All RX messages ignored */ +#define CANAF_AFMR_ACCBP (1 << 1) /* Bit 1: AF bypass: All RX messages accepted */ +#define CANAF_AFMR_EFCAN (1 << 2) /* Bit 2: Enable Full CAN mode */ + /* Bits 3-31: Reserved */ +/* Standard Frame Individual Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_SFFSA_SHIFT (2) /* Bits 2-10: Address of Standard Identifiers in AF Lookup RAM */ +#define CANAF_SFFSA_MASK (0x01ff << CANAF_SFFSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Standard Frame Group Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_SFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Standard Identifiers in AF Lookup RAM */ +#define CANAF_SFFGRPSA_MASK (0x01ff << CANAF_SFFGRPSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Extended Frame Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_EFFSA_SHIFT (2) /* Bits 2-10: Address of Extended Identifiers in AF Lookup RAM */ +#define CANAF_EFFSA_MASK (0x01ff << CANAF_EFFSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Extended Frame Group Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_EFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Extended Identifiers in AF Lookup RAM */ +#define CANAF_EFFGRPSA_MASK (0x01ff << CANAF_EFFGRPSA_SHIFT) + /* Bits 11-31: Reserved */ +/* End of AF Tables register */ + /* Bits 0-1: Reserved */ +#define CANAF_EOT_SHIFT (2) /* Bits 2-10: Last active address in last active AF table */ +#define CANAF_EOT_MASK (0x01ff << CANAF_EOT_SHIFT) + /* Bits 11-31: Reserved */ +/* LUT Error Address register */ + /* Bits 0-1: Reserved */ +#define CANAF_LUTERRAD_SHIFT (2) /* Bits 2-10: Address in AF Lookup RAM of error */ +#define CANAF_LUTERRAD_MASK (0x01ff << CANAF_EOT_SHIFT) + /* Bits 11-31: Reserved */ +/* LUT Error Register */ + +#define CANAF_LUTERR_LUTERR (1 << 0) /* Bit 0: AF error in AF RAM tables */ + /* Bits 1-31: Reserved */ +/* FullCAN interrupt enable register */ + +#define CANAF_FCANIE_FCANIE (1 << 0) /* Bit 0: Global FullCAN Interrupt Enable */ + /* Bits 1-31: Reserved */ + +/* FullCAN interrupt and capture register 0 */ + +#define CANAF_FCANIC0_INTPND(n) (1 << (n)) /* n=0,1,2,... 31 */ + +/* FullCAN interrupt and capture register 1 */ + +#define CANAF_FCANIC1_INTPND(n) (1 << ((n)-32)) /* n=32,33,...63 */ + +/* Central CAN registers */ +/* CAN Central Transmit Status Register */ + +#define CAN_TXSR_TS1 (1 << 0) /* Bit 0: CAN1 sending */ +#define CAN_TXSR_TS2 (1 << 1) /* Bit 1: CAN2 sending */ + /* Bits 2-7: Reserved */ +#define CAN_TXSR_TBS1 (1 << 8) /* Bit 8: All 3 CAN1 TX buffers available */ +#define CAN_TXSR_TBS2 (1 << 9) /* Bit 9: All 3 CAN2 TX buffers available */ + /* Bits 10-15: Reserved */ +#define CAN_TXSR_TCS1 (1 << 16) /* Bit 16: All CAN1 xmissions completed */ +#define CAN_TXSR_TCS2 (1 << 17) /* Bit 17: All CAN2 xmissions completed */ + /* Bits 18-31: Reserved */ +/* CAN Central Receive Status Register */ + +#define CAN_RXSR_RS1 (1 << 0) /* Bit 0: CAN1 receiving */ +#define CAN_RXSR_RS2 (1 << 1) /* Bit 1: CAN2 receiving */ + /* Bits 2-7: Reserved */ +#define CAN_RXSR_RB1 (1 << 8) /* Bit 8: CAN1 received message available */ +#define CAN_RXSR_RB2 (1 << 9) /* Bit 9: CAN2 received message available */ + /* Bits 10-15: Reserved */ +#define CAN_RXSR_DOS1 (1 << 16) /* Bit 16: All CAN1 message lost */ +#define CAN_RXSR_DOS2 (1 << 17) /* Bit 17: All CAN2 message lost */ + /* Bits 18-31: Reserved */ +/* CAN Central Miscellaneous Register */ + +#define CAN_MSR_E1 (1 << 0) /* Bit 0: CAN1 error counters at limit */ +#define CAN_MSR_E2 (1 << 1) /* Bit 1: CAN2 error counters at limit */ + /* Bits 2-7: Reserved */ +#define CAN_MSR_BS1 (1 << 8) /* Bit 8: CAN1 busy */ +#define CAN_MSR_BS2 (1 << 9) /* Bit 7: CAN2 busy */ + /* Bits 10-31: Reserved */ +/* CAN1/2 registers */ +/* CAN operating mode */ + +#define CAN_MOD_RM (1 << 0) /* Bit 0: Reset Mode */ +#define CAN_MOD_LOM (1 << 1) /* Bit 1: Listen Only Mode */ +#define CAN_MOD_STM (1 << 2) /* Bit 2: Self Test Mode */ +#define CAN_MOD_TPM (1 << 3) /* Bit 3: Transmit Priority Mode */ +#define CAN_MOD_SM (1 << 4) /* Bit 4: Sleep Mode */ +#define CAN_MOD_RPM (1 << 5) /* Bit 5: Receive Polarity Mode */ + /* Bit 6: Reserved */ +#define CAN_MOD_TM (1 << 7) /* Bit 7: Test Mode */ + /* Bits 8-31: Reserved */ +/* Command bits */ + +#define CAN_CMR_TR (1 << 0) /* Bit 0: Transmission Request */ +#define CAN_CMR_AT (1 << 1) /* Bit 1: Abort Transmission */ +#define CAN_CMR_RRB (1 << 2) /* Bit 2: Release Receive Buffer */ +#define CAN_CMR_CDO (1 << 3) /* Bit 3: Clear Data Overrun */ +#define CAN_CMR_SRR (1 << 4) /* Bit 4: Self Reception Request */ +#define CAN_CMR_STB1 (1 << 5) /* Bit 5: Select Tx Buffer 1 */ +#define CAN_CMR_STB2 (1 << 6) /* Bit 6: Select Tx Buffer 2 */ +#define CAN_CMR_STB3 (1 << 7) /* Bit 7: Select Tx Buffer 3 */ + /* Bits 8-31: Reserved */ +/* Controller Status and Error Counters */ + +#define CAN_GSR_RBS (1 << 0) /* Bit 0: Receive Buffer Status */ +#define CAN_GSR_DOS (1 << 1) /* Bit 1: Data Overrun Status */ +#define CAN_GSR_TBS (1 << 2) /* Bit 2: Transmit Buffer Status */ +#define CAN_GSR_TCS (1 << 3) /* Bit 3: Transmit Complete Status */ +#define CAN_GSR_RS (1 << 4) /* Bit 4: Receive Status */ +#define CAN_GSR_TS (1 << 5) /* Bit 5: Transmit Status */ +#define CAN_GSR_ES (1 << 6) /* Bit 6: Error Status */ +#define CAN_GSR_BS (1 << 7) /* Bit 7: Bus Status */ + /* Bits 8-15: Reserved */ +#define CAN_GSR_RXERR_SHIFT (16) /* Bits 16-23: Rx Error Counter */ +#define CAN_GSR_RXERR_MASK (0xff << CAN_GSR_RXERR_SHIFT) +#define CAN_GSR_TXERR_SHIFT (24) /* Bits 24-31: Tx Error Counter */ +#define CAN_GSR_TXERR_MASK (0xff << CAN_GSR_TXERR_SHIFT) + +/* Interrupt and capture register */ + +#define CAN_ICR_RI (1 << 0) /* Bit 0: Receive Interrupt */ +#define CAN_ICR_TI1 (1 << 1) /* Bit 1: Transmit Interrupt 1 */ +#define CAN_ICR_EI (1 << 2) /* Bit 2: Error Warning Interrupt */ +#define CAN_ICR_DOI (1 << 3) /* Bit 3: Data Overrun Interrupt */ +#define CAN_ICR_WUI (1 << 4) /* Bit 4: Wake-Up Interrupt */ +#define CAN_ICR_EPI (1 << 5) /* Bit 5: Error Passive Interrupt */ +#define CAN_ICR_ALI (1 << 6) /* Bit 6: Arbitration Lost Interrupt */ +#define CAN_ICR_BEI (1 << 7) /* Bit 7: Bus Error Interrupt */ +#define CAN_ICR_IDI (1 << 8) /* Bit 8: ID Ready Interrupt */ +#define CAN_ICR_TI2 (1 << 9) /* Bit 9: Transmit Interrupt 2 */ +#define CAN_ICR_TI3 (1 << 10) /* Bit 10: Transmit Interrupt 3 */ + /* Bits 11-15: Reserved */ +#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */ +#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT) +# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ +# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ +# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ +# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ +# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ +# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ +# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ +# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ +# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ +# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ +# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ +# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ +# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ +# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ +# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ +# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ +# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ +# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ +# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ +# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ +# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ +# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ +#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */ +#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */ +#define CAN_ICR_ERRC_MASK (3 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_BIT (0 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_FORM (1 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_STUFF (2 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_OTHER (3 << CAN_ICR_ERRC_SHIFT) +#define CAN_ICR_ALCBIT_SHIFT (24) /* Bits 24-31: Bit number within frame */ +#define CAN_ICR_ALCBIT_MASK (0xff << CAN_ICR_ALCBIT_SHIFT) + +/* Interrupt Enable */ + +#define CAN_IER_RIE (1 << 0) /* Bit 0: Receiver Interrupt Enable */ +#define CAN_IER_TIE1 (1 << 1) /* Bit 1: Transmit Interrupt Enable for Buffer1 */ +#define CAN_IER_EIE (1 << 2) /* Bit 2: Error Warning Interrupt Enable */ +#define CAN_IER_DOIE (1 << 3) /* Bit 3: Data Overrun Interrupt Enable */ +#define CAN_IER_WUIE (1 << 4) /* Bit 4: Wake-Up Interrupt Enable */ +#define CAN_IER_EPIE (1 << 5) /* Bit 5: Error Passive Interrupt Enable */ +#define CAN_IER_ALIE (1 << 6) /* Bit 6: Arbitration Lost Interrupt Enable */ +#define CAN_IER_BEIE (1 << 7) /* Bit 7: Bus Error Interrupt */ +#define CAN_IER_IDIE (1 << 8) /* Bit 8: ID Ready Interrupt Enable */ +#define CAN_IER_TIE2 (1 << 9) /* Bit 9: Transmit Interrupt Enable for Buffer2 */ +#define CAN_IER_TIE3 (1 << 10) /* Bit 10: Transmit Interrupt Enable for Buffer3 */ + /* Bits 11-31: Reserved */ +/* Bus Timing */ + +#define CAN_BTR_BRP_SHIFT (0) /* Bits 0-9: Baud Rate Prescaler */ +#define CAN_BTR_BRP_MASK (0x3ff << CAN_BTR_BRP_SHIFT) + /* Bits 10-13: Reserved */ +#define CAN_BTR_SJW_SHIFT (14) /* Bits 14-15: Synchronization Jump Width */ +#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) +#define CAN_BTR_TSEG1_SHIFT (16) /* Bits 16-19: Sync to sample delay */ +#define CAN_BTR_TSEG1_MASK (15 << CAN_BTR_TSEG1_SHIFT) +#define CAN_BTR_TSEG2_SHIFT (20) /* Bits 20-22: smaple to next delay */ +#define CAN_BTR_TSEG2_MASK (7 << CAN_BTR_TSEG2_SHIFT) +#define CAN_BTR_SAM (1 << 23) /* Bit 23: Sampling */ + /* Bits 24-31: Reserved */ + +#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ +#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ +#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ + +/* Error Warning Limit */ + +#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ +#define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT) + /* Bits 8-31: Reserved */ +/* Status Register */ + +#define CAN_SR_RBS1 (1 << 0) /* Bit 0: Receive Buffer Status */ +#define CAN_SR_DOS1 (1 << 1) /* Bit 1: Data Overrun Status */ +#define CAN_SR_TBS1 (1 << 2) /* Bit 2: Transmit Buffer Status 1 */ +#define CAN_SR_TCS1 (1 << 3) /* Bit 3: Transmission Complete Status */ +#define CAN_SR_RS1 (1 << 4) /* Bit 4: Receive Status */ +#define CAN_SR_TS1 (1 << 5) /* Bit 5: Transmit Status 1 */ +#define CAN_SR_ES1 (1 << 6) /* Bit 6: Error Status */ +#define CAN_SR_BS1 (1 << 7) /* Bit 7: Bus Status */ +#define CAN_SR_RBS2 (1 << 8) /* Bit 8: Receive Buffer Status */ +#define CAN_SR_DOS2 (1 << 9) /* Bit 9: Data Overrun Status */ +#define CAN_SR_TBS2 (1 << 10) /* Bit 10: Transmit Buffer Status 2 */ +#define CAN_SR_TCS2 (1 << 11) /* Bit 11: Transmission Complete Status */ +#define CAN_SR_RS2 (1 << 12) /* Bit 12: Receive Status */ +#define CAN_SR_TS2 (1 << 13) /* Bit 13: Transmit Status 2 */ +#define CAN_SR_ES2 (1 << 14) /* Bit 14: Error Status */ +#define CAN_SR_BS2 (1 << 15) /* Bit 15: Bus Status */ +#define CAN_SR_RBS3 (1 << 16) /* Bit 16: Receive Buffer Status */ +#define CAN_SR_DOS3 (1 << 17) /* Bit 17: Data Overrun Status */ +#define CAN_SR_TBS3 (1 << 18) /* Bit 18: Transmit Buffer Status 3 */ +#define CAN_SR_TCS3 (1 << 19) /* Bit 19: Transmission Complete Status */ +#define CAN_SR_RS3 (1 << 20) /* Bit 20: Receive Status */ +#define CAN_SR_TS3 (1 << 21) /* Bit 21: Transmit Status 3 */ +#define CAN_SR_ES3 (1 << 22) /* Bit 22: Error Status */ +#define CAN_SR_BS3 (1 << 23) /* Bit 23: Bus Status */ + /* Bits 24-31: Reserved */ +/* Receive frame status */ + +#define CAN_RFS_ID_SHIFT (0) /* Bits 0-9: ID Index */ +#define CAN_RFS_ID_MASK (0x03ff << CAN_RFS_ID_SHIFT) +#define CAN_RFS_BP (1 << 10) /* Bit 10: Received in AF Bypass mode */ + /* Bits 11-15: Reserved */ +#define CAN_RFS_DLC_SHIFT (16) /* Bits 16-19: Message Data Length Code (DLC) */ +#define CAN_RFS_DLC_MASK (15 << CAN_RFS_DLC_SHIFT) + /* Bits 20-29: Reserved */ +#define CAN_RFS_RTR (1 << 30) /* Bit 30: Message Remote Transmission Request */ +#define CAN_RFS_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ + +/* Received Identifier */ + +#define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ + /* Bits 11-31: Reserved */ +#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ + /* Bits 29-31: Reserved */ +/* Received data bytes 1-4 */ + +#define CAN_RDA_DATA1_SHIFT (0) /* Bits 0-7: If CANRFS >= 1 */ +#define CAN_RDA_DATA1_MASK (0x0ff << CAN_RDA_DATA1_SHIFT) +#define CAN_RDA_DATA2_SHIFT (8) /* Bits 8-15: If CANRFS >= 2 */ +#define CAN_RDA_DATA2_MASK (0x0ff << CAN_RDA_DATA2_SHIFT) +#define CAN_RDA_DATA3_SHIFT (16) /* Bits 16-23: If CANRFS >= 3 */ +#define CAN_RDA_DATA3_MASK (0x0ff << CAN_RDA_DATA3_SHIFT) +#define CAN_RDA_DATA4_SHIFT (24) /* Bits 24-31: If CANRFS >= 4 */ +#define CAN_RDA_DATA4_MASK (0x0ff << CAN_RDA_DATA4_SHIFT) + +/* Received data bytes 5-8 */ + +#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: If CANRFS >= 5 */ +#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) +#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: If CANRFS >= 6 */ +#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) +#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: If CANRFS >= 7 */ +#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) +#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: If CANRFS >= 8 */ +#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) + +/* Transmit frame info (Tx Buffer 1), Transmit frame info (Tx Buffer 2), and + * Transmit frame info (Tx Buffer 3) common bit field definitions + */ + +#define CAN_TFI_PRIO_SHIFT (0) /* Bits 0-7: TX buffer priority */ +#define CAN_TFI_PRIO_MASK (0xff << CAN_TFI_PRIO_SHIFT) + /* Bits 8-15: Reserved */ +#define CAN_TFI_DLC_SHIFT (16) /* Bits 16-19: TX Data Length Code */ +#define CAN_TFI_DLC_MASK (15 << CAN_TFI_DLC_SHIFT) + /* Bits 20-29: Reserved */ +#define CAN_TFI_RTR (1 << 30) /* Bit 30: TX RTR bit */ +#define CAN_TFI_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ + +/* Transmit Identifier (Tx Buffer 1), Transmit Identifier (Tx Buffer 2), and + * Transmit Identifier (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ + /* Bits 11-31: Reserved */ +#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ + /* Bits 29-31: Reserved */ + +/* Transmit data bytes 1-4 (Tx Buffer 1), Transmit data bytes 1-4 (Tx Buffer 2), and + * Transmit data bytes 1-4 (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_TDA_DATA1_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 1 */ +#define CAN_TDA_DATA1_MASK (0x0ff << CAN_TDA_DATA1_SHIFT) +#define CAN_TDA_DATA2_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 2 */ +#define CAN_TDA_DATA2_MASK (0x0ff << CAN_TDA_DATA2_SHIFT) +#define CAN_TDA_DATA3_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 3 */ +#define CAN_TDA_DATA3_MASK (0x0ff << CAN_TDA_DATA3_SHIFT) +#define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */ +#define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT) + +/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and + * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 5 */ +#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) +#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 6 */ +#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) +#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 7 */ +#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) +#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 8 */ +#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_CAN_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_dac.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_dac.h similarity index 64% rename from arch/arm/src/lpc17xx/hardware/lpc17_dac.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_dac.h index 9e39c1e9825..8b46edb525f 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_dac.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_dac.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_dac.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_dac.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_DAC_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_DAC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_DAC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_DAC_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "hardware/lpc17_memorymap.h" +#include "hardware/lpc17_40_memorymap.h" /************************************************************************************ * Pre-processor Definitions @@ -51,36 +51,36 @@ /* Register offsets *****************************************************************/ -#define LPC17_DAC_CR_OFFSET 0x0000 /* D/A Converter Register */ -#define LPC17_DAC_CTRL_OFFSET 0x0004 /* DAC Control register */ -#define LPC17_DAC_CNTVAL_OFFSET 0x0008 /* DAC Counter Value register */ +#define LPC17_40_DAC_CR_OFFSET 0x0000 /* D/A Converter Register */ +#define LPC17_40_DAC_CTRL_OFFSET 0x0004 /* DAC Control register */ +#define LPC17_40_DAC_CNTVAL_OFFSET 0x0008 /* DAC Counter Value register */ /* Register addresses ***************************************************************/ -#define LPC17_DAC_CR (LPC17_DAC_BASE+LPC17_DAC_CR_OFFSET) -#define LPC17_DAC_CTRL (LPC17_DAC_BASE+LPC17_DAC_CTRL_OFFSET) -#define LPC17_DAC_CNTVAL (LPC17_DAC_BASE+LPC17_DAC_CNTVAL_OFFSET) +#define LPC17_40_DAC_CR (LPC17_40_DAC_BASE+LPC17_40_DAC_CR_OFFSET) +#define LPC17_40_DAC_CTRL (LPC17_40_DAC_BASE+LPC17_40_DAC_CTRL_OFFSET) +#define LPC17_40_DAC_CNTVAL (LPC17_40_DAC_BASE+LPC17_40_DAC_CNTVAL_OFFSET) /* Register bit definitions *********************************************************/ /* D/A Converter Register */ - /* Bits 0-5: Reserved */ -#define DAC_CR_VALUE_SHIFT (6) /* Bits 6-15: Controls voltage on the AOUT pin */ -#define DAC_CR_VALUE_MASK (0x3ff << DAC_CR_VALUE_SHIFT) -#define DAC_CR_BIAS (1 << 16) /* Bit 16: Controls DAC settling time */ - /* Bits 17-31: Reserved */ + /* Bits 0-5: Reserved */ +#define DAC_CR_VALUE_SHIFT (6) /* Bits 6-15: Controls voltage on the AOUT pin */ +#define DAC_CR_VALUE_MASK (0x3ff << DAC_CR_VALUE_SHIFT) +#define DAC_CR_BIAS (1 << 16) /* Bit 16: Controls DAC settling time */ + /* Bits 17-31: Reserved */ /* DAC Control register */ -#define DAC_CTRL_INTDMAREQ (1 << 0) /* Bit 0: Timer timed out */ -#define DAC_CTRL_DBLBUFEN (1 << 1) /* Bit 1: Enable DACR double-buffering */ -#define DAC_CTRL_CNTEN (1 << 2) /* Bit 2: Enable timeout counter */ -#define DAC_CTRL_DMAEN (1 << 3) /* Bit 3: Enable DMA access */ - /* Bits 4-31: Reserved */ +#define DAC_CTRL_INTDMAREQ (1 << 0) /* Bit 0: Timer timed out */ +#define DAC_CTRL_DBLBUFEN (1 << 1) /* Bit 1: Enable DACR double-buffering */ +#define DAC_CTRL_CNTEN (1 << 2) /* Bit 2: Enable timeout counter */ +#define DAC_CTRL_DMAEN (1 << 3) /* Bit 3: Enable DMA access */ + /* Bits 4-31: Reserved */ /* DAC Counter Value register */ -#define DAC_CNTVAL_SHIFT (0) /* Bits 0-15: Reload value for DAC interrupt/DMA timer */ -#define DAC_CNTVAL_MASK (0xffff << DAC_CNTVAL_SHIFT) - /* Bits 8-31: Reserved */ +#define DAC_CNTVAL_SHIFT (0) /* Bits 0-15: Reload value for DAC interrupt/DMA timer */ +#define DAC_CNTVAL_MASK (0xffff << DAC_CNTVAL_SHIFT) + /* Bits 8-31: Reserved */ /************************************************************************************ * Public Types @@ -94,4 +94,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_DAC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_DAC_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_eeprom.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_eeprom.h new file mode 100644 index 00000000000..b216ecdf1e4 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_eeprom.h @@ -0,0 +1,186 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_eeprom.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_EEPROM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_EEPROM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_EEPROM_EECMD_OFFSET 0x0080 /* Command register */ +#define LPC17_40_EEPROM_EEADDR_OFFSET 0x0084 /* Address register */ +#define LPC17_40_EEPROM_EEWDATA_OFFSET 0x0088 /* Write Data register */ +#define LPC17_40_EEPROM_EERDATA_OFFSET 0x008c /* Read Data register */ +#define LPC17_40_EEPROM_EEWSTATE_OFFSET 0x0090 /* Wait state register */ +#define LPC17_40_EEPROM_EECLKDIV_OFFSET 0x0094 /* Clock divider register */ +#define LPC17_40_EEPROM_EEPWRDWN_OFFSET 0x0098 /* Power down register */ + +#define LPC17_40_EEPROM_INTSTAT_OFFSET 0x0fe0 /* Interrupt status */ +#define LPC17_40_EEPROM_INTEN_OFFSET 0x0fe4 /* Interrupt enable */ +#define LPC17_40_EEPROM_INTSTATCLR_OFFSET 0x0fe8 /* Interrupt status clear */ +#define LPC17_40_EEPROM_INTENCLR_OFFSET 0x0fd8 /* Interrupt enable clear */ +#define LPC17_40_EEPROM_INTENSET_OFFSET 0x0fdc /* Interrupt enable set */ +#define LPC17_40_EEPROM_INTSTATSET_OFFSET 0x0fec /* Interrupt status set */ + +#define LPC17_40_EEPROM_EECMD (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EECMD_OFFSET) +#define LPC17_40_EEPROM_EEADDR (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EEADDR_OFFSET) +#define LPC17_40_EEPROM_EEWDATA (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EEWDATA_OFFSET) +#define LPC17_40_EEPROM_EERDATA (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EERDATA_OFFSET) +#define LPC17_40_EEPROM_EEWSTATE (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EEWSTATE_OFFSET) +#define LPC17_40_EEPROM_EECLKDIV (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EECLKDIV_OFFSET) +#define LPC17_40_EEPROM_EEPWRDWN (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_EEPWRDWN_OFFSET) + +#define LPC17_40_EEPROM_INTSTAT (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_INTSTAT_OFFSET) +#define LPC17_40_EEPROM_INTEN (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_INTEN_OFFSET) +#define LPC17_40_EEPROM_INTSTATCLR (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_INTSTATCLR_OFFSET) +#define LPC17_40_EEPROM_INTENCLR (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_INTENCLR_OFFSET) +#define LPC17_40_EEPROM_INTENSET (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_INTENSET_OFFSET) +#define LPC17_40_EEPROM_INTSTATSET (LPC17_40_EEPROM_BASE+LPC17_40_EEPROM_INTSTATSET_OFFSET) + +/* EECMD - EEPROM Command Register */ + +#define EEPROM_CMD_SHIFT (0) /* Bit 0-2: Command */ +#define EEPROM_CMD_MASK (7 << EEPROM_CMD_SHIFT) +# define EECMD_READ8 (0) /* 000: 8bit read */ +# define EECMD_READ16 (1) /* 001: 16bit read */ +# define EECMD_READ32 (2) /* 010: 32bit read */ +# define EECMD_WRITE8 (3) /* 011: 8bit write */ +# define EECMD_WRITE16 (4) /* 100: 16bit write */ +# define EECMD_WRITE32 (5) /* 101: 32bit write */ +# define EEMCD_ERASE (6) /* 110: erase/program page */ + /* 111: Reserved */ +#define EEPROM_RDPREFETCH (1 << 3) /* Bit 3: Read data prefetch bit */ + /* Bits 4-31: Reserved */ +/* EEADDR - EEPROM Address Register */ + +#define EEPROM_ADDR_SHIFT (0) /* Bits 0-11: Address */ +#define EEPROM_ADDR_MASK (0x7ff << EEPROM_EEADDR_ADDR_SHIFT) + /* Bits 12-31: Reserved */ +/* EEPROM Read/Write Data Registers */ +/* R/W registers has no bitfields, data read/write + * must conforms to the expected sizes + */ + +/* EEWSTATE - EEPROM Wait State Register */ + +#define EEPROM_WSTATE_PHASE3_SHIFT (0) /* Bits 0-7: Wait states 3 (minus 1 encoded) */ +#define EEPROM_WSTATE_PHASE3_MASK (0xff << EEWSTATE_PHASE3_SHIFT) +#define EEPROM_WSTATE_PHASE2_SHIFT (8) /* Bits 8-15: Wait states 2 (minus 1 encoded) */ +#define EEPROM_WSTATE_PHASE2_MASK (0xff << EEWSTATE_PHASE2_SHIFT) +#define EEPROM_WSTATE_PHASE1_SHIFT (16) /* Bits 16-23: Wait states 1 (minus 1 encoded) */ +#define EEPROM_WSTATE_PHASE1_MASK (0xff << EEWSTATE_PHASE1_SHIFT) + /* Bits 24-31: Reserved */ + +/* EECLKDIV - EEPROM Clock Divider Register */ + +#define EEPROM_CLKDIV_SHIFT (0) /* Bits 0-15: Division factor (minus 1 encoded) */ +#define EEPROM_CLKDIV_MASK (0xffff << EECLKDIV_CLKDIV_SHIFT) + /* Bits 16-31: Reserved */ + +/* EEPWRDWN - EEPROM Power Down Register */ + +#define EEPROM_PWRDWN (1) /* Bit 0: Power down mode bit */ + /* Bits 1-31: Reserved */ + +/* EEPROM Interrupt Registers ******************************************/ + +/* INTEN - Interrupt Enable Register */ + + /* Bits 0-25: Reserved */ +#define EEPROM_INTEN_RW_DONE (1 << 26) /* Bit 26: Read/Write finished interrupt bit */ + /* Bit 27: Reserved */ +#define EEPROM_INTEN_PROG_DONE (1 << 28) /* Bit 28: Program finished interrupt bit */ + /* Bits 29-31: Reserved */ + +/* INTENCLR - Interrupt Enable Clear Register */ + /* Bits 0-25: Reserved */ +#define EEPROM_INTENCLR_RWCLR_EN (1 << 26) /* Bit 26: Clear R/W interrupt enable bit */ + /* Bits27: Reserved */ +#define EEPROM_INTENCLR_PROG1CLR_EN (1 << 28) /* Bit 28: Clear program interrupt bit */ + /* Bits 29-31: Reserved */ + +/* INTENSET - Interrupt Enable Set Register */ + /* Bits 0-25: Reserved */ +#define EEPROM_INTENSET_RWSET_EN (1 << 26) /* Bit 26: Set Read/Write finished interrupt bit */ + /* Bit 27: Reserved */ +#define EEPROM_INTENSET_PROG1SET_EN (1 << 28) /* Bit 28: Set program interrupt bit */ + /* Bits 29-31: Reserved */ + +/* INTSTAT - Interrupt Status Register */ + /* Bits 0-25: Reserved */ +#define EEPROM_INTSTAT_RW_END (1 << 26) /* Bit 26: Read/Write done status bit */ + /* Bit 27: Reserved */ +#define EEPROM_INTSTAT_PROG1_END (1 << 28) /* Bit 28: Program done status bit */ + /* Bits 29-31: Reserved */ + +/* INTSTATCLR - Interrupt Status Clear Register */ + /* Bits 0-25: Reserved */ +#define EEPROM_INTSTATCLR_RW_CLR (1 << 26) /* Bit 26: Set Read/Write finished interrupt bit */ + /* Bit 27: Reserved */ +#define EEPROM_INTSTATCLR_PROG_1CLR (1 << 28) /* Bit 28: Set program interrupt bit */ + /* Bits 29-31: Reserved */ + +/* INTSTATSET - Interrupt Status Set Register */ + /* Bits 0-25: Reserved */ +#define EEPROM_INTSTATSET_RW_SET (1 << 26) /* Bit 26: Read/Write done status bit */ + /* Bit 27: Reserved */ +#define EEPROM_INTSTATSET_PROG1_SET (1 << 28) /* Bit 28: Program done status bit */ + /* Bits 29-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_EEPROM_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_emc.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_emc.h new file mode 100644 index 00000000000..544702bba34 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_emc.h @@ -0,0 +1,350 @@ +/**************************************************************************************************** + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_emc + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_EMC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_EMC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ +/* Register Offsets */ + +#define LPC17_40_EMC_CONTROL_OFFSET 0x0000 /* EMC Control register */ +#define LPC17_40_EMC_STATUS_OFFSET 0x0004 /* EMC Status register */ +#define LPC17_40_EMC_CONFIG_OFFSET 0x0008 /* EMC Configuration register */ +#define LPC17_40_EMC_DYNAMICCONTROL_OFFSET 0x0020 /* Dynamic Memory Control register */ +#define LPC17_40_EMC_DYNAMICREFRESH_OFFSET 0x0024 /* Dynamic Memory Refresh Timer register */ +#define LPC17_40_EMC_DYNAMICREADCONFIG_OFFSET 0x0028 /* Dynamic Memory Read Configuration register */ +#define LPC17_40_EMC_DYNAMICRP_OFFSET 0x0030 /* Dynamic Memory Precharge Command Period register */ +#define LPC17_40_EMC_DYNAMICRAS_OFFSET 0x0034 /* Dynamic Memory Active to Precharge Command Period register */ +#define LPC17_40_EMC_DYNAMICSREX_OFFSET 0x0038 /* Dynamic Memory Self-refresh Exit Time register */ +#define LPC17_40_EMC_DYNAMICAPR_OFFSET 0x003c /* Dynamic Memory Last Data Out to Active Time register */ +#define LPC17_40_EMC_DYNAMICDAL_OFFSET 0x0040 /* Dynamic Memory Data-in to Active Command Time register */ +#define LPC17_40_EMC_DYNAMICWR_OFFSET 0x0044 /* Dynamic Memory Write Recovery Time register */ +#define LPC17_40_EMC_DYNAMICRC_OFFSET 0x0048 /* Dynamic Memory Active to Active Command Period register */ +#define LPC17_40_EMC_DYNAMICRFC_OFFSET 0x004c /* Dynamic Memory Auto-refresh Period register */ +#define LPC17_40_EMC_DYNAMICXSR_OFFSET 0x0050 /* Dynamic Memory Exit Self-refresh register */ +#define LPC17_40_EMC_DYNAMICRRD_OFFSET 0x0054 /* Dynamic Memory Active Bank A to Active Bank B Time register */ +#define LPC17_40_EMC_DYNAMICMRD_OFFSET 0x0058 /* Dynamic Memory Load Mode register to Active Command Time */ +#define LPC17_40_EMC_STATICEXTENDEDWAIT_OFFSET 0x0080 /* Static Memory Extended Wait register */ + +#define LPC17_40_EMC_DYNAMICCONFIG0_OFFSET 0x0100 /* Dynamic Memory Configuration register 0 */ +#define LPC17_40_EMC_DYNAMICRASCAS0_OFFSET 0x0104 /* Dynamic Memory RAS & CAS Delay register 0 */ + +#define LPC17_40_EMC_DYNAMICCONFIG1_OFFSET 0x0120 /* Dynamic Memory Configuration register 1 */ +#define LPC17_40_EMC_DYNAMICRASCAS1_OFFSET 0x0124 /* Dynamic Memory RAS & CAS Delay register 1 */ + +#define LPC17_40_EMC_DYNAMICCONFIG2_OFFSET 0x0140 /* Dynamic Memory Configuration register 2 */ +#define LPC17_40_EMC_DYNAMICRASCAS2_OFFSET 0x0144 /* Dynamic Memory RAS & CAS Delay register 2 */ + +#define LPC17_40_EMC_DYNAMICCONFIG3_OFFSET 0x0160 /* Dynamic Memory Configuration register 3 */ +#define LPC17_40_EMC_DYNAMICRASCAS3_OFFSET 0x0164 /* Dynamic Memory RAS & CAS Delay register 3 */ + +#define LPC17_40_EMC_STATICCONFIG0_OFFSET 0x0200 /* Static Memory Configuration register 0 */ +#define LPC17_40_EMC_STATICWAITWEN0_OFFSET 0x0204 /* Static Memory Write Enable Delay register 0 */ +#define LPC17_40_EMC_STATICWAITOEN0_OFFSET 0x0208 /* Static Memory Output Enable Delay registers 0 */ +#define LPC17_40_EMC_STATICWAITRD0_OFFSET 0x020c /* Static Memory Read Delay register 0 */ +#define LPC17_40_EMC_STATICWAITPAGE0_OFFSET 0x0210 /* Static Memory Page Mode Read Delay register 0*/ +#define LPC17_40_EMC_STATICWAITWR0_OFFSET 0x0214 /* Static Memory Write Delay register 0 */ +#define LPC17_40_EMC_STATICWAITTURN0_OFFSET 0x0218 /* Static Memory Turn Round Delay register 0 */ + +#define LPC17_40_EMC_STATICCONFIG1_OFFSET 0x0220 /* Static Memory Configuration register 1 */ +#define LPC17_40_EMC_STATICWAITWEN1_OFFSET 0x0224 /* Static Memory Write Enable Delay register 1 */ +#define LPC17_40_EMC_STATICWAITOEN1_OFFSET 0x0228 /* Static Memory Output Enable Delay register 1 */ +#define LPC17_40_EMC_STATICWAITRD1_OFFSET 0x022c /* Static Memory Read Delay register 1 */ +#define LPC17_40_EMC_STATICWAITPAGE1_OFFSET 0x0230 /* Static Memory Page Mode Read Delay register 1 */ +#define LPC17_40_EMC_STATICWAITWR1_OFFSET 0x0234 /* Static Memory Write Delay register 1 */ +#define LPC17_40_EMC_STATICWAITTURN1_OFFSET 0x0238 /* Static Memory Turn Round Delay register 1 */ + +#define LPC17_40_EMC_STATICCONFIG2_OFFSET 0x0240 /* Static Memory Configuration register 2 */ +#define LPC17_40_EMC_STATICWAITWEN2_OFFSET 0x0244 /* Static Memory Write Enable Delay register 2 */ +#define LPC17_40_EMC_STATICWAITOEN2_OFFSET 0x0248 /* Static Memory Output Enable Delay register 2 */ +#define LPC17_40_EMC_STATICWAITRD2_OFFSET 0x024c /* Static Memory Read Delay register 2 */ +#define LPC17_40_EMC_STATICWAITPAGE2_OFFSET 0x0250 /* Static Memory Page Mode Read Delay registers 3 */ +#define LPC17_40_EMC_STATICWAITWR2_OFFSET 0x0254 /* Static Memory Write Delay register 2 */ +#define LPC17_40_EMC_EMCSTATICWAITTURN2_OFFSET 0x0258 /* Static Memory Turn Round Delay register 2 */ + +#define LPC17_40_EMC_STATICCONFIG3_OFFSET 0x0260 /* Static Memory Configuration register 3 */ +#define LPC17_40_EMC_STATICWAITWEN3_OFFSET 0x0264 /* Static Memory Write Enable Delay register 3 */ +#define LPC17_40_EMC_STATICWAITOEN3_OFFSET 0x0268 /* Static Memory Output Enable Delay register 3 */ +#define LPC17_40_EMC_STATICWAITRD3_OFFSET 0x026c /* Static Memory Read Delay register 3 */ +#define LPC17_40_EMC_STATICWAITPAGE3_OFFSET 0x0270 /* Static Memory Page Mode Read Delay register 4 */ +#define LPC17_40_EMC_STATICWAITWR3_OFFSET 0x0274 /* Static Memory Write Delay register 3 */ +#define LPC17_40_EMC_STATICWAITTURN3_OFFSET 0x0278 /* Static Memory Turn Round Delay register 3 */ + +/* Register Addresses */ + +#define LPC17_40_EMC_CONTROL (LPC17_40_EMC_BASE+LPC17_40_EMC_CONTROL_OFFSET) +#define LPC17_40_EMC_STATUS (LPC17_40_EMC_BASE+LPC17_40_EMC_STATUS_OFFSET) +#define LPC17_40_EMC_CONFIG (LPC17_40_EMC_BASE+LPC17_40_EMC_CONFIG_OFFSET) +#define LPC17_40_EMC_DYNAMICCONTROL (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICCONTROL_OFFSET) +#define LPC17_40_EMC_DYNAMICREFRESH (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICREFRESH_OFFSET) +#define LPC17_40_EMC_DYNAMICREADCONFIG (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICREADCONFIG_OFFSET) +#define LPC17_40_EMC_DYNAMICRP (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRP_OFFSET) +#define LPC17_40_EMC_DYNAMICRAS (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRAS_OFFSET) +#define LPC17_40_EMC_DYNAMICSREX (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICSREX_OFFSET) +#define LPC17_40_EMC_DYNAMICAPR (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICAPR_OFFSET) +#define LPC17_40_EMC_DYNAMICDAL (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICDAL_OFFSET) +#define LPC17_40_EMC_DYNAMICWR (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICWR_OFFSET) +#define LPC17_40_EMC_DYNAMICRC (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRC_OFFSET) +#define LPC17_40_EMC_DYNAMICRFC (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRFC_OFFSET) +#define LPC17_40_EMC_DYNAMICXSR (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICXSR_OFFSET) +#define LPC17_40_EMC_DYNAMICRRD (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRRD_OFFSET) +#define LPC17_40_EMC_DYNAMICMRD (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICMRD_OFFSET) +#define LPC17_40_EMC_STATICEXTENDEDWAIT (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICEXTENDEDWAIT_OFFSET) + +#define LPC17_40_EMC_DYNAMICCONFIG0 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICCONFIG0_OFFSET) +#define LPC17_40_EMC_DYNAMICRASCAS0 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRASCAS0_OFFSET) + +#define LPC17_40_EMC_DYNAMICCONFIG1 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICCONFIG1_OFFSET) +#define LPC17_40_EMC_DYNAMICRASCAS1 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRASCAS1_OFFSET) + +#define LPC17_40_EMC_DYNAMICCONFIG2 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICCONFIG2_OFFSET) +#define LPC17_40_EMC_DYNAMICRASCAS2 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRASCAS2_OFFSET) + +#define LPC17_40_EMC_DYNAMICCONFIG3 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICCONFIG3_OFFSET) +#define LPC17_40_EMC_DYNAMICRASCAS3 (LPC17_40_EMC_BASE+LPC17_40_EMC_DYNAMICRASCAS3_OFFSET) + +#define LPC17_40_EMC_STATICCONFIG0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICCONFIG0_OFFSET) +#define LPC17_40_EMC_STATICWAITWEN0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWEN0_OFFSET) +#define LPC17_40_EMC_STATICWAITOEN0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITOEN0_OFFSET) +#define LPC17_40_EMC_STATICWAITRD0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITRD0_OFFSET) +#define LPC17_40_EMC_STATICWAITPAGE0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITPAGE0_OFFSET) +#define LPC17_40_EMC_STATICWAITWR0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWR0_OFFSET) +#define LPC17_40_EMC_STATICWAITTURN0 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITTURN0_OFFSET) + +#define LPC17_40_EMC_STATICCONFIG1 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICCONFIG1_OFFSET) +#define LPC17_40_EMC_STATICWAITWEN1 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWEN1_OFFSET) +#define LPC17_40_EMC_STATICWAITOEN1 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITOEN1_OFFSET) +#define LPC17_40_EMC_STATICWAITRD (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITRD1_OFFSET) +#define LPC17_40_EMC_STATICWAITPAGE1 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITPAGE1_OFFSET) +#define LPC17_40_EMC_STATICWAITWR1 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWR1_OFFSET) +#define LPC17_40_EMC_STATICWAITTURN1 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITTURN1_OFFSET) + +#define LPC17_40_EMC_STATICCONFIG2 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICCONFIG2_OFFSET) +#define LPC17_40_EMC_STATICWAITWEN2 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWEN2_OFFSET) +#define LPC17_40_EMC_STATICWAITOEN2 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITOEN2_OFFSET) +#define LPC17_40_EMC_STATICWAITRD2 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITRD2_OFFSET) +#define LPC17_40_EMC_STATICWAITPAGE2 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITPAGE2_OFFSET) +#define LPC17_40_EMC_STATICWAITWR2 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWR2_OFFSET) +#define LPC17_40_EMC_EMCSTATICWAITTURN2 (LPC17_40_EMC_BASE+LPC17_40_EMC_EMCSTATICWAITTURN2_OFFSET) + +#define LPC17_40_EMC_STATICCONFIG3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICCONFIG3_OFFSET) +#define LPC17_40_EMC_STATICWAITWEN3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWEN3_OFFSET) +#define LPC17_40_EMC_STATICWAITOEN3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITOEN3_OFFSET) +#define LPC17_40_EMC_STATICWAITRD3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITRD3_OFFSET) +#define LPC17_40_EMC_STATICWAITPAGE3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITPAGE3_OFFSET) +#define LPC17_40_EMC_STATICWAITWR3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITWR3_OFFSET) +#define LPC17_40_EMC_STATICWAITTURN3 (LPC17_40_EMC_BASE+LPC17_40_EMC_STATICWAITTURN3_OFFSET) + +/* Register Bitfield Definitions */ + +/* EMC Control register */ + +#define EMC_CONTROL_E (1 << 0) /* Bit 0: EMC Enable */ +#define EMC_CONTROL_M (1 << 1) /* Bit 1: Address mirror */ +#define EMC_CONTROL_L (1 << 2) /* Bit 2: Low-power mode */ + +/* EMC Status register */ + +#define EMC_STATUS_B (1 << 0) /* Bit 0: Busy */ +#define EMC_STATUS_S (1 << 1) /* Bit 1: Write buffer status */ +#define EMC_STATUS_SA (1 << 2) /* Bit 2: Self-refresh acknowledge */ + +/* EMC Configuration register */ + +#define EMC_CONFIG_EM (1 << 0) /* Bit 0: Endian mode */ +#define EMC_CONFIG_CLKR (1 << 8) /* Bit 8: CCLK:CLKOUT ratio */ + +/* Dynamic Memory Control register */ + +#define EMC_DYNAMICCONTROL_CE (1 << 0) /* Bit 0: Dynamic memory clock enable */ +#define EMC_DYNAMICCONTROL_CS (1 << 1) /* Bit 1: Dynamic memory clock control */ +#define EMC_DYNAMICCONTROL_SR (1 << 2) /* Bit 2: Self-refresh request */ +#define EMC_DYNAMICCONTROL_MMC (1 << 5) /* Bit 5: Memory clock control */ +#define EMC_DYNAMICCONTROL_I_SHIFT (7) /* Bits 7-8: SDRAM initialization */ +#define EMC_DYNAMICCONTROL_I_MASK (3 << EMC_DYNAMICCONTROL_I_SHIFT) +# define EMC_DYNAMICCONTROL_I_NORMAL (0 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM NORMAL operation command */ +# define EMC_DYNAMICCONTROL_I_MODE (1 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM MODE command */ +# define EMC_DYNAMICCONTROL_I_PALL (2 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM PALL (precharge all) command */ +# define EMC_DYNAMICCONTROL_I_NOP (3 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM NOP (no operation) command) */ + +/* Dynamic Memory Refresh Timer register */ + +#define EMC_DYNAMICREFRESH_MASK (0x000007ff) /* Bits 0-10: REFRESH Refresh timer */ + +/* Dynamic Memory Read Configuration register */ + +#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0) /* Bits 0-1: Read data strategy */ +#define EMC_DYNAMICREADCONFIG_RD_MASK (3 << EMC_DYNAMICREADCONFIG_RD_SHIFT) +# define EMC_DYNAMICREADCONFIG_RD_CLKOUT (0 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Clock out delayed strategy */ +# define EMC_DYNAMICREADCONFIG_RD_CMD (1 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy */ +# define EMC_DYNAMICREADCONFIG_RD_CMD1 (2 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy + 1 cycle */ +# define EMC_DYNAMICREADCONFIG_RD_CMD2 (3 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy + 2 cycles */ + +/* Dynamic Memory Precharge Command Period register */ + +#define EMC_DYNAMICRP_TRP_MASK (0x0000000f) /* Bits 0-3: Precharge command period */ + +/* Dynamic Memory Active to Precharge Command Period register */ + +#define EMC_DYNAMICRAS_TRAS_MASK (0x0000000f) /* Bits 0-3: Active to precharge command period */ + +/* Dynamic Memory Self-refresh Exit Time register */ + +#define EMC_DYNAMICSREX_TSREX_MASK (0x0000000f) /* Bits 0-3: Self-refresh exit time */ + +/* Dynamic Memory Last Data Out to Active Time register */ + +#define EMC_DYNAMICAPR_TAPR_MASK (0x0000000f) /* Bits 0-3: Last-data-out to active command time */ + +/* Dynamic Memory Data-in to Active Command Time register */ + +#define EMC_DYNAMICDAL_TDAL_MASK (0x0000000f) /* Bits 0-3: Data-in to active command */ + +/* Dynamic Memory Write Recovery Time register */ + +#define EMC_DYNAMICWR_TWR_MASK (0x0000000f) /* Bits 0-3: Write recovery time */ + +/* Dynamic Memory Active to Active Command Period register */ + +#define EMC_DYNAMICRC_TRC_MASK (0x0000001f) /* Bits 0-4: Active to active command period */ + +/* Dynamic Memory Auto-refresh Period register */ + +#define EMC_DYNAMICRFC_TRFC_MASK (0x0000001f) /* Bits 0-4: Auto-refresh period and auto-refresh to active command period */ + +/* Dynamic Memory Exit Self-refresh register */ + +#define EMC_DYNAMICXSR_TXSR_MASK (0x0000001f) /* Bits 0-4: Exit self-refresh to active command time */ + +/* Dynamic Memory Active Bank A to Active Bank B Time register */ + +#define EMC_DYNAMICRRD_TRRD_MASK (0x0000000f) /* Bits 0-3: Active bank A to active bank B latency */ + +/* Dynamic Memory Load Mode register to Active Command Time */ + +#define EMC_DYNAMICMRD_TMRD_MASK (0x0000000f) /* Bits 0-3: Load mode register to active command time */ + +/* Static Memory Extended Wait register */ + +#define EMC_STATICEXTENDEDWAIT_MASK (0x000003ff) /* Bits 0-9: Extended wait time out */ + +/* Dynamic Memory Configuration registers (0-3) */ + +#define EMC_DYNAMICCONFIG_MD_SHIFT (3) /* Bits 3-4: Memory device */ +#define EMC_DYNAMICCONFIG_MD_MASK (3 << EMC_DYNAMICCONFIG_MD_SHIFT) +# define EMC_DYNAMICCONFIG_MD_SDRAM (0 << EMC_DYNAMICCONFIG_MD_SHIFT) /* SDRAM */ +# define EMC_DYNAMICCONFIG_MD_LOWPOWER (1 << EMC_DYNAMICCONFIG_MD_SHIFT) /* Low-power SDRAM */ +#define EMC_DYNAMICCONFIG_AM0_SHIFT (7) /* Bits 7-12: */ +#define EMC_DYNAMICCONFIG_AM0_MASK (63 << EMC_DYNAMICCONFIG_AM0_SHIFT) +# define EMC_DYNAMICCONFIG_AM0(n) ((n) << EMC_DYNAMICCONFIG_AM0_SHIFT) +#define EMC_DYNAMICCONFIG_AM1 (1 << 14) /* Bit 14: */ +#define EMC_DYNAMICCONFIG_B (1 << 19) /* Bit 19: Buffer enable */ +#define EMC_DYNAMICCONFIG_P (1 << 20) /* Bit 20: Write protect */ + +/* Dynamic Memory RAS & CAS Delay registers (0-3) */ + +#define EMC_DYNAMICRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency (active to read/write delay) */ +#define EMC_DYNAMICRASCAS_RAS_MASK (3 << EMC_DYNAMICRASCAS_RAS_SHIFT) +# define EMC_DYNAMICRASCAS_RAS_1CCLK (1 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* One CCLK cycle */ +# define EMC_DYNAMICRASCAS_RAS_2CCLK (2 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* Two CCLK cycles */ +# define EMC_DYNAMICRASCAS_RAS_3CCLK (3 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* Three CCLK cycles */ +#define EMC_DYNAMICRASCAS_CAS_SHIFT (8) /* Bits 8-9: CAS latency */ +#define EMC_DYNAMICRASCAS_CAS_MASK (3 << EMC_DYNAMICRASCAS_CAS_SHIFT) +# define EMC_DYNAMICRASCAS_CAS_1CCLK (1 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* One CCLK cycle */ +# define EMC_DYNAMICRASCAS_CAS_2CCLK (2 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* Two CCLK cycles */ +# define EMC_DYNAMICRASCAS_CAS_3CCLK (3 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* Three CCLK cycles */ + +/* Static Memory Configuration registers (0-3) */ + +#define EMC_STATICCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */ +#define EMC_STATICCONFIG_MW_MASK (3 << EMC_STATICCONFIG_MW_SHIFT) +# define EMC_STATICCONFIG_MW_8BIT (0 << EMC_STATICCONFIG_MW_SHIFT) +# define EMC_STATICCONFIG_MW_16BIT (1 << EMC_STATICCONFIG_MW_SHIFT) +# define EMC_STATICCONFIG_MW_32BIT (2 << EMC_STATICCONFIG_MW_SHIFT) +#define EMC_STATICCONFIG_PM (1 << 3) /* Bit 3: Page mode */ +#define EMC_STATICCONFIG_PC (1 << 6) /* Bit 6: Chip select polarity */ +#define EMC_STATICCONFIG_PB (1 << 7) /* Bit 7: Byte lane state */ +#define EMC_STATICCONFIG_EW (1 << 8) /* Bit 8: Extended wait */ +#define EMC_STATICCONFIG_B (1 << 19) /* Bit 19: Buffer enable */ +#define EMC_STATICCONFIG_P (1 << 20) /* Bit 20: Write protect */ + +/* Static Memory Write Enable Delay registers (0-3) */ + +#define EMC_STATICWAITWEN_MASK (0x0000000f) /* Bits 0-3: Wait write enable */ + +/* Static Memory Output Enable Delay registers (0-3) */ + +#define EMC_STATICWAITOEN_MASK (0x0000000f) /* Bits 0-3: Wait output enable */ + +/* Static Memory Read Delay registers (0-3) */ + +#define EMC_STATICWAITRD_MASK (0x0000001f) /* Bits 0-4: Exit self-refresh to active command time */ + +/* Static Memory Page Mode Read Delay registers (0-3) */ + +#define EMC_STATICWAITPAGE_MASK (0x0000001f) /* Bits 0-4: Asynchronous page mode read after the first read wait states */ + +/* Static Memory Write Delay registers (0-3) */ + +#define EMC_STATICWAITWR_MASK (0x0000001f) /* Bits 0-4: Write wait states */ + +/* Static Memory Turn Round Delay registers (0-3) */ + +#define EMC_STATICWAITTURN_MASK (0x0000000f) /* Bits 0-3: Bus turn-around cycles */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_EMC_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ethernet.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ethernet.h new file mode 100644 index 00000000000..ce77c66603b --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ethernet.h @@ -0,0 +1,597 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ethernet.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_ETHERNET_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* MAC registers */ + +#define LPC17_40_ETH_MAC1_OFFSET 0x0000 /* MAC configuration register 1 */ +#define LPC17_40_ETH_MAC2_OFFSET 0x0004 /* MAC configuration register 2 */ +#define LPC17_40_ETH_IPGT_OFFSET 0x0008 /* Back-to-Back Inter-Packet-Gap register */ +#define LPC17_40_ETH_IPGR_OFFSET 0x000c /* Non Back-to-Back Inter-Packet-Gap register */ +#define LPC17_40_ETH_CLRT_OFFSET 0x0010 /* Collision window / Retry register */ +#define LPC17_40_ETH_MAXF_OFFSET 0x0014 /* Maximum Frame register */ +#define LPC17_40_ETH_SUPP_OFFSET 0x0018 /* PHY Support register */ +#define LPC17_40_ETH_TEST_OFFSET 0x001c /* Test register */ +#define LPC17_40_ETH_MCFG_OFFSET 0x0020 /* MII Mgmt Configuration register */ +#define LPC17_40_ETH_MCMD_OFFSET 0x0024 /* MII Mgmt Command register */ +#define LPC17_40_ETH_MADR_OFFSET 0x0028 /* MII Mgmt Address register */ +#define LPC17_40_ETH_MWTD_OFFSET 0x002c /* MII Mgmt Write Data register */ +#define LPC17_40_ETH_MRDD_OFFSET 0x0030 /* MII Mgmt Read Data register */ +#define LPC17_40_ETH_MIND_OFFSET 0x0034 /* MII Mgmt Indicators register */ +#define LPC17_40_ETH_SA0_OFFSET 0x0040 /* Station Address 0 register */ +#define LPC17_40_ETH_SA1_OFFSET 0x0044 /* Station Address 1 register */ +#define LPC17_40_ETH_SA2_OFFSET 0x0048 /* Station Address 2 register */ + +/* Control registers */ + +#define LPC17_40_ETH_CMD_OFFSET 0x0100 /* Command register */ +#define LPC17_40_ETH_STAT_OFFSET 0x0104 /* Status register */ +#define LPC17_40_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */ +#define LPC17_40_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */ +#define LPC17_40_ETH_RXDESCNO_OFFSET 0x0110 /* Receive number of descriptors register */ +#define LPC17_40_ETH_RXPRODIDX_OFFSET 0x0114 /* Receive produce index register */ +#define LPC17_40_ETH_RXCONSIDX_OFFSET 0x0118 /* Receive consume index register */ +#define LPC17_40_ETH_TXDESC_OFFSET 0x011c /* Transmit descriptor base address register */ +#define LPC17_40_ETH_TXSTAT_OFFSET 0x0120 /* Transmit status base address register */ +#define LPC17_40_ETH_TXDESCRNO_OFFSET 0x0124 /* Transmit number of descriptors register */ +#define LPC17_40_ETH_TXPRODIDX_OFFSET 0x0128 /* Transmit produce index register */ +#define LPC17_40_ETH_TXCONSIDX_OFFSET 0x012c /* Transmit consume index register */ +#define LPC17_40_ETH_TSV0_OFFSET 0x0158 /* Transmit status vector 0 register */ +#define LPC17_40_ETH_TSV1_OFFSET 0x015c /* Transmit status vector 1 register */ +#define LPC17_40_ETH_RSV_OFFSET 0x0160 /* Receive status vector register */ +#define LPC17_40_ETH_FCCNTR_OFFSET 0x0170 /* Flow control counter register */ +#define LPC17_40_ETH_FCSTAT_OFFSET 0x0174 /* Flow control status register */ + +/* Rx filter registers */ + +#define LPC17_40_ETH_RXFLCTRL_OFFSET 0x0200 /* Receive filter control register */ +#define LPC17_40_ETH_RXFLWOLST_OFFSET 0x0204 /* Receive filter WoL status register */ +#define LPC17_40_ETH_RXFLWOLCLR_OFFSET 0x0208 /* Receive filter WoL clear register */ +#define LPC17_40_ETH_HASHFLL_OFFSET 0x0210 /* Hash filter table LSBs register */ +#define LPC17_40_ETH_HASHFLH_OFFSET 0x0214 /* Hash filter table MSBs register */ + +/* Module control registers */ + +#define LPC17_40_ETH_INTST_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_40_ETH_INTEN_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_40_ETH_INTCLR_OFFSET 0x0fe8 /* Interrupt clear register */ +#define LPC17_40_ETH_INTSET_OFFSET 0x0fec /* Interrupt set register */ +#define LPC17_40_ETH_PWRDOWN_OFFSET 0x0ff4 /* Power-down register */ + +/* Register addresses ***************************************************************/ +/* MAC registers */ + +#define LPC17_40_ETH_MAC1 (LPC17_40_ETH_BASE+LPC17_40_ETH_MAC1_OFFSET) +#define LPC17_40_ETH_MAC2 (LPC17_40_ETH_BASE+LPC17_40_ETH_MAC2_OFFSET) +#define LPC17_40_ETH_IPGT (LPC17_40_ETH_BASE+LPC17_40_ETH_IPGT_OFFSET) +#define LPC17_40_ETH_IPGR (LPC17_40_ETH_BASE+LPC17_40_ETH_IPGR_OFFSET) +#define LPC17_40_ETH_CLRT (LPC17_40_ETH_BASE+LPC17_40_ETH_CLRT_OFFSET) +#define LPC17_40_ETH_MAXF (LPC17_40_ETH_BASE+LPC17_40_ETH_MAXF_OFFSET) +#define LPC17_40_ETH_SUPP (LPC17_40_ETH_BASE+LPC17_40_ETH_SUPP_OFFSET) +#define LPC17_40_ETH_TEST (LPC17_40_ETH_BASE+LPC17_40_ETH_TEST_OFFSET) +#define LPC17_40_ETH_MCFG (LPC17_40_ETH_BASE+LPC17_40_ETH_MCFG_OFFSET) +#define LPC17_40_ETH_MCMD (LPC17_40_ETH_BASE+LPC17_40_ETH_MCMD_OFFSET) +#define LPC17_40_ETH_MADR (LPC17_40_ETH_BASE+LPC17_40_ETH_MADR_OFFSET) +#define LPC17_40_ETH_MWTD (LPC17_40_ETH_BASE+LPC17_40_ETH_MWTD_OFFSET) +#define LPC17_40_ETH_MRDD (LPC17_40_ETH_BASE+LPC17_40_ETH_MRDD_OFFSET) +#define LPC17_40_ETH_MIND (LPC17_40_ETH_BASE+LPC17_40_ETH_MIND_OFFSET) +#define LPC17_40_ETH_SA0 (LPC17_40_ETH_BASE+LPC17_40_ETH_SA0_OFFSET) +#define LPC17_40_ETH_SA1 (LPC17_40_ETH_BASE+LPC17_40_ETH_SA1_OFFSET) +#define LPC17_40_ETH_SA2 (LPC17_40_ETH_BASE+LPC17_40_ETH_SA2_OFFSET) + +/* Control registers */ + +#define LPC17_40_ETH_CMD (LPC17_40_ETH_BASE+LPC17_40_ETH_CMD_OFFSET) +#define LPC17_40_ETH_STAT (LPC17_40_ETH_BASE+LPC17_40_ETH_STAT_OFFSET) +#define LPC17_40_ETH_RXDESC (LPC17_40_ETH_BASE+LPC17_40_ETH_RXDESC_OFFSET) +#define LPC17_40_ETH_RXSTAT (LPC17_40_ETH_BASE+LPC17_40_ETH_RXSTAT_OFFSET) +#define LPC17_40_ETH_RXDESCNO (LPC17_40_ETH_BASE+LPC17_40_ETH_RXDESCNO_OFFSET) +#define LPC17_40_ETH_RXPRODIDX (LPC17_40_ETH_BASE+LPC17_40_ETH_RXPRODIDX_OFFSET) +#define LPC17_40_ETH_RXCONSIDX (LPC17_40_ETH_BASE+LPC17_40_ETH_RXCONSIDX_OFFSET) +#define LPC17_40_ETH_TXDESC (LPC17_40_ETH_BASE+LPC17_40_ETH_TXDESC_OFFSET) +#define LPC17_40_ETH_TXSTAT (LPC17_40_ETH_BASE+LPC17_40_ETH_TXSTAT_OFFSET) +#define LPC17_40_ETH_TXDESCRNO (LPC17_40_ETH_BASE+LPC17_40_ETH_TXDESCRNO_OFFSET) +#define LPC17_40_ETH_TXPRODIDX (LPC17_40_ETH_BASE+LPC17_40_ETH_TXPRODIDX_OFFSET) +#define LPC17_40_ETH_TXCONSIDX (LPC17_40_ETH_BASE+LPC17_40_ETH_TXCONSIDX_OFFSET) +#define LPC17_40_ETH_TSV0 (LPC17_40_ETH_BASE+LPC17_40_ETH_TSV0_OFFSET) +#define LPC17_40_ETH_TSV1 (LPC17_40_ETH_BASE+LPC17_40_ETH_TSV1_OFFSET) +#define LPC17_40_ETH_RSV (LPC17_40_ETH_BASE+LPC17_40_ETH_RSV_OFFSET) +#define LPC17_40_ETH_FCCNTR (LPC17_40_ETH_BASE+LPC17_40_ETH_FCCNTR_OFFSET) +#define LPC17_40_ETH_FCSTAT (LPC17_40_ETH_BASE+LPC17_40_ETH_FCSTAT_OFFSET) + +/* Rx filter registers */ + +#define LPC17_40_ETH_RXFLCTRL (LPC17_40_ETH_BASE+LPC17_40_ETH_RXFLCTRL_OFFSET) +#define LPC17_40_ETH_RXFLWOLST (LPC17_40_ETH_BASE+LPC17_40_ETH_RXFLWOLST_OFFSET) +#define LPC17_40_ETH_RXFLWOLCLR (LPC17_40_ETH_BASE+LPC17_40_ETH_RXFLWOLCLR_OFFSET) +#define LPC17_40_ETH_HASHFLL (LPC17_40_ETH_BASE+LPC17_40_ETH_HASHFLL_OFFSET) +#define LPC17_40_ETH_HASHFLH (LPC17_40_ETH_BASE+LPC17_40_ETH_HASHFLH_OFFSET) + +/* Module control registers */ + +#define LPC17_40_ETH_INTST (LPC17_40_ETH_BASE+LPC17_40_ETH_INTST_OFFSET) +#define LPC17_40_ETH_INTEN (LPC17_40_ETH_BASE+LPC17_40_ETH_INTEN_OFFSET) +#define LPC17_40_ETH_INTCLR (LPC17_40_ETH_BASE+LPC17_40_ETH_INTCLR_OFFSET) +#define LPC17_40_ETH_INTSET (LPC17_40_ETH_BASE+LPC17_40_ETH_INTSET_OFFSET) +#define LPC17_40_ETH_PWRDOWN (LPC17_40_ETH_BASE+LPC17_40_ETH_PWRDOWN_OFFSET) + +/* Register bit definitions *********************************************************/ +/* MAC registers */ +/* MAC configuration register 1 (MAC1) */ + +#define ETH_MAC1_RE (1 << 0) /* Bit 0: Receive enable */ +#define ETH_MAC1_PARF (1 << 1) /* Bit 1: Passall all receive frames */ +#define ETH_MAC1_RFC (1 << 2) /* Bit 2: RX flow control */ +#define ETH_MAC1_TFC (1 << 3) /* Bit 3: TX flow control */ +#define ETH_MAC1_LPBK (1 << 4) /* Bit 4: Loopback */ + /* Bits 5-7: Reserved */ +#define ETH_MAC1_TXRST (1 << 8) /* Bit 8: Reset TX */ +#define ETH_MAC1_MCSTXRST (1 << 9) /* Bit 9: Reset MCS/TX */ +#define ETH_MAC1_RXRST (1 << 10) /* Bit 10: Reset RX */ +#define ETH_MAC1_MCSRXRST (1 << 11) /* Bit 11: Reset MCS/RX */ + /* Bits 12-13: Reserved */ +#define ETH_MAC1_SIMRST (1 << 14) /* Bit 14: Simulation reset */ +#define ETH_MAC1_SOFTRST (1 << 15) /* Bit 15: Soft reset */ + /* Bits 16-31: Reserved */ +/* MAC configuration register 2 (MAC2) */ + +#define ETH_MAC2_FD (1 << 0) /* Bit 0: Full duplex */ +#define ETH_MAC2_FLC (1 << 1) /* Bit 1: Frame length checking */ +#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge frame enable */ +#define ETH_MAC2_DCRC (1 << 3) /* Bit 3: Delayed CRC */ +#define ETH_MAC2_CRCEN (1 << 4) /* Bit 4: CRC enable */ +#define ETH_MAC2_PADCRCEN (1 << 5) /* Bit 5: Pad/CRC enable */ +#define ETH_MAC2_VLANPADEN (1 << 6) /* Bit 6: VLAN pad enable */ +#define ETH_MAC2_AUTOPADEN (1 << 7) /* Bit 7: Auto detect pad enable */ +#define ETH_MAC2_PPE (1 << 8) /* Bit 8: Pure preamble enforcement */ +#define ETH_MAC2_LPE (1 << 9) /* Bit 9: Long preamble enforcement */ + /* Bits 10-11: Reserved */ +#define ETH_MAC2_NBKOFF (1 << 12) /* Bit 12: No backoff */ +#define ETH_MAC2_BPNBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */ +#define ETH_MAC2_EXDEF (1 << 14) /* Bit 14: Excess defer */ + /* Bits 15-31: Reserved */ +/* Back-to-Back Inter-Packet-Gap register (IPGT) */ + +#define ETH_IPGT_SHIFT (0) /* Bits 0-6 */ +#define ETH_IPGT_MASK (0x7f << ETH_IPGT_SHIFT) + /* Bits 7-31: Reserved */ +/* Non Back-to-Back Inter-Packet-Gap register (IPGR) */ + +#define ETH_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */ +#define ETH_IPGR_GAP2_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) + /* Bit 7: Reserved */ +#define ETH_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */ +#define ETH_IPGR_GAP1_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) + /* Bits 15-31: Reserved */ +/* Collision window / Retry register (CLRT) */ + +#define ETH_CLRT_RMAX_SHIFT (0) /* Bits 0-3: Retransmission maximum */ +#define ETH_CLRT_RMAX_MASK (15 << ETH_CLRT_RMAX_SHIFT) + /* Bits 4-7: Reserved */ +#define ETH_CLRT_COLWIN_SHIFT (8) /* Bits 8-13: Collision window */ +#define ETH_CLRT_COLWIN_MASK (0x3f << ETH_CLRT_COLWIN_SHIFT) + /* Bits 14-31: Reserved */ +/* Maximum Frame register (MAXF) */ + +#define ETH_MAXF_SHIFT (0) /* Bits 0-15 */ +#define ETH_MAXF_MASK (0xffff << ETH_MAXF_SHIFT) + /* Bits 16-31: Reserved */ +/* PHY Support register (SUPP) */ + /* Bits 0-7: Reserved */ +#define ETH_SUPP_SPEED (1 << 8) /* Bit 8: 0=10Bps 1=100Bps */ + /* Bits 9-31: Reserved */ +/* Test register (TEST) */ + +#define ETH_TEST_SPQ (1 << 0) /* Bit 0: Shortcut pause quanta */ +#define ETH_TEST_TP (1 << 1) /* Bit 1: Test pause */ +#define ETH_TEST_TBP (1 << 2) /* Bit 2: Test packpressure */ + /* Bits 3-31: Reserved */ +/* MII Mgmt Configuration register (MCFG) */ + +#define ETH_MCFG_SCANINC (1 << 0) /* Bit 0: Scan increment */ +#define ETH_MCFG_SUPPRE (1 << 1) /* Bit 1: Suppress preamble */ +#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5: Clock select */ +#define ETH_MCFG_CLKSEL_MASK (15 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV4 (0 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV6 (2 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV8 (3 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV10 (4 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV14 (5 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV20 (6 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV28 (7 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV36 (8 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV40 (9 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV44 (10 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV48 (11 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV52 (12 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV56 (13 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV60 (14 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV64 (15 << ETH_MCFG_CLKSEL_SHIFT) + /* Bits 6-14: Reserved */ +#define ETH_MCFG_MIIRST (1 << 15) /* Bit 15: Reset MII mgmt */ + /* Bits 16-31: Reserved */ +/* MII Mgmt Command register (MCMD) */ + +#define ETH_MCMD_READ (1 << 0) /* Bit 0: Single read cycle */ +#define ETH_MCMD_SCAN (1 << 1) /* Bit 1: Continuous read cycles */ + /* Bits 2-31: Reserved */ +#define ETH_MCMD_WRITE (0) + +/* MII Mgmt Address register (MADR) */ + +#define ETH_MADR_REGADDR_SHIFT (0) /* Bits 0-4: Register address */ +#define ETH_MADR_REGADDR_MASK (31 << ETH_MADR_REGADDR_SHIFT) + /* Bits 7-5: Reserved */ +#define ETH_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */ +#define ETH_MADR_PHYADDR_MASK (31 << ETH_MADR_PHYADDR_SHIFT) + /* Bits 13-31: Reserved */ +/* MII Mgmt Write Data register (MWTD) */ + +#define ETH_MWTD_SHIFT (0) /* Bits 0-15 */ +#define ETH_MWTD_MASK (0xffff << ETH_MWTD_SHIFT) + /* Bits 16-31: Reserved */ +/* MII Mgmt Read Data register (MRDD) */ + +#define ETH_MRDD_SHIFT (0) /* Bits 0-15 */ +#define ETH_MRDD_MASK (0xffff << ETH_MRDD_SHIFT) + /* Bits 16-31: Reserved */ +/* MII Mgmt Indicators register (MIND) */ + +#define ETH_MIND_BUSY (1 << 0) /* Bit 0: Busy */ +#define ETH_MIND_SCANNING (1 << 1) /* Bit 1: Scanning */ +#define ETH_MIND_NVALID (1 << 2) /* Bit 2: Not valid */ +#define ETH_MIND_MIIFAIL (1 << 3) /* Bit 3: MII link fail */ + /* Bits 4-31: Reserved */ +/* Station Address 0 register (SA0) */ + +#define ETH_SA0_OCTET2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */ +#define ETH_SA0_OCTET2_MASK (0xff << ETH_SA0_OCTET2_SHIFT) +#define ETH_SA0_OCTET1_SHIFT (8) /* Bits 8-15: Station address 1st octet */ +#define ETH_SA0_OCTET1_MASK (0xff << ETH_SA0_OCTET1_SHIFT) + /* Bits 16-31: Reserved */ +/* Station Address 1 register (SA1) */ + +#define ETH_SA1_OCTET4_SHIFT (0) /* Bits 0-7: Station address 4th octet */ +#define ETH_SA1_OCTET4_MASK (0xff << ETH_SA0_OCTET4_SHIFT) +#define ETH_SA1_OCTET3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */ +#define ETH_SA1_OCTET3_MASK (0xff << ETH_SA0_OCTET3_SHIFT) + /* Bits 16-31: Reserved */ +/* Station Address 2 register (SA2) */ + +#define ETH_SA2_OCTET6_SHIFT (0) /* Bits 0-7: Station address 5th octet */ +#define ETH_SA2_OCTET6_MASK (0xff << ETH_SA0_OCTET6_SHIFT) +#define ETH_SA2_OCTET5_SHIFT (8) /* Bits 8-15: Station address 6th octet */ +#define ETH_SA2_OCTET5_MASK (0xff << ETH_SA0_OCTET5_SHIFT) + /* Bits 16-31: Reserved */ +/* Control registers */ +/* Command register (CMD) */ + +#define ETH_CMD_RXEN (1 << 0) /* Bit 0: Receive enable */ +#define ETH_CMD_TXEN (1 << 1) /* Bit 1: Transmit enable */ + /* Bit 2: Reserved */ +#define ETH_CMD_REGRST (1 << 3) /* Bit 3: Reset host registers */ +#define ETH_CMD_TXRST (1 << 4) /* Bit 4: Reset transmit datapath */ +#define ETH_CMD_RXRST (1 << 5) /* Bit 5: Reset receive datapath */ +#define ETH_CMD_PRFRAME (1 << 6) /* Bit 6: Pass run frame */ +#define ETH_CMD_PRFILTER (1 << 7) /* Bit 7: Pass RX filter */ +#define ETH_CMD_TXFC (1 << 8) /* Bit 8: TX flow control */ +#define ETH_CMD_RMII (1 << 9) /* Bit 9: RMII mode */ +#define ETH_CMD_FD (1 << 10) /* Bit 10: Full duplex */ + /* Bits 11-31: Reserved */ +/* Status register */ + +#define ETH_STAT_RX (1 << 0) /* Bit 0: RX status */ +#define ETH_STAT_TX (1 << 1) /* Bit 1: TX status */ + /* Bits 2-31: Reserved */ +/* Receive descriptor base address register (RXDESC) + * + * The receive descriptor base address is a byte address aligned to a word + * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest + * address in the array of descriptors. + */ + +/* Receive status base address register (RXSTAT) + * + * The receive status base address is a byte address aligned to a double word + * boundary i.e. LSB 2:0 are fixed to 000. + */ + +/* Receive number of descriptors register (RXDESCNO) */ + +#define ETH_RXDESCNO_SHIFT (0) /* Bits 0-15 */ +#define ETH_RXDESCNO_MASK (0xffff << ETH_RXDESCNO_SHIFT) + /* Bits 16-31: Reserved */ +/* Receive produce index register (RXPRODIDX) */ + +#define ETH_RXPRODIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_RXPRODIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Receive consume index register (RXCONSIDX) */ + +#define ETH_RXCONSIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_RXCONSIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit descriptor base address register (TXDESC) + * + * The transmit descriptor base address is a byte address aligned to a word + * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest + * address in the array of descriptors. + */ + +/* Transmit status base address register (TXSTAT) + * + * The transmit status base address is a byte address aligned to a word + * boundary i.e. LSB1:0 are fixed to 00. The register contains the lowest + * address in the array of statuses. + */ + +/* Transmit number of descriptors register (TXDESCRNO) */ + +#define ETH_TXDESCRNO_SHIFT (0) /* Bits 0-15 */ +#define ETH_TXDESCRNO_MASK (0xffff << ETH_TXDESCRNO_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit produce index register (TXPRODIDX) */ + +#define ETH_TXPRODIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_TXPRODIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit consume index register (TXCONSIDX) */ + +#define ETH_TXCONSIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_TXCONSIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit status vector 0 register (TSV0) */ + +#define ETH_TSV0_CRCERR (1 << 0) /* Bit 0: CRC error */ +#define ETH_TSV0_LENCHKERR (1 << 1) /* Bit 1: Length check error */ +#define ETH_TSV0_LENOOR (1 << 2) /* Bit 2: Length out of range */ +#define ETH_TSV0_DONE (1 << 3) /* Bit 3: Done */ +#define ETH_TSV0_MCAST (1 << 4) /* Bit 4: Multicast */ +#define ETH_TSV0_BCAST (1 << 5) /* Bit 5: Broadcast */ +#define ETH_TSV0_PKTDEFER (1 << 6) /* Bit 6: Packet Defer */ +#define ETH_TSV0_EXCDEFER (1 << 7) /* Bit 7: Excessive Defer */ +#define ETH_TSV0_EXCCOL (1 << 8) /* Bit 8: Excessive Collision */ +#define ETH_TSV0_LATECOL (1 << 9) /* Bit 9: Late Collision */ +#define ETH_TSV0_GIANT (1 << 10) /* Bit 10: Giant */ +#define ETH_TSV0_UNDRUN (1 << 11) /* Bit 11: Underrun */ +#define ETH_TSV0_TOTBYTES_SHIFT (12) /* Bits 12-27:Total bytes */ +#define ETH_TSV0_TOTBYTES_MASK (0xffff << ETH_TSV0_TOTBYTES_SHIFT) +#define ETH_TSV0_CTLFRAME (1 << 28) /* Bit 28: Control frame */ +#define ETH_TSV0_PAUSE (1 << 29) /* Bit 29: Pause */ +#define ETH_TSV0_BP (1 << 30) /* Bit 30: Backpressure */ +#define ETH_TSV0_VLAN (1 << 31) /* Bit 31: VLAN */ + +/* Transmit status vector 1 register (TSV1) */ + +#define ETH_TSV1_TXCNT_SHIFT (0) /* Bits 0-15: Transmit byte count */ +#define ETH_TSV1_TXCNT_MASK (0xffff << ETH_TSV1_TXCNT_SHIFT) +#define ETH_TSV1_COLCNT_SHIFT (16) /* Bits 16-19: Transmit collision count */ +#define ETH_TSV1_COLCNT_MASK (15 << ETH_TSV1_COLCNT_SHIFT) + /* Bits 20-31: Reserved */ +/* Receive status vector register (RSV) */ + +#define ETH_RSV_RXCNT_SHIFT (0) /* Bits 0-15: Received byte count */ +#define ETH_RSV_RXCNT_MASK (0xffff << ETH_RSV_RXCNT_SHIFT) +#define ETH_RSV_PKTPI (1 << 16) /* Bit 16: Packet previously ignored */ +#define ETH_RSV_RXEPS (1 << 17) /* Bit 17: RXDV event previously seen */ +#define ETH_RSV_CEPS (1 << 18) /* Bit 18: Carrier event previously seen */ +#define ETH_RSV_RXCV (1 << 19) /* Bit 19: Receive code violation */ +#define ETH_RSV_CRCERR (1 << 20) /* Bit 20: CRC error */ +#define ETH_RSV_LENCHKERR (1 << 21) /* Bit 21: Length check error */ +#define ETH_RSV_LENOOR (1 << 22) /* Bit 22: Length out of range */ +#define ETH_RSV_RXOK (1 << 23) /* Bit 23: Receive OK */ +#define ETH_RSV_MCAST (1 << 24) /* Bit 24: Multicast */ +#define ETH_RSV_BCAST (1 << 25) /* Bit 25: Broadcast */ +#define ETH_RSV_DRIBNIB (1 << 26) /* Bit 26: Dribble Nibble */ +#define ETH_RSV_CTLFRAME (1 << 27) /* Bit 27: Control frame */ +#define ETH_RSV_PAUSE (1 << 28) /* Bit 28: Pause */ +#define ETH_RSV_UNSUPOP (1 << 29) /* Bit 29: Unsupported Opcode */ +#define ETH_RSV_VLAN (1 << 30) /* Bit 30: VLAN */ + /* Bit 31: Reserved */ +/* Flow control counter register (FCCNTR) */ + +#define ETH_FCCNTR_MCOUNT_SHIFT (0) /* Bits 0-15: Mirror count */ +#define ETH_FCCNTR_MCOUNT_MASK (0xffff << ETH_FCCNTR_MCOUNT_SHIFT) +#define ETH_FCCNTR_PTMR_SHIFT (16) /* Bits 16-31: Pause timer */ +#define ETH_FCCNTR_PTMR_MASK (0xffff << ETH_FCCNTR_PTMR_SHIFT) + +/* Flow control status register (FCSTAT) */ + +#define ETH_FCSTAT_MCOUNT_SHIFT (0) /* Bits 0-15: Current mirror count */ +#define ETH_FCSTAT_MCOUNT_MASK (0xffff << ETH_FCSTAT_MCOUNT_SHIFT) + /* Bits 16-31: Reserved */ +/* Rx filter registers */ +/* Receive filter control register (RXFLCTRL) */ + +#define ETH_RXFLCTRL_UCASTEN (1 << 0) /* Bit 0: Accept all unicast frames */ +#define ETH_RXFLCTRL_BCASTEN (1 << 1) /* Bit 1: Accept all broadcast frames */ +#define ETH_RXFLCTRL_MCASTEN (1 << 2) /* Bit 2: Accept all multicast frames */ +#define ETH_RXFLCTRL_UCASTHASHEN (1 << 3) /* Bit 3: Accept hashed unicast */ +#define ETH_RXFLCTRL_MCASTHASHEN (1 << 4) /* Bit 4: Accect hashed multicast */ +#define ETH_RXFLCTRL_PERFEN (1 << 5) /* Bit 5: Accept perfect dest match */ + /* Bits 6-11: Reserved */ +#define ETH_RXFLCTRL_MPKTEN (1 << 12) /* Bit 12: Magic pkt filter WoL int */ +#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect match WoL interrupt */ + /* Bits 14-31: Reserved */ +/* Receive filter WoL status register (RXFLWOLST) AND + * Receive filter WoL clear register (RXFLWOLCLR) + */ + +#define ETH_RXFLWOL_UCAST (1 << 0) /* Bit 0: Unicast frame WoL */ +#define ETH_RXFLWOL_BCAST (1 << 1) /* Bit 1: Broadcast frame WoL */ +#define ETH_RXFLWOL_MCAST (1 << 2) /* Bit 2: Multicast frame WoL */ +#define ETH_RXFLWOL_UCASTHASH (1 << 3) /* Bit 3: Unicast hash filter WoL */ +#define ETH_RXFLWOL_MCASTHASH (1 << 4) /* Bit 4: Multiicast hash filter WoL */ +#define ETH_RXFLWOL_PERF (1 << 5) /* Bit 5: Perfect addr match WoL */ + /* Bit 6: Reserved */ +#define ETH_RXFLWOL_RXFIL (1 << 7) /* Bit 7: Receive filter WoL */ +#define ETH_RXFLWOL_MPKT (1 << 8) /* Bit 8: Magic pkt filter WoL */ + /* Bits 9-31: Reserved */ +/* Hash filter table LSBs register (HASHFLL) AND Hash filter table MSBs register +* (HASHFLH) Are registers containing a 32-bit value with no bitfield. + */ + +/* Module control registers */ +/* Interrupt status register (INTST), Interrupt enable register (INTEN), Interrupt + * clear register (INTCLR), and Interrupt set register (INTSET) common bit field + * definition: + */ + +#define ETH_INT_RXOVR (1 << 0) /* Bit 0: RX overrun interrupt */ +#define ETH_INT_RXERR (1 << 1) /* Bit 1: RX error interrupt */ +#define ETH_INT_RXFIN (1 << 2) /* Bit 2: RX finished interrupt */ +#define ETH_INT_RXDONE (1 << 3) /* Bit 3: RX done interrupt */ +#define ETH_INT_TXUNR (1 << 4) /* Bit 4: TX underrun interrupt */ +#define ETH_INT_TXERR (1 << 5) /* Bit 5: TX error interrupt */ +#define ETH_INT_TXFIN (1 << 6) /* Bit 6: TX finished interrupt */ +#define ETH_INT_TXDONE (1 << 7) /* Bit 7: TX done interrupt */ + /* Bits 8-11: Reserved */ +#define ETH_INT_SOFT (1 << 12) /* Bit 12: Soft interrupt */ +#define ETH_INT_WKUP (1 << 13) /* Bit 13: Wakeup interrupt */ + /* Bits 14-31: Reserved */ +/* Power-down register */ + /* Bits 0-30: Reserved */ +#define ETH_PWRDOWN_MACAHB (1 << 31) /* Power down MAC/AHB */ + +/* Descriptors Offsets **************************************************************/ + +/* Tx descriptor offsets */ + +#define LPC17_40_TXDESC_PACKET 0x00 /* Base address of the Tx data buffer */ +#define LPC17_40_TXDESC_CONTROL 0x04 /* Control Information */ +#define LPC17_40_TXDESC_SIZE 0x08 /* Size in bytes of one Tx descriptor */ + +/* Tx status offsets */ + +#define LPC17_40_TXSTAT_INFO 0x00 /* Transmit status return flags */ +#define LPC17_40_TXSTAT_SIZE 0x04 /* Size in bytes of one Tx status */ + +/* Rx descriptor offsets */ + +#define LPC17_40_RXDESC_PACKET 0x00 /* Base address of the Rx data buffer */ +#define LPC17_40_RXDESC_CONTROL 0x04 /* Control Information */ +#define LPC17_40_RXDESC_SIZE 0x08 /* Size in bytes of one Rx descriptor */ + +/* Rx status offsets */ + +#define LPC17_40_RXSTAT_INFO 0x00 /* Receive status return flags */ +#define LPC17_40_RXSTAT_HASHCRC 0x04 /* Dest and source hash CRC */ +#define LPC17_40_RXSTAT_SIZE 0x08 /* Size in bytes of one Rx status */ + +/* Descriptor Bit Definitions *******************************************************/ + +/* Tx descriptor bit definitions */ + +#define TXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ +#define TXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) + +#define TXDESC_CONTROL_OVERRIDE (1 << 26 /* Bit 26: Per-frame override */ +#define TXDESC_CONTROL_HUGE (1 << 27) /* Bit 27: Enable huge frame size */ +#define TXDESC_CONTROL_PAD (1 << 28) /* Bit 28: Pad short frames */ +#define TXDESC_CONTROL_CRC (1 << 29) /* Bit 29: Append CRC */ +#define TXDESC_CONTROL_LAST (1 << 30) /* Bit 30: Last descriptor of a fragment */ +#define TXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate TxDone interrupt */ + +/* Tx status bit definitions */ + +#define TXSTAT_INFO_COLCNT_SHIFT (21) /* Bits 21-24: Number of collisions */ +#define TXSTAT_INFO_COLCNT_MASK (15 << TXSTAT_INFO_COLCNT_SHIFT) +#define TXSTAT_INFO_DEFER (1 << 25) /* Bit 25: Packet deffered */ +#define TXSTAT_INFO_EXCESSDEFER (1 << 26) /* Bit 26: Excessive packet defferals */ +#define TXSTAT_INFO_EXCESSCOL (1 << 27) /* Bit 27: Excessive packet collisions */ +#define TXSTAT_INFO_LATECOL (1 << 28) /* Bit 28: Out of window collision */ +#define TXSTAT_INFO_UNDERRUN (1 << 29) /* Bit 29: Tx underrun */ +#define TXSTAT_INFO_NODESC (1 << 30) /* Bit 29: No Tx descriptor available */ +#define TXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ + +/* Rx descriptor bit definitions */ + +#define RXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ +#define RXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) +#define RXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate RxDone interrupt */ + +/* Rx status bit definitions */ + +#define RXSTAT_SAHASHCRC_SHIFT (0) /* Bits 0-8: Hash CRC calculated from the source address */ +#define RXSTAT_SAHASHCRC_MASK (0x1ff << RXSTAT_SAHASHCRC_SHIFT) +#define RXSTAT_DAHASHCRC_SHIFT (16) /* Bits 16-24: Hash CRC calculated from the dest address */ +#define RXSTAT_DAHASHCRC_MASK (0x1ff << RXSTAT_DAHASHCRC_SHIFT) + +#define RXSTAT_INFO_RXSIZE_SHIFT (0) /* Bits 0-10: Size of actual data transferred */ +#define RXSTAT_INFO_RXSIZE_MASK (0x7ff << RXSTAT_INFO_RXSIZE_SHIFT) +#define RXSTAT_INFO_CONTROL (1 << 18) /* Bit 18: This is a control frame */ +#define RXSTAT_INFO_VLAN (1 << 19) /* Bit 19: This is a VLAN frame */ +#define RXSTAT_INFO_FAILFILTER (1 << 20) /* Bit 20: Frame failed Rx filter */ +#define RXSTAT_INFO_MULTICAST (1 << 21) /* Bit 21: This is a multicast frame */ +#define RXSTAT_INFO_BROADCAST (1 << 22) /* Bit 22: This is a broadcast frame */ +#define RXSTAT_INFO_CRCERROR (1 << 23) /* Bit 23: Received frame had a CRC error */ +#define RXSTAT_INFO_SYMBOLERROR (1 << 24) /* Bit 24: PHY reported bit error */ +#define RXSTAT_INFO_LENGTHERROR (1 << 25) /* Bit 25: Invalid frame length */ +#define RXSTAT_INFO_RANGEERROR (1 << 26) /* Bit 26: Exceeds maximum packet size */ +#define RXSTAT_INFO_ALIGNERROR (1 << 27) /* Bit 27: Alignment error */ +#define RXSTAT_INFO_OVERRUN (1 << 28) /* Bit 28: Receive overrun error */ +#define RXSTAT_INFO_NODESC (1 << 29) /* Bit 29: No Rx descriptor available */ +#define RXSTAT_INFO_LASTFLAG (1 << 30) /* Bit 30: Last fragment of a frame */ +#define RXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_ETHERNET_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpdma.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpdma.h new file mode 100644 index 00000000000..43ab92d7e9c --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpdma.h @@ -0,0 +1,597 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpdma.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_GPDMA_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_GPDMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register offsets *****************************************************************/ + +/* General registers (see also LPC17_40_SYSCON_DMAREQSEL_OFFSET in lpc17_40_syscon.h) */ + +#define LPC17_40_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ +#define LPC17_40_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ +#define LPC17_40_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ +#define LPC17_40_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ +#define LPC17_40_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ +#define LPC17_40_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ +#define LPC17_40_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ +#define LPC17_40_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ +#define LPC17_40_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ +#define LPC17_40_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ +#define LPC17_40_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ +#define LPC17_40_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ +#define LPC17_40_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ +#define LPC17_40_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ + +/* Channel Registers */ + +#define LPC17_40_NDMACH 8 /* Eight DMA channels */ +#define LPC17_40_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...,(LPC17_40_NDMACH-1) */ + +#define LPC17_40_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ +#define LPC17_40_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ +#define LPC17_40_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ +#define LPC17_40_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ +#define LPC17_40_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ + +#define LPC17_40_DMACH0_SRCADDR_OFFSET (0x100+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH0_DESTADDR_OFFSET (0x100+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH0_LLI_OFFSET (0x100+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH0_CONTROL_OFFSET (0x100+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH0_CONFIG_OFFSET (0x100+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH1_SRCADDR_OFFSET (0x120+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH1_DESTADDR_OFFSET (0x120+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH1_LLI_OFFSET (0x120+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH1_CONTROL_OFFSET (0x120+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH1_CONFIG_OFFSET (0x120+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH2_SRCADDR_OFFSET (0x140+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH2_DESTADDR_OFFSET (0x140+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH2_LLI_OFFSET (0x140+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH2_CONTROL_OFFSET (0x140+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH2_CONFIG_OFFSET (0x140+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH3_SRCADDR_OFFSET (0x160+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH3_DESTADDR_OFFSET (0x160+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH3_LLI_OFFSET (0x160+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH3_CONTROL_OFFSET (0x160+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH3_CONFIG_OFFSET (0x160+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH4_SRCADDR_OFFSET (0x180+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH4_DESTADDR_OFFSET (0x180+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH4_LLI_OFFSET (0x180+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH4_CONTROL_OFFSET (0x180+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH4_CONFIG_OFFSET (0x180+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH5_LLI_OFFSET (0x1a0+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH6_LLI_OFFSET (0x1c0+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH7_LLI_OFFSET (0x1e0+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_40_DMACH_CONFIG_OFFSET) + +/* Register addresses ***************************************************************/ +/* General registers (see also LPC17_40_SYSCON_DMAREQSEL in lpc17_40_syscon.h) */ + +#define LPC17_40_DMA_INTST (LPC17_40_GPDMA_BASE+LPC17_40_DMA_INTST_OFFSET) +#define LPC17_40_DMA_INTTCST (LPC17_40_GPDMA_BASE+LPC17_40_DMA_INTTCST_OFFSET) +#define LPC17_40_DMA_INTTCCLR (LPC17_40_GPDMA_BASE+LPC17_40_DMA_INTTCCLR_OFFSET) +#define LPC17_40_DMA_INTERRST (LPC17_40_GPDMA_BASE+LPC17_40_DMA_INTERRST_OFFSET) +#define LPC17_40_DMA_INTERRCLR (LPC17_40_GPDMA_BASE+LPC17_40_DMA_INTERRCLR_OFFSET) +#define LPC17_40_DMA_RAWINTTCST (LPC17_40_GPDMA_BASE+LPC17_40_DMA_RAWINTTCST_OFFSET) +#define LPC17_40_DMA_RAWINTERRST (LPC17_40_GPDMA_BASE+LPC17_40_DMA_RAWINTERRST_OFFSET) +#define LPC17_40_DMA_ENBLDCHNS (LPC17_40_GPDMA_BASE+LPC17_40_DMA_ENBLDCHNS_OFFSET) +#define LPC17_40_DMA_SOFTBREQ (LPC17_40_GPDMA_BASE+LPC17_40_DMA_SOFTBREQ_OFFSET) +#define LPC17_40_DMA_SOFTSREQ (LPC17_40_GPDMA_BASE+LPC17_40_DMA_SOFTSREQ_OFFSET) +#define LPC17_40_DMA_SOFTLBREQ (LPC17_40_GPDMA_BASE+LPC17_40_DMA_SOFTLBREQ_OFFSET) +#define LPC17_40_DMA_SOFTLSREQ (LPC17_40_GPDMA_BASE+LPC17_40_DMA_SOFTLSREQ_OFFSET) +#define LPC17_40_DMA_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMA_CONFIG_OFFSET) +#define LPC17_40_DMA_SYNC (LPC17_40_GPDMA_BASE+LPC17_40_DMA_SYNC_OFFSET) + +/* Channel Registers */ + +#define LPC17_40_DMACH_BASE(n) (LPC17_40_GPDMA_BASE+LPC17_40_DMA_CHAN_OFFSET(n)) + +#define LPC17_40_DMACH_SRCADDR(n) (LPC17_40_DMACH_BASE(n)+LPC17_40_DMACH_SRCADDR_OFFSET) +#define LPC17_40_DMACH_DESTADDR(n) (LPC17_40_DMACH_BASE(n)+LPC17_40_DMACH_DESTADDR_OFFSET) +#define LPC17_40_DMACH_LLI(n) (LPC17_40_DMACH_BASE(n)+LPC17_40_DMACH_LLI_OFFSET) +#define LPC17_40_DMACH_CONTROL(n) (LPC17_40_DMACH_BASE(n)+LPC17_40_DMACH_CONTROL_OFFSET) +#define LPC17_40_DMACH_CONFIG(n) (LPC17_40_DMACH_BASE(n)+LPC17_40_DMACH_CONFIG_OFFSET) + +#define LPC17_40_DMACH0_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH0_SRCADDR_OFFSET) +#define LPC17_40_DMACH0_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH0_DESTADDR_OFFSET) +#define LPC17_40_DMACH0_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH0_LLI_OFFSET) +#define LPC17_40_DMACH0_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH0_CONTROL_OFFSET) +#define LPC17_40_DMACH0_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH0_CONFIG_OFFSET) + +#define LPC17_40_DMACH1_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH1_SRCADDR_OFFSET) +#define LPC17_40_DMACH1_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH1_DESTADDR_OFFSET) +#define LPC17_40_DMACH1_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH1_LLI_OFFSET) +#define LPC17_40_DMACH1_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH1_CONTROL_OFFSET) +#define LPC17_40_DMACH1_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH1_CONFIG_OFFSET) + +#define LPC17_40_DMACH2_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH2_SRCADDR_OFFSET) +#define LPC17_40_DMACH2_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH2_DESTADDR_OFFSET) +#define LPC17_40_DMACH2_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH2_LLI_OFFSET) +#define LPC17_40_DMACH2_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH2_CONTROL_OFFSET) +#define LPC17_40_DMACH2_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH2_CONFIG_OFFSET) + +#define LPC17_40_DMACH3_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH3_SRCADDR_OFFSET) +#define LPC17_40_DMACH3_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH3_DESTADDR_OFFSET) +#define LPC17_40_DMACH3_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH3_LLI_OFFSET) +#define LPC17_40_DMACH3_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH3_CONTROL_OFFSET) +#define LPC17_40_DMACH3_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH3_CONFIG_OFFSET) + +#define LPC17_40_DMACH4_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH4_SRCADDR_OFFSET) +#define LPC17_40_DMACH4_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH4_DESTADDR_OFFSET) +#define LPC17_40_DMACH4_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH4_LLI_OFFSET) +#define LPC17_40_DMACH4_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH4_CONTROL_OFFSET) +#define LPC17_40_DMACH4_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH4_CONFIG_OFFSET) + +#define LPC17_40_DMACH5_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH5_SRCADDR_OFFSET) +#define LPC17_40_DMACH5_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH5_DESTADDR_OFFSET) +#define LPC17_40_DMACH5_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH5_LLI_OFFSET) +#define LPC17_40_DMACH5_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH5_CONTROL_OFFSET) +#define LPC17_40_DMACH5_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH5_CONFIG_OFFSET) + +#define LPC17_40_DMACH6_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH6_SRCADDR_OFFSET) +#define LPC17_40_DMACH6_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH6_DESTADDR_OFFSET) +#define LPC17_40_DMACH6_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH6_LLI_OFFSET) +#define LPC17_40_DMACH6_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH6_CONTROL_OFFSET) +#define LPC17_40_DMACH6_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH6_CONFIG_OFFSET) + +#define LPC17_40_DMACH7_SRCADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH7_SRCADDR_OFFSET) +#define LPC17_40_DMACH7_DESTADDR (LPC17_40_GPDMA_BASE+LPC17_40_DMACH7_DESTADDR_OFFSET) +#define LPC17_40_DMACH7_LLI (LPC17_40_GPDMA_BASE+LPC17_40_DMACH7_LLI_OFFSET) +#define LPC17_40_DMACH7_CONTROL (LPC17_40_GPDMA_BASE+LPC17_40_DMACH7_CONTROL_OFFSET) +#define LPC17_40_DMACH7_CONFIG (LPC17_40_GPDMA_BASE+LPC17_40_DMACH7_CONFIG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* DMA Request Connections **********************************************************/ + +#define LPC17_40_NDMAREQ (16) /* The number of DMA requests */ +#if defined(LPC176x) +/* Request Numbers */ + +# define DMA_REQ_SSP0TX (0) +# define DMA_REQ_SSP0RX (1) +# define DMA_REQ_SSP1TX (2) +# define DMA_REQ_SSP1RX (3) + +# define DMA_REQ_ADC (4) + +# define DMA_REQ_I2SCH0 (5) +# define DMA_REQ_I2SCH1 (6) + +# define DMA_REQ_DAC (7) + +# define DMA_REQ_UART0TX (8) /* DMASEL08=0*/ +# define DMA_REQ_UART0RX (9) /* DMASEL09=0*/ +# define DMA_REQ_UART1TX (10) /* DMASEL010=0*/ +# define DMA_REQ_UART1RX (11) /* DMASEL011=0*/ +# define DMA_REQ_UART2TX (12) /* DMASEL012=0*/ +# define DMA_REQ_UART2RX (13) /* DMASEL013=0*/ +# define DMA_REQ_UART3TX (14) /* DMASEL014=0*/ +# define DMA_REQ_UART3RX (15) /* DMASEL015=0*/ + +# define DMA_REQ_MAT0p0 (8) /* DMASEL08=1 */ +# define DMA_REQ_MAT0p1 (9) /* DMASEL09=1 */ +# define DMA_REQ_MAT1p0 (10) /* DMASEL010=1 */ +# define DMA_REQ_MAT1p1 (11) /* DMASEL011=1 */ +# define DMA_REQ_MAT2p0 (12) /* DMASEL012=1 */ +# define DMA_REQ_MAT2p1 (13) /* DMASEL013=1 */ +# define DMA_REQ_MAT3p0 (14) /* DMASEL014=1 */ +# define DMA_REQ_MAT3p1 (15) /* DMASEL015=1 */ + +/* DMASEL values. For the LPC176x family, only request numbers 8-15 have + * DMASEL bits. + */ + +# define DMA_DMASEL_SSP0TX (0) /* Not applicable */ +# define DMA_DMASEL_SSP0RX (0) /* Not applicable */ +# define DMA_DMASEL_SSP1TX (0) /* Not applicable */ +# define DMA_DMASEL_SSP1RX (0) /* Not applicable */ + +# define DMA_DMASEL_ADC (0) /* Not applicable */ + +# define DMA_DMASEL_I2SCH0 (0) /* Not applicable */ +# define DMA_DMASEL_I2SCH1 (0) /* Not applicable */ + +# define DMA_DMASEL_DAC (0) /* Not applicable */ + +# define DMA_DMASEL_UART0TX (0) +# define DMA_DMASEL_UART0RX (0) +# define DMA_DMASEL_UART1TX (0) +# define DMA_DMASEL_UART1RX (0) +# define DMA_DMASEL_UART2TX (0) +# define DMA_DMASEL_UART2RX (0) +# define DMA_DMASEL_UART3TX (0) +# define DMA_DMASEL_UART3RX (0) + +# define DMA_DMASEL_MAT0p0 (1) +# define DMA_DMASEL_MAT0p1 (1) +# define DMA_DMASEL_MAT1p0 (1) +# define DMA_DMASEL_MAT1p1 (1) +# define DMA_DMASEL_MAT2p0 (1) +# define DMA_DMASEL_MAT2p1 (1) +# define DMA_DMASEL_MAT3p0 (1) +# define DMA_DMASEL_MAT3p1 (1) + +#elif defined(LPC178x_40xx) +/* Request Numbers */ + +# define DMA_REQ_SDCARD (1) /* DMASEL01=0 */ + +# define DMA_REQ_SSP0TX (2) /* DMASEL02=0 */ +# define DMA_REQ_SSP0RX (3) /* DMASEL03=0 */ +# define DMA_REQ_SSP1TX (4) /* DMASEL04=0 */ +# define DMA_REQ_SSP1RX (5) /* DMASEL05=0 */ +# define DMA_REQ_SSP2TX (6) /* DMASEL06=0 */ +# define DMA_REQ_SSP2RX (7) /* DMASEL07=0 */ + +# define DMA_REQ_MAT0p0 (0) /* DMASEL00=1 */ +# define DMA_REQ_MAT0p1 (1) /* DMASEL01=1 */ +# define DMA_REQ_MAT1p0 (2) /* DMASEL02=1 */ +# define DMA_REQ_MAT1p1 (3) /* DMASEL03=1 */ +# define DMA_REQ_MAT2p0 (4) /* DMASEL04=1 */ +# define DMA_REQ_MAT2p1 (5) /* DMASEL05=1 */ +# define DMA_REQ_MAT3p0 (14) /* DMASEL14=1 */ +# define DMA_REQ_MAT3p1 (15) /* DMASEL15=1 */ + +# define DMA_REQ_I2SCH0 (6) /* DMASEL06=1 */ +# define DMA_REQ_I2SCH1 (7) /* DMASEL07=1 */ + +# define DMA_REQ_ADC (8) /* Not applicable */ +# define DMA_REQ_DAC (9) /* Not applicable */ + +# define DMA_REQ_UART0TX (10) /* DMASEL10=0 */ +# define DMA_REQ_UART0RX (11) /* DMASEL11=0 */ +# define DMA_REQ_UART1TX (12) /* DMASEL12=0 */ +# define DMA_REQ_UART1RX (13) /* DMASEL13=0 */ +# define DMA_REQ_UART2TX (14) /* DMASEL14=0 */ +# define DMA_REQ_UART2RX (15) /* DMASEL15=0 */ +# define DMA_REQ_UART3TX (10) /* DMASEL10=1 */ +# define DMA_REQ_UART3RX (11) /* DMASEL11=1 */ +# define DMA_REQ_UART4TX (12) /* DMASEL12=1 */ +# define DMA_REQ_UART4RX (13) /* DMASEL13=1 */ + +/* DMASEL values */ + +# define DMA_DMASEL_SDCARD (0) + +# define DMA_DMASEL_SSP0TX (0) +# define DMA_DMASEL_SSP0RX (0) +# define DMA_DMASEL_SSP1TX (0) +# define DMA_DMASEL_SSP1RX (0) +# define DMA_DMASEL_SSP2TX (0) +# define DMA_DMASEL_SSP2RX (0) + +# define DMA_DMASEL_MAT0p0 (1) +# define DMA_DMASEL_MAT0p1 (1) +# define DMA_DMASEL_MAT1p0 (1) +# define DMA_DMASEL_MAT1p1 (1) +# define DMA_DMASEL_MAT2p0 (1) +# define DMA_DMASEL_MAT2p1 (1) +# define DMA_DMASEL_MAT3p0 (1) +# define DMA_DMASEL_MAT3p1 (1) + +# define DMA_DMASEL_I2SCH0 (1) +# define DMA_DMASEL_I2SCH1 (1) + +# define DMA_DMASEL_ADC (0) /* Not applicable */ +# define DMA_DMASEL_DAC (0) /* Not applicable */ + +# define DMA_DMASEL_UART0TX (0) +# define DMA_DMASEL_UART0RX (0) +# define DMA_DMASEL_UART1TX (0) +# define DMA_DMASEL_UART1RX (0) +# define DMA_DMASEL_UART2TX (0) +# define DMA_DMASEL_UART2RX (0) +# define DMA_DMASEL_UART3TX (1) +# define DMA_DMASEL_UART3RX (1) +# define DMA_DMASEL_UART4TX (1) +# define DMA_DMASEL_UART4RX (1) +#endif + +/* General registers (see also LPC17_40_SYSCON_DMAREQSEL in lpc17_40_syscon.h) */ +/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, + * respectively. Bits 8-31 are reserved. + * + * DMA Interrupt Status Register + * DMA Interrupt Terminal Count Request Status Register + * DMA Interrupt Terminal Count Request Clear Register + * DMA Interrupt Error Status Register + * DMA Interrupt Error Clear Register + * DMA Raw Interrupt Terminal Count Status Register + * DMA Raw Error Interrupt Status Register + * DMA Enabled Channel Register + */ + +#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ +#define DMACH_ALL (0xff) + +/* For each of the following registers, bits 0-15 represent a set of encoded + * DMA sources. Bits 16-31 are reserved in each case. + * + * DMA Software Burst Request Register + * DMA Software Single Request Register + * DMA Software Last Burst Request Register + * DMA Software Last Single Request Register + * DMA Synchronization Register + */ + +#if defined(LPC176x) +# define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) +# define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) +# define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) +# define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) +# define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) +# define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) +# define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) +# define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) + +# define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) +# define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) +# define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) +# define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) +# define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) +# define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) +# define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) +# define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) + +# define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) +# define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) +# define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) +# define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) +# define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) +# define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) +# define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) +# define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) +#elif defined(LPC178x_40xx) +# define DMA_REQ_SDCARD_BIT (1 << DMA_REQ_SDCARD) + +# define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) +# define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) +# define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) +# define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP1RX) +# define DMA_REQ_SSP2TX_BIT (1 << DMA_REQ_SSP2TX) +# define DMA_REQ_SSP2RX_BIT (1 << DMA_REQ_SSP2RX) + +# define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) +# define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) +# define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) +# define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) +# define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) +# define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) +# define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) +# define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) + +# define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) +# define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) + +# define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) +# define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) + +# define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) +# define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) +# define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) +# define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) +# define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) +# define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) +# define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) +# define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) +# define DMA_REQ_UART4TX_BIT (1 << DMA_REQ_UART4TX) +# define DMA_REQ_UART4RX_BIT (1 << DMA_REQ_UART4RX) +#endif + +/* DMA Configuration Register */ + +#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ +#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ + /* Bits 2-31: Reserved */ +/* Channel Registers */ + +/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ +/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ +/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list + * item. Bits 0-1 must be zero. + */ + +/* DMA Channel Control Register */ + +#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ +#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) +# define DMACH_CONTROL_XFRSIZE(n) ((n) << DMACH_CONTROL_XFRSIZE_SHIFT) +#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ +#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) +#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ +#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) +#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ +#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) +# define DMACH_CONTROL_SWIDTH_8BIT (0 << DMACH_CONTROL_SWIDTH_SHIFT) /* Byte (8-bit) */ +# define DMACH_CONTROL_SWIDTH_16BIT (1 << DMACH_CONTROL_SWIDTH_SHIFT) /* Halfword (16-bit) */ +# define DMACH_CONTROL_SWIDTH_32BIT (2 << DMACH_CONTROL_SWIDTH_SHIFT) /* Word (32-bit) */ +#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ +#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) +# define DMACH_CONTROL_DWIDTH_8BIT (0 << DMACH_CONTROL_DWIDTH_SHIFT) /* Byte (8-bit) */ +# define DMACH_CONTROL_DWIDTH_16BIT (1 << DMACH_CONTROL_DWIDTH_SHIFT) /* Halfword (16-bit) */ +# define DMACH_CONTROL_DWIDTH_32BIT (2 << DMACH_CONTROL_DWIDTH_SHIFT) /* Word (32-bit) */ +#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ +#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ +#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ +#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ +#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ +#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ + +/* DMA Channel Configuration Register */ + +#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ +#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ +#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SDCARD (DMA_REQ_SDCARD << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP1RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP2TX (DMA_REQ_SSP2TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP2RX (DMA_REQ_SSP2RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART4TX (DMA_REQ_UART4TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART4RX (DMA_REQ_UART4RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) +#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Destination peripheral */ +#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SDCARD (DMA_REQ_SDCARD << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP1RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP2TX (DMA_REQ_SSP2TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP2RX (DMA_REQ_SSP2RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART4TX (DMA_REQ_UART4TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART4RX (DMA_REQ_UART4RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) +#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ +#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) + /* Flow controller = DMA controller */ +# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory */ +# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral */ +# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory */ +# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral */ +#ifdef LPC178x_40xx + /* Flow controller = Dest peripheral */ +# define DMACH_CONFIG_XFRTYPE_M2M_DC (4 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory */ +# define DMACH_CONFIG_XFRTYPE_M2P_DC (5 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral */ + /* Flow controller = Source peripheral */ +# define DMACH_CONFIG_XFRTYPE_P2M_SC (6 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory */ +# define DMACH_CONFIG_XFRTYPE_P2P_SC (7 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral */ +#endif +#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ +#define DMACH_CONFIG_ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ +#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ +#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ +#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ + /* Bits 19-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_GPDMA_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpio.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpio.h new file mode 100644 index 00000000000..b18e7075447 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpio.h @@ -0,0 +1,210 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_gpio.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* GPIO block register offsets ******************************************************/ + +#define LPC17_40_FIO0_OFFSET 0x0000 +#define LPC17_40_FIO1_OFFSET 0x0020 +#define LPC17_40_FIO2_OFFSET 0x0040 +#define LPC17_40_FIO3_OFFSET 0x0060 +#define LPC17_40_FIO4_OFFSET 0x0080 +#ifdef LPC178x_40xx +# define LPC17_40_FIO5_OFFSET 0x00a0 +#endif + +#define LPC17_40_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ +#define LPC17_40_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ +#define LPC17_40_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ +#define LPC17_40_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ +#define LPC17_40_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ + +/* GPIO interrupt block register offsets ********************************************/ + +#define LPC17_40_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) +#define LPC17_40_GPIOINT0_OFFSET 0x0080 +#define LPC17_40_GPIOINT2_OFFSET 0x00a0 + +#define LPC17_40_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ +#define LPC17_40_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ +#define LPC17_40_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ +#define LPC17_40_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ +#define LPC17_40_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ +#define LPC17_40_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ + +/* Register addresses ***************************************************************/ +/* GPIO block register addresses ****************************************************/ + +#define LPC17_40_FIO_BASE(n) (LPC17_40_GPIO_BASE+LPC17_40_GPIOINT_OFFSET(n)) +#define LPC17_40_FIO0_BASE (LPC17_40_GPIO_BASE+LPC17_40_FIO0_OFFSET) +#define LPC17_40_FIO1_BASE (LPC17_40_GPIO_BASE+LPC17_40_FIO1_OFFSET) +#define LPC17_40_FIO2_BASE (LPC17_40_GPIO_BASE+LPC17_40_FIO2_OFFSET) +#define LPC17_40_FIO3_BASE (LPC17_40_GPIO_BASE+LPC17_40_FIO3_OFFSET) +#define LPC17_40_FIO4_BASE (LPC17_40_GPIO_BASE+LPC17_40_FIO4_OFFSET) +#ifdef LPC178x_40xx +# define LPC17_40_FIO5_BASE (LPC17_40_GPIO_BASE+LPC17_40_FIO5_OFFSET) +#endif + +#define LPC17_40_FIO_DIR(n) (LPC17_40_FIO_BASE(n)+LPC17_40_FIO_DIR_OFFSET) +#define LPC17_40_FIO_MASK(n) (LPC17_40_FIO_BASE(n)+LPC17_40_FIO_MASK_OFFSET) +#define LPC17_40_FIO_PIN(n) (LPC17_40_FIO_BASE(n)+LPC17_40_FIO_PIN_OFFSET) +#define LPC17_40_FIO_SET(n) (LPC17_40_FIO_BASE(n)+LPC17_40_FIO_SET_OFFSET) +#define LPC17_40_FIO_CLR(n) (LPC17_40_FIO_BASE(n)+LPC17_40_FIO_CLR_OFFSET) + +#define LPC17_40_FIO0_DIR (LPC17_40_FIO0_BASE+LPC17_40_FIO_DIR_OFFSET) +#define LPC17_40_FIO0_MASK (LPC17_40_FIO0_BASE+LPC17_40_FIO_MASK_OFFSET) +#define LPC17_40_FIO0_PIN (LPC17_40_FIO0_BASE+LPC17_40_FIO_PIN_OFFSET) +#define LPC17_40_FIO0_SET (LPC17_40_FIO0_BASE+LPC17_40_FIO_SET_OFFSET) +#define LPC17_40_FIO0_CLR (LPC17_40_FIO0_BASE+LPC17_40_FIO_CLR_OFFSET) + +#define LPC17_40_FIO1_DIR (LPC17_40_FIO1_BASE+LPC17_40_FIO_DIR_OFFSET) +#define LPC17_40_FIO1_MASK (LPC17_40_FIO1_BASE+LPC17_40_FIO_MASK_OFFSET) +#define LPC17_40_FIO1_PIN (LPC17_40_FIO1_BASE+LPC17_40_FIO_PIN_OFFSET) +#define LPC17_40_FIO1_SET (LPC17_40_FIO1_BASE+LPC17_40_FIO_SET_OFFSET) +#define LPC17_40_FIO1_CLR (LPC17_40_FIO1_BASE+LPC17_40_FIO_CLR_OFFSET) + +#define LPC17_40_FIO2_DIR (LPC17_40_FIO2_BASE+LPC17_40_FIO_DIR_OFFSET) +#define LPC17_40_FIO2_MASK (LPC17_40_FIO2_BASE+LPC17_40_FIO_MASK_OFFSET) +#define LPC17_40_FIO2_PIN (LPC17_40_FIO2_BASE+LPC17_40_FIO_PIN_OFFSET) +#define LPC17_40_FIO2_SET (LPC17_40_FIO2_BASE+LPC17_40_FIO_SET_OFFSET) +#define LPC17_40_FIO2_CLR (LPC17_40_FIO2_BASE+LPC17_40_FIO_CLR_OFFSET) + +#define LPC17_40_FIO3_DIR (LPC17_40_FIO3_BASE+LPC17_40_FIO_DIR_OFFSET) +#define LPC17_40_FIO3_MASK (LPC17_40_FIO3_BASE+LPC17_40_FIO_MASK_OFFSET) +#define LPC17_40_FIO3_PIN (LPC17_40_FIO3_BASE+LPC17_40_FIO_PIN_OFFSET) +#define LPC17_40_FIO3_SET (LPC17_40_FIO3_BASE+LPC17_40_FIO_SET_OFFSET) +#define LPC17_40_FIO3_CLR (LPC17_40_FIO3_BASE+LPC17_40_FIO_CLR_OFFSET) + +#define LPC17_40_FIO4_DIR (LPC17_40_FIO4_BASE+LPC17_40_FIO_DIR_OFFSET) +#define LPC17_40_FIO4_MASK (LPC17_40_FIO4_BASE+LPC17_40_FIO_MASK_OFFSET) +#define LPC17_40_FIO4_PIN (LPC17_40_FIO4_BASE+LPC17_40_FIO_PIN_OFFSET) +#define LPC17_40_FIO4_SET (LPC17_40_FIO4_BASE+LPC17_40_FIO_SET_OFFSET) +#define LPC17_40_FIO4_CLR (LPC17_40_FIO4_BASE+LPC17_40_FIO_CLR_OFFSET) + +#ifdef LPC178x_40xx +# define LPC17_40_FIO5_DIR (LPC17_40_FIO5_BASE+LPC17_40_FIO_DIR_OFFSET) +# define LPC17_40_FIO5_MASK (LPC17_40_FIO5_BASE+LPC17_40_FIO_MASK_OFFSET) +# define LPC17_40_FIO5_PIN (LPC17_40_FIO5_BASE+LPC17_40_FIO_PIN_OFFSET) +# define LPC17_40_FIO5_SET (LPC17_40_FIO5_BASE+LPC17_40_FIO_SET_OFFSET) +# define LPC17_40_FIO5_CLR (LPC17_40_FIO5_BASE+LPC17_40_FIO_CLR_OFFSET) +#endif + +/* GPIO interrupt block register addresses ******************************************/ + +#define LPC17_40_GPIOINTn_BASE(n) (LPC17_40_GPIOINT_BASE+LPC17_40_GPIOINT_OFFSET(n)) +#define LPC17_40_GPIOINT0_BASE (LPC17_40_GPIOINT_BASE+LPC17_40_GPIOINT0_OFFSET) +#define LPC17_40_GPIOINT2_BASE (LPC17_40_GPIOINT_BASE+LPC17_40_GPIOINT2_OFFSET) + +#define LPC17_40_GPIOINT_IOINTSTATUS (LPC17_40_GPIOINT0_BASE+LPC17_40_GPIOINT_IOINTSTATUS_OFFSET) + +#define LPC17_40_GPIOINT_INTSTATR(n) (LPC17_40_GPIOINTn_BASE(n)+LPC17_40_GPIOINT_INTSTATR_OFFSET) +#define LPC17_40_GPIOINT_INTSTATF(n) (LPC17_40_GPIOINTn_BASE(n)+LPC17_40_GPIOINT_INTSTATF_OFFSET) +#define LPC17_40_GPIOINT_INTCLR(n) (LPC17_40_GPIOINTn_BASE(n)+LPC17_40_GPIOINT_INTCLR_OFFSET) +#define LPC17_40_GPIOINT_INTENR(n) (LPC17_40_GPIOINTn_BASE(n)+LPC17_40_GPIOINT_INTENR_OFFSET) +#define LPC17_40_GPIOINT_INTENF(n) (LPC17_40_GPIOINTn_BASE(n)+LPC17_40_GPIOINT_INTENF_OFFSET) + +/* Pins P0.0-31 */ + +#define LPC17_40_GPIOINT0_INTSTATR (LPC17_40_GPIOINT0_BASE+LPC17_40_GPIOINT_INTSTATR_OFFSET) +#define LPC17_40_GPIOINT0_INTSTATF (LPC17_40_GPIOINT0_BASE+LPC17_40_GPIOINT_INTSTATF_OFFSET) +#define LPC17_40_GPIOINT0_INTCLR (LPC17_40_GPIOINT0_BASE+LPC17_40_GPIOINT_INTCLR_OFFSET) +#define LPC17_40_GPIOINT0_INTENR (LPC17_40_GPIOINT0_BASE+LPC17_40_GPIOINT_INTENR_OFFSET) +#define LPC17_40_GPIOINT0_INTENF (LPC17_40_GPIOINT0_BASE+LPC17_40_GPIOINT_INTENF_OFFSET) + +/* Pins P2.0-31 */ + +#define LPC17_40_GPIOINT2_INTSTATR (LPC17_40_GPIOINT2_BASE+LPC17_40_GPIOINT_INTSTATR_OFFSET) +#define LPC17_40_GPIOINT2_INTSTATF (LPC17_40_GPIOINT2_BASE+LPC17_40_GPIOINT_INTSTATF_OFFSET) +#define LPC17_40_GPIOINT2_INTCLR (LPC17_40_GPIOINT2_BASE+LPC17_40_GPIOINT_INTCLR_OFFSET) +#define LPC17_40_GPIOINT2_INTENR (LPC17_40_GPIOINT2_BASE+LPC17_40_GPIOINT_INTENR_OFFSET) +#define LPC17_40_GPIOINT2_INTENF (LPC17_40_GPIOINT2_BASE+LPC17_40_GPIOINT_INTENF_OFFSET) + +/* Register bit definitions *********************************************************/ +/* GPIO block register bit definitions **********************************************/ + +/* Fast GPIO Port Direction control registers (FIODIR) */ +/* Fast Mask register for ports (FIOMASK) */ +/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ +/* Fast Port Output Set registers using FIOMASK (FIOSET) */ +/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ + +#define FIO(n) (1 << (n)) /* n=0,1,..31 */ + +/* GPIO interrupt block register bit definitions ************************************/ + +/* GPIO overall Interrupt Status (IOINTSTATUS) */ +#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ + /* Bit 1: Reserved */ +#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ + /* Bits 3-31: Reserved */ + +/* GPIO Interrupt Status for Rising edge (INTSTATR) + * GPIO Interrupt Status for Falling edge (INTSTATF) + * GPIO Interrupt Clear (INTCLR) + * GPIO Interrupt Enable for Rising edge (INTENR) + * GPIO Interrupt Enable for Falling edge (INTENF) + */ + +#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_CHIP_GPIO_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2c.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2c.h new file mode 100644 index 00000000000..c542b0c4b86 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2c.h @@ -0,0 +1,208 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2c.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2C_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ +#define LPC17_40_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ +#define LPC17_40_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ +#define LPC17_40_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ +#define LPC17_40_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ +#define LPC17_40_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ +#define LPC17_40_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ +#define LPC17_40_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ +#define LPC17_40_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ +#define LPC17_40_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ +#define LPC17_40_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ +#define LPC17_40_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ +#define LPC17_40_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ +#define LPC17_40_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ +#define LPC17_40_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ +#define LPC17_40_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_I2C0_CONSET (LPC17_40_I2C0_BASE+LPC17_40_I2C_CONSET_OFFSET) +#define LPC17_40_I2C0_STAT (LPC17_40_I2C0_BASE+LPC17_40_I2C_STAT_OFFSET) +#define LPC17_40_I2C0_DAT (LPC17_40_I2C0_BASE+LPC17_40_I2C_DAT_OFFSET) +#define LPC17_40_I2C0_ADR0 (LPC17_40_I2C0_BASE+LPC17_40_I2C_ADR0_OFFSET) +#define LPC17_40_I2C0_SCLH (LPC17_40_I2C0_BASE+LPC17_40_I2C_SCLH_OFFSET) +#define LPC17_40_I2C0_SCLL (LPC17_40_I2C0_BASE+LPC17_40_I2C_SCLL_OFFSET) +#define LPC17_40_I2C0_CONCLR (LPC17_40_I2C0_BASE+LPC17_40_I2C_CONCLR_OFFSET) +#define LPC17_40_I2C0_MMCTRL (LPC17_40_I2C0_BASE+LPC17_40_I2C_MMCTRL_OFFSET) +#define LPC17_40_I2C0_ADR1 (LPC17_40_I2C0_BASE+LPC17_40_I2C_ADR1_OFFSET) +#define LPC17_40_I2C0_ADR2 (LPC17_40_I2C0_BASE+LPC17_40_I2C_ADR2_OFFSET) +#define LPC17_40_I2C0_ADR3 (LPC17_40_I2C0_BASE+LPC17_40_I2C_ADR3_OFFSET) +#define LPC17_40_I2C0_BUFR (LPC17_40_I2C0_BASE+LPC17_40_I2C_BUFR_OFFSET) +#define LPC17_40_I2C0_MASK0 (LPC17_40_I2C0_BASE+LPC17_40_I2C_MASK0_OFFSET) +#define LPC17_40_I2C0_MASK1 (LPC17_40_I2C0_BASE+LPC17_40_I2C_MASK1_OFFSET) +#define LPC17_40_I2C0_MASK2 (LPC17_40_I2C0_BASE+LPC17_40_I2C_MASK2_OFFSET) +#define LPC17_40_I2C0_MASK3 (LPC17_40_I2C0_BASE+LPC17_40_I2C_MASK3_OFFSET) + +#define LPC17_40_I2C1_CONSET (LPC17_40_I2C1_BASE+LPC17_40_I2C_CONSET_OFFSET) +#define LPC17_40_I2C1_STAT (LPC17_40_I2C1_BASE+LPC17_40_I2C_STAT_OFFSET) +#define LPC17_40_I2C1_DAT (LPC17_40_I2C1_BASE+LPC17_40_I2C_DAT_OFFSET) +#define LPC17_40_I2C1_ADR0 (LPC17_40_I2C1_BASE+LPC17_40_I2C_ADR0_OFFSET) +#define LPC17_40_I2C1_SCLH (LPC17_40_I2C1_BASE+LPC17_40_I2C_SCLH_OFFSET) +#define LPC17_40_I2C1_SCLL (LPC17_40_I2C1_BASE+LPC17_40_I2C_SCLL_OFFSET) +#define LPC17_40_I2C1_CONCLR (LPC17_40_I2C1_BASE+LPC17_40_I2C_CONCLR_OFFSET) +#define LPC17_40_I2C1_MMCTRL (LPC17_40_I2C1_BASE+LPC17_40_I2C_MMCTRL_OFFSET) +#define LPC17_40_I2C1_ADR1 (LPC17_40_I2C1_BASE+LPC17_40_I2C_ADR1_OFFSET) +#define LPC17_40_I2C1_ADR2 (LPC17_40_I2C1_BASE+LPC17_40_I2C_ADR2_OFFSET) +#define LPC17_40_I2C1_ADR3 (LPC17_40_I2C1_BASE+LPC17_40_I2C_ADR3_OFFSET) +#define LPC17_40_I2C1_BUFR (LPC17_40_I2C1_BASE+LPC17_40_I2C_BUFR_OFFSET) +#define LPC17_40_I2C1_MASK0 (LPC17_40_I2C1_BASE+LPC17_40_I2C_MASK0_OFFSET) +#define LPC17_40_I2C1_MASK1 (LPC17_40_I2C1_BASE+LPC17_40_I2C_MASK1_OFFSET) +#define LPC17_40_I2C1_MASK2 (LPC17_40_I2C1_BASE+LPC17_40_I2C_MASK2_OFFSET) +#define LPC17_40_I2C1_MASK3 (LPC17_40_I2C1_BASE+LPC17_40_I2C_MASK3_OFFSET) + +#define LPC17_40_I2C2_CONSET (LPC17_40_I2C2_BASE+LPC17_40_I2C_CONSET_OFFSET) +#define LPC17_40_I2C2_STAT (LPC17_40_I2C2_BASE+LPC17_40_I2C_STAT_OFFSET) +#define LPC17_40_I2C2_DAT (LPC17_40_I2C2_BASE+LPC17_40_I2C_DAT_OFFSET) +#define LPC17_40_I2C2_ADR0 (LPC17_40_I2C2_BASE+LPC17_40_I2C_ADR0_OFFSET) +#define LPC17_40_I2C2_SCLH (LPC17_40_I2C2_BASE+LPC17_40_I2C_SCLH_OFFSET) +#define LPC17_40_I2C2_SCLL (LPC17_40_I2C2_BASE+LPC17_40_I2C_SCLL_OFFSET) +#define LPC17_40_I2C2_CONCLR (LPC17_40_I2C2_BASE+LPC17_40_I2C_CONCLR_OFFSET) +#define LPC17_40_I2C2_MMCTRL (LPC17_40_I2C2_BASE+LPC17_40_I2C_MMCTRL_OFFSET) +#define LPC17_40_I2C2_ADR1 (LPC17_40_I2C2_BASE+LPC17_40_I2C_ADR1_OFFSET) +#define LPC17_40_I2C2_ADR2 (LPC17_40_I2C2_BASE+LPC17_40_I2C_ADR2_OFFSET) +#define LPC17_40_I2C2_ADR3 (LPC17_40_I2C2_BASE+LPC17_40_I2C_ADR3_OFFSET) +#define LPC17_40_I2C2_BUFR (LPC17_40_I2C2_BASE+LPC17_40_I2C_BUFR_OFFSET) +#define LPC17_40_I2C2_MASK0 (LPC17_40_I2C2_BASE+LPC17_40_I2C_MASK0_OFFSET) +#define LPC17_40_I2C2_MASK1 (LPC17_40_I2C2_BASE+LPC17_40_I2C_MASK1_OFFSET) +#define LPC17_40_I2C2_MASK2 (LPC17_40_I2C2_BASE+LPC17_40_I2C_MASK2_OFFSET) +#define LPC17_40_I2C2_MASK3 (LPC17_40_I2C2_BASE+LPC17_40_I2C_MASK3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* I2C Control Set Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ + /* Bits 7-31: Reserved */ +/* I2C Control Clear Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ +#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ + /* Bit 4: Reserved */ +#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ +#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ + /* Bits 7-31: Reserved */ +/* I2C Status Register + * + * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January + * 2010, NXP for definitions of status codes. + */ + +#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status + * Bits 0-1 always zero */ + /* Bits 8-31: Reserved */ +/* I2C Data Register */ + +#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ + /* Bits 8-31: Reserved */ +/* Monitor mode control register */ + +#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ +#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ +#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ + /* Bits 3-31: Reserved */ +/* Data buffer register */ + +#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ + /* Bits 8-31: Reserved */ +/* I2C Slave address registers: + * + * I2C Slave Address Register 0 + * I2C Slave Address Register 1 + * I2C Slave Address Register 2 + * I2C Slave Address Register 3 + */ + +#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ +#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ +#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Slave address mask registers: + * + * I2C Slave address mask register 0 + * I2C Slave address mask register 1 + * I2C Slave address mask register 2 + * I2C Slave address mask register 3 + */ + /* Bit 0: Reserved */ +#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ +#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* SCH Duty Cycle Register High Half Word */ + +#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ + /* Bits 16-31: Reserved */ +/* SCL Duty Cycle Register Low Half Word */ + +#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ + /* Bits 16-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2C_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2s.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2s.h new file mode 100644 index 00000000000..0cd43c24dee --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2s.h @@ -0,0 +1,190 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2s + * + * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2S_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2S_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */ +#define LPC17_40_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */ +#define LPC17_40_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */ +#define LPC17_40_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */ +#define LPC17_40_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */ +#define LPC17_40_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */ +#define LPC17_40_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */ +#define LPC17_40_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */ +#define LPC17_40_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */ +#define LPC17_40_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */ +#define LPC17_40_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */ +#define LPC17_40_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */ +#define LPC17_40_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */ +#define LPC17_40_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_I2S_DAO (LPC17_40_I2S_BASE+LPC17_40_I2S_DAO_OFFSET) +#define LPC17_40_I2S_DAI (LPC17_40_I2S_BASE+LPC17_40_I2S_DAI_OFFSET) +#define LPC17_40_I2S_TXFIFO (LPC17_40_I2S_BASE+LPC17_40_I2S_TXFIFO_OFFSET) +#define LPC17_40_I2S_RXFIFO (LPC17_40_I2S_BASE+LPC17_40_I2S_RXFIFO_OFFSET) +#define LPC17_40_I2S_STATE (LPC17_40_I2S_BASE+LPC17_40_I2S_STATE_OFFSET) +#define LPC17_40_I2S_DMA1 (LPC17_40_I2S_BASE+LPC17_40_I2S_DMA1_OFFSET) +#define LPC17_40_I2S_DMA2 (LPC17_40_I2S_BASE+LPC17_40_I2S_DMA2_OFFSET) +#define LPC17_40_I2S_IRQ (LPC17_40_I2S_BASE+LPC17_40_I2S_IRQ_OFFSET) +#define LPC17_40_I2S_TXRATE (LPC17_40_I2S_BASE+LPC17_40_I2S_TXRATE_OFFSET) +#define LPC17_40_I2S_RXRATE (LPC17_40_I2S_BASE+LPC17_40_I2S_RXRATE_OFFSET) +#define LPC17_40_I2S_TXBITRATE (LPC17_40_I2S_BASE+LPC17_40_I2S_TXBITRATE_OFFSET) +#define LPC17_40_I2S_RXBITRATE (LPC17_40_I2S_BASE+LPC17_40_I2S_RXBITRATE_OFFSET) +#define LPC17_40_I2S_TXMODE (LPC17_40_I2S_BASE+LPC17_40_I2S_TXMODE_OFFSET) +#define LPC17_40_I2S_RXMODE (LPC17_40_I2S_BASE+LPC17_40_I2S_RXMODE_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Digital Audio Output Register */ + +#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ +#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT) +#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */ +#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ +#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ +#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */ +#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ +#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT) +#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */ + /* Bits 16-31: Reserved */ +/* Digital Audio Input Register */ + +#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ +#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT) +#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */ +#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ +#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ +#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */ +#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ +#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT) + /* Bits 15-31: Reserved */ +/* Transmit FIFO: 8 � 32-bit transmit FIFO */ +/* Receive FIFO: 8 � 32-bit receive FIFO */ + +/* Status Feedback Register */ + +#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */ +#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */ +#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */ + /* Bits 3-7: Reserved */ +#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */ +#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */ +#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT) + /* Bits 20-31: Reserved */ +/* DMA Configuration Register 1 and 2 */ + +#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */ +#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */ + /* Bits 2-7: Reserved */ +#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */ +#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */ +#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT) + /* Bits 20-31: Reserved */ +/* Interrupt Request Control Register */ + +#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */ +#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */ + /* Bits 2-7: Reserved */ +#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */ +#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */ +#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT) + /* Bits 20-31: Reserved */ +/* Transmit and Receive MCLK divider */ + +#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */ +#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT) +#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */ +#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT) + /* Bits 16-31: Reserved */ + +/* Transmit and received bit rate divider */ + +#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */ +#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT) + /* Bits 6-31: Reserved */ +/* Transmit and Receive mode control */ + +#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */ +#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT) +# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */ +# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */ +# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */ +#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */ +#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2S_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h new file mode 100644 index 00000000000..9b895fc59ce --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h @@ -0,0 +1,346 @@ +/************************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_LCD_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_LCD_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define LPC17_40_LCD_TIMH_OFFSET (0x0000) /* Horizontal Timing Control register */ +#define LPC17_40_LCD_TIMV_OFFSET (0x0004) /* Vertical Timing Control register */ +#define LPC17_40_LCD_POL_OFFSET (0x0008) /* Clock & Signal Polarity Control register */ +#define LPC17_40_LCD_LE_OFFSET (0x000c) /* Line End Control register */ +#define LPC17_40_LCD_UPBASE_OFFSET (0x0010) /* Upper Panel Frame Base Address register */ +#define LPC17_40_LCD_LPBASE_OFFSET (0x0014) /* Lower Panel Frame Base Address register */ +#define LPC17_40_LCD_CTRL_OFFSET (0x0018) /* LCD Control register */ +#define LPC17_40_LCD_INTMSK_OFFSET (0x001c) /* Interrupt Mask register */ +#define LPC17_40_LCD_INTRAW_OFFSET (0x0020) /* Raw Interrupt Status register */ +#define LPC17_40_LCD_INTSTAT_OFFSET (0x0024) /* Masked Interrupt Status register */ +#define LPC17_40_LCD_INTCLR_OFFSET (0x0028) /* Interrupt Clear register */ +#define LPC17_40_LCD_UPCURR_OFFSET (0x002c) /* Upper Panel Current Address Value register */ +#define LPC17_40_LCD_LPCURR_OFFSET (0x0030) /* Lower Panel Current Address Value register */ + +/* 256x16-bit Color Palette registers, n=0-127 */ + +#define LPC17_40_LCD_PAL_OFFSET(n) (0x0200 + ((n) << 2)) + +/* Cursor Image registers, n=0-255 */ + +#define LPC17_40_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2)) + +#define LPC17_40_LCD_CRSR_CRTL_OFFSET (0x0c00) /* Cursor Control register */ +#define LPC17_40_LCD_CRSR_CFG_OFFSET (0x0c04) /* Cursor Configuration register */ +#define LPC17_40_LCD_CRSR_PAL0_OFFSET (0x0c08) /* Cursor Palette register 0 */ +#define LPC17_40_LCD_CRSR_PAL1_OFFSET (0x0c0c) /* Cursor Palette register 1 */ +#define LPC17_40_LCD_CRSR_XY_OFFSET (0x0c10) /* Cursor XY Position register */ +#define LPC17_40_LCD_CRSR_CLIP_OFFSET (0x0c14) /* Cursor Clip Position register */ +#define LPC17_40_LCD_CRSR_INTMSK_OFFSET (0x0c20) /* Cursor Interrupt Mask regsiter */ +#define LPC17_40_LCD_CRSR_INTCLR_OFFSET (0x0c24) /* Cursor Interrupt Clear register */ +#define LPC17_40_LCD_CRSR_INTRAW_OFFSET (0x0c28) /* Cursor Raw Interrupt Status register */ +#define LPC17_40_LCD_CRSR_INTSTAT_OFFSET (0x0c2c) /* Cursor Masked Interrupt Status register */ + +/* Register Addresses ***************************************************************************/ + +#define LPC17_40_LCD_TIMH (LPC17_40_LCD_BASE+LPC17_40_LCD_TIMH_OFFSET) +#define LPC17_40_LCD_TIMV (LPC17_40_LCD_BASE+LPC17_40_LCD_TIMV_OFFSET) +#define LPC17_40_LCD_POL (LPC17_40_LCD_BASE+LPC17_40_LCD_POL_OFFSET) +#define LPC17_40_LCD_LE (LPC17_40_LCD_BASE+LPC17_40_LCD_LE_OFFSET) +#define LPC17_40_LCD_UPBASE (LPC17_40_LCD_BASE+LPC17_40_LCD_UPBASE_OFFSET) +#define LPC17_40_LCD_LPBASE (LPC17_40_LCD_BASE+LPC17_40_LCD_LPBASE_OFFSET) +#define LPC17_40_LCD_CTRL (LPC17_40_LCD_BASE+LPC17_40_LCD_CTRL_OFFSET) +#define LPC17_40_LCD_INTMSK (LPC17_40_LCD_BASE+LPC17_40_LCD_INTMSK_OFFSET) +#define LPC17_40_LCD_INTRAW (LPC17_40_LCD_BASE+LPC17_40_LCD_INTRAW_OFFSET) +#define LPC17_40_LCD_INTSTAT (LPC17_40_LCD_BASE+LPC17_40_LCD_INTSTAT_OFFSET) +#define LPC17_40_LCD_INTCLR (LPC17_40_LCD_BASE+ LPC17_40_LCD_INTCLR_OFFSET) +#define LPC17_40_LCD_UPCURR (LPC17_40_LCD_BASE+LPC17_40_LCD_UPCURR_OFFSET) +#define LPC17_40_LCD_LPCURR (LPC17_40_LCD_BASE+LPC17_40_LCD_LPCURR_OFFSET) + +#define LPC17_40_LCD_PAL(n) (LPC17_40_LCD_BASE+LPC17_40_LCD_PAL_OFFSET(n)) +#define LPC17_40_LCD_CRSR_IMG(n) (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_IMG_OFFSET(n)) + +#define LPC17_40_LCD_CRSR_CRTL (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_CRTL_OFFSET) +#define LPC17_40_LCD_CRSR_CFG (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_CFG_OFFSET) +#define LPC17_40_LCD_CRSR_PAL0 (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_PAL0_OFFSET) +#define LPC17_40_LCD_CRSR_PAL1 (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_PAL1_OFFSET) +#define LPC17_40_LCD_CRSR_XY (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_XY_OFFSET) +#define LPC17_40_LCD_CRSR_CLIP (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_CLIP_OFFSET) +#define LPC17_40_LCD_CRSR_INTMSK (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_INTMSK_OFFSET) +#define LPC17_40_LCD_CRSR_INTCLR (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_INTCLR_OFFSET) +#define LPC17_40_LCD_CRSR_INTRAW (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_INTRAW_OFFSET) +#define LPC17_40_LCD_CRSR_INTSTAT (LPC17_40_LCD_BASE+LPC17_40_LCD_CRSR_INTSTAT_OFFSET) + +/* Register Bitfield Definitions ****************************************************************/ + +/* LCD_TIMH - Horizontal Timing Register */ + /* Bits 0-1: Reserved */ +#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */ +#define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT) +#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */ +#define LCD_TIMH_HWS_MASK (0xff << LCD_TIMH_HSW_SHIFT) +#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */ +#define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT) +#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */ +#define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT) + +/* LCD_TIMV - Vertical Timing Register */ + +#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/ +#define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT) +#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */ +#define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT) +#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */ +#define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT) +#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */ +#define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT) + +/* LCD_POL - Clock and Signal Polarity Register */ + +#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */ +#define LCD_POL_PCDLO_MASK (0x1f << LCD_POL_PCDLO_SHIFT) +#define LCD_POL_CLKSEL (1 << 5) /* Bit 5: Clock select- 0=PCLK, 1=LCD_CLKIN */ +#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ +#define LCD_POL_ACB_MASK (0x1f << LCD_POL_ACB_SHIFT) +#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical sync */ +#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal sync */ +#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */ +#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */ + /* Bit 15: Reserved */ +#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */ +#define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT) +#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */ +#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */ +#define LCD_POL_PCDHI_MASK (0x1f << LCD_POL_PCDHI_SHIFT) + +/* LCD_LE - Line End Control Register */ + +#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */ +#define LCD_LE_LED_MASK (0x7f << LCD_LE_LED_SHIFT) + /* Bits 7-15: Reserved */ +#define LCD_LE_LEE (1 << 16) /* Bit 16: LCD line end enable */ + /* Bit 17-31: Reserved */ +/* LCD_UPBASE - Upper Panel Frame Base Address Register */ + /* Bits 0-2: Reserved */ +#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */ +#define LCD_UPBASE_LCDUPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) + +/* LCD_UPBASE - Lower Panel Frame Base Address Register */ + /* Bits 0-2: Reserved */ +#define LCD_UPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */ +#define LCD_UPBASE_LCDLPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) + +/* LCD_CTRL - Controle Register */ + +#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */ +#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ +#define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT) +# define LCD_CTRL_LCDBPP_1 (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */ +# define LCD_CTRL_LCDBPP_2 (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */ +# define LCD_CTRL_LCDBPP_4 (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */ +# define LCD_CTRL_LCDBPP_8 (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */ +# define LCD_CTRL_LCDBPP_16 (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */ +# define LCD_CTRL_LCDBPP_24 (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */ +# define LCD_CTRL_LCDBPP_565 (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */ +# define LCD_CTRL_LCDBPP_444 (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */ +#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */ +#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD TFT type selection */ +#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface bit */ +#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */ +#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format */ +#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-Endian Byte Order */ +#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */ +#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD Power enable */ +#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */ +#define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT) + /* Bits 14-15: Reserved */ +#define LCD_CTRL_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */ + /* Bits 17-31: Reserved */ +/* LCD_INTMSK - Interrupt Mask Register */ + /* Bits 0: Reserved */ +#define LCD_INTMSK_FUFIM (1 << 1) /* Bit 1: FIFO underflow interrupt enable */ +#define LCD_INTMSK_LNBUIM (1 << 2) /* Bit 2: LCD next base address interrupt enable */ +#define LCD_INTMSK_VCOMPIM (1 << 3) /* Bit 3: Vertical compare interrupt enable */ +#define LCD_INTMSK_BERIM (1 << 4) /* Bit 4: AHB Master error interrupt enable */ + /* Bits 5-31: Reserved */ +#define LCD_INTMSK_ALL (0x1e) + +/* LCD_INTRAW - Raw Interrupt Status Register */ + /* Bits 0: Reserved */ +#define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 5-31: Reserved */ +#define LCD_INTRAW_ALL (0x1e) + +/* LCD_INTSTAT - Masked Interrupt Status Register */ + /* Bits 0: Reserved */ +#define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 15-31: Reserved */ +#define LCD_INTSTAT_ALL (0x1e) + +/* LCD_INTCLR - Interrupt Clear Register */ + /* Bits 0: Reserved */ +#define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt clear */ +#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ +#define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ + /* Bits 15-31: Reserved */ +#define LCD_INTCLR_ALL (0x1e) + +/* Upper and Lower Panel Address register has no bitfields */ +/* + * Upper Panel Current Address register (LCDUPCURR) + * Lower Panel Current Address register (LCDLPCURR) + */ + +/* LCD_PAL - Color Palette Registers */ + +#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */ +#define LCD_PAL_R0_MASK (0x1f << LCD_PAL_R0_SHIFT) +#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */ +#define LCD_PAL_G0_MASK (0x1f << LCD_PAL_G0_SHIFT) +#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue paletted data */ +#define LCD_PAL_B0_MASK (0x1f << LCD_PAL_B0_SHIFT) +#define LCD_PAL_I0 (1 << 15) /* Bit 15: Intensity/Unused bit */ +#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */ +#define LCD_PAL_R1_MASK (0x1f << LCD_PAL_R1_SHIFT) +#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */ +#define LCD_PAL_G1_MASK (0x1f << LCD_PAL_G1_SHIFT) +#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */ +#define LCD_PAL_B1_MASK (0x1f << LCD_PAL_B1_SHIFT) +#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity/Unused bit */ + +/* LCD_CRSR_IMG - Cursor Image Register - has no bitfields */ +/* The 256 words of the cursor image register defines the appearance + * of either one 64x64 cursor, or 4 32x32 cursors. + */ + +/* LCD CRSR_CTRL - Cursor Control Register */ + +#define LCD_CRSR_CTRL_CRSON (1 << 0) /* Bit 0: Cursor enable */ + /* Bits 1-3: Reserved */ +#define LCD_CRSR_CTRL_CRSRNUM_SHIFT (4) /* Bits 4-5: Cursor image number */ +#define LCD_CRSR_CTRL_CRSRNUM_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT) + /* Bits 6-31: Reserved */ +/* If the selected cursor is 32x32 */ + +#define LCD_CURSOR0 (0) +#define LCD_CURSOR1 (1) +#define LCD_CURSOR2 (2) +#define LCD_CURSOR3 (3) + +/* LCD CRSR_CFG - Cursor Configuration Register */ + +#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */ +#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame sync type */ + /* Bits 2-31: Reserved */ + +#define LCD_CURSOR_SIZE32 (0) /* 32x32 */ +#define LCD_CURSOR_SIZE64 (1) /* 64x64 */ +#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */ +#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */ + +/* LCD CRSR_PAL0/1 - Cursor Palette Registers */ + +#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ +#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) +#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ +#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) +#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ +#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT) + /* Bits 24-31: Reserved */ +/* LCD CRSR_XY - Cursor XY Position Register */ + +#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */ +#define LCD_CRSR_CRSRX_MASK (0x3ff << LCD_CRSR_CRSRX_SHIFT) + /* Bits 10-15: Reserved */ +#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */ +#define LCD_CRSR_CRSRY_MASK (0x3ff << LCD_CRSR_CRSRY_SHIFT) + /* Bits 26-31: Reserved */ +/* LCD CRSR_CLIP - Cursor Clip Position Register */ + +#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */ +#define LCD_CRSR_CRSRCLIPX_MASK (0x3f << LCD_CRSR_CRSRCLIPX_SHIFT) + /* Bits 6-7: Reserved */ +#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */ +#define LCD_CRSR_CRSRCLIPY_MASK (0x3f << LCD_CRSR_CRSRCLIPY_SHIFT) + /* Bits 14-31: Reserved */ +/* LCD CRSR_INTMSK - Cursor Interrrupt Mask Register */ + +#define LCD_CRSR_INTMSK_CRSRIM (1 << 0) /* Bit 0: Cursor interrupt mask */ + /* Bits 1-31: Reserved */ +/* LCD CRSR_INTCLR - Cursor Interrrupt Clear Register */ + +#define LCD_CRSR_INTCLR_CRSRIC (1 << 0) /* Bit 0: Cursor interrupt clear */ + /* Bits 1-31: Reserved */ + +/* LCD CRSR_INTRAW - Cursor Raw Interrrupt Status Register */ + +#define LCD_CRSR_INTRAW_CRSRRIS (1 << 0) /* Bit 0: Cursor raw interrupt status */ + /* Bits 1-31: Reserved */ +/* LCD CRSR_INTSTAT - Mask Interrrupt Status Register */ + +#define LCD_CRSR_INTSTAT_CRSRMIS (1 << 0) /* Bit 0: Cursor mask interrupt status */ + /* Bits 1-31: Reserved */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_LCD_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_mcpwm.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_mcpwm.h new file mode 100644 index 00000000000..2d6646d1491 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_mcpwm.h @@ -0,0 +1,280 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_mcpwm.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_MCPWM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_MCPWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ +#define LPC17_40_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ +#define LPC17_40_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ +#define LPC17_40_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ +#define LPC17_40_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ +#define LPC17_40_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ +#define LPC17_40_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ +#define LPC17_40_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ +#define LPC17_40_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ +#define LPC17_40_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ +#define LPC17_40_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ +#define LPC17_40_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ +#define LPC17_40_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ +#define LPC17_40_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ +#define LPC17_40_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ +#define LPC17_40_MCPWM_DT_OFFSET 0x003c /* Dead time register */ +#define LPC17_40_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ +#define LPC17_40_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ +#define LPC17_40_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ +#define LPC17_40_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ +#define LPC17_40_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ +#define LPC17_40_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ +#define LPC17_40_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ +#define LPC17_40_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ +#define LPC17_40_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ +#define LPC17_40_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ +#define LPC17_40_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ +#define LPC17_40_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ +#define LPC17_40_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ +#define LPC17_40_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_MCPWM_CON (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CON_OFFSET) +#define LPC17_40_MCPWM_CONSET (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CONSET_OFFSET) +#define LPC17_40_MCPWM_CONCLR (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CONCLR_OFFSET) +#define LPC17_40_MCPWM_CAPCON (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAPCON_OFFSET) +#define LPC17_40_MCPWM_CAPCONSET (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAPCONSET_OFFSET) +#define LPC17_40_MCPWM_CAPCONCLR (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAPCONCLR_OFFSET) +#define LPC17_40_MCPWM_TC0 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_TC0_OFFSET) +#define LPC17_40_MCPWM_TC1 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_TC1_OFFSET) +#define LPC17_40_MCPWM_TC2 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_TC2_OFFSET) +#define LPC17_40_MCPWM_LIM0 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_LIM0_OFFSET) +#define LPC17_40_MCPWM_LIM1 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_LIM1_OFFSET) +#define LPC17_40_MCPWM_LIM2 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_LIM2_OFFSET) +#define LPC17_40_MCPWM_MAT0 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_MAT0_OFFSET) +#define LPC17_40_MCPWM_MAT1 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_MAT1_OFFSET) +#define LPC17_40_MCPWM_MAT2 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_MAT2_OFFSET) +#define LPC17_40_MCPWM_DT (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_DT_OFFSET) +#define LPC17_40_MCPWM_CP (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CP_OFFSET) +#define LPC17_40_MCPWM_CAP0 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAP0_OFFSET) +#define LPC17_40_MCPWM_CAP1 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAP1_OFFSET) +#define LPC17_40_MCPWM_CAP2 (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAP2_OFFSET) +#define LPC17_40_MCPWM_INTEN (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_INTEN_OFFSET) +#define LPC17_40_MCPWM_INTENSET (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_INTENSET_OFFSET) +#define LPC17_40_MCPWM_INTENCLR (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_INTENCLR_OFFSET) +#define LPC17_40_MCPWM_CNTCON (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CNTCON_OFFSET) +#define LPC17_40_MCPWM_CNTCONSET (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CNTCONSET_OFFSET) +#define LPC17_40_MCPWM_CNTCONCLR (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CNTCONCLR_OFFSET) +#define LPC17_40_MCPWM_INTF (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_INTF_OFFSET) +#define LPC17_40_MCPWM_INTFSET (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_INTFSET_OFFSET) +#define LPC17_40_MCPWM_INTFCLR (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_INTFCLR_OFFSET) +#define LPC17_40_MCPWM_CAPCLR (LPC17_40_MCPWM_BASE+LPC17_40_MCPWM_CAPCLR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* There are no bit field definitions for the following registers because they support + * 32-bit values: + * + * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), + * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for + * channels 0, 1, 2 (no bit field definitions) + * + * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit + * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field + * definitions) + * + * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match + * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field + * definitions). + * + * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and + * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for + * channels 0, 1, 2 (no bit field definitions) + */ + +/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control + * clear address (CONCLR) common regiser bit definitions. + */ + +#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ +#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ +#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ +#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ +#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ + /* Bits 5-7: Reserved */ +#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ +#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ +#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ +#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ + /* Bits 13-15: Reserved */ +#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ +#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ +#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ +#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ + /* Bits 21-28: Reserved */ +#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ +#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ +#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ + +/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), + * and Event Control clear address (CAPCONCLR) common register bit defintions + */ + +#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ +#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ +#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ +#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ +#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ + /* Bits 24-31: Reserved */ +/* Dead time register */ + +#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ +#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) +#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ +#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) +#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ +#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) + /* Bits 30-31: reserved */ +/* Commutation Pattern register */ + +#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ +#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ + /* Bits 6-31: reserved */ + +/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), + * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), + * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) + * common bit field definitions + */ + +#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ +#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ +#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ + /* Bit 3: Reserved */ +#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ +#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ +#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ + /* Bit 7: Reserved */ +#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ +#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ +#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ + /* Bits 11-14: Reserved */ +#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ + /* Bits 16-31: Reserved */ + +/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and + * Count Control clear address (CNTCONCLR) common register bit definitions. + */ + +#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ + /* Bits 28-28: Reserved */ +#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ +#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ +#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ + +/* Capture clear address */ + +#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ +#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ +#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_MCPWM_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_memorymap.h similarity index 86% rename from arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_memorymap.h index 54dcc06b75e..cb90225d74b 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_memorymap.h * * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_MEMORYMAP_H /************************************************************************************ * Included Files @@ -43,17 +43,17 @@ #include /* This file is only a thin shell that includes the correct memory map definitions - * for the selected LPC17xx family. + * for the selected LPC17xx/LPC40xx family. */ -#include +#include #if defined(LPC176x) # include "hardware/lpc176x_memorymap.h" -#elif defined(LPC178x) -# include "hardware/lpc178x_memorymap.h" +#elif defined(LPC178x_40xx) +# include "hardware/lpc178x_40xx_memorymap.h" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /************************************************************************************ @@ -72,4 +72,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconfig.h similarity index 86% rename from arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconfig.h index 39a9fe09082..cf530596684 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconfig.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconfig.h * * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONFIG_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONFIG_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PINCONFIG_H /************************************************************************************ * Included Files @@ -43,17 +43,17 @@ #include /* This file is only a thin shell that includes the correct pin configuration - * definitions for the selected LPC17xx family. + * definitions for the selected LPC17xx/LPC40xx family. */ -#include +#include #if defined(LPC176x) # include "hardware/lpc176x_pinconfig.h" -#elif defined(LPC178x) -# include "hardware/lpc178x_pinconfig.h" +#elif defined(LPC178x_40xx) +# include "hardware/lpc178x_40xx_pinconfig.h" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /************************************************************************************ @@ -72,4 +72,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONFIG_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PINCONFIG_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconn.h similarity index 86% rename from arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconn.h index f9f46dfb5f4..a36c3b60d0d 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconn.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pinconn.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONN_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONN_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PINCONN_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PINCONN_H /************************************************************************************ * Included Files @@ -43,17 +43,17 @@ #include /* This file is only a thin shell that includes the correct pin configuration - * register definitions for the selected LPC17xx family. + * register definitions for the selected LPC17xx/LPC40xx family. */ -#include +#include #if defined(LPC176x) # include "hardware/lpc176x_pinconn.h" -#elif defined(LPC178x) -# include "hardware/lpc178x_iocon.h" +#elif defined(LPC178x_40xx) +# include "hardware/lpc178x_40xx_iocon.h" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /************************************************************************************ @@ -72,4 +72,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONN_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PINCONN_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pwm.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pwm.h new file mode 100644 index 00000000000..14e59cf3f66 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pwm.h @@ -0,0 +1,223 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_pwm.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PWM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_PWM_IR_OFFSET 0x0000 /* Interrupt Register */ +#define LPC17_40_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */ +#define LPC17_40_PWM_TC_OFFSET 0x0008 /* Timer Counter */ +#define LPC17_40_PWM_PR_OFFSET 0x000c /* Prescale Register */ +#define LPC17_40_PWM_PC_OFFSET 0x0010 /* Prescale Counter */ +#define LPC17_40_PWM_MCR_OFFSET 0x0014 /* Match Control Register */ +#define LPC17_40_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */ +#define LPC17_40_PWM_MR1_OFFSET 0x001c /* Match Register 1 */ +#define LPC17_40_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */ +#define LPC17_40_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */ +#define LPC17_40_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */ +#define LPC17_40_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */ +#define LPC17_40_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */ +#define LPC17_40_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */ +#define LPC17_40_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */ +#define LPC17_40_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */ +#define LPC17_40_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */ +#define LPC17_40_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */ +#define LPC17_40_PWM_PCR_OFFSET 0x004c /* PWM Control Register */ +#define LPC17_40_PWM_LER_OFFSET 0x0050 /* Load Enable Register */ +#define LPC17_40_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_PWM1_IR (LPC17_40_PWM1_BASE+LPC17_40_PWM_IR_OFFSET) +#define LPC17_40_PWM1_TCR (LPC17_40_PWM1_BASE+LPC17_40_PWM_TCR_OFFSET) +#define LPC17_40_PWM1_TC (LPC17_40_PWM1_BASE+LPC17_40_PWM_TC_OFFSET) +#define LPC17_40_PWM1_PR (LPC17_40_PWM1_BASE+LPC17_40_PWM_PR_OFFSET) +#define LPC17_40_PWM1_PC (LPC17_40_PWM1_BASE+LPC17_40_PWM_PC_OFFSET) +#define LPC17_40_PWM1_MCR (LPC17_40_PWM1_BASE+LPC17_40_PWM_MCR_OFFSET) +#define LPC17_40_PWM1_MR0 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR0_OFFSET) +#define LPC17_40_PWM1_MR1 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR1_OFFSET) +#define LPC17_40_PWM1_MR2 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR2_OFFSET) +#define LPC17_40_PWM1_MR3 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR3_OFFSET) +#define LPC17_40_PWM1_MR4 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR4_OFFSET) +#define LPC17_40_PWM1_MR5 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR5_OFFSET) +#define LPC17_40_PWM1_MR6 (LPC17_40_PWM1_BASE+LPC17_40_PWM_MR6_OFFSET) +#define LPC17_40_PWM1_CCR (LPC17_40_PWM1_BASE+LPC17_40_PWM_CCR_OFFSET) +#define LPC17_40_PWM1_CR0 (LPC17_40_PWM1_BASE+LPC17_40_PWM_CR0_OFFSET) +#define LPC17_40_PWM1_CR1 (LPC17_40_PWM1_BASE+LPC17_40_PWM_CR1_OFFSET) +#define LPC17_40_PWM1_CR2 (LPC17_40_PWM1_BASE+LPC17_40_PWM_CR2_OFFSET) +#define LPC17_40_PWM1_CR3 (LPC17_40_PWM1_BASE+LPC17_40_PWM_CR3_OFFSET) +#define LPC17_40_PWM1_PCR (LPC17_40_PWM1_BASE+LPC17_40_PWM_PCR_OFFSET) +#define LPC17_40_PWM1_LER (LPC17_40_PWM1_BASE+LPC17_40_PWM_LER_OFFSET) +#define LPC17_40_PWM1_CTCR (LPC17_40_PWM1_BASE+LPC17_40_PWM_CTCR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Registers holding 32-bit numeric values (no bit field definitions): + * + * Timer Counter (TC) + * Prescale Register (PR) + * Prescale Counter (PC) + * Match Register 0 (MR0) + * Match Register 1 (MR1) + * Match Register 2 (MR2) + * Match Register 3 (MR3) + * Match Register 4 (MR3) + * Match Register 5 (MR3) + * Match Register 6 (MR3) + * Capture Register 0 (CR0) + * Capture Register 1 (CR1) + * Capture Register 1 (CR2) + * Capture Register 1 (CR3) + */ + +/* Interrupt Register */ + +#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrupt */ +#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrupt */ +#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrupt */ +#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrupt */ +#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrupt */ +#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrupt */ + /* Bits 6-7: Reserved */ +#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrupt */ +#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrupt */ +#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrupt */ + /* Bits 11-31: Reserved */ +/* Timer Control Register */ + +#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */ +#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */ + /* Bit 2: Reserved */ +#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */ + /* Bits 4-31: Reserved */ +/* Match Control Register */ + +#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ +#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ +#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ +#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ +#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ +#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ +#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ +#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ +#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ +#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ +#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ +#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ +#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */ +#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */ +#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */ +#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */ +#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/ +#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */ +#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */ +#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */ +#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */ + /* Bits 21-31: Reserved */ +/* Capture Control Register (Where are CAP2 and 3?) */ + +#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ +#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */ +#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ +#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ +#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */ +#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ + /* Bits 6-31: Reserved */ +/* PWM Control Register */ + /* Bits 0-1: Reserved */ +#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */ +#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */ +#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */ +#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */ +#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */ + /* Bits 7-8: Reserved */ +#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */ +#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */ +#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */ +#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */ +#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */ +#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */ + /* Bits 15-31: Reserved */ +/* Load Enable Register */ + +#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */ +#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */ +#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */ +#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */ +#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */ +#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */ +#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */ + /* Bits 7-31: Reserved */ +/* Counter/Timer Control Register */ + +#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ +#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT) +# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */ +# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ +# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ +# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ +#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ +#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT) +# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ +# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_PWM_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_qei.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_qei.h new file mode 100644 index 00000000000..7f2db27b036 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_qei.h @@ -0,0 +1,214 @@ +/******************************************************************************************** + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_qei.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_QEI_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_QEI_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register offsets *************************************************************************/ +/* Control registers */ + +#define LPC17_40_QEI_CON_OFFSET 0x0000 /* Control register */ +#define LPC17_40_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ +#define LPC17_40_QEI_CONF_OFFSET 0x0008 /* Configuration register */ + +/* Position, index, and timer registers */ + +#define LPC17_40_QEI_POS_OFFSET 0x000c /* Position register */ +#define LPC17_40_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ +#define LPC17_40_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ +#define LPC17_40_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ +#define LPC17_40_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ +#define LPC17_40_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ +#define LPC17_40_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ +#define LPC17_40_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ +#define LPC17_40_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ +#define LPC17_40_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ +#define LPC17_40_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ +#define LPC17_40_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ +#define LPC17_40_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ + +#ifdef LPC178 +# define LPC17_40_QEI_INXCMP0_OFFSET 0x0024 /* Index compare0 register */ +# define LPC17_40_QEI_INXCMP1_OFFSET 0x004c /* Index compare1 register */ +# define LPC17_40_QEI_INXCMP2_OFFSET 0x0050 /* Index compare2 register */ +# define LPC17_40_QEI_FILTER_PHA_OFFSET 0x003c /* Digital filter register */ +# define LPC17_40_QEI_FILTER_PHB_OFFSET 0x0040 /* Digital filter register */ +# define LPC17_40_QEI_FILTER_INX_OFFSET 0x0044 /* Digital filter register */ +# define LPC17_40_QEI_WINDOW_OFFSET 0x0048 /* Index acceptance register */ +#endif + +/* Interrupt registers */ + +#define LPC17_40_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ +#define LPC17_40_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ +#define LPC17_40_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_40_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_40_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ +#define LPC17_40_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ + +/* Register addresses ***********************************************************************/ +/* Control registers */ + +#define LPC17_40_QEI_CON (LPC17_40_QEI_BASE+LPC17_40_QEI_CON_OFFSET) +#define LPC17_40_QEI_STAT (LPC17_40_QEI_BASE+LPC17_40_QEI_STAT_OFFSET) +#define LPC17_40_QEI_CONF (LPC17_40_QEI_BASE+LPC17_40_QEI_CONF_OFFSET) + +/* Position, index, and timer registers */ + +#define LPC17_40_QEI_POS (LPC17_40_QEI_BASE+LPC17_40_QEI_POS_OFFSET) +#define LPC17_40_QEI_MAXPOS (LPC17_40_QEI_BASE+LPC17_40_QEI_MAXPOS_OFFSET) +#define LPC17_40_QEI_CMPOS0 (LPC17_40_QEI_BASE+LPC17_40_QEI_CMPOS0_OFFSET) +#define LPC17_40_QEI_CMPOS1 (LPC17_40_QEI_BASE+LPC17_40_QEI_CMPOS1_OFFSET) +#define LPC17_40_QEI_CMPOS2 (LPC17_40_QEI_BASE+LPC17_40_QEI_CMPOS2_OFFSET) +#define LPC17_40_QEI_INXCNT (LPC17_40_QEI_BASE+LPC17_40_QEI_INXCNT_OFFSET) +#define LPC17_40_QEI_INXCMP (LPC17_40_QEI_BASE+LPC17_40_QEI_INXCMP_OFFSET) +#define LPC17_40_QEI_LOAD (LPC17_40_QEI_BASE+LPC17_40_QEI_LOAD_OFFSET) +#define LPC17_40_QEI_TIME (LPC17_40_QEI_BASE+LPC17_40_QEI_TIME_OFFSET) +#define LPC17_40_QEI_VEL (LPC17_40_QEI_BASE+LPC17_40_QEI_VEL_OFFSET) +#define LPC17_40_QEI_CAP (LPC17_40_QEI_BASE+LPC17_40_QEI_CAP_OFFSET) +#define LPC17_40_QEI_VELCOMP (LPC17_40_QEI_BASE+LPC17_40_QEI_VELCOMP_OFFSET) +#define LPC17_40_QEI_FILTER (LPC17_40_QEI_BASE+LPC17_40_QEI_FILTER_OFFSET) + +/* Interrupt registers */ + +#define LPC17_40_QEI_IEC (LPC17_40_QEI_BASE+LPC17_40_QEI_IEC_OFFSET) +#define LPC17_40_QEI_IES (LPC17_40_QEI_BASE+LPC17_40_QEI_IES_OFFSET) +#define LPC17_40_QEI_INTSTAT (LPC17_40_QEI_BASE+LPC17_40_QEI_INTSTAT_OFFSET) +#define LPC17_40_QEI_IE (LPC17_40_QEI_BASE+LPC17_40_QEI_IE_OFFSET) +#define LPC17_40_QEI_CLR (LPC17_40_QEI_BASE+LPC17_40_QEI_CLR_OFFSET) +#define LPC17_40_QEI_SET (LPC17_40_QEI_BASE+LPC17_40_QEI_SET_OFFSET) + +/* Register bit definitions *****************************************************************/ +/* The following registers hold 32-bit integer values and have no bit fields defined + * in this section: + * + * Position register (POS) + * Maximum position register (MAXPOS) + * Position compare register 0 (CMPOS0) + * Position compare register 1 (CMPOS) + * Position compare register 2 (CMPOS2) + * Index count register (INXCNT) + * Index compare register (INXCMP) + * Velocity timer reload register (LOAD) + * Velocity timer register (TIME) + * Velocity counter register (VEL) + * Velocity capture register (CAP) + * Velocity compare register (VELCOMP) + * Digital filter register (FILTER) + */ + +/* Control registers */ +/* Control register */ + +#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ +#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ +#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ +#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ + /* Bits 4-31: reserved */ +/* Encoder status register */ + +#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ + /* Bits 1-31: reserved */ +/* Configuration register */ + +#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ +#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ +#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ +#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ + +#ifdef LPC178x_40xx +# define QEI_CONF_CRESPI (1 << 4) /* Bit 4: Continuous Index reset */ + /* Bits 5-15: reserved */ +# define QEI_CONF_INXGATE_SHIFT (16) /* Bit 16:19 Index Gating */ +# define QEI_CONF_INXGATE_MASK (15 << QEI_CONF_INXGATE_SHIFT) +#endif + /* Bits 20-31: reserved */ + +/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ + +/* Interrupt registers */ +/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), + * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt + * status clear register (CLR), and Interrupt status set register (SET) common + * bit definitions. + */ + +#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ +#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ +#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ +#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ +#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ +#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ +#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ +#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ +#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ +#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ +#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ +#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ +#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ + +#ifdef LPC178x_40xx +# define QEI_INT_REV1 (1 << 13) /* Bit 13: Index compare1 value to current index interrupt */ +# define QEI_INT_REV2 (1 << 14) /* Bit 14: Index compare2 value to current index interrupt */ +# define QEI_INT_MAXPOS (1 << 15) /* Bit 15: Current position count interrupt */ +#endif + /* Bits 16-31: reserved */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_QEI_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_rit.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rit.h similarity index 72% rename from arch/arm/src/lpc17xx/hardware/lpc17_rit.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rit.h index 7ddf129e922..3b8e5249038 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_rit.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rit.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_rit.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rit.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RIT_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RIT_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RIT_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RIT_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "hardware/lpc17_memorymap.h" +#include "hardware/lpc17_40_memorymap.h" /************************************************************************************ * Pre-processor Definitions @@ -51,17 +51,17 @@ /* Register offsets *****************************************************************/ -#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ -#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */ -#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */ -#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ +#define LPC17_40_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ +#define LPC17_40_RIT_MASK_OFFSET 0x0004 /* Mask register */ +#define LPC17_40_RIT_CTRL_OFFSET 0x0008 /* Control register */ +#define LPC17_40_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ /* Register addresses ***************************************************************/ -#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET) -#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET) -#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET) -#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET) +#define LPC17_40_RIT_COMPVAL (LPC17_40_RIT_BASE+LPC17_40_RIT_COMPVAL_OFFSET) +#define LPC17_40_RIT_MASK (LPC17_40_RIT_BASE+LPC17_40_RIT_MASK_OFFSET) +#define LPC17_40_RIT_CTRL (LPC17_40_RIT_BASE+LPC17_40_RIT_CTRL_OFFSET) +#define LPC17_40_RIT_COUNTER (LPC17_40_RIT_BASE+LPC17_40_RIT_COUNTER_OFFSET) /* Register bit definitions *********************************************************/ /* Compare register (Bits 0-31: value compared to the counter) */ @@ -70,11 +70,11 @@ /* Control register */ -#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ -#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ -#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ -#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ - /* Bits 4-31: Reserved */ +#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ +#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ +#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ +#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ + /* Bits 4-31: Reserved */ /* 32-bit counter (Bits 0-31: 32-bit up counter) */ /************************************************************************************ @@ -89,4 +89,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RIT_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RIT_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtc.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtc.h new file mode 100644 index 00000000000..ce42c039b35 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtc.h @@ -0,0 +1,277 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtc.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RTC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Miscellaneous registers */ + +#define LPC17_40_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */ +#define LPC17_40_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */ +#define LPC17_40_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */ +#define LPC17_40_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */ +#define LPC17_40_RTC_AUXEN_OFFSET 0x0058 /* RTC Auxiliary Enable register */ +#define LPC17_40_RTC_AUX_OFFSET 0x005c /* RTC Auxiliary control register */ + +/* Consolidated time registers */ + +#define LPC17_40_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */ +#define LPC17_40_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */ +#define LPC17_40_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */ + +/* Time counter registers */ + +#define LPC17_40_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */ +#define LPC17_40_RTC_MIN_OFFSET 0x0024 /* Minutes Register */ +#define LPC17_40_RTC_HOUR_OFFSET 0x0028 /* Hours Register */ +#define LPC17_40_RTC_DOM_OFFSET 0x002c /* Day of Month Register */ +#define LPC17_40_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */ +#define LPC17_40_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */ +#define LPC17_40_RTC_MONTH_OFFSET 0x0038 /* Months Register */ +#define LPC17_40_RTC_YEAR_OFFSET 0x003c /* Years Register */ +#define LPC17_40_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */ + +/* General purpose registers */ + +#define LPC17_40_RTC_GPREG0_OFFSET 0x0044 /* General Purpose Register 0 */ +#define LPC17_40_RTC_GPREG1_OFFSET 0x0048 /* General Purpose Register 1 */ +#define LPC17_40_RTC_GPREG2_OFFSET 0x004c /* General Purpose Register 2 */ +#define LPC17_40_RTC_GPREG3_OFFSET 0x0050 /* General Purpose Register 3 */ +#define LPC17_40_RTC_GPREG4_OFFSET 0x0054 /* General Purpose Register 4 */ + +/* Alarm register group */ + +#define LPC17_40_RTC_ALSEC_OFFSET 0x0060 /* Alarm value for Seconds */ +#define LPC17_40_RTC_ALMIN_OFFSET 0x0064 /* Alarm value for Minutes */ +#define LPC17_40_RTC_ALHOUR_OFFSET 0x0068 /* Alarm value for Hours */ +#define LPC17_40_RTC_ALDOM_OFFSET 0x006c /* Alarm value for Day of Month */ +#define LPC17_40_RTC_ALDOW_OFFSET 0x0070 /* Alarm value for Day of Week */ +#define LPC17_40_RTC_ALDOY_OFFSET 0x0074 /* Alarm value for Day of Year */ +#define LPC17_40_RTC_ALMON_OFFSET 0x0078 /* Alarm value for Months */ +#define LPC17_40_RTC_ALYEAR_OFFSET 0x007c /* Alarm value for Year */ + +/* Register addresses ***************************************************************/ +/* Miscellaneous registers */ + +#define LPC17_40_RTC_ILR (LPC17_40_RTC_BASE+LPC17_40_RTC_ILR_OFFSET) +#define LPC17_40_RTC_CCR (LPC17_40_RTC_BASE+LPC17_40_RTC_CCR_OFFSET) +#define LPC17_40_RTC_CIIR (LPC17_40_RTC_BASE+LPC17_40_RTC_CIIR_OFFSET) +#define LPC17_40_RTC_AMR (LPC17_40_RTC_BASE+LPC17_40_RTC_AMR_OFFSET) +#define LPC17_40_RTC_AUXEN (LPC17_40_RTC_BASE+LPC17_40_RTC_AUXEN_OFFSET) +#define LPC17_40_RTC_AUX (LPC17_40_RTC_BASE+LPC17_40_RTC_AUX_OFFSET) + +/* Consolidated time registers */ + +#define LPC17_40_RTC_CTIME0 (LPC17_40_RTC_BASE+LPC17_40_RTC_CTIME0_OFFSET) +#define LPC17_40_RTC_CTIME1 (LPC17_40_RTC_BASE+LPC17_40_RTC_CTIME1_OFFSET) +#define LPC17_40_RTC_CTIME2 (LPC17_40_RTC_BASE+LPC17_40_RTC_CTIME2_OFFSET) + +/* Time counter registers */ + +#define LPC17_40_RTC_SEC (LPC17_40_RTC_BASE+LPC17_40_RTC_SEC_OFFSET) +#define LPC17_40_RTC_MIN (LPC17_40_RTC_BASE+LPC17_40_RTC_MIN_OFFSET) +#define LPC17_40_RTC_HOUR (LPC17_40_RTC_BASE+LPC17_40_RTC_HOUR_OFFSET) +#define LPC17_40_RTC_DOM (LPC17_40_RTC_BASE+LPC17_40_RTC_DOM_OFFSET) +#define LPC17_40_RTC_DOW (LPC17_40_RTC_BASE+LPC17_40_RTC_DOW_OFFSET) +#define LPC17_40_RTC_DOY (LPC17_40_RTC_BASE+LPC17_40_RTC_DOY_OFFSET) +#define LPC17_40_RTC_MONTH (LPC17_40_RTC_BASE+LPC17_40_RTC_MONTH_OFFSET) +#define LPC17_40_RTC_YEAR (LPC17_40_RTC_BASE+LPC17_40_RTC_YEAR_OFFSET) +#define LPC17_40_RTC_CALIB (LPC17_40_RTC_BASE+LPC17_40_RTC_CALIB_OFFSET) + +/* General purpose registers */ + +#define LPC17_40_RTC_GPREG0 (LPC17_40_RTC_BASE+LPC17_40_RTC_GPREG0_OFFSET) +#define LPC17_40_RTC_GPREG1 (LPC17_40_RTC_BASE+LPC17_40_RTC_GPREG1_OFFSET) +#define LPC17_40_RTC_GPREG2 (LPC17_40_RTC_BASE+LPC17_40_RTC_GPREG2_OFFSET) +#define LPC17_40_RTC_GPREG3 (LPC17_40_RTC_BASE+LPC17_40_RTC_GPREG3_OFFSET) +#define LPC17_40_RTC_GPREG4 (LPC17_40_RTC_BASE+LPC17_40_RTC_GPREG4_OFFSET) + +/* Alarm register group */ + +#define LPC17_40_RTC_ALSEC (LPC17_40_RTC_BASE+LPC17_40_RTC_ALSEC_OFFSET) +#define LPC17_40_RTC_ALMIN (LPC17_40_RTC_BASE+LPC17_40_RTC_ALMIN_OFFSET) +#define LPC17_40_RTC_ALHOUR (LPC17_40_RTC_BASE+LPC17_40_RTC_ALHOUR_OFFSET) +#define LPC17_40_RTC_ALDOM (LPC17_40_RTC_BASE+LPC17_40_RTC_ALDOM_OFFSET) +#define LPC17_40_RTC_ALDOW (LPC17_40_RTC_BASE+LPC17_40_RTC_ALDOW_OFFSET) +#define LPC17_40_RTC_ALDOY (LPC17_40_RTC_BASE+LPC17_40_RTC_ALDOY_OFFSET) +#define LPC17_40_RTC_ALMON (LPC17_40_RTC_BASE+LPC17_40_RTC_ALMON_OFFSET) +#define LPC17_40_RTC_ALYEAR (LPC17_40_RTC_BASE+LPC17_40_RTC_ALYEAR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* The following registers hold 32-bit values and have no bit fields to be defined: + * + * General Purpose Register 0 + * General Purpose Register 1 + * General Purpose Register 2 + * General Purpose Register 3 + * General Purpose Register 4 + */ + +/* Miscellaneous registers */ +/* Interrupt Location Register */ + +#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */ +#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */ + /* Bits 2-31: Reserved */ +/* Clock Control Register */ + +#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */ +#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */ + /* Bits 2-3: Internal test mode controls */ +#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */ + /* Bits 5-31: Reserved */ +/* Counter Increment Interrupt Register */ + +#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */ +#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */ +#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */ +#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */ +#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */ +#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */ +#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */ +#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */ + /* Bits 8-31: Reserved */ +/* Alarm Mask Register */ + +#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */ +#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */ +#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */ +#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */ +#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */ +#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */ +#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */ +#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */ + /* Bits 8-31: Reserved */ + +/* RTC Auxiliary Control Register */ + /* Bits 0-3: Reserved */ +#define RTC_AUXEN_RTCOSCF (1 << 4) /* Bit 4: RTC Oscillator Fail detect flag */ +#ifdef LPC178x_40xx + /* Bit 5: Reserved */ +# define RTC_AUXEN_RTCPDOUT (1 << 6) /* Bit 6: RTC power down mode flag */ + /* Bits 7-31: Reserved */ +#endif + +/* RTC Auxiliary Enable Register */ + /* Bits 0-3: Reserved */ +#define RTC_AUX_OSCFEN (1 << 4) /* Bit 4: Oscillator Fail Detect interrupt enable */ + /* Bits 5-31: Reserved */ + +/* Consolidated Time Registers */ +/* Consolidated Time Register 0 */ + +#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */ +#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT) + /* Bits 6-7: Reserved */ +#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */ +#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT) + /* Bits 14-15: Reserved */ +#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */ +#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT) + /* Bits 21-23: Reserved */ +#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */ +#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT) + /* Bits 27-31: Reserved */ +/* Consolidated Time Register 1 */ + +#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */ +#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT) + /* Bits 5-7: Reserved */ +#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */ +#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT) + /* Bits 12-15: Reserved */ +#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */ +#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT) + /* Bits 28-31: Reserved */ +/* Consolidated Time Register 2 */ + +#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */ +#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT) + /* Bits 12-31: Reserved */ +/* Time counter registers */ + +#define RTC_SEC_MASK (0x003f) +#define RTC_MIN_MASK (0x003f) +#define RTC_HOUR_MASK (0x001f) +#define RTC_DOM_MASK (0x001f) +#define RTC_DOW_MASK (0x0007) +#define RTC_DOY_MASK (0x01ff) +#define RTC_MONTH_MASK (0x000f) +#define RTC_YEAR_MASK (0x0fff) + +/* Calibration Value Register */ + +#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */ +#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT) +#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */ + /* Bits 18-31: Reserved */ +/* Alarm register group */ + +#define RTC_ALSEC_MASK (0x003f) +#define RTC_ALMIN_MASK (0x003f) +#define RTC_ALHOUR_MASK (0x001f) +#define RTC_ALDOM_MASK (0x001f) +#define RTC_ALDOW_MASK (0x0007) +#define RTC_ALDOY_MASK (0x01ff) +#define RTC_ALMON_MASK (0x000f) +#define RTC_ALYEAR_MASK (0x0fff) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RTC_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtcevmr.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtcevmr.h new file mode 100644 index 00000000000..6df87091a1c --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtcevmr.h @@ -0,0 +1,143 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_rtcevmr.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RTCEVMR_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RTCEVMR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_RTCEV_ERCONTROL_OFFSET 0x0084 /* Monitor/Recorder Control register */ +#define LPC17_40_RTCEV_ERSTATUS_OFFSET 0x0080 /* Status register */ +#define LPC17_40_RTCEV_ERCOUNTERS_OFFSET 0x0088 /* Counters register */ +#define LPC17_40_RTCEV_ERFIRSTSTAMP0_OFFSET 0x0090 /* Channel 0 first Stamp register */ +#define LPC17_40_RTCEV_ERFIRSTSTAMP1_OFFSET 0x0090 /* Channel 1 first Stamp register */ +#define LPC17_40_RTCEV_ERFIRSTSTAMP2_OFFSET 0x0090 /* Channel 2 first Stamp register */ +#define LPC17_40_RTCEV_ERLASTSTAMP0_OFFSET 0x0098 /* Channel 0 last stamp register */ +#define LPC17_40_RTCEV_ERLASTSTAMP1_OFFSET 0x00a0 /* Channel 1 last stamp register */ +#define LPC17_40_RTCEV_ERLASTSTAMP2_OFFSET 0x00a8 /* Channel 2 last stamp register */ + +#define LPC17_40_RTCEV_ERCONTROL (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERCONTROL_OFFSET) +#define LPC17_40_RTCEV_ERSTATUS (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERSTATUS_OFFSET) +#define LPC17_40_RTCEV_ERCOUNTERS (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERCOUNTERS_OFFSET) +#define LPC17_40_RTCEV_ERFIRSTSTAMP0 (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERFIRSTSTAMP0_OFFSET) +#define LPC17_40_RTCEV_ERFIRSTSTAMP1 (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERFIRSTSTAMP1_OFFSET) +#define LPC17_40_RTCEV_ERFIRSTSTAMP2 (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERFIRSTSTAMP2_OFFSET) +#define LPC17_40_RTCEV_ERLASTSTAMP0 (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERLASTSTAMP0_OFFSET) +#define LPC17_40_RTCEV_ERLASTSTAMP1 (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERLASTSTAMP1_OFFSET) +#define LPC17_40_RTCEV_ERLASTSTAMP2 (LPC17_40_RTC_BASE+LPC17_40_RTCEV_ERLASTSTAMP2_OFFSET) + +/* RTCEV ERCONTROL Event Monitor/Recorder Control Register */ + +#define RTCEV_ERCONTROL_INTWAKE_EN0 (1) /* Bit 0: Interrupt/wakeup enable channel 0 */ +#define RTCEV_ERCONTROL_GPCLEAR_EN0 (1 << 1) /* Bit 1: Automatic clearing of RTC - channel 0 */ +#define RTCEV_ERCONTROL_POL0 (1 << 2) /* Bit 2: Edge polarity on RTC_EV0 pins */ +#define RTCEV_ERCONTROL_EV0_INPUT_EN (1 << 3) /* Bit 3: Event enable for channel 0 */ + /* Bits 4-9: Reserved */ +#define RTCEV_ERCONTROL_INTWAKE_EN1 (1 << 10) /* Bit 10: Interrupt/wakeup enable - channel 1 */ +#define RTCEV_ERCONTROL_GPCLEAR_EN1 (1 << 11) /* Bit 11: Automatic clearing of RTC - channel 1 */ +#define RTCEV_ERCONTROL_POL1 (1 << 12) /* Bit 12: Edge polarity on RTC_EV1 pins */ +#define RTCEV_ERCONTROL_EV1_INPUT_EN (1 << 13) /* Bit 13: Event enable for channel 1 */ + /* Bits 14-19: Reserved */ +#define RTCEV_ERCONTROL_INTWAKE_EN2 (1 << 20) /* Bit 20: Interrupt/wakeup enable - channel 2 */ +#define RTCEV_ERCONTROL_GPCLEAR_EN2 (1 << 21) /* Bit 21: Automatic clearing of RTC - channel 2 */ +#define RTCEV_ERCONTROL_POL2 (1 << 22) /* Bit 22: Edge polarity on RTC_EV2 pins */ +#define RTCEV_ERCONTROL_EV2_INPUT_EN (1 << 23) /* Bit 23: Event enable for channel 1 */ + /* Bits 24-29: Reserved */ +#define RTCEV_ERCONTROL_ERMODE_SHIFT (30) /* Bits 30-31: Event monitoring mode */ +#define RTCEV_ERCONTROL_ERMODE_MASK (3 << RTCEV_ERCONTROL_ERMODE_SHIFT) +# define ERMODE0 (0) /* monitor/clocks disabled */ +# define ERMODE1 (1) /* 16Hz sample clock */ +# define ERMODE2 (2) /* 64Hz sample clock */ +# define ERMODE3 (3) /* 1000Hz sample clock */ + +/* RTCEV ERSTATUS - Monitor/Recorder Status Register */ + +#define RTCEV_ERSTATUS_EV0 (1) /* Bit 0: Event flag - channel 0 */ +#define RTCEV_ERSTATUS_EV1 (1 << 1) /* Bit 1: Event flag - channel 1 */ +#define RTCEV_ERSTATUS_EV2 (1 << 2) /* Bit 2: Event flag - channel 2 */ +#define RTCEV_ERSTATUS_EV2 (1 << 3) /* Bit 3: GPReg async clear flag */ + /* Bits 4-30: Reserved */ +#define RTCEV_ERSTATUS_WAKEUP (1 << 31) /* Bit 31: Interrupt/Wakeup request flag */ + +/* RTCEV ERCOUNTERS - Monitor/Recorder Counters Register */ + +#define RTCEV_ERCOUNTER_COUNTER0_SHIFT (0) /* Bits 0-2: Value for event 0 */ +#define RTCEV_ERCOUNTER_COUNTER0_MASK (7 << RTCEV_ERCOUNTER_COUNTER0_SHIFT) + /* Bits 3-7: Reserved */ +#define RTCEV_ERCOUNTER_COUNTER1_SHIFT (8) i /* Bits 8-10: Value for event 1 */ +#define RTCEV_ERCOUNTER_COUNTER1_MASK (7 << RTCEV_ERCOUNTER_COUNTER1_SHIFT) + /* Bits 11-15: Reserved */ +#define RTCEV_ERCOUNTER_COUNTER2_SHIFT (16) /* Bits 16-18: Value for event 2 */ +#define RTCEV_ERCOUNTER_COUNTER2_MASK (7 << RTCEV_ERCOUNTER_COUNTER2_SHIFT) + /* Bits 19-31: Reserved */ + +/* RTCEV ERFIRSTSTAMP[0-2] - Monitor/Recorder First Stamp Registers */ +/* RTCEV ERLASTSTAMP[0-2] - Monitor/Recorder Last Stamp Registers */ + +#define RTCEV_TIMESTAMP_SEC_SHIFT (0) /* Bits 0-5: Seconds value 0-59 */ +#define RTCEV_TIMESTAMP_SEC_MASK (0x3f << RTCEV_TIMESTAMP_SEC_SHIFT) +#define RTCEV_TIMESTAMP_MIN_SHIFT (6) /* Bits 6-11: Minutes value 0-59 */ +#define RTCEV_TIMESTAMP_MIN_MASK (0x3f << RTCEV_TIMESTAMP_MIN_SHIFT) +#define RTCEV_TIMESTAMP_HOUR_SHIFT (12) /* Bits 12-16: Hours value 0-23 */ +#define RTCEV_TIMESTAMP_HOUR_MASK (0x1f << RTCEV_TIMESTAMP_HOUR_SHIFT) +#define RTCEV_TIMESTAMP_DOY_SHIFT (17) /* Bits 17-25: Day of the year value 1-366 */ +#define RTCEV_TIMESTAMP_DOY_MASK (0x1ff << RTCEV_TIMESTAMP_DOY_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_RTCEVMR_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_sdcard.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_sdcard.h new file mode 100644 index 00000000000..cac8c1b7336 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_sdcard.h @@ -0,0 +1,272 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_sdcard.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SDCARD_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SDCARD_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define LPC17_40_SDCARD_PWR_OFFSET 0x0000 /* SD card power control register */ +#define LPC17_40_SDCARD_CLOCK_OFFSET 0x0004 /* SD card clock control register */ +#define LPC17_40_SDCARD_ARG_OFFSET 0x0008 /* SD card argument register */ +#define LPC17_40_SDCARD_CMD_OFFSET 0x000c /* SD card command register */ +#define LPC17_40_SDCARD_RESPCMD_OFFSET 0x0010 /* SD card command response register */ +#define LPC17_40_SDCARD_RESP_OFFSET(n) (0x0010+4*(n)) +# define LPC17_40_SDCARD_RESP0_OFFSET 0x0014 /* SD card response 1 register */ +# define LPC17_40_SDCARD_RESP1_OFFSET 0x0018 /* SD card response 2 register */ +# define LPC17_40_SDCARD_RESP2_OFFSET 0x001c /* SD card response 3 register */ +# define LPC17_40_SDCARD_RESP3_OFFSET 0x0020 /* SD card response 4 register */ +#define LPC17_40_SDCARD_DTIMER_OFFSET 0x0024 /* SD card data timer register */ +#define LPC17_40_SDCARD_DLEN_OFFSET 0x0028 /* SD card data length register */ +#define LPC17_40_SDCARD_DCTRL_OFFSET 0x002c /* SD card data control register */ +#define LPC17_40_SDCARD_DCOUNT_OFFSET 0x0030 /* SD card data counter register */ +#define LPC17_40_SDCARD_STATUS_OFFSET 0x0034 /* SD card status register */ +#define LPC17_40_SDCARD_CLEAR_OFFSET 0x0038 /* SD card interrupt clear register */ +#define LPC17_40_SDCARD_MASK0_OFFSET 0x003c /* SD card mask register */ +#define LPC17_40_SDCARD_FIFOCNT_OFFSET 0x0048 /* SD card FIFO counter register */ +#define LPC17_40_SDCARD_FIFO_OFFSET 0x0080 /* SD card data FIFO register */ + +/* Register Addresses ***************************************************************/ + +#define LPC17_40_SDCARD_PWR (LPC17_40_MCI_BASE+LPC17_40_SDCARD_PWR_OFFSET) +#define LPC17_40_SDCARD_CLOCK (LPC17_40_MCI_BASE+LPC17_40_SDCARD_CLOCK_OFFSET) +#define LPC17_40_SDCARD_ARG (LPC17_40_MCI_BASE+LPC17_40_SDCARD_ARG_OFFSET) +#define LPC17_40_SDCARD_CMD (LPC17_40_MCI_BASE+LPC17_40_SDCARD_CMD_OFFSET) +#define LPC17_40_SDCARD_RESPCMD (LPC17_40_MCI_BASE+LPC17_40_SDCARD_RESPCMD_OFFSET) +#define LPC17_40_SDCARD_RESP(n) (LPC17_40_MCI_BASE+LPC17_40_SDCARD_RESP_OFFSET(n)) +#define LPC17_40_SDCARD_RESP0 (LPC17_40_MCI_BASE+LPC17_40_SDCARD_RESP0_OFFSET) +#define LPC17_40_SDCARD_RESP1 (LPC17_40_MCI_BASE+LPC17_40_SDCARD_RESP1_OFFSET) +#define LPC17_40_SDCARD_RESP2 (LPC17_40_MCI_BASE+LPC17_40_SDCARD_RESP2_OFFSET) +#define LPC17_40_SDCARD_RESP3 (LPC17_40_MCI_BASE+LPC17_40_SDCARD_RESP3_OFFSET) +#define LPC17_40_SDCARD_DTIMER (LPC17_40_MCI_BASE+LPC17_40_SDCARD_DTIMER_OFFSET) +#define LPC17_40_SDCARD_DLEN (LPC17_40_MCI_BASE+LPC17_40_SDCARD_DLEN_OFFSET) +#define LPC17_40_SDCARD_DCTRL (LPC17_40_MCI_BASE+LPC17_40_SDCARD_DCTRL_OFFSET) +#define LPC17_40_SDCARD_DCOUNT (LPC17_40_MCI_BASE+LPC17_40_SDCARD_DCOUNT_OFFSET) +#define LPC17_40_SDCARD_STATUS (LPC17_40_MCI_BASE+LPC17_40_SDCARD_STATUS_OFFSET) +#define LPC17_40_SDCARD_CLEAR (LPC17_40_MCI_BASE+LPC17_40_SDCARD_CLEAR_OFFSET) +#define LPC17_40_SDCARD_MASK0 (LPC17_40_MCI_BASE+LPC17_40_SDCARD_MASK0_OFFSET) +#define LPC17_40_SDCARD_FIFOCNT (LPC17_40_MCI_BASE+LPC17_40_SDCARD_FIFOCNT_OFFSET) +#define LPC17_40_SDCARD_FIFO (LPC17_40_MCI_BASE+LPC17_40_SDCARD_FIFO_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* MCI Power Control Registers - PWR - 0x400c 0000*/ + +#define SDCARD_PWR_CTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define SDCARD_PWR_CTRL_MASK (3 << SDCARD_PWR_CTRL_SHIFT) +# define SDCARD_PWR_CTRL_OFF (0 << SDCARD_PWR_CTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define SDCARD_PWR_CTRL_PWRUP (2 << SDCARD_PWR_CTRL_SHIFT) /* 10: Reserved power-up */ +# define SDCARD_PWR_CTRL_ON (3 << SDCARD_PWR_CTRL_SHIFT) /* 11: Power-on: card is clocked */ + /* Bits 2-5 Reserved */ +#define SDCARD_PWR_OPENDRAIN (1 << 6) /* SD_CMD Output Control */ +#define SDCARD_PWR_ROD (1 << 7) /* Rod Control */ + /* Bits 8-31: Reserved */ +#define SDCARD_PWR_RESET (0) /* Reset value */ + +/* MCI Clock Control Register - CLOCK - 0x400c 0004 */ + +#define SDCARD_CLOCK_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define SDCARD_CLOCK_CLKDIV_MASK (0xff << SDCARD_CLOCK_CLKDIV_SHIFT) +#define SDCARD_CLOCK_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define SDCARD_CLOCK_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define SDCARD_CLOCK_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define SDCARD_CLOCK_WIDBUS (1 << 11) /* Bit 11: Wide bus mode enable bit */ +# define SDCARD_CLOCK_WIDBUS_D1 (0) /* 0: Default (SDIO_D0) */ +# define SDCARD_CLOCK_WIDBUS_D4 (SDCARD_CLOCK_WIDBUS) /* 1: 4-wide (SDIO_D[3:0]) */ + /* Bits 12-31: Reserved */ + +#define SDCARD_CLOCK_RESET (0) /* Reset value */ + +/* MCI Argument Register - ARGUMENT - 0x400c 0008 has no bitfields */ + +#define SDCARD_ARG_RESET (0) /* Reset value */ + +/* MCI Command Register - COMMAND - 0x400c 000c */ + +#define SDCARD_CMD_INDEX_SHIFT (0) /* Bits 0-5: Command Index */ +#define SDCARD_CMD_INDEX_MASK (0x3f << SDCARD_CMD_INDEX_SHIFT) +#define SDCARD_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define SDCARD_CMD_WAITRESP_MASK (3 << SDCARD_CMD_WAITRESP_SHIFT) +# define SDCARD_CMD_NORESPONSE (0 << SDCARD_CMD_WAITRESP_SHIFT) /* 00/01: No response */ +# define SDCARD_CMD_SHORTRESPONSE (1 << SDCARD_CMD_WAITRESP_SHIFT) /* 10: Short response */ +# define SDCARD_CMD_LONGRESPONSE (3 << SDCARD_CMD_WAITRESP_SHIFT) /* 11: Long response */ +#define SDCARD_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define SDCARD_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define SDCARD_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ + /* Bits 11-31: Reserved */ + +#define SDCARD_CMD_RESET (0) /* Reset value */ + +/* MCI Command Response Register - RESPCOMMAND - 0x400c 0010 */ + +#define SDCARD_RESPCMD_SHIFT (0) /* Bits 0-5: Resopnse Command index */ +#define SDCARD_RESPCMD_MASK (0x3f << SDCARD_RESPCMD_SHIFT) + /* Bits 6-31: Reserved */ + +/* MCI Response Registers RESPONSE0-3 - 0x400c 0014, 0x400c 0018, + No bitfields 0x400c 001c, 0x400c 0020 */ + + +/* MCI - Data Timer Register DATATIMER - 0x400c 0024 */ +/* No bitfields */ + +#define SDCARD_DTIMER_RESET (0) /* Reset value */ + +/* MCI - Data Length Register DATALENGTH - 0x400C 0028 */ + +#define SDCARD_DATALENGTH_SHIFT (0) /* Bits 0-15: Data length value */ +#define SDCARD_DATALENGTH_MASK (0xffff << SDCARD_DATALENGTH_SHIFT) + /* Bits 16-31: Reserved */ + +#define SDCARD_DLEN_RESET (0) /* Reset value */ + +/* MCI - Data Control Register - DATACTRL - 0x400c 002c */ + +#define SDCARD_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define SDCARD_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define SDCARD_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define SDCARD_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define SDCARD_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 4-7: Data block size */ +#define SDCARD_DCTRL_DBLOCKSIZE_MASK (15 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_1BYTE (0 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_2BYTES (1 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_4BYTES (2 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_8BYTES (3 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_16BYTES (4 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_32BYTES (5 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_64BYTES (6 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_128BYTES (7 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_256BYTES (8 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_512BYTES (9 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_1KBYTE (10 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) +# define SDCARD_DCTRL_2KBYTES (11 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT) + /* Bits 8-31: Reserved */ + +#define SDCARD_DCTRL_RESET (0) /* Reset value */ + +/* MCI - Data Length Register DATALENGTH - 0x400c 0028 */ + +#define SDCARD_DATACOUNT_SHIFT (0) /* Bits 0-15: Remaining data */ +#define SDCARD_DATACOUNT_MASK (0xffff << SDCARD_DATACOUNT_SHIFT) + /* Bits 16-31: Reserved */ + +/* MCI - Status Register -Status - 0x400c 0034 */ + +#define SDCARD_STATUS_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define SDCARD_STATUS_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define SDCARD_STATUS_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define SDCARD_STATUS_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define SDCARD_STATUS_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define SDCARD_STATUS_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define SDCARD_STATUS_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define SDCARD_STATUS_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define SDCARD_STATUS_DATAEND (1 << 8) /* Bit 8: Data end */ +#define SDCARD_STATUS_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ +#define SDCARD_STATUS_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define SDCARD_STATUS_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define SDCARD_STATUS_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define SDCARD_STATUS_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define SDCARD_STATUS_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define SDCARD_STATUS_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define SDCARD_STATUS_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define SDCARD_STATUS_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define SDCARD_STATUS_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define SDCARD_STATUS_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define SDCARD_STATUS_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define SDCARD_STATUS_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ + /* Bits 22-31: Reserved */ + +/* MCI - Clear Register CLEAR - 0x400c 0038 */ + +#define SDCARD_CLEAR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define SDCARD_CLEAR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define SDCARD_CLEAR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define SDCARD_CLEAR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define SDCARD_CLEAR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define SDCARD_CLEAR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define SDCARD_CLEAR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define SDCARD_CLEAR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define SDCARD_CLEAR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ +#define SDCARD_CLEAR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ +#define SDCARD_CLEAR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ + /* Bits 11-31: Reserved */ + +#define SDCARD_CLEAR_RESET 0x000007ff +#define SDCARD_CLEAR_STATICFLAGS 0x000005ff + +/* MCI - Interrupt Mask Registers - MASK0 - 0x400c 003c */ + +#define SDCARD_MASK0_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define SDCARD_MASK0_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define SDCARD_MASK0_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define SDCARD_MASK0_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define SDCARD_MASK0_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define SDCARD_MASK0_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define SDCARD_MASK0_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define SDCARD_MASK0_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define SDCARD_MASK0_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ +#define SDCARD_MASK0_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ +#define SDCARD_MASK0_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define SDCARD_MASK0_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define SDCARD_MASK0_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define SDCARD_MASK0_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define SDCARD_MASK0_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define SDCARD_MASK0_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define SDCARD_MASK0_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define SDCARD_MASK0_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define SDCARD_MASK0_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define SDCARD_MASK0_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define SDCARD_MASK0_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define SDCARD_MASK0_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ + /* Bits 22-31: Reserved */ +#define SDCARD_MASK0_RESET (0) + +/* MCI - FIFO Counter Register (FIFOCNT - 0x400c 0048 */ + +#define SDCARD_FIFOCNT_SHIFT (0) /* Bits 0-14: Remaining data */ +#define SDCARD_FIFOCNT_MASK (0x7fff << SDCARD_FIFOCNT_SHIFT) + /* Bits 15-31: Reserved */ + +/* MCI - Data FIFO Register - FIFO - 0x400c 0080 to 0x400c 00bc */ +/* The receive and transmit FIFOs can be read or written as 32 bit wide registers. + * The FIFOs contain 16 entries on 16 sequential addresses. + */ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SDCARD_H */ + diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_spi.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_spi.h new file mode 100644 index 00000000000..fdd991ccc1f --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_spi.h @@ -0,0 +1,141 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_spi.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SPI_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_SPI_CR_OFFSET 0x0000 /* Control Register */ +#define LPC17_40_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ +#define LPC17_40_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ +#define LPC17_40_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ +#define LPC17_40_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ +#define LPC17_40_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ +#define LPC17_40_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_SPI_CR (LPC17_40_SPI_BASE+LPC17_40_SPI_CR_OFFSET) +#define LPC17_40_SPI_SR (LPC17_40_SPI_BASE+LPC17_40_SPI_SR_OFFSET) +#define LPC17_40_SPI_DR (LPC17_40_SPI_BASE+LPC17_40_SPI_DR_OFFSET) +#define LPC17_40_SPI_CCR (LPC17_40_SPI_BASE+LPC17_40_SPI_CCR_OFFSET) +#define LPC17_40_TCR_CCR (LPC17_40_SPI_BASE+LPC17_40_SPI_TCR_OFFSET) +#define LPC17_40_TSR_CCR (LPC17_40_SPI_BASE+LPC17_40_SPI_TSR_OFFSET) +#define LPC17_40_SPI_INT (LPC17_40_SPI_BASE+LPC17_40_SPI_INT_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Control Register */ + /* Bits 0-1: Reserved */ +#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ +#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ +#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ +#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ +#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ +#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ +#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ +#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) +# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ +# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ +# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ +# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ +# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ +# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ +# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ +# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ +# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ + /* Bits 12-31: Reserved */ +/* SPI Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Data Register */ + +#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ +#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ + /* Bits 8-31: Reserved */ +/* SPI Clock Counter Register */ + +#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ + /* Bits 8-31: Reserved */ +/* SPI Test Control Register */ + /* Bit 0: Reserved */ +#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ +#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) + /* Bits 8-31: Reserved */ +/* SPI Test Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Interrupt Register */ + +#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ + /* Bits 1-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SPI_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ssp.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ssp.h new file mode 100644 index 00000000000..21e74239fa8 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ssp.h @@ -0,0 +1,185 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_ssp.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SSP_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SSP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* 8 frame FIFOs for both transmit and receive */ + +#define LPC17_40_SSP_FIFOSZ 8 + +/* Register offsets *****************************************************************/ + +#define LPC17_40_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */ +#define LPC17_40_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */ +#define LPC17_40_SSP_DR_OFFSET 0x0008 /* Data Register */ +#define LPC17_40_SSP_SR_OFFSET 0x000c /* Status Register */ +#define LPC17_40_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */ +#define LPC17_40_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */ +#define LPC17_40_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */ +#define LPC17_40_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */ +#define LPC17_40_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */ +#define LPC17_40_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_SSP0_CR0 (LPC17_40_SSP0_BASE+LPC17_40_SSP_CR0_OFFSET) +#define LPC17_40_SSP0_CR1 (LPC17_40_SSP0_BASE+LPC17_40_SSP_CR1_OFFSET) +#define LPC17_40_SSP0_DR (LPC17_40_SSP0_BASE+LPC17_40_SSP_DR_OFFSET) +#define LPC17_40_SSP0_SR (LPC17_40_SSP0_BASE+LPC17_40_SSP_SR_OFFSET) +#define LPC17_40_SSP0_CPSR (LPC17_40_SSP0_BASE+LPC17_40_SSP_CPSR_OFFSET) +#define LPC17_40_SSP0_IMSC (LPC17_40_SSP0_BASE+LPC17_40_SSP_IMSC_OFFSET) +#define LPC17_40_SSP0_RIS (LPC17_40_SSP0_BASE+LPC17_40_SSP_RIS_OFFSET) +#define LPC17_40_SSP0_MIS (LPC17_40_SSP0_BASE+LPC17_40_SSP_MIS_OFFSET) +#define LPC17_40_SSP0_ICR (LPC17_40_SSP0_BASE+LPC17_40_SSP_ICR_OFFSET) +#define LPC17_40_SSP0_DMACR (LPC17_40_SSP0_BASE+LPC17_40_SSP_DMACR_OFFSET) + +#define LPC17_40_SSP1_CR0 (LPC17_40_SSP1_BASE+LPC17_40_SSP_CR0_OFFSET) +#define LPC17_40_SSP1_CR1 (LPC17_40_SSP1_BASE+LPC17_40_SSP_CR1_OFFSET) +#define LPC17_40_SSP1_DR (LPC17_40_SSP1_BASE+LPC17_40_SSP_DR_OFFSET) +#define LPC17_40_SSP1_SR (LPC17_40_SSP1_BASE+LPC17_40_SSP_SR_OFFSET) +#define LPC17_40_SSP1_CPSR (LPC17_40_SSP1_BASE+LPC17_40_SSP_CPSR_OFFSET) +#define LPC17_40_SSP1_IMSC (LPC17_40_SSP1_BASE+LPC17_40_SSP_IMSC_OFFSET) +#define LPC17_40_SSP1_RIS (LPC17_40_SSP1_BASE+LPC17_40_SSP_RIS_OFFSET) +#define LPC17_40_SSP1_MIS (LPC17_40_SSP1_BASE+LPC17_40_SSP_MIS_OFFSET) +#define LPC17_40_SSP1_ICR (LPC17_40_SSP1_BASE+LPC17_40_SSP_ICR_OFFSET) +#define LPC17_40_SSP1_DMACR (LPC17_40_SSP1_BASE+LPC17_40_SSP_DMACR_OFFSET) + +#define LPC17_40_SSP2_CR0 (LPC17_40_SSP2_BASE+LPC17_40_SSP_CR0_OFFSET) +#define LPC17_40_SSP2_CR1 (LPC17_40_SSP2_BASE+LPC17_40_SSP_CR1_OFFSET) +#define LPC17_40_SSP2_DR (LPC17_40_SSP2_BASE+LPC17_40_SSP_DR_OFFSET) +#define LPC17_40_SSP2_SR (LPC17_40_SSP2_BASE+LPC17_40_SSP_SR_OFFSET) +#define LPC17_40_SSP2_CPSR (LPC17_40_SSP2_BASE+LPC17_40_SSP_CPSR_OFFSET) +#define LPC17_40_SSP2_IMSC (LPC17_40_SSP2_BASE+LPC17_40_SSP_IMSC_OFFSET) +#define LPC17_40_SSP2_RIS (LPC17_40_SSP2_BASE+LPC17_40_SSP_RIS_OFFSET) +#define LPC17_40_SSP2_MIS (LPC17_40_SSP2_BASE+LPC17_40_SSP_MIS_OFFSET) +#define LPC17_40_SSP2_ICR (LPC17_40_SSP2_BASE+LPC17_40_SSP_ICR_OFFSET) +#define LPC17_40_SSP2_DMACR (LPC17_40_SSP2_BASE+LPC17_40_SSP_DMACR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Control Register 0 */ + +#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */ +#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT) +#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */ +#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT) +#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */ +#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */ +#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */ +#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT) + /* Bits 8-31: Reserved */ +/* Control Register 1 */ + +#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */ +#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */ +#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */ +#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */ + /* Bits 4-31: Reserved */ +/* Data Register */ + +#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */ + /* Bits 16-31: Reserved */ +/* Status Register */ + +#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */ +#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ +#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */ +#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */ +#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */ + /* Bits 5-31: Reserved */ +/* Clock Prescale Register */ + +#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */ + /* Bits 8-31: Reserved */ +/* Common format for interrupt control registers: + * + * Interrupt Mask Set and Clear Register (IMSC) + * Raw Interrupt Status Register (RIS) + * Masked Interrupt Status Register (MIS) + * Interrupt Clear Register (ICR) + */ + +#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */ +#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */ +#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */ +#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */ + /* Bits 4-31: Reserved */ +/* DMA Control Register */ + +#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */ +#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SSP_H */ diff --git a/arch/arm/src/lpc17xx/hardware/lpc17_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_syscon.h similarity index 86% rename from arch/arm/src/lpc17xx/hardware/lpc17_syscon.h rename to arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_syscon.h index 29d4380f29f..61e6b1b69b4 100644 --- a/arch/arm/src/lpc17xx/hardware/lpc17_syscon.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_syscon.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/hardware/lpc17_syscon.h + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_syscon.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SYSCON_H -#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SYSCON_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SYSCON_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SYSCON_H /************************************************************************************ * Included Files @@ -43,17 +43,17 @@ #include /* This file is only a thin shell that includes the correct system controller - * register definitions for the selected LPC17xx family. + * register definitions for the selected LPC17xx/LPC40xx family. */ -#include +#include #if defined(LPC176x) # include "hardware/lpc176x_syscon.h" -#elif defined(LPC178x) -# include "hardware/lpc178x_syscon.h" +#elif defined(LPC178x_40xx) +# include "hardware/lpc178x_40xx_syscon.h" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /************************************************************************************ @@ -72,4 +72,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SYSCON_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_SYSCON_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_timer.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_timer.h new file mode 100644 index 00000000000..68aaeb3ef5c --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_timer.h @@ -0,0 +1,250 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_timer.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_TIMER_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ +#define LPC17_40_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */ +#define LPC17_40_TMR_TC_OFFSET 0x0008 /* Timer Counter */ +#define LPC17_40_TMR_PR_OFFSET 0x000c /* Prescale Register */ +#define LPC17_40_TMR_PC_OFFSET 0x0010 /* Prescale Counter */ +#define LPC17_40_TMR_MCR_OFFSET 0x0014 /* Match Control Register */ +#define LPC17_40_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */ +#define LPC17_40_TMR_MR1_OFFSET 0x001c /* Match Register 1 */ +#define LPC17_40_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */ +#define LPC17_40_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */ +#define LPC17_40_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */ +#define LPC17_40_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */ +#define LPC17_40_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */ +#define LPC17_40_TMR_EMR_OFFSET 0x003c /* External Match Register */ +#define LPC17_40_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_40_TMR0_IR (LPC17_40_TMR0_BASE+LPC17_40_TMR_IR_OFFSET) +#define LPC17_40_TMR0_TCR (LPC17_40_TMR0_BASE+LPC17_40_TMR_TCR_OFFSET) +#define LPC17_40_TMR0_TC (LPC17_40_TMR0_BASE+LPC17_40_TMR_TC_OFFSET) +#define LPC17_40_TMR0_PR (LPC17_40_TMR0_BASE+LPC17_40_TMR_PR_OFFSET) +#define LPC17_40_TMR0_PC (LPC17_40_TMR0_BASE+LPC17_40_TMR_PC_OFFSET) +#define LPC17_40_TMR0_MCR (LPC17_40_TMR0_BASE+LPC17_40_TMR_MCR_OFFSET) +#define LPC17_40_TMR0_MR0 (LPC17_40_TMR0_BASE+LPC17_40_TMR_MR0_OFFSET) +#define LPC17_40_TMR0_MR1 (LPC17_40_TMR0_BASE+LPC17_40_TMR_MR1_OFFSET) +#define LPC17_40_TMR0_MR2 (LPC17_40_TMR0_BASE+LPC17_40_TMR_MR2_OFFSET) +#define LPC17_40_TMR0_MR3 (LPC17_40_TMR0_BASE+LPC17_40_TMR_MR3_OFFSET) +#define LPC17_40_TMR0_CCR (LPC17_40_TMR0_BASE+LPC17_40_TMR_CCR_OFFSET) +#define LPC17_40_TMR0_CR0 (LPC17_40_TMR0_BASE+LPC17_40_TMR_CR0_OFFSET) +#define LPC17_40_TMR0_CR1 (LPC17_40_TMR0_BASE+LPC17_40_TMR_CR1_OFFSET) +#define LPC17_40_TMR0_EMR (LPC17_40_TMR0_BASE+LPC17_40_TMR_EMR_OFFSET) +#define LPC17_40_TMR0_CTCR (LPC17_40_TMR0_BASE+LPC17_40_TMR_CTCR_OFFSET) + +#define LPC17_40_TMR1_IR (LPC17_40_TMR1_BASE+LPC17_40_TMR_IR_OFFSET) +#define LPC17_40_TMR1_TCR (LPC17_40_TMR1_BASE+LPC17_40_TMR_TCR_OFFSET) +#define LPC17_40_TMR1_TC (LPC17_40_TMR1_BASE+LPC17_40_TMR_TC_OFFSET) +#define LPC17_40_TMR1_PR (LPC17_40_TMR1_BASE+LPC17_40_TMR_PR_OFFSET) +#define LPC17_40_TMR1_PC (LPC17_40_TMR1_BASE+LPC17_40_TMR_PC_OFFSET) +#define LPC17_40_TMR1_MCR (LPC17_40_TMR1_BASE+LPC17_40_TMR_MCR_OFFSET) +#define LPC17_40_TMR1_MR0 (LPC17_40_TMR1_BASE+LPC17_40_TMR_MR0_OFFSET) +#define LPC17_40_TMR1_MR1 (LPC17_40_TMR1_BASE+LPC17_40_TMR_MR1_OFFSET) +#define LPC17_40_TMR1_MR2 (LPC17_40_TMR1_BASE+LPC17_40_TMR_MR2_OFFSET) +#define LPC17_40_TMR1_MR3 (LPC17_40_TMR1_BASE+LPC17_40_TMR_MR3_OFFSET) +#define LPC17_40_TMR1_CCR (LPC17_40_TMR1_BASE+LPC17_40_TMR_CCR_OFFSET) +#define LPC17_40_TMR1_CR0 (LPC17_40_TMR1_BASE+LPC17_40_TMR_CR0_OFFSET) +#define LPC17_40_TMR1_CR1 (LPC17_40_TMR1_BASE+LPC17_40_TMR_CR1_OFFSET) +#define LPC17_40_TMR1_EMR (LPC17_40_TMR1_BASE+LPC17_40_TMR_EMR_OFFSET) +#define LPC17_40_TMR1_CTCR (LPC17_40_TMR1_BASE+LPC17_40_TMR_CTCR_OFFSET) + +#define LPC17_40_TMR2_IR (LPC17_40_TMR2_BASE+LPC17_40_TMR_IR_OFFSET) +#define LPC17_40_TMR2_TCR (LPC17_40_TMR2_BASE+LPC17_40_TMR_TCR_OFFSET) +#define LPC17_40_TMR2_TC (LPC17_40_TMR2_BASE+LPC17_40_TMR_TC_OFFSET) +#define LPC17_40_TMR2_PR (LPC17_40_TMR2_BASE+LPC17_40_TMR_PR_OFFSET) +#define LPC17_40_TMR2_PC (LPC17_40_TMR2_BASE+LPC17_40_TMR_PC_OFFSET) +#define LPC17_40_TMR2_MCR (LPC17_40_TMR2_BASE+LPC17_40_TMR_MCR_OFFSET) +#define LPC17_40_TMR2_MR0 (LPC17_40_TMR2_BASE+LPC17_40_TMR_MR0_OFFSET) +#define LPC17_40_TMR2_MR1 (LPC17_40_TMR2_BASE+LPC17_40_TMR_MR1_OFFSET) +#define LPC17_40_TMR2_MR2 (LPC17_40_TMR2_BASE+LPC17_40_TMR_MR2_OFFSET) +#define LPC17_40_TMR2_MR3 (LPC17_40_TMR2_BASE+LPC17_40_TMR_MR3_OFFSET) +#define LPC17_40_TMR2_CCR (LPC17_40_TMR2_BASE+LPC17_40_TMR_CCR_OFFSET) +#define LPC17_40_TMR2_CR0 (LPC17_40_TMR2_BASE+LPC17_40_TMR_CR0_OFFSET) +#define LPC17_40_TMR2_CR1 (LPC17_40_TMR2_BASE+LPC17_40_TMR_CR1_OFFSET) +#define LPC17_40_TMR2_EMR (LPC17_40_TMR2_BASE+LPC17_40_TMR_EMR_OFFSET) +#define LPC17_40_TMR2_CTCR (LPC17_40_TMR2_BASE+LPC17_40_TMR_CTCR_OFFSET) + +#define LPC17_40_TMR3_IR (LPC17_40_TMR3_BASE+LPC17_40_TMR_IR_OFFSET) +#define LPC17_40_TMR3_TCR (LPC17_40_TMR3_BASE+LPC17_40_TMR_TCR_OFFSET) +#define LPC17_40_TMR3_TC (LPC17_40_TMR3_BASE+LPC17_40_TMR_TC_OFFSET) +#define LPC17_40_TMR3_PR (LPC17_40_TMR3_BASE+LPC17_40_TMR_PR_OFFSET) +#define LPC17_40_TMR3_PC (LPC17_40_TMR3_BASE+LPC17_40_TMR_PC_OFFSET) +#define LPC17_40_TMR3_MCR (LPC17_40_TMR3_BASE+LPC17_40_TMR_MCR_OFFSET) +#define LPC17_40_TMR3_MR0 (LPC17_40_TMR3_BASE+LPC17_40_TMR_MR0_OFFSET) +#define LPC17_40_TMR3_MR1 (LPC17_40_TMR3_BASE+LPC17_40_TMR_MR1_OFFSET) +#define LPC17_40_TMR3_MR2 (LPC17_40_TMR3_BASE+LPC17_40_TMR_MR2_OFFSET) +#define LPC17_40_TMR3_MR3 (LPC17_40_TMR3_BASE+LPC17_40_TMR_MR3_OFFSET) +#define LPC17_40_TMR3_CCR (LPC17_40_TMR3_BASE+LPC17_40_TMR_CCR_OFFSET) +#define LPC17_40_TMR3_CR0 (LPC17_40_TMR3_BASE+LPC17_40_TMR_CR0_OFFSET) +#define LPC17_40_TMR3_CR1 (LPC17_40_TMR3_BASE+LPC17_40_TMR_CR1_OFFSET) +#define LPC17_40_TMR3_EMR (LPC17_40_TMR3_BASE+LPC17_40_TMR_EMR_OFFSET) +#define LPC17_40_TMR3_CTCR (LPC17_40_TMR3_BASE+LPC17_40_TMR_CTCR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Registers holding 32-bit numeric values (no bit field definitions): + * + * Timer Counter (TC) + * Prescale Register (PR) + * Prescale Counter (PC) + * Match Register 0 (MR0) + * Match Register 1 (MR1) + * Match Register 2 (MR2) + * Match Register 3 (MR3) + * Capture Register 0 (CR0) + * Capture Register 1 (CR1) + */ + +/* Interrupt Register */ + +#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */ +#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */ +#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */ +#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */ +#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */ +#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */ + /* Bits 6-31: Reserved */ +/* Timer Control Register */ + +#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */ +#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */ + /* Bits 2-31: Reserved */ +/* Match Control Register */ + +#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ +#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ +#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ +#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ +#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ +#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ +#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ +#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ +#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ +#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ +#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ +#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ + /* Bits 12-31: Reserved */ +/* Capture Control Register */ + +#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ +#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */ +#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ +#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ +#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */ +#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ + /* Bits 6-31: Reserved */ +/* External Match Register */ + +#define TMR_EMR_NOTHING (0) /* Do Nothing */ +#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */ +#define TMR_EMR_SET (2) /* Set external match bit MATn.m */ +#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */ + +#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */ +#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */ +#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */ +#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */ +#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */ +#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy) +# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT) +#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */ +#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT) +#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */ +#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT) +#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */ +#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT) + /* Bits 12-31: Reserved */ +/* Count Control Register */ + +#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ +#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT) +# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */ +# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ +# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ +# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ +#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ +#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT) +# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ +# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_TIMER_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_uart.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_uart.h new file mode 100644 index 00000000000..44c781244f8 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_uart.h @@ -0,0 +1,414 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_uart.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_UART_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */ +#define LPC17_40_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */ +#define LPC17_40_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */ +#define LPC17_40_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */ +#define LPC17_40_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */ +#define LPC17_40_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */ +#define LPC17_40_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */ +#define LPC17_40_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */ +#define LPC17_40_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */ +#define LPC17_40_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */ +#define LPC17_40_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */ +#define LPC17_40_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */ +#define LPC17_40_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */ +#define LPC17_40_UART_ICR_OFFSET 0x0024 /* IrDA Control Register (UART0,2,3 only) */ +#define LPC17_40_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */ +#define LPC17_40_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */ +#define LPC17_40_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */ +#define LPC17_40_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */ +#define LPC17_40_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */ +#define LPC17_40_UART_FIFOLVL_OFFSET 0x0058 /* FIFO Level register (all) */ + +#ifdef LPC178x_40xx +# define LPC17_40_UART_OSR_OFFSET 0x002c /* Oversampling Register (UART4 only) */ +# define LPC17_40_UART_SCICTRL_OFFSET 0x0048 /* Smart Card Interface Register (UART4 only) */ +# define LPC17_40_UART_SYNCCTRL_OFFSET 0x0058 /* Synchronous Mode Register (UART4 only) */ +#endif + +/* Register addresses ***************************************************************/ + +#define LPC17_40_UART0_RBR (LPC17_40_UART0_BASE+LPC17_40_UART_RBR_OFFSET) +#define LPC17_40_UART0_THR (LPC17_40_UART0_BASE+LPC17_40_UART_THR_OFFSET) +#define LPC17_40_UART0_DLL (LPC17_40_UART0_BASE+LPC17_40_UART_DLL_OFFSET) +#define LPC17_40_UART0_DLM (LPC17_40_UART0_BASE+LPC17_40_UART_DLM_OFFSET) +#define LPC17_40_UART0_IER (LPC17_40_UART0_BASE+LPC17_40_UART_IER_OFFSET) +#define LPC17_40_UART0_IIR (LPC17_40_UART0_BASE+LPC17_40_UART_IIR_OFFSET) +#define LPC17_40_UART0_FCR (LPC17_40_UART0_BASE+LPC17_40_UART_FCR_OFFSET) +#define LPC17_40_UART0_LCR (LPC17_40_UART0_BASE+LPC17_40_UART_LCR_OFFSET) +#define LPC17_40_UART0_LSR (LPC17_40_UART0_BASE+LPC17_40_UART_LSR_OFFSET) +#define LPC17_40_UART0_SCR (LPC17_40_UART0_BASE+LPC17_40_UART_SCR_OFFSET) +#define LPC17_40_UART0_ACR (LPC17_40_UART0_BASE+LPC17_40_UART_ACR_OFFSET) +#define LPC17_40_UART0_ICR (LPC17_40_UART0_BASE+LPC17_40_UART_ICR_OFFSET) +#define LPC17_40_UART0_FDR (LPC17_40_UART0_BASE+LPC17_40_UART_FDR_OFFSET) +#define LPC17_40_UART0_TER (LPC17_40_UART0_BASE+LPC17_40_UART_TER_OFFSET) + +#ifdef LPC178x_40xx +# define LPC17_40_UART0_RS485CTRL (LPC17_40_UART0_BASE+LPC17_40_UART_RS485CTRL_OFFSET) +# define LPC17_40_UART0_ADRMATCH (LPC17_40_UART0_BASE+LPC17_40_UART_ADRMATCH_OFFSET) +# define LPC17_40_UART0_RS485DLY (LPC17_40_UART0_BASE+LPC17_40_UART_RS485DLY_OFFSET) +#endif + +#define LPC17_40_UART0_FIFOLVL (LPC17_40_UART0_BASE+LPC17_40_UART_FIFOLVL_OFFSET) + +#define LPC17_40_UART1_RBR (LPC17_40_UART1_BASE+LPC17_40_UART_RBR_OFFSET) +#define LPC17_40_UART1_THR (LPC17_40_UART1_BASE+LPC17_40_UART_THR_OFFSET) +#define LPC17_40_UART1_DLL (LPC17_40_UART1_BASE+LPC17_40_UART_DLL_OFFSET) +#define LPC17_40_UART1_DLM (LPC17_40_UART1_BASE+LPC17_40_UART_DLM_OFFSET) +#define LPC17_40_UART1_IER (LPC17_40_UART1_BASE+LPC17_40_UART_IER_OFFSET) +#define LPC17_40_UART1_IIR (LPC17_40_UART1_BASE+LPC17_40_UART_IIR_OFFSET) +#define LPC17_40_UART1_FCR (LPC17_40_UART1_BASE+LPC17_40_UART_FCR_OFFSET) +#define LPC17_40_UART1_LCR (LPC17_40_UART1_BASE+LPC17_40_UART_LCR_OFFSET) +#define LPC17_40_UART1_MCR (LPC17_40_UART1_BASE+LPC17_40_UART_MCR_OFFSET) +#define LPC17_40_UART1_LSR (LPC17_40_UART1_BASE+LPC17_40_UART_LSR_OFFSET) +#define LPC17_40_UART1_MSR (LPC17_40_UART1_BASE+LPC17_40_UART_MSR_OFFSET) +#define LPC17_40_UART1_SCR (LPC17_40_UART1_BASE+LPC17_40_UART_SCR_OFFSET) +#define LPC17_40_UART1_ACR (LPC17_40_UART1_BASE+LPC17_40_UART_ACR_OFFSET) +#define LPC17_40_UART1_FDR (LPC17_40_UART1_BASE+LPC17_40_UART_FDR_OFFSET) +#define LPC17_40_UART1_TER (LPC17_40_UART1_BASE+LPC17_40_UART_TER_OFFSET) +#define LPC17_40_UART1_RS485CTRL (LPC17_40_UART1_BASE+LPC17_40_UART_RS485CTRL_OFFSET) +#define LPC17_40_UART1_ADRMATCH (LPC17_40_UART1_BASE+LPC17_40_UART_ADRMATCH_OFFSET) +#define LPC17_40_UART1_RS485DLY (LPC17_40_UART1_BASE+LPC17_40_UART_RS485DLY_OFFSET) +#define LPC17_40_UART1_FIFOLVL (LPC17_40_UART1_BASE+LPC17_40_UART_FIFOLVL_OFFSET) + +#define LPC17_40_UART2_RBR (LPC17_40_UART2_BASE+LPC17_40_UART_RBR_OFFSET) +#define LPC17_40_UART2_THR (LPC17_40_UART2_BASE+LPC17_40_UART_THR_OFFSET) +#define LPC17_40_UART2_DLL (LPC17_40_UART2_BASE+LPC17_40_UART_DLL_OFFSET) +#define LPC17_40_UART2_DLM (LPC17_40_UART2_BASE+LPC17_40_UART_DLM_OFFSET) +#define LPC17_40_UART2_IER (LPC17_40_UART2_BASE+LPC17_40_UART_IER_OFFSET) +#define LPC17_40_UART2_IIR (LPC17_40_UART2_BASE+LPC17_40_UART_IIR_OFFSET) +#define LPC17_40_UART2_FCR (LPC17_40_UART2_BASE+LPC17_40_UART_FCR_OFFSET) +#define LPC17_40_UART2_LCR (LPC17_40_UART2_BASE+LPC17_40_UART_LCR_OFFSET) +#define LPC17_40_UART2_LSR (LPC17_40_UART2_BASE+LPC17_40_UART_LSR_OFFSET) +#define LPC17_40_UART2_SCR (LPC17_40_UART2_BASE+LPC17_40_UART_SCR_OFFSET) +#define LPC17_40_UART2_ACR (LPC17_40_UART2_BASE+LPC17_40_UART_ACR_OFFSET) +#define LPC17_40_UART2_ICR (LPC17_40_UART2_BASE+LPC17_40_UART_ICR_OFFSET) +#define LPC17_40_UART2_FDR (LPC17_40_UART2_BASE+LPC17_40_UART_FDR_OFFSET) +#define LPC17_40_UART2_TER (LPC17_40_UART2_BASE+LPC17_40_UART_TER_OFFSET) + +#ifdef LPC178x_40xx +# define LPC17_40_UART2_RS485CTRL (LPC17_40_UART2_BASE+LPC17_40_UART_RS485CTRL_OFFSET) +# define LPC17_40_UART2_ADRMATCH (LPC17_40_UART2_BASE+LPC17_40_UART_ADRMATCH_OFFSET) +# define LPC17_40_UART2_RS485DLY (LPC17_40_UART2_BASE+LPC17_40_UART_RS485DLY_OFFSET) +#endif + +#define LPC17_40_UART2_FIFOLVL (LPC17_40_UART2_BASE+LPC17_40_UART_FIFOLVL_OFFSET) + +#define LPC17_40_UART3_RBR (LPC17_40_UART3_BASE+LPC17_40_UART_RBR_OFFSET) +#define LPC17_40_UART3_THR (LPC17_40_UART3_BASE+LPC17_40_UART_THR_OFFSET) +#define LPC17_40_UART3_DLL (LPC17_40_UART3_BASE+LPC17_40_UART_DLL_OFFSET) +#define LPC17_40_UART3_DLM (LPC17_40_UART3_BASE+LPC17_40_UART_DLM_OFFSET) +#define LPC17_40_UART3_IER (LPC17_40_UART3_BASE+LPC17_40_UART_IER_OFFSET) +#define LPC17_40_UART3_IIR (LPC17_40_UART3_BASE+LPC17_40_UART_IIR_OFFSET) +#define LPC17_40_UART3_FCR (LPC17_40_UART3_BASE+LPC17_40_UART_FCR_OFFSET) +#define LPC17_40_UART3_LCR (LPC17_40_UART3_BASE+LPC17_40_UART_LCR_OFFSET) +#define LPC17_40_UART3_LSR (LPC17_40_UART3_BASE+LPC17_40_UART_LSR_OFFSET) +#define LPC17_40_UART3_SCR (LPC17_40_UART3_BASE+LPC17_40_UART_SCR_OFFSET) +#define LPC17_40_UART3_ACR (LPC17_40_UART3_BASE+LPC17_40_UART_ACR_OFFSET) +#define LPC17_40_UART3_ICR (LPC17_40_UART3_BASE+LPC17_40_UART_ICR_OFFSET) +#define LPC17_40_UART3_FDR (LPC17_40_UART3_BASE+LPC17_40_UART_FDR_OFFSET) +#define LPC17_40_UART3_TER (LPC17_40_UART3_BASE+LPC17_40_UART_TER_OFFSET) + +#ifdef LPC178x_40xx +# define LPC17_40_UART3_RS485CTRL (LPC17_40_UART3_BASE+LPC17_40_UART_RS485CTRL_OFFSET) +# define LPC17_40_UART3_ADRMATCH (LPC17_40_UART3_BASE+LPC17_40_UART_ADRMATCH_OFFSET) +# define LPC17_40_UART3_RS485DLY (LPC17_40_UART3_BASE+LPC17_40_UART_RS485DLY_OFFSET) +#endif + +#define LPC17_40_UART3_FIFOLVL (LPC17_40_UART3_BASE+LPC17_40_UART_FIFOLVL_OFFSET) + +#ifdef LPC178x_40xx +# define LPC17_40_UART4_RBR (LPC17_40_UART4_BASE+LPC17_40_UART_RBR_OFFSET) +# define LPC17_40_UART4_THR (LPC17_40_UART4_BASE+LPC17_40_UART_THR_OFFSET) +# define LPC17_40_UART4_DLL (LPC17_40_UART4_BASE+LPC17_40_UART_DLL_OFFSET) +# define LPC17_40_UART4_DLM (LPC17_40_UART4_BASE+LPC17_40_UART_DLM_OFFSET) +# define LPC17_40_UART4_IER (LPC17_40_UART4_BASE+LPC17_40_UART_IER_OFFSET) +# define LPC17_40_UART4_IIR (LPC17_40_UART4_BASE+LPC17_40_UART_IIR_OFFSET) +# define LPC17_40_UART4_FCR (LPC17_40_UART4_BASE+LPC17_40_UART_FCR_OFFSET) +# define LPC17_40_UART4_LCR (LPC17_40_UART4_BASE+LPC17_40_UART_LCR_OFFSET) +# define LPC17_40_UART4_LSR (LPC17_40_UART4_BASE+LPC17_40_UART_LSR_OFFSET) +# define LPC17_40_UART4_SCR (LPC17_40_UART4_BASE+LPC17_40_UART_SCR_OFFSET) +# define LPC17_40_UART4_ACR (LPC17_40_UART4_BASE+LPC17_40_UART_ACR_OFFSET) +# define LPC17_40_UART4_ICR (LPC17_40_UART4_BASE+LPC17_40_UART_ICR_OFFSET) +# define LPC17_40_UART4_FDR (LPC17_40_UART4_BASE+LPC17_40_UART_FDR_OFFSET) +# define LPC17_40_UART4_TER (LPC17_40_UART4_BASE+LPC17_40_UART_TER_OFFSET) +# define LPC17_40_UART4_RS485CTRL (LPC17_40_UART4_BASE+LPC17_40_UART_RS485CTRL_OFFSET) +# define LPC17_40_UART4_ADRMATCH (LPC17_40_UART4_BASE+LPC17_40_UART_ADRMATCH_OFFSET) +# define LPC17_40_UART4_RS485DLY (LPC17_40_UART4_BASE+LPC17_40_UART_RS485DLY_OFFSET) +# define LPC17_40_UART4_FIFOLVL (LPC17_40_UART4_BASE+LPC17_40_UART_FIFOLVL_OFFSET) +# define LPC17_40_UART4_OSR (LPC17_40_UART4_BASE+LPC17_40_UART4_OSR_OFFSET) +# define LPC17_40_UART4_SCICTRL (LPC17_40_UART4_BASE+LPC17_40_UART4_SCICTRL_OFFSET) +# define LPC17_40_UART4_SYNCCTRL (LPC17_40_UART4_BASE+LPC17_40_UART4_SYNCCTRL_OFFSET) +#endif + +/* Register bit definitions *********************************************************/ + +/* RBR (DLAB =0) Receiver Buffer Register (all) */ + +#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ + /* Bits 8-31: Reserved */ + +/* THR (DLAB =0) Transmit Holding Register (all) */ + +#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ + /* Bits 8-31: Reserved */ + +/* DLL (DLAB =1) Divisor Latch LSB (all) */ + +#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ + /* Bits 8-31: Reserved */ + +/* DLM (DLAB =1) Divisor Latch MSB (all) */ + +#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ + /* Bits 8-31: Reserved */ + +/* IER (DLAB =0) Interrupt Enable Register (all) */ + +#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */ +#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */ +#define UART_IER_RLSIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */ +#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART1 only) */ + /* Bits 4-6: Reserved */ +#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART1 only) */ +#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ +#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ + /* Bits 10-31: Reserved */ +#define UART_IER_ALLIE (0x038f) + +/* IIR Interrupt ID Register (all) */ + +#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ +#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ +#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) +# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */ +# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ +# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */ +# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ +# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ + /* Bits 4-5: Reserved */ +#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ +#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) +#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ +#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ + /* Bits 10-31: Reserved */ +/* FCR FIFO Control Register (all) */ + +#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ +#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ +#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ +#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */ + /* Bits 4-5: Reserved */ +#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ +#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) +# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ +# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ +# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ +# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ + /* Bits 8-31: Reserved */ +/* LCR Line Control Register (all) */ + +#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ +#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) +#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */ +#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */ +#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */ +#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT) +# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */ +# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */ +# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */ +# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */ +#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ +#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ + /* Bits 8-31: Reserved */ +/* MCR Modem Control Register (UART1 only) */ + +#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ +#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ + /* Bits 2-3: Reserved */ +#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ + /* Bit 5: Reserved */ +#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */ +#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */ + /* Bits 8-31: Reserved */ +/* LSR Line Status Register (all) */ + +#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */ +#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ +#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ +#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ +#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ +#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ +#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ +#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ + /* Bits 8-31: Reserved */ +/* MSR Modem Status Register (UART1 only) */ + +#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */ +#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */ +#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */ +#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */ +#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */ +#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */ +#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */ +#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */ + /* Bits 8-31: Reserved */ +/* SCR Scratch Pad Register (all) */ + +#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ + /* Bits 8-31: Reserved */ +/* ACR Auto-baud Control Register (all) */ + +#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/ +#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/ +#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/ + /* Bits 3-7: Reserved */ +#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ +#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ + /* Bits 10-31: Reserved */ +/* ICA IrDA Control Register (UART0,2,3 only) */ + +#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */ +#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */ +#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */ +#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT) +# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */ +# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */ +# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */ +# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */ +# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */ +# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */ +# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */ +# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 246 x TPCLK */ + /* Bits 6-31: Reserved */ +/* FDR Fractional Divider Register (all) */ + +#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */ +#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT) +#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */ +#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT) + /* Bits 8-31: Reserved */ +/* TER Transmit Enable Register (all) */ + /* Bits 0-6: Reserved */ +#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */ + /* Bits 8-31: Reserved */ +/* RS-485/EIA-485 Control (UART1 only) */ + +#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */ +#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */ +#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */ +#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */ +#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */ +#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */ + /* Bits 6-31: Reserved */ +/* RS-485/EIA-485 address match (UART1 only) */ + +#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */ + /* Bits 8-31: Reserved */ +/* RS-485/EIA-485 direction control delay (UART1 only) */ + +#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */ + /* Bits 8-31: Reserved */ +/* FIFOLVL FIFO Level register (all) */ + +#define UART_FIFOLVL_RX_SHIFT (0) /* Bits 0-3: Current level of the UART RX FIFO */ +#define UART_FIFOLVL_RX_MASK (15 << UART_FIFOLVL_RX_SHIFT) + /* Bits 4-7: Reserved */ +#define UART_FIFOLVL_TX_SHIFT (8) /* Bits 8-11: Current level of the UART TX FIFO */ +#define UART_FIFOLVL_TX_MASK (15 << UART_FIFOLVL_TX_SHIFT) + /* Bits 12-31: Reserved */ + +/* SCICTL Smart Card Interface (UART4 only) */ + +#ifdef LPC178x_40xx +# define UART_SCIEN (1 << 0) /* Bit 0: Smart Card Interface enable */ +# define UART_NACKDIS (1 << 1) /* Bit 1: NACK response disable.Applicable if PROTSEL=0 */ +# define UART_PROTSEL (1 << 2) /* Bit 2: Protocol Selection ISO7816-3 */ +# define UART_TXRETRY (7 << 5) /* Bits 5-7: Maximum number of Re-Transmission */ +# define UART_GUARDTIME_SHIFT (8) /* Bits 8-15: Extra guard time */ +# define UART_GUARDTIME_MASK (0xff << UART_GUARDTIME_SHIFT) + /* Bits 16-31: Reserved */ +#endif + +/* OSR Oversampling Register (UART4 only) */ + +#ifdef LPC178x_40xx + /* Bit 0: Reserved */ +# define UART_OSFRAC (7 << 1) /* Bits 1-3: Fractional part of Oversampling Ratio */ +# define UART_OSINT_SHIFT (4) /* Bits 4-7: Integer part of (Oversampling Ratio -1) */ +# define UART_OSINT_MASK (0x0f << UART_OSINT_SHIFT) +# define UART_FDINT_SHIFT (8) /* Bits 8-14: OSINT extension in Smart Card mode */ +# define UART_FDINT_MASK (0x7f << UART_FDINT_SHIFT) + /* Bits 15-31: Reserved */ +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_UART_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h new file mode 100644 index 00000000000..d0248b30590 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h @@ -0,0 +1,778 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_USB_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_USB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +#define LPC17_40_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_40_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ +#define LPC17_40_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ +#define LPC17_40_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ +#define LPC17_40_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ +#define LPC17_40_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ +#define LPC17_40_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_40_syscon.h */ + +#define LPC17_40_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ +#define LPC17_40_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ +#define LPC17_40_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ +#define LPC17_40_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ + +/* SIE Command registers */ + +#define LPC17_40_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ +#define LPC17_40_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ + +/* USB transfer registers */ + +#define LPC17_40_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ +#define LPC17_40_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ +#define LPC17_40_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ +#define LPC17_40_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ +#define LPC17_40_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ + +/* More Device interrupt registers */ + +#define LPC17_40_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ + +/* Endpoint interrupt registers */ + +#define LPC17_40_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ +#define LPC17_40_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ +#define LPC17_40_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ +#define LPC17_40_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ +#define LPC17_40_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ + +/* Endpoint realization registers */ + +#define LPC17_40_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ +#define LPC17_40_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ +#define LPC17_40_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ + +/* DMA registers */ + +#define LPC17_40_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ +#define LPC17_40_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ +#define LPC17_40_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ +#define LPC17_40_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ +#define LPC17_40_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ +#define LPC17_40_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ +#define LPC17_40_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ +#define LPC17_40_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ +#define LPC17_40_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ +#define LPC17_40_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ +#define LPC17_40_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ +#define LPC17_40_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ +#define LPC17_40_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ +#define LPC17_40_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ +#define LPC17_40_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ +#define LPC17_40_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ +#define LPC17_40_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ +#define LPC17_40_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_40_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ +#define LPC17_40_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ +#define LPC17_40_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ +#define LPC17_40_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ +#define LPC17_40_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ +#define LPC17_40_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ + +/* Clock control registers ***********************************************************/ + +#define LPC17_40_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ +#define LPC17_40_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ + +#define LPC17_40_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ +#define LPC17_40_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ + +/* Register addresses ***************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* Control and status registers (section 7.1) */ + +#define LPC17_40_USBHOST_HCIREV (LPC17_40_USB_BASE+OHCI_HCIREV_OFFSET) +#define LPC17_40_USBHOST_CTRL (LPC17_40_USB_BASE+OHCI_CTRL_OFFSET) +#define LPC17_40_USBHOST_CMDST (LPC17_40_USB_BASE+OHCI_CMDST_OFFSET) +#define LPC17_40_USBHOST_INTST (LPC17_40_USB_BASE+OHCI_INTST_OFFSET) +#define LPC17_40_USBHOST_INTEN (LPC17_40_USB_BASE+OHCI_INTEN_OFFSET) +#define LPC17_40_USBHOST_INTDIS (LPC17_40_USB_BASE+OHCI_INTDIS_OFFSET) + +/* Memory pointers (section 7.2) */ + +#define LPC17_40_USBHOST_HCCA (LPC17_40_USB_BASE+OHCI_HCCA_OFFSET) +#define LPC17_40_USBHOST_PERED (LPC17_40_USB_BASE+OHCI_PERED_OFFSET) +#define LPC17_40_USBHOST_CTRLHEADED (LPC17_40_USB_BASE+OHCI_CTRLHEADED_OFFSET) +#define LPC17_40_USBHOST_CTRLED (LPC17_40_USB_BASE+OHCI_CTRLED_OFFSET) +#define LPC17_40_USBHOST_BULKHEADED (LPC17_40_USB_BASE+OHCI_BULKHEADED_OFFSET) +#define LPC17_40_USBHOST_BULKED (LPC17_40_USB_BASE+OHCI_BULKED_OFFSET) +#define LPC17_40_USBHOST_DONEHEAD (LPC17_40_USB_BASE+OHCI_DONEHEAD_OFFSET) + +/* Frame counters (section 7.3) */ + +#define LPC17_40_USBHOST_FMINT (LPC17_40_USB_BASE+OHCI_FMINT_OFFSET) +#define LPC17_40_USBHOST_FMREM (LPC17_40_USB_BASE+OHCI_FMREM_OFFSET) +#define LPC17_40_USBHOST_FMNO (LPC17_40_USB_BASE+OHCI_FMNO_OFFSET) +#define LPC17_40_USBHOST_PERSTART (LPC17_40_USB_BASE+OHCI_PERSTART_OFFSET) + +/* Root hub ports (section 7.4) */ + +#define LPC17_40_USBHOST_LSTHRES (LPC17_40_USB_BASE+OHCI_LSTHRES_OFFSET) +#define LPC17_40_USBHOST_RHDESCA (LPC17_40_USB_BASE+OHCI_RHDESCA_OFFSET) +#define LPC17_40_USBHOST_RHDESCB (LPC17_40_USB_BASE+OHCI_RHDESCB_OFFSET) +#define LPC17_40_USBHOST_RHSTATUS (LPC17_40_USB_BASE+OHCI_RHSTATUS_OFFSET) +#define LPC17_40_USBHOST_RHPORTST1 (LPC17_40_USB_BASE+OHCI_RHPORTST1_OFFSET) +#define LPC17_40_USBHOST_RHPORTST2 (LPC17_40_USB_BASE+OHCI_RHPORTST2_OFFSET) +#define LPC17_40_USBHOST_MODID (LPC17_40_USB_BASE+LPC17_40_USBHOST_MODID_OFFSET) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_40_USBOTG_INTST (LPC17_40_USB_BASE+LPC17_40_USBOTG_INTST_OFFSET) +#define LPC17_40_USBOTG_INTEN (LPC17_40_USB_BASE+LPC17_40_USBOTG_INTEN_OFFSET) +#define LPC17_40_USBOTG_INTSET (LPC17_40_USB_BASE+LPC17_40_USBOTG_INTSET_OFFSET) +#define LPC17_40_USBOTG_INTCLR (LPC17_40_USB_BASE+LPC17_40_USBOTG_INTCLR_OFFSET) +#define LPC17_40_USBOTG_STCTRL (LPC17_40_USB_BASE+LPC17_40_USBOTG_STCTRL_OFFSET) +#define LPC17_40_USBOTG_TMR (LPC17_40_USB_BASE+LPC17_40_USBOTG_TMR_OFFSET) + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_40_syscon.h */ + +#define LPC17_40_USBDEV_INTST (LPC17_40_USB_BASE+LPC17_40_USBDEV_INTST_OFFSET) +#define LPC17_40_USBDEV_INTEN (LPC17_40_USB_BASE+LPC17_40_USBDEV_INTEN_OFFSET) +#define LPC17_40_USBDEV_INTCLR (LPC17_40_USB_BASE+LPC17_40_USBDEV_INTCLR_OFFSET) +#define LPC17_40_USBDEV_INTSET (LPC17_40_USB_BASE+LPC17_40_USBDEV_INTSET_OFFSET) + +/* SIE Command registers */ + +#define LPC17_40_USBDEV_CMDCODE (LPC17_40_USB_BASE+LPC17_40_USBDEV_CMDCODE_OFFSET) +#define LPC17_40_USBDEV_CMDDATA (LPC17_40_USB_BASE+LPC17_40_USBDEV_CMDDATA_OFFSET) + +/* USB transfer registers */ + +#define LPC17_40_USBDEV_RXDATA (LPC17_40_USB_BASE+LPC17_40_USBDEV_RXDATA_OFFSET) +#define LPC17_40_USBDEV_RXPLEN (LPC17_40_USB_BASE+LPC17_40_USBDEV_RXPLEN_OFFSET) +#define LPC17_40_USBDEV_TXDATA (LPC17_40_USB_BASE+LPC17_40_USBDEV_TXDATA_OFFSET) +#define LPC17_40_USBDEV_TXPLEN (LPC17_40_USB_BASE+LPC17_40_USBDEV_TXPLEN_OFFSET) +#define LPC17_40_USBDEV_CTRL (LPC17_40_USB_BASE+LPC17_40_USBDEV_CTRL_OFFSET) + +/* More Device interrupt registers */ + +#define LPC17_40_USBDEV_INTPRI (LPC17_40_USB_BASE+LPC17_40_USBDEV_INTPRI_OFFSET) + +/* Endpoint interrupt registers */ + +#define LPC17_40_USBDEV_EPINTST (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPINTST_OFFSET) +#define LPC17_40_USBDEV_EPINTEN (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPINTEN_OFFSET) +#define LPC17_40_USBDEV_EPINTCLR (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPINTCLR_OFFSET) +#define LPC17_40_USBDEV_EPINTSET (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPINTSET_OFFSET) +#define LPC17_40_USBDEV_EPINTPRI (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPINTPRI_OFFSET) + +/* Endpoint realization registers */ + +#define LPC17_40_USBDEV_REEP (LPC17_40_USB_BASE+LPC17_40_USBDEV_REEP_OFFSET) +#define LPC17_40_USBDEV_EPIND (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPIND_OFFSET) +#define LPC17_40_USBDEV_MAXPSIZE (LPC17_40_USB_BASE+LPC17_40_USBDEV_MAXPSIZE_OFFSET) + +/* DMA registers */ + +#define LPC17_40_USBDEV_DMARST (LPC17_40_USB_BASE+LPC17_40_USBDEV_DMARST_OFFSET) +#define LPC17_40_USBDEV_DMARCLR (LPC17_40_USB_BASE+LPC17_40_USBDEV_DMARCLR_OFFSET) +#define LPC17_40_USBDEV_DMARSET (LPC17_40_USB_BASE+LPC17_40_USBDEV_DMARSET_OFFSET) +#define LPC17_40_USBDEV_UDCAH (LPC17_40_USB_BASE+LPC17_40_USBDEV_UDCAH_OFFSET) +#define LPC17_40_USBDEV_EPDMAST (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPDMAST_OFFSET) +#define LPC17_40_USBDEV_EPDMAEN (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPDMAEN_OFFSET) +#define LPC17_40_USBDEV_EPDMADIS (LPC17_40_USB_BASE+LPC17_40_USBDEV_EPDMADIS_OFFSET) +#define LPC17_40_USBDEV_DMAINTST (LPC17_40_USB_BASE+LPC17_40_USBDEV_DMAINTST_OFFSET) +#define LPC17_40_USBDEV_DMAINTEN (LPC17_40_USB_BASE+LPC17_40_USBDEV_DMAINTEN_OFFSET) +#define LPC17_40_USBDEV_EOTINTST (LPC17_40_USB_BASE+LPC17_40_USBDEV_EOTINTST_OFFSET) +#define LPC17_40_USBDEV_EOTINTCLR (LPC17_40_USB_BASE+LPC17_40_USBDEV_EOTINTCLR_OFFSET) +#define LPC17_40_USBDEV_EOTINTSET (LPC17_40_USB_BASE+LPC17_40_USBDEV_EOTINTSET_OFFSET) +#define LPC17_40_USBDEV_NDDRINTST (LPC17_40_USB_BASE+LPC17_40_USBDEV_NDDRINTST_OFFSET) +#define LPC17_40_USBDEV_NDDRINTCLR (LPC17_40_USB_BASE+LPC17_40_USBDEV_NDDRINTCLR_OFFSET) +#define LPC17_40_USBDEV_NDDRINTSET (LPC17_40_USB_BASE+LPC17_40_USBDEV_NDDRINTSET_OFFSET) +#define LPC17_40_USBDEV_SYSERRINTST (LPC17_40_USB_BASE+LPC17_40_USBDEV_SYSERRINTST_OFFSET) +#define LPC17_40_USBDEV_SYSERRINTCLR (LPC17_40_USB_BASE+LPC17_40_USBDEV_SYSERRINTCLR_OFFSET) +#define LPC17_40_USBDEV_SYSERRINTSET (LPC17_40_USB_BASE+LPC17_40_USBDEV_SYSERRINTSET_OFFSET) + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_40_OTGI2C_RX (LPC17_40_USB_BASE+LPC17_40_OTGI2C_RX_OFFSET) +#define LPC17_40_OTGI2C_TX (LPC17_40_USB_BASE+LPC17_40_OTGI2C_TX_OFFSET) +#define LPC17_40_OTGI2C_STS (LPC17_40_USB_BASE+LPC17_40_OTGI2C_STS_OFFSET) +#define LPC17_40_OTGI2C_CTL (LPC17_40_USB_BASE+LPC17_40_OTGI2C_CTL_OFFSET) +#define LPC17_40_OTGI2C_CLKHI (LPC17_40_USB_BASE+LPC17_40_OTGI2C_CLKHI_OFFSET) +#define LPC17_40_OTGI2C_CLKLO (LPC17_40_USB_BASE+LPC17_40_OTGI2C_CLKLO_OFFSET) + +/* Clock control registers ***********************************************************/ + +#define LPC17_40_USBOTG_CLKCTRL (LPC17_40_USB_BASE+LPC17_40_USBOTG_CLKCTRL_OFFSET) +#define LPC17_40_USBOTG_CLKST (LPC17_40_USB_BASE+LPC17_40_USBOTG_CLKST_OFFSET) + +#define LPC17_40_USBDEV_CLKCTRL (LPC17_40_USB_BASE+LPC17_40_USBDEV_CLKCTRL_OFFSET) +#define LPC17_40_USBDEV_CLKST (LPC17_40_USB_BASE+LPC17_40_USBDEV_CLKST_OFFSET) + +/* Register bit definitions *********************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +/* Module ID/Revision ID */ + +#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ +#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) +#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ +#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) +#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ +#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) +# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers: + * + * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt + * Clear + */ + +#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ +#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ +#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ +#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ + /* Bits 4-31: Reserved */ +/* OTG Status and Control */ + +#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ +#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) +# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ +#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ +#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) +# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ +#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ +#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ +#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ + /* Bit 7: Reserved */ +#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ +#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ +#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ + /* Bits 11-15: Reserved */ +#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ +#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) + +/* OTG Timer */ + +#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ +#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) + /* Bits 16-31: Reserved */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_40_syscon.h */ +/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt + * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority + */ + +#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ +#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ +#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ +#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ +#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ +#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ +#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ +#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ +#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ +#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ + /* Bits 10-31: Reserved */ +/* SIE Command registers: + * + * USB Command Code + */ + /* Bits 0-7: Reserved */ +#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ +#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) +#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ +#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) +#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ +#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) + /* Bits 24-31: Reserved */ +/* USB Command Data */ + +#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ +#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) + /* Bits 8-31: Reserved */ +/* USB transfer registers: + * + * USB Receive Data (Bits 0-31: Received data) + */ + +/* USB Receive Packet Length */ + +#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ +#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) +#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ +#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ + /* Bits 12-31: Reserved */ +/* USB Transmit Data (Bits 0-31: Transmit data) */ + +/* USB Transmit Packet Length */ + +#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ +#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) + /* Bits 10-31: Reserved */ +/* USB Control */ + +#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ +#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ +#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ +#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) + /* Bits 6-31: Reserved */ +/* Endpoint interrupt registers: + * + * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt + * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond + * to on RX or TX value for any of 15 logical endpoints). + */ + +#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) +#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) +#define USBDEV_LOGEPRX0 (1 << 0) +#define USBDEV_LOGEPTX0 (1 << 1) +#define USBDEV_LOGEPRX1 (1 << 2) +#define USBDEV_LOGEPTX1 (1 << 3) +#define USBDEV_LOGEPRX2 (1 << 4) +#define USBDEV_LOGEPTX2 (1 << 5) +#define USBDEV_LOGEPRX3 (1 << 6) +#define USBDEV_LOGEPTX3 (1 << 7) +#define USBDEV_LOGEPRX4 (1 << 8) +#define USBDEV_LOGEPTX4 (1 << 9) +#define USBDEV_LOGEPRX5 (1 << 10) +#define USBDEV_LOGEPTX5 (1 << 11) +#define USBDEV_LOGEPRX6 (1 << 12) +#define USBDEV_LOGEPTX6 (1 << 13) +#define USBDEV_LOGEPRX7 (1 << 14) +#define USBDEV_LOGEPTX7 (1 << 15) +#define USBDEV_LOGEPRX8 (1 << 16) +#define USBDEV_LOGEPTX8 (1 << 17) +#define USBDEV_LOGEPRX9 (1 << 18) +#define USBDEV_LOGEPTX9 (1 << 19) +#define USBDEV_LOGEPRX10 (1 << 20) +#define USBDEV_LOGEPTX10 (1 << 21) +#define USBDEV_LOGEPRX11 (1 << 22) +#define USBDEV_LOGEPTX11 (1 << 23) +#define USBDEV_LOGEPRX12 (1 << 24) +#define USBDEV_LOGEPTX12 (1 << 25) +#define USBDEV_LOGEPRX13 (1 << 26) +#define USBDEV_LOGEPTX13 (1 << 27) +#define USBDEV_LOGEPRX14 (1 << 28) +#define USBDEV_LOGEPTX14 (1 << 29) +#define USBDEV_LOGEPRX15 (1 << 30) +#define USBDEV_LOGEPTX15 (1 << 31) + +/* Endpoint realization registers: + * + * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) + */ + +#define USBDEV_PHYEP(n) (1 << (n)) +#define USBDEV_PHYEP0 (1 << 0) +#define USBDEV_PHYEP1 (1 << 1) +#define USBDEV_PHYEP2 (1 << 2) +#define USBDEV_PHYEP3 (1 << 3) +#define USBDEV_PHYEP4 (1 << 4) +#define USBDEV_PHYEP5 (1 << 5) +#define USBDEV_PHYEP6 (1 << 6) +#define USBDEV_PHYEP7 (1 << 7) +#define USBDEV_PHYEP8 (1 << 8) +#define USBDEV_PHYEP9 (1 << 9) +#define USBDEV_PHYEP10 (1 << 10) +#define USBDEV_PHYEP11 (1 << 11) +#define USBDEV_PHYEP12 (1 << 12) +#define USBDEV_PHYEP13 (1 << 13) +#define USBDEV_PHYEP14 (1 << 14) +#define USBDEV_PHYEP15 (1 << 15) +#define USBDEV_PHYEP16 (1 << 16) +#define USBDEV_PHYEP17 (1 << 17) +#define USBDEV_PHYEP18 (1 << 18) +#define USBDEV_PHYEP19 (1 << 19) +#define USBDEV_PHYEP20 (1 << 20) +#define USBDEV_PHYEP21 (1 << 21) +#define USBDEV_PHYEP22 (1 << 22) +#define USBDEV_PHYEP23 (1 << 23) +#define USBDEV_PHYEP24 (1 << 24) +#define USBDEV_PHYEP25 (1 << 25) +#define USBDEV_PHYEP26 (1 << 26) +#define USBDEV_PHYEP27 (1 << 27) +#define USBDEV_PHYEP28 (1 << 28) +#define USBDEV_PHYEP29 (1 << 29) +#define USBDEV_PHYEP30 (1 << 30) +#define USBDEV_PHYEP31 (1 << 31) + +/* USB Endpoint Index */ + +#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ +#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) + /* Bits 5-31: Reserved */ +/* USB MaxPacketSize */ + +#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ +#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) + /* Bits 10-31: Reserved */ +/* DMA registers: + * + * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers + * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions + * above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB UDCA Head */ + /* Bits 0-6: Reserved */ +#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ +#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) + +/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. + * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* + * definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ + +#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ +#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ +#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ + /* Bits 3-31: Reserved */ +/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB + * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB + * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System + * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use + * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* OTG I2C registers ****************************************************************/ + +/* I2C Receive */ + +#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ +#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Transmit */ + +#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ +#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) +#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ +#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ + /* Bits 3-31: Reserved */ +/* I2C Status */ + +#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ +#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ +#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ +#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ +#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ +#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ +#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ +#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ +#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ +#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ +#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ +#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ + /* Bits 12-31: Reserved */ +/* I2C Control */ + +#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ +#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ +#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ +#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ +#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ +#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ +#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ + /* Bits 9-31: Reserved */ +/* I2C Clock High */ + +#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Clock Low */ + +#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) + /* Bits 8-31: Reserved */ +/* Clock control registers ***********************************************************/ + +/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ + +#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ +#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ +#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ +#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ +#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ +#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ + /* Bits 5-31: Reserved */ +/* Alternate naming */ + +#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK +#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK +#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK +#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK +#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK +#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK + +/* Endpoints *************************************************************************/ + +#define LPC17_40_EP0_OUT 0 +#define LPC17_40_EP0_IN 1 +#define LPC17_40_CTRLEP_OUT LPC17_40_EP0_OUT +#define LPC17_40_CTRLEP_IN LPC17_40_EP0_IN +#define LPC17_40_EP1_OUT 2 +#define LPC17_40_EP1_IN 3 +#define LPC17_40_EP2_OUT 4 +#define LPC17_40_EP2_IN 5 +#define LPC17_40_EP3_OUT 6 +#define LPC17_40_EP3_IN 7 +#define LPC17_40_EP4_OUT 8 +#define LPC17_40_EP4_IN 9 +#define LPC17_40_EP5_OUT 10 +#define LPC17_40_EP5_IN 11 +#define LPC17_40_EP6_OUT 12 +#define LPC17_40_EP6_IN 13 +#define LPC17_40_EP7_OUT 14 +#define LPC17_40_EP7_IN 15 +#define LPC17_40_EP8_OUT 16 +#define LPC17_40_EP8_IN 17 +#define LPC17_40_EP9_OUT 18 +#define LPC17_40_EP9_IN 19 +#define LPC17_40_EP10_OUT 20 +#define LPC17_40_EP10_IN 21 +#define LPC17_40_EP11_OUT 22 +#define LPC17_40_EP11_IN 23 +#define LPC17_40_EP12_OUT 24 +#define LPC17_40_EP12_IN 25 +#define LPC17_40_EP13_OUT 26 +#define LPC17_40_EP13_IN 27 +#define LPC17_40_EP14_OUT 28 +#define LPC17_40_EP14_IN 29 +#define LPC17_40_EP15_OUT 30 +#define LPC17_40_EP15_IN 31 +#define LPC17_40_NUMEPS 32 + +/* Commands *************************************************************************/ + +/* USB Command Code Register */ + +#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ +#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) +#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ +#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) +#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT +#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK + +/* Device Commands */ + +#define CMD_USBDEV_SETADDRESS (0x00d0) +#define CMD_USBDEV_CONFIG (0x00d8) +#define CMD_USBDEV_SETMODE (0x00f3) +#define CMD_USBDEV_READFRAMENO (0x00f5) +#define CMD_USBDEV_READTESTREG (0x00fd) +#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ +#define CMD_USBDEV_GETSTATUS (0x00fe) +#define CMD_USBDEV_GETERRORCODE (0x00ff) +#define CMD_USBDEV_READERRORSTATUS (0x00fb) + +/* Endpoint Commands */ + +#define CMD_USBDEV_EPSELECT (0x0000) +#define CMD_USBDEV_EPSELECTCLEAR (0x0040) +#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ +#define CMD_USBDEV_EPCLRBUFFER (0x00f2) +#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) + +/* Command/response bit definitions ********************************************/ +/* SETADDRESS (0xd0) command definitions */ + +#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ +#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ + +/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ + +#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ +#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ +#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ +#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ +#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ + +/* EPSELECT (0x00) endpoint status response */ + +#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ +#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ +#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ +#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ +#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ +#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ +#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ + /* Bit 7: Reserved */ +/* EPSETSTATUS (0x40) command */ + +#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ + /* Bits 1-4: Reserved */ +#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ +#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ +#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ + +/* EPCLRBUFFER (0xf2) response */ + +#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) + +/* SETMODE(0xf3) command */ + +#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ +#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ +#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ +#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ +#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ +#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ +#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ + +/* READERRORSTATUS (0xFb) command */ + +#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ +#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ +#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ +#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ +#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ +#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ +#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ +#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ +#define CMD_READERRORSTATUS_ALLERRS (0xff) + +/* DMA ******************************************************************************/ +/* The DMA descriptor */ + +#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ +#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ +#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ +#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ +#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ + +/* Bit settings for CONFIG (offset 1 )*/ + +#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ +#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) +# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ +# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ +#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ + /* Bit 3: Reserved */ +#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ +#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ +#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) +#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ +#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT + +/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ + +#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ +#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) +#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ +#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ +#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ +#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ +#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) +#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ +#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) + +/* DMA packet size format */ + +#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ +#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) +#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ +#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ +#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_USB_H */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h new file mode 100644 index 00000000000..26a257ea694 --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h @@ -0,0 +1,156 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_WDT_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_WDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/lpc17_40_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_40_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */ +#define LPC17_40_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */ +#define LPC17_40_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */ +#define LPC17_40_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */ + +#ifdef LPC176x +# define LPC17_40_WDT_CLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ +#endif + +#ifdef LPC178x_40xx +# define LPC17_40_WDT_WARNINT_OFFSET 0x0014 /* Watchdog warning interrupt */ +# define LPC17_40_WDT_WINDOW_OFFSET 0x0018 /* Watchdog window compare value */ +#endif + +/* Register addresses ***************************************************************/ + +#define LPC17_40_WDT_MOD (LPC17_40_WDT_BASE+LPC17_40_WDT_MOD_OFFSET) +#define LPC17_40_WDT_TC (LPC17_40_WDT_BASE+LPC17_40_WDT_TC_OFFSET) +#define LPC17_40_WDT_FEED (LPC17_40_WDT_BASE+LPC17_40_WDT_FEED_OFFSET) +#define LPC17_40_WDT_TV (LPC17_40_WDT_BASE+LPC17_40_WDT_TV_OFFSET) +#define LPC17_40_WDT_CLKSEL (LPC17_40_WDT_BASE+LPC17_40_WDT_CLKSEL_OFFSET) + +#ifdef LPC178x_40xx +# define LPC17_40_WDT_WARNINT (LPC17_40_WDT_BASE+LPC17_40_WDT_WARNINT_OFFSET) +# define LPC17_40_WDT_WINDOW (LPC17_40_WDT_BASE+LPC17_40_WDT_WINDOW_OFFSET) +#endif + +/* Register bit definitions *********************************************************/ + +/* Watchdog mode register */ + +#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ +#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ +#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ +#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ +#ifdef LPC178x_40xx +# define WDT_MOD_WDPROTECT (1 << 4) /* Bit 4: Watchdog interrupt */ +#endif + /* Bits 5-31: Reserved */ +/* Watchdog timer constant register */ + +#ifdef LPC176x +# define WDT_TC (0xffffffff) /* Bits 0-31: Watchdog time-out interval */ +#endif +#ifdef LPC178x_40xx +# define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */ + /* Bits 24-31: Reserved */ +#endif + +/* Watchdog feed sequence register */ + +#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa + * followed by 0x55 */ + /* Bits 14-31: Reserved */ +/* Watchdog timer value register */ + +#ifdef LPC176x +# define WDT_TVT (0xffffffff) /* Bits 0-31: Watchdog timer value */ +#endif +#ifdef LPC178x_40xx +# define WDT_TVT (0xffffff) /* Bits 0-23: Watchdog timer value */ + /* Bits 24-31: Reserved */ +#endif + +/* Watchdog clock source selection register */ + +#ifdef LPC176x +# define WDT_CLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ +# define WDT_CLKSEL_WDSEL_MASK (3 << WDT_CLKSEL_WDSEL_SHIFT) +# define WDT_CLKSEL_WDSEL_INTRC (0 << WDT_CLKSEL_WDSEL_SHIFT) /* Internal RC osc */ +# define WDT_CLKSEL_WDSEL_APB (1 << WDT_CLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ +# define WDT_CLKSEL_WDSEL_RTC (2 << WDT_CLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ + /* Bits 2-30: Reserved */ +# define WDT_CLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ +#endif + +/* Watchdog timer warning interrupt register */ + +#ifdef LPC178x_40xx +# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */ + /* Bits 10-31: Reserved */ +#endif + +/* Watchdog timer value register */ + +#ifdef LPC178x_40xx +# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */ + /* Bits 24-31: Reserved */ +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_WDT_H */ diff --git a/arch/arm/src/lpc17xx/lpc176x_clockconfig.c b/arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c similarity index 71% rename from arch/arm/src/lpc17xx/lpc176x_clockconfig.c rename to arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c index cc9cc89b8b3..c857e8a27af 100644 --- a/arch/arm/src/lpc17xx/lpc176x_clockconfig.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c @@ -1,6 +1,6 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_clockconfig.c - * arch/arm/src/chip/lpc17_clockconfig.c + * arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c + * arch/arm/src/chip/lpc17_40_clockconfig.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,8 +48,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_clockconfig.h" -#include "hardware/lpc17_syscon.h" +#include "lpc17_40_clockconfig.h" +#include "hardware/lpc17_40_syscon.h" /**************************************************************************** * Pre-processor Definitions @@ -76,30 +76,30 @@ ****************************************************************************/ /************************************************************************************ - * Name: lpc17_clockconfig + * Name: lpc17_40_clockconfig * * Description: * Called to initialize the LPC176x. This does whatever setup is needed to put the * SoC in a usable state. This includes the initialization of clocking using the * settings in board.h. * - * The LPC176x and LPC178x system control block is *nearly* identical but we have - * found that the LPC178x is more sensitive to the ordering of certain operations. + * The LPC176x and LPC178x/40xx system control block is *nearly* identical but we have + * found that the LPC178x/40xx is more sensitive to the ordering of certain operations. * So, although the hardware seems very similar, the safer thing to do is to - * separate the LPC176x and LPC178x into separate files. + * separate the LPC176x and LPC178x/40xx into separate files. * ************************************************************************************/ -void lpc17_clockconfig(void) +void lpc17_40_clockconfig(void) { /* Enable the main oscillator (or not) and the frequency range of the main oscillator */ - putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS); + putreg32(BOARD_SCS_VALUE, LPC17_40_SYSCON_SCS); /* Wait for the main oscillator to be ready. */ -#ifdef CONFIG_LPC17_MAINOSC - while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); +#ifdef CONFIG_LPC17_40_MAINOSC + while ((getreg32(LPC17_40_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); #endif /* Setup up the divider value for the CPU clock. The output of the divider is CCLK. @@ -109,112 +109,112 @@ void lpc17_clockconfig(void) * configured. */ - putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG); + putreg32(BOARD_CCLKCFG_VALUE, LPC17_40_SYSCON_CCLKCFG); /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */ -#ifdef CONFIG_LPC17_PLL0 +#ifdef CONFIG_LPC17_40_PLL0 /* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that * a special "feed" sequence must be written to the PLL0FEED register in order * for changes to the PLL0CFG register to take effect. */ - putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL); - putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG); - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); + putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_40_SYSCON_CLKSRCSEL); + putreg32(BOARD_PLL0CFG_VALUE, LPC17_40_SYSCON_PLL0CFG); + putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL0FEED); /* Enable the PLL. NOTE that a special "feed" sequence must be written to the * PLL0FEED register in order for changes to the PLL0CON register to take effect. */ - putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON); - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); + putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL0CON); + putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL0FEED); /* Wait for PLL0 to lock */ - while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); + while ((getreg32(LPC17_40_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); /* Enable and connect PLL0 */ - putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON); - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); + putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_40_SYSCON_PLL0CON); + putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL0FEED); /* Wait for PLL to report that it is connected and enabled */ - while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC)) + while ((getreg32(LPC17_40_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC)) != (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC)); -#endif /* CONFIG_LPC17_PLL0 */ +#endif /* CONFIG_LPC17_40_PLL0 */ /* PLL1 receives its clock input from the main oscillator only and can be used to * provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be * obtained from PLL0). */ -#ifdef CONFIG_LPC17_PLL1 +#ifdef CONFIG_LPC17_40_PLL1 /* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed" * sequence must be written to the PLL1FEED register in order for changes to the * PLL1CFG register to take effect. */ - putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG); - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); + putreg32(BOARD_PLL1CFG_VALUE, LPC17_40_SYSCON_PLL1CFG); + putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL1FEED); /* Enable the PLL. NOTE that a special "feed" sequence must be written to the * PLL1FEED register in order for changes to the PLL1CON register to take effect. */ - putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON); - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); + putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL1CON); + putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL1FEED); /* Wait for PLL1 to lock */ - while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); + while ((getreg32(LPC17_40_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); /* Enable and connect PLL1 */ - putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON); - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); + putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_40_SYSCON_PLL1CON); + putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL1FEED); /* Wait for PLL to report that it is connected and enabled */ - while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC)) + while ((getreg32(LPC17_40_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC)) != (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC)); -#else /* CONFIG_LPC17_PLL1 */ +#else /* CONFIG_LPC17_40_PLL1 */ /* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */ - putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG); + putreg32(BOARD_USBCLKCFG_VALUE, LPC17_40_SYSCON_USBCLKCFG); -#endif /* CONFIG_LPC17_PLL1 */ +#endif /* CONFIG_LPC17_40_PLL1 */ /* Disable all peripheral clocks. They must be configured by each device driver * when the device driver is initialized. */ - putreg32(0, LPC17_SYSCON_PCLKSEL0); - putreg32(0, LPC17_SYSCON_PCLKSEL1); + putreg32(0, LPC17_40_SYSCON_PCLKSEL0); + putreg32(0, LPC17_40_SYSCON_PCLKSEL1); /* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered * one at a time by each device driver when the driver is initialized. */ - putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP); + putreg32(SYSCON_PCONP_PCGPIO, LPC17_40_SYSCON_PCONP); /* Disable CLKOUT */ - putreg32(0, LPC17_SYSCON_CLKOUTCFG); + putreg32(0, LPC17_40_SYSCON_CLKOUTCFG); /* Configure FLASH */ -#ifdef CONFIG_LPC17_FLASH +#ifdef CONFIG_LPC17_40_FLASH { uint32_t regval; @@ -224,12 +224,12 @@ void lpc17_clockconfig(void) } else { - regval = getreg32(LPC17_SYSCON_FLASHCFG); + regval = getreg32(LPC17_40_SYSCON_FLASHCFG); regval &= ~SYSCON_FLASHCFG_TIM_MASK; regval |= BOARD_FLASHCFG_VALUE; } - putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG); + putreg32(BOARD_FLASHCFG_VALUE, LPC17_40_SYSCON_FLASHCFG); } #endif } diff --git a/arch/arm/src/lpc17xx/lpc176x_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c similarity index 78% rename from arch/arm/src/lpc17xx/lpc176x_gpio.c rename to arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c index b2b8e9805ab..4cf6b4e2c29 100644 --- a/arch/arm/src/lpc17xx/lpc176x_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc176x_gpio.c + * arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c * * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,7 +49,7 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -71,14 +71,14 @@ * Public Data ****************************************************************************/ /* These tables have global scope because they are also used in - * lpc17_gpiodbg.c + * lpc17_40_gpiodbg.c */ /* We have to remember the configured interrupt setting.. PINs are not * actually set up to interrupt until the interrupt is enabled. */ -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ uint64_t g_intedge0; uint64_t g_intedge2; #endif @@ -87,13 +87,13 @@ uint64_t g_intedge2; const uint32_t g_fiobase[GPIO_NPORTS] = { - LPC17_FIO0_BASE, - LPC17_FIO1_BASE, - LPC17_FIO2_BASE, - LPC17_FIO3_BASE, - LPC17_FIO4_BASE + LPC17_40_FIO0_BASE, + LPC17_40_FIO1_BASE, + LPC17_40_FIO2_BASE, + LPC17_40_FIO3_BASE, + LPC17_40_FIO4_BASE #if GPIO_NPORTS > 5 - , LPC17_FIO5_BASE + , LPC17_40_FIO5_BASE #endif }; @@ -103,9 +103,9 @@ const uint32_t g_fiobase[GPIO_NPORTS] = const uint32_t g_intbase[GPIO_NPORTS] = { - LPC17_GPIOINT0_BASE, + LPC17_40_GPIOINT0_BASE, 0, - LPC17_GPIOINT2_BASE, + LPC17_40_GPIOINT2_BASE, 0, 0 #if GPIO_NPORTS > 5 @@ -115,9 +115,9 @@ const uint32_t g_intbase[GPIO_NPORTS] = const uint32_t g_lopinsel[GPIO_NPORTS] = { - LPC17_PINCONN_PINSEL0, - LPC17_PINCONN_PINSEL2, - LPC17_PINCONN_PINSEL4, + LPC17_40_PINCONN_PINSEL0, + LPC17_40_PINCONN_PINSEL2, + LPC17_40_PINCONN_PINSEL4, 0, 0 #if GPIO_NPORTS > 5 @@ -127,11 +127,11 @@ const uint32_t g_lopinsel[GPIO_NPORTS] = const uint32_t g_hipinsel[GPIO_NPORTS] = { - LPC17_PINCONN_PINSEL1, - LPC17_PINCONN_PINSEL3, + LPC17_40_PINCONN_PINSEL1, + LPC17_40_PINCONN_PINSEL3, 0, - LPC17_PINCONN_PINSEL7, - LPC17_PINCONN_PINSEL9 + LPC17_40_PINCONN_PINSEL7, + LPC17_40_PINCONN_PINSEL9 #if GPIO_NPORTS > 5 , 0 #endif @@ -139,9 +139,9 @@ const uint32_t g_hipinsel[GPIO_NPORTS] = const uint32_t g_lopinmode[GPIO_NPORTS] = { - LPC17_PINCONN_PINMODE0, - LPC17_PINCONN_PINMODE2, - LPC17_PINCONN_PINMODE4, + LPC17_40_PINCONN_PINMODE0, + LPC17_40_PINCONN_PINMODE2, + LPC17_40_PINCONN_PINMODE4, 0, 0 #if GPIO_NPORTS > 5 @@ -151,11 +151,11 @@ const uint32_t g_lopinmode[GPIO_NPORTS] = const uint32_t g_hipinmode[GPIO_NPORTS] = { - LPC17_PINCONN_PINMODE1, - LPC17_PINCONN_PINMODE3, + LPC17_40_PINCONN_PINMODE1, + LPC17_40_PINCONN_PINMODE3, 0, - LPC17_PINCONN_PINMODE7, - LPC17_PINCONN_PINMODE9 + LPC17_40_PINCONN_PINMODE7, + LPC17_40_PINCONN_PINMODE9 #if GPIO_NPORTS > 5 , 0 #endif @@ -163,11 +163,11 @@ const uint32_t g_hipinmode[GPIO_NPORTS] = const uint32_t g_odmode[GPIO_NPORTS] = { - LPC17_PINCONN_ODMODE0, - LPC17_PINCONN_ODMODE1, - LPC17_PINCONN_ODMODE2, - LPC17_PINCONN_ODMODE3, - LPC17_PINCONN_ODMODE4 + LPC17_40_PINCONN_ODMODE0, + LPC17_40_PINCONN_ODMODE1, + LPC17_40_PINCONN_ODMODE2, + LPC17_40_PINCONN_ODMODE3, + LPC17_40_PINCONN_ODMODE4 #if GPIO_NPORTS > 5 , 0 #endif @@ -178,7 +178,7 @@ const uint32_t g_odmode[GPIO_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Name: lpc17_pinsel + * Name: lpc17_40_pinsel * * Description: * Get the address of the PINSEL register corresponding to this port and @@ -186,7 +186,7 @@ const uint32_t g_odmode[GPIO_NPORTS] = * ****************************************************************************/ -static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value) +static int lpc17_40_pinsel(unsigned int port, unsigned int pin, unsigned int value) { const uint32_t *table; uint32_t regaddr; @@ -224,7 +224,7 @@ static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value) } /**************************************************************************** - * Name: lpc17_pullup + * Name: lpc17_40_pullup * * Description: * Get the address of the PINMODE register corresponding to this port and @@ -232,7 +232,7 @@ static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value) * ****************************************************************************/ -static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port, +static int lpc17_40_pullup(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { const uint32_t *table; @@ -292,7 +292,7 @@ static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port, } /**************************************************************************** - * Name: lpc17_setintedge + * Name: lpc17_40_setintedge * * Description: * Remember the configured interrupt edge. We can't actually enable the @@ -300,8 +300,8 @@ static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port, * ****************************************************************************/ -#ifdef CONFIG_LPC17_GPIOIRQ -static void lpc17_setintedge(unsigned int port, unsigned int pin, +#ifdef CONFIG_LPC17_40_GPIOIRQ +static void lpc17_40_setintedge(unsigned int port, unsigned int pin, unsigned int value) { uint64_t *intedge; @@ -328,17 +328,17 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin, *intedge &= ~((uint64_t)3 << shift); *intedge |= ((uint64_t)value << shift); } -#endif /* CONFIG_LPC17_GPIOIRQ */ +#endif /* CONFIG_LPC17_40_GPIOIRQ */ /**************************************************************************** - * Name: lpc17_setopendrain + * Name: lpc17_40_setopendrain * * Description: * Set the ODMODE register for open drain mode * ****************************************************************************/ -static void lpc17_setopendrain(unsigned int port, unsigned int pin) +static void lpc17_40_setopendrain(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; @@ -350,14 +350,14 @@ static void lpc17_setopendrain(unsigned int port, unsigned int pin) } /**************************************************************************** - * Name: lpc17_clropendrain + * Name: lpc17_40_clropendrain * * Description: * Reset the ODMODE register to disable open drain mode * ****************************************************************************/ -static void lpc17_clropendrain(unsigned int port, unsigned int pin) +static void lpc17_40_clropendrain(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; @@ -369,14 +369,14 @@ static void lpc17_clropendrain(unsigned int port, unsigned int pin) } /**************************************************************************** - * Name: lpc17_configinput + * Name: lpc17_40_configinput * * Description: * Configure a GPIO inpue pin based on bit-encoded description of the pin. * ****************************************************************************/ -static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin) +static inline int lpc17_40_configinput(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regval; uint32_t fiobase; @@ -389,9 +389,9 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un /* Set as input */ - regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET); + regval = getreg32(fiobase + LPC17_40_FIO_DIR_OFFSET); regval &= ~pinmask; - putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET); + putreg32(regval, fiobase + LPC17_40_FIO_DIR_OFFSET); /* Set up interrupt registers */ @@ -400,74 +400,74 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un { /* Disable any rising edge interrupts */ - regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + regval = getreg32(intbase + LPC17_40_GPIOINT_INTENR_OFFSET); regval &= ~pinmask; - putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET); + putreg32(regval, intbase + LPC17_40_GPIOINT_INTENR_OFFSET); /* Disable any falling edge interrupts */ - regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + regval = getreg32(intbase + LPC17_40_GPIOINT_INTENF_OFFSET); regval &= ~pinmask; - putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET); + putreg32(regval, intbase + LPC17_40_GPIOINT_INTENF_OFFSET); /* Forget about any falling/rising edge interrupt enabled */ -#ifdef CONFIG_LPC17_GPIOIRQ - lpc17_setintedge(port, pin, 0); +#ifdef CONFIG_LPC17_40_GPIOIRQ + lpc17_40_setintedge(port, pin, 0); #endif } /* Set up PINSEL registers */ /* Configure as GPIO */ - lpc17_pinsel(port, pin, PINCONN_PINSEL_GPIO); + lpc17_40_pinsel(port, pin, PINCONN_PINSEL_GPIO); /* Set pull-up mode */ - lpc17_pullup(cfgset, port, pin); + lpc17_40_pullup(cfgset, port, pin); /* Open drain only applies to outputs */ - lpc17_clropendrain(port, pin); + lpc17_40_clropendrain(port, pin); return OK; } /**************************************************************************** - * Name: lpc17_configinterrupt + * Name: lpc17_40_configinterrupt * * Description: * Configure a GPIO interrupt pin based on bit-encoded description of the pin. * ****************************************************************************/ -static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port, +static inline int lpc17_40_configinterrupt(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { /* First, configure the port as a generic input so that we have a known * starting point and consistent behavior during the re-configuration. */ - (void)lpc17_configinput(cfgset, port, pin); + (void)lpc17_40_configinput(cfgset, port, pin); /* Then just remember the rising/falling edge interrupt enabled */ DEBUGASSERT(port == 0 || port == 2); -#ifdef CONFIG_LPC17_GPIOIRQ - lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); +#ifdef CONFIG_LPC17_40_GPIOIRQ + lpc17_40_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); #endif return OK; } /**************************************************************************** - * Name: lpc17_configoutput + * Name: lpc17_40_configoutput * * Description: * Configure a GPIO output pin based on bit-encoded description of the pin. * ****************************************************************************/ -static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, +static inline int lpc17_40_configoutput(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t fiobase; @@ -477,7 +477,7 @@ static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, * starting point and consistent behavior during the re-configuration. */ - (void)lpc17_configinput(DEFAULT_INPUT, port, pin); + (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin); /* Check for open drain output */ @@ -487,30 +487,30 @@ static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, * meaning if the port is an open drain output. */ - lpc17_pullup(cfgset, port, pin); + lpc17_40_pullup(cfgset, port, pin); /* Select open drain output */ - lpc17_setopendrain(port, pin); + lpc17_40_setopendrain(port, pin); } /* Set the initial value of the output */ - lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + lpc17_40_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); /* Now, reconfigure the pin as an output */ fiobase = g_fiobase[port]; - regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET); + regval = getreg32(fiobase + LPC17_40_FIO_DIR_OFFSET); regval |= (1 << pin); - putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET); + putreg32(regval, fiobase + LPC17_40_FIO_DIR_OFFSET); return OK; } /**************************************************************************** - * Name: lpc17_configalternate + * Name: lpc17_40_configalternate * * Description: * Configure a GPIO alternate function pin based on bit-encoded description @@ -518,23 +518,23 @@ static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, * ****************************************************************************/ -static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, +static int lpc17_40_configalternate(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin, uint32_t alt) { /* First, configure the port as an input so that we have a known * starting point and consistent behavior during the re-configuration. */ - (void)lpc17_configinput(DEFAULT_INPUT, port, pin); + (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin); /* Set up PINSEL registers */ /* Configure as GPIO */ - lpc17_pinsel(port, pin, alt); + lpc17_40_pinsel(port, pin, alt); /* Set pull-up mode */ - lpc17_pullup(cfgset, port, pin); + lpc17_40_pullup(cfgset, port, pin); /* Check for open drain output */ @@ -542,7 +542,7 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, { /* Select open drain output */ - lpc17_setopendrain(port, pin); + lpc17_40_setopendrain(port, pin); } return OK; @@ -553,14 +553,14 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, ****************************************************************************/ /**************************************************************************** - * Name: lpc17_configgpio + * Name: lpc17_40_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * ****************************************************************************/ -int lpc17_configgpio(lpc17_pinset_t cfgset) +int lpc17_40_configgpio(lpc17_40_pinset_t cfgset) { unsigned int port; unsigned int pin; @@ -580,29 +580,29 @@ int lpc17_configgpio(lpc17_pinset_t cfgset) switch (cfgset & GPIO_FUNC_MASK) { case GPIO_INPUT: /* GPIO input pin */ - ret = lpc17_configinput(cfgset, port, pin); + ret = lpc17_40_configinput(cfgset, port, pin); break; case GPIO_INTFE: /* GPIO interrupt falling edge */ case GPIO_INTRE: /* GPIO interrupt rising edge */ case GPIO_INTBOTH: /* GPIO interrupt both edges */ - ret = lpc17_configinterrupt(cfgset, port, pin); + ret = lpc17_40_configinterrupt(cfgset, port, pin); break; case GPIO_OUTPUT: /* GPIO outpout pin */ - ret = lpc17_configoutput(cfgset, port, pin); + ret = lpc17_40_configoutput(cfgset, port, pin); break; case GPIO_ALT1: /* Alternate function 1 */ - ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1); + ret = lpc17_40_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1); break; case GPIO_ALT2: /* Alternate function 2 */ - ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2); + ret = lpc17_40_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2); break; case GPIO_ALT3: /* Alternate function 3 */ - ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3); + ret = lpc17_40_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3); break; default: @@ -614,14 +614,14 @@ int lpc17_configgpio(lpc17_pinset_t cfgset) } /**************************************************************************** - * Name: lpc17_gpiowrite + * Name: lpc17_40_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) +void lpc17_40_gpiowrite(lpc17_40_pinset_t pinset, bool value) { uint32_t fiobase; uint32_t offset; @@ -643,11 +643,11 @@ void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) if (value) { - offset = LPC17_FIO_SET_OFFSET; + offset = LPC17_40_FIO_SET_OFFSET; } else { - offset = LPC17_FIO_CLR_OFFSET; + offset = LPC17_40_FIO_CLR_OFFSET; } putreg32((1 << pin), fiobase + offset); @@ -655,14 +655,14 @@ void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) } /**************************************************************************** - * Name: lpc17_gpioread + * Name: lpc17_40_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool lpc17_gpioread(lpc17_pinset_t pinset) +bool lpc17_40_gpioread(lpc17_40_pinset_t pinset) { uint32_t fiobase; unsigned int port; @@ -678,7 +678,7 @@ bool lpc17_gpioread(lpc17_pinset_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0); + return ((getreg32(fiobase + LPC17_40_FIO_PIN_OFFSET) & (1 << pin)) != 0); } return false; diff --git a/arch/arm/src/lpc17xx/lpc176x_gpio.h b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h similarity index 95% rename from arch/arm/src/lpc17xx/lpc176x_gpio.h rename to arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h index acdd1dcf695..8fdc07bf089 100644 --- a/arch/arm/src/lpc17xx/lpc176x_gpio.h +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc176x_gpio.h + * arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC176X_GPIO_H -#define __ARCH_ARM_SRC_LPC17XX_LPC176X_GPIO_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC176X_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC176X_GPIO_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Bit-encoded input to lpc17_configgpio() ******************************************/ +/* Bit-encoded input to lpc17_40_configgpio() ******************************************/ /* Encoding: FFFx MMOV PPPN NNNN * @@ -159,7 +159,7 @@ * Public Types ************************************************************************************/ -typedef uint16_t lpc17_pinset_t; +typedef uint16_t lpc17_40_pinset_t; /************************************************************************************ * Public Data @@ -175,8 +175,8 @@ extern "C" #define EXTERN extern #endif -/* These tables have global scope only because they are shared between lpc17_gpio.c, - * lpc17_gpioint.c, and lpc17_gpiodbg.c +/* These tables have global scope only because they are shared between lpc17_40_gpio.c, + * lpc17_40_gpioint.c, and lpc17_40_gpiodbg.c */ EXTERN const uint32_t g_lopinsel[GPIO_NPORTS]; @@ -194,4 +194,4 @@ EXTERN const uint32_t g_odmode[GPIO_NPORTS]; #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC176X_GPIO_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC176X_GPIO_H */ diff --git a/arch/arm/src/lpc17xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c similarity index 87% rename from arch/arm/src/lpc17xx/lpc176x_rtc.c rename to arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c index ae5a18949d7..b56d73cb580 100644 --- a/arch/arm/src/lpc17xx/lpc176x_rtc.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc176x_rtcc.c + * arch/arm/src/lpc17xx_40xx/lpc176x_rtcc.c * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,9 +52,9 @@ #include "up_internal.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" +#include "hardware/lpc17_40_syscon.h" -#include "lpc17_rtc.h" +#include "lpc17_40_rtc.h" #ifdef CONFIG_RTC @@ -111,8 +111,8 @@ volatile bool g_rtc_enabled = false; static void rtc_dumpregs(FAR const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" DOM : %08x\n", (getreg32(LPC17_RTC_DOM) & RTC_DOM_MASK)); - rtcinfo(" DOW : %08x\n", (getreg32(LPC17_RTC_DOW) & RTC_DOW_MASK)); + rtcinfo(" DOM : %08x\n", (getreg32(LPC17_40_RTC_DOM) & RTC_DOM_MASK)); + rtcinfo(" DOW : %08x\n", (getreg32(LPC17_40_RTC_DOW) & RTC_DOW_MASK)); } #else # define rtc_dumpregs(msg) @@ -169,21 +169,21 @@ static int rtc_setup(void) /* Clear all register to be default */ - putreg32((uint32_t)0x00, LPC17_RTC_ILR); - putreg32((uint32_t)0x00, LPC17_RTC_CCR); - putreg32((uint32_t)0x00, LPC17_RTC_CIIR); - putreg32((uint32_t)0xff, LPC17_RTC_AMR); - putreg32((uint32_t)0x00, LPC17_RTC_CALIB); + putreg32((uint32_t)0x00, LPC17_40_RTC_ILR); + putreg32((uint32_t)0x00, LPC17_40_RTC_CCR); + putreg32((uint32_t)0x00, LPC17_40_RTC_CIIR); + putreg32((uint32_t)0xff, LPC17_40_RTC_AMR); + putreg32((uint32_t)0x00, LPC17_40_RTC_CALIB); /* Enable power to the RTC module */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCRTC; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Enable counters */ - putreg32((uint32_t)0x01, LPC17_RTC_CCR); + putreg32((uint32_t)0x01, LPC17_40_RTC_CCR); return OK; } @@ -262,10 +262,10 @@ int up_rtc_initialize(void) /* Attach the RTC interrupt handler */ #ifdef CONFIG_RTC_ALARM - ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt, NULL); + ret = irq_attach(LPC17_40_IRQ_RTC, rtc_interrupt, NULL); if (ret == OK) { - up_enable_irq(LPC17_IRQ_RTC); + up_enable_irq(LPC17_40_IRQ_RTC); } #endif /* CONFIG_RTC_ALARM */ @@ -320,9 +320,9 @@ int up_rtc_getdatetime(FAR struct tm *tp) * register. */ - tp->tm_sec = ((getreg32(LPC17_RTC_SEC) & RTC_SEC_MASK)); - tp->tm_min = ((getreg32(LPC17_RTC_MIN) & RTC_MIN_MASK)); - tp->tm_hour = ((getreg32(LPC17_RTC_HOUR) & RTC_HOUR_MASK)); + tp->tm_sec = ((getreg32(LPC17_40_RTC_SEC) & RTC_SEC_MASK)); + tp->tm_min = ((getreg32(LPC17_40_RTC_MIN) & RTC_MIN_MASK)); + tp->tm_hour = ((getreg32(LPC17_40_RTC_HOUR) & RTC_HOUR_MASK)); /* Now convert the RTC date to fields in struct tm format: * Days: 1-31 match in both cases. @@ -333,9 +333,9 @@ int up_rtc_getdatetime(FAR struct tm *tp) * years 2000-2099? I'll assume so. */ - tp->tm_mday = ((getreg32(LPC17_RTC_DOM) & RTC_DOM_MASK)); - tp->tm_mon = ((getreg32(LPC17_RTC_MONTH) & RTC_MONTH_MASK)) - 1; - tp->tm_year = ((getreg32(LPC17_RTC_YEAR) & RTC_YEAR_MASK)-1900); + tp->tm_mday = ((getreg32(LPC17_40_RTC_DOM) & RTC_DOM_MASK)); + tp->tm_mon = ((getreg32(LPC17_40_RTC_MONTH) & RTC_MONTH_MASK)) - 1; + tp->tm_year = ((getreg32(LPC17_40_RTC_YEAR) & RTC_YEAR_MASK)-1900); rtc_dumptime(tp, "Returning"); return OK; @@ -367,18 +367,18 @@ int up_rtc_settime(FAR const struct timespec *tp) /* Then write the broken out values to the RTC */ - putreg32(((newtime.tm_sec) & RTC_SEC_MASK), LPC17_RTC_SEC); - putreg32(((newtime.tm_min) & RTC_MIN_MASK), LPC17_RTC_MIN); - putreg32(((newtime.tm_hour) & RTC_HOUR_MASK), LPC17_RTC_HOUR); - putreg32(((newtime.tm_mday) & RTC_DOM_MASK), LPC17_RTC_DOM); - putreg32((((newtime.tm_mon)+1) & RTC_MONTH_MASK), LPC17_RTC_MONTH); - putreg32(((newtime.tm_year) & RTC_YEAR_MASK)+1900, LPC17_RTC_YEAR); + putreg32(((newtime.tm_sec) & RTC_SEC_MASK), LPC17_40_RTC_SEC); + putreg32(((newtime.tm_min) & RTC_MIN_MASK), LPC17_40_RTC_MIN); + putreg32(((newtime.tm_hour) & RTC_HOUR_MASK), LPC17_40_RTC_HOUR); + putreg32(((newtime.tm_mday) & RTC_DOM_MASK), LPC17_40_RTC_DOM); + putreg32((((newtime.tm_mon)+1) & RTC_MONTH_MASK), LPC17_40_RTC_MONTH); + putreg32(((newtime.tm_year) & RTC_YEAR_MASK)+1900, LPC17_40_RTC_YEAR); return OK; } /************************************************************************************ - * Name: lpc17_rtc_setalarm + * Name: lpc17_40_rtc_setalarm * * Description: * Set up an alarm. Up to two alarms can be supported (ALARM A and ALARM B). @@ -393,7 +393,7 @@ int up_rtc_settime(FAR const struct timespec *tp) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -int lpc17_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) +int lpc17_40_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) { int ret = -EBUSY; diff --git a/arch/arm/src/lpc17xx/lpc178x_clockconfig.c b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_clockconfig.c similarity index 77% rename from arch/arm/src/lpc17xx/lpc178x_clockconfig.c rename to arch/arm/src/lpc17xx_40xx/lpc178x_40xx_clockconfig.c index 216d27012ff..c068dba23fe 100644 --- a/arch/arm/src/lpc17xx/lpc178x_clockconfig.c +++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_clockconfig.c @@ -1,6 +1,6 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_clockconfig.c - * arch/arm/src/chip/lpc17_clockconfig.c + * arch/arm/src/lpc17xx_40xx/lpc178x_40xx_clockconfig.c + * arch/arm/src/chip/lpc17_40_clockconfig.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,15 +48,15 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_clockconfig.h" -#include "hardware/lpc17_syscon.h" +#include "lpc17_40_clockconfig.h" +#include "hardware/lpc17_40_syscon.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifndef LPC178x -# error "The logic in this file applies only to the LPC178x family" +#ifndef LPC178x_40xx +# error "The logic in this file applies only to the LPC178x/40xx family" #endif /**************************************************************************** @@ -76,21 +76,21 @@ ****************************************************************************/ /************************************************************************************ - * Name: lpc17_clockconfig + * Name: lpc17_40_clockconfig * * Description: - * Called to initialize the LPC17xx. This does whatever setup is needed to put the + * Called to initialize the LPC17xx/LPC40xx. This does whatever setup is needed to put the * SoC in a usable state. This includes the initialization of clocking using the * settings in board.h. * - * The LPC176x and LPC178x system control block is *nearly* identical but we have - * found that the LPC178x is more sensitive to the ordering of certain operations. + * The LPC176x and LPC178x/40xx system control block is *nearly* identical but we have + * found that the LPC178x/40xx is more sensitive to the ordering of certain operations. * So, although the hardware seems very similar, the safer thing to do is to - * separate the LPC176x and LPC178x into separate files. + * separate the LPC176x and LPC178x/40xx into separate files. * ************************************************************************************/ -void lpc17_clockconfig(void) +void lpc17_40_clockconfig(void) { uint32_t regval; @@ -113,17 +113,17 @@ void lpc17_clockconfig(void) /* Enable the main oscillator (or not) and the frequency range of the main oscillator */ - putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS); + putreg32(BOARD_SCS_VALUE, LPC17_40_SYSCON_SCS); /* Wait for the main oscillator to be ready. */ -#ifdef CONFIG_LPC17_MAINOSC - while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); +#ifdef CONFIG_LPC17_40_MAINOSC + while ((getreg32(LPC17_40_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); #endif /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */ -#ifdef CONFIG_LPC17_PLL0 +#ifdef CONFIG_LPC17_40_PLL0 /* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to the * PLLE bit in the PLLCON register. Perform a PLL feed sequence by writing * first the value 0xAA, then the value 0x55 to the PLLFEED register" @@ -133,32 +133,32 @@ void lpc17_clockconfig(void) * for changes to the PLL0CFG register to take effect. */ - putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL); - putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG); - putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON); + putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_40_SYSCON_CLKSRCSEL); + putreg32(BOARD_PLL0CFG_VALUE, LPC17_40_SYSCON_PLL0CFG); + putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL0CON); /* Enable the PLL. NOTE that a special "feed" sequence must be written to the * PLL0FEED register in order for changes to the PLL0CON register to take effect. */ - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); + putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL0FEED); /* (4) "Set up the necessary clock dividers. These may include the CCLKSEL, * PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers. */ - putreg32(BOARD_CCLKSEL_VALUE, LPC17_SYSCON_CCLKSEL); - putreg32(BOARD_PCLKDIV, LPC17_SYSCON_PCLKSEL); + putreg32(BOARD_CCLKSEL_VALUE, LPC17_40_SYSCON_CCLKSEL); + putreg32(BOARD_PCLKDIV, LPC17_40_SYSCON_PCLKSEL); -#ifdef CONFIG_LPC17_EMC - putreg32(BOARD_EMCCLKSEL_VALUE, LPC17_SYSCON_EMCCLKSEL); +#ifdef CONFIG_LPC17_40_EMC + putreg32(BOARD_EMCCLKSEL_VALUE, LPC17_40_SYSCON_EMCCLKSEL); #endif -#if defined(CONFIG_LPC17_USBDEV) || defined(CONFIG_LPC17_USBHOST) - putreg32(BOARD_USBCLKSEL_VALUE, LPC17_SYSCON_USBCLKSEL); +#if defined(CONFIG_LPC17_40_USBDEV) || defined(CONFIG_LPC17_40_USBHOST) + putreg32(BOARD_USBCLKSEL_VALUE, LPC17_40_SYSCON_USBCLKSEL); #endif -#ifdef CONFIG_LPC17_SPIFI - putreg32(BOARD_SPIFICLKSEL_VALUE, LPC17_SPIFICLKSEL_CCLKSEL); +#ifdef CONFIG_LPC17_40_SPIFI + putreg32(BOARD_SPIFICLKSEL_VALUE, LPC17_40_SPIFICLKSEL_CCLKSEL); #endif /* (5) "Wait for the PLL to lock. This may be accomplished by polling the @@ -166,20 +166,20 @@ void lpc17_clockconfig(void) * interrupt.Wait for PLL0 to lock. */ - while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); + while ((getreg32(LPC17_40_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); /* (6) "Connect the PLL by selecting its output in the appropriate places. This * may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers. */ -#endif /* CONFIG_LPC17_PLL0 */ +#endif /* CONFIG_LPC17_40_PLL0 */ /* PLL1 receives its clock input from the main oscillator only and can be used to * provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be * obtained from PLL0). */ -#ifdef CONFIG_LPC17_PLL1 +#ifdef CONFIG_LPC17_40_PLL1 /* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to the * PLLE bit in the PLLCON register. Perform a PLL feed sequence by writing * first the value 0xAA, then the value 0x55 to the PLLFEED register" @@ -189,15 +189,15 @@ void lpc17_clockconfig(void) * PLL1CFG register to take effect. */ - putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG); - putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON); + putreg32(BOARD_PLL1CFG_VALUE, LPC17_40_SYSCON_PLL1CFG); + putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL1CON); /* Enable the PLL. NOTE that a special "feed" sequence must be written to the * PLL1FEED register in order for changes to the PLL1CON register to take effect. */ - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); + putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_40_SYSCON_PLL1FEED); /* (4) "Set up the necessary clock dividers. These may include the CCLKSEL, * PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers. @@ -208,13 +208,13 @@ void lpc17_clockconfig(void) * interrupt.Wait for PLL0 to lock. */ - while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); + while ((getreg32(LPC17_40_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); /* (6) "Connect the PLL by selecting its output in the appropriate places. This * may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers. */ -#endif /* CONFIG_LPC17_PLL1 */ +#endif /* CONFIG_LPC17_40_PLL1 */ /* Disable power to all peripherals (except GPIO and left EMC intact). * EMC is switched off after reset but if there is boot-loader, @@ -223,19 +223,19 @@ void lpc17_clockconfig(void) * one at a time by each device driver when the driver is initialized. */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval &= SYSCON_PCONP_PCEMC; regval |= SYSCON_PCONP_PCGPIO; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Disable CLKOUT */ - putreg32(0, LPC17_SYSCON_CLKOUTCFG); + putreg32(0, LPC17_40_SYSCON_CLKOUTCFG); /* Configure FLASH */ -#ifdef CONFIG_LPC17_FLASH - putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG); +#ifdef CONFIG_LPC17_40_FLASH + putreg32(BOARD_FLASHCFG_VALUE, LPC17_40_SYSCON_FLASHCFG); #endif } diff --git a/arch/arm/src/lpc17xx/lpc178x_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c similarity index 77% rename from arch/arm/src/lpc17xx/lpc178x_gpio.c rename to arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c index a6892d597f6..be114cac937 100644 --- a/arch/arm/src/lpc17xx/lpc178x_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc178x_gpio.c + * arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c * * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -72,14 +72,14 @@ * Public Data ****************************************************************************/ /* These tables have global scope because they are also used in - * lpc17_gpiodbg.c + * lpc17_40_gpiodbg.c */ /* We have to remember the configured interrupt setting.. PINs are not * actually set up to interrupt until the interrupt is enabled. */ -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ uint64_t g_intedge0; uint64_t g_intedge2; #endif @@ -88,13 +88,13 @@ uint64_t g_intedge2; const uint32_t g_fiobase[GPIO_NPORTS] = { - LPC17_FIO0_BASE, - LPC17_FIO1_BASE, - LPC17_FIO2_BASE, - LPC17_FIO3_BASE, - LPC17_FIO4_BASE + LPC17_40_FIO0_BASE, + LPC17_40_FIO1_BASE, + LPC17_40_FIO2_BASE, + LPC17_40_FIO3_BASE, + LPC17_40_FIO4_BASE #if GPIO_NPORTS > 5 - , LPC17_FIO5_BASE + , LPC17_40_FIO5_BASE #endif }; @@ -104,9 +104,9 @@ const uint32_t g_fiobase[GPIO_NPORTS] = const uint32_t g_intbase[GPIO_NPORTS] = { - LPC17_GPIOINT0_BASE, + LPC17_40_GPIOINT0_BASE, 0, - LPC17_GPIOINT2_BASE, + LPC17_40_GPIOINT2_BASE, 0, 0 #if GPIO_NPORTS > 5 @@ -119,10 +119,10 @@ const uint32_t g_intbase[GPIO_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Name: lpc17_getioconmask + * Name: lpc17_40_getioconmask * * Description: - * Get the LPC178x IOCON register mask. + * Get the LPC178x/40xx IOCON register mask. * * Type D: FUNC, MODE, HYS, INV, SLEW, OD - * Type A: FUNC, MODE, INV, ADMODE, FILTER, OD, DACEN -P0[12:13,23:26],P1[30:31] @@ -133,7 +133,7 @@ const uint32_t g_intbase[GPIO_NPORTS] = ****************************************************************************/ #if 0 /* Not used */ -static uint32_t lpc17_getioconmask(unsigned int port, unsigned int pin) +static uint32_t lpc17_40_getioconmask(unsigned int port, unsigned int pin) { uint32_t typemask = IOCON_TYPE_D_MASK; @@ -210,20 +210,20 @@ static uint32_t lpc17_getioconmask(unsigned int port, unsigned int pin) #endif /**************************************************************************** - * Name: lpc17_seti2cmode + * Name: lpc17_40_seti2cmode * * Description: * Configure I2C pin drive mode. Applies to Type I pins * ****************************************************************************/ -static void lpc17_seti2cmode(unsigned int port, unsigned int pin, +static void lpc17_40_seti2cmode(unsigned int port, unsigned int pin, uint32_t value) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval &= ~IOCON_I2CMODE_MASK; regval |= ((value << IOCON_I2CMODE_SHIFT) & IOCON_I2CMODE_MASK); @@ -231,20 +231,20 @@ static void lpc17_seti2cmode(unsigned int port, unsigned int pin, } /**************************************************************************** - * Name: lpc17_setpinfunction + * Name: lpc17_40_setpinfunction * * Description: * Select pin function. * ****************************************************************************/ -static void lpc17_setpinfunction(unsigned int port, unsigned int pin, +static void lpc17_40_setpinfunction(unsigned int port, unsigned int pin, unsigned int value) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval &= ~IOCON_FUNC_MASK; @@ -253,33 +253,33 @@ static void lpc17_setpinfunction(unsigned int port, unsigned int pin, } /**************************************************************************** - * Name: lpc17_setinvertinput + * Name: lpc17_40_setinvertinput * * Description: * Configure pin input polarity. Applies to Type D, A, I and W pins. * ****************************************************************************/ -static void lpc17_setinvertinput(unsigned int port, unsigned int pin) +static void lpc17_40_setinvertinput(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval |= IOCON_INV_MASK; putreg32(regval, regaddr); } /**************************************************************************** - * Name: lpc17_setslewfast + * Name: lpc17_40_setslewfast * * Description: * Configure pin mode slew rate drive. Applies to Type D and Type W pins * ****************************************************************************/ -static void lpc17_setslewmode(lpc17_pinset_t cfgset, unsigned int port, +static void lpc17_40_setslewmode(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regaddr; @@ -292,7 +292,7 @@ static void lpc17_setslewmode(lpc17_pinset_t cfgset, unsigned int port, /* Get the current IOCON register contents */ - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); /* Set the driver slew rate */ @@ -303,7 +303,7 @@ static void lpc17_setslewmode(lpc17_pinset_t cfgset, unsigned int port, } /**************************************************************************** - * Name: lpc17_setmodedigital + * Name: lpc17_40_setmodedigital * * Description: * Configure pin mode as analog or digital IO. Applies to Type A pins @@ -311,12 +311,12 @@ static void lpc17_setslewmode(lpc17_pinset_t cfgset, unsigned int port, ****************************************************************************/ #if 0 /* Not used */ -static void lpc17_setmodedigital(unsigned int port, unsigned int pin) +static void lpc17_40_setmodedigital(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval |= IOCON_ADMODE_MASK; putreg32(regval, regaddr); @@ -324,45 +324,45 @@ static void lpc17_setmodedigital(unsigned int port, unsigned int pin) #endif /**************************************************************************** - * Name: lpc17_setmodeanalog + * Name: lpc17_40_setmodeanalog * * Description: * Configure pin mode as analog or digital IO. Applies to Type A pins * ****************************************************************************/ -static void lpc17_setmodeanalog(unsigned int port, unsigned int pin) +static void lpc17_40_setmodeanalog(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval &= ~IOCON_ADMODE_MASK; putreg32(regval, regaddr); } /**************************************************************************** - * Name: lpc17_setdacenable + * Name: lpc17_40_setdacenable * * Description: * Configure DAC output. Applies to Type A pins P0:26 only * ****************************************************************************/ -static void lpc17_setdacenable(unsigned int port, unsigned int pin) +static void lpc17_40_setdacenable(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval |= IOCON_DACEN_MASK; putreg32(regval, regaddr); } /**************************************************************************** - * Name: lpc17_setdacdisable + * Name: lpc17_40_setdacdisable * * Description: * Configure DAC output. Applies to Type A pins P0:26 only @@ -370,12 +370,12 @@ static void lpc17_setdacenable(unsigned int port, unsigned int pin) ****************************************************************************/ #if 0 /* Not used */ -static void lpc17_setdacdisable(unsigned int port, unsigned int pin) +static void lpc17_40_setdacdisable(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval &= ~IOCON_DACEN_MASK; putreg32(regval, regaddr); @@ -383,14 +383,14 @@ static void lpc17_setdacdisable(unsigned int port, unsigned int pin) #endif /**************************************************************************** - * Name: lpc17_setfilter + * Name: lpc17_40_setfilter * * Description: * Configure analog pin's glitch filter. Applies to Type A and Type W pins * ****************************************************************************/ -static void lpc17_setfilter(lpc17_pinset_t cfgset, unsigned int port, +static void lpc17_40_setfilter(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regaddr; @@ -403,7 +403,7 @@ static void lpc17_setfilter(lpc17_pinset_t cfgset, unsigned int port, /* Get the current IOCON register contents */ - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); /* Set the input filter enable bit */ @@ -414,7 +414,7 @@ static void lpc17_setfilter(lpc17_pinset_t cfgset, unsigned int port, } /**************************************************************************** - * Name: lpc17_setopendrain + * Name: lpc17_40_setopendrain * * Description: * Configure a GPIO's opendrain mode. Applies to Type A, Type D, and @@ -422,19 +422,19 @@ static void lpc17_setfilter(lpc17_pinset_t cfgset, unsigned int port, * ****************************************************************************/ -static void lpc17_setopendrain(unsigned int port, unsigned int pin) +static void lpc17_40_setopendrain(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval |= IOCON_OD_MASK; putreg32(regval, regaddr); } /**************************************************************************** - * Name: lpc17_clropendrain + * Name: lpc17_40_clropendrain * * Description: * Configure a GPIO's opendrain mode. Applies to Type A, Type D, and @@ -442,19 +442,19 @@ static void lpc17_setopendrain(unsigned int port, unsigned int pin) * ****************************************************************************/ -static void lpc17_clropendrain(unsigned int port, unsigned int pin) +static void lpc17_40_clropendrain(unsigned int port, unsigned int pin) { uint32_t regaddr; uint32_t regval; - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); regval &= ~IOCON_OD_MASK; putreg32(regval, regaddr); } /**************************************************************************** - * Name: lpc17_sethysteresis + * Name: lpc17_40_sethysteresis * * Description: * Configure a GPIO's hysteresis mode. Applies to Type D and Type W pins @@ -462,7 +462,7 @@ static void lpc17_clropendrain(unsigned int port, unsigned int pin) * ****************************************************************************/ -static void lpc17_sethysteresis(lpc17_pinset_t cfgset, unsigned int port, +static void lpc17_40_sethysteresis(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regaddr; @@ -475,7 +475,7 @@ static void lpc17_sethysteresis(lpc17_pinset_t cfgset, unsigned int port, /* Get the current IOCON register contents */ - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); /* Set the input buffer enable bit */ @@ -486,7 +486,7 @@ static void lpc17_sethysteresis(lpc17_pinset_t cfgset, unsigned int port, } /**************************************************************************** - * Name: lpc17_pullup + * Name: lpc17_40_pullup * * Description: * Clear and set the pin mode bits. Applies to Type A, Type D, and @@ -494,7 +494,7 @@ static void lpc17_sethysteresis(lpc17_pinset_t cfgset, unsigned int port, * ****************************************************************************/ -static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port, +static void lpc17_40_setpullup(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regaddr; @@ -507,7 +507,7 @@ static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port, /* Get the current IOCON register contents */ - regaddr = LPC17_IOCON_P(port, pin); + regaddr = LPC17_40_IOCON_P(port, pin); regval = getreg32(regaddr); /* Set the new mode bits */ @@ -518,7 +518,7 @@ static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port, } /**************************************************************************** - * Name: lpc17_setintedge + * Name: lpc17_40_setintedge * * Description: * Remember the configured interrupt edge. We can't actually enable the @@ -526,8 +526,8 @@ static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port, * ****************************************************************************/ -#ifdef CONFIG_LPC17_GPIOIRQ -static void lpc17_setintedge(unsigned int port, unsigned int pin, +#ifdef CONFIG_LPC17_40_GPIOIRQ +static void lpc17_40_setintedge(unsigned int port, unsigned int pin, unsigned int value) { uint64_t *intedge; @@ -554,17 +554,17 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin, *intedge &= ~((uint64_t)3 << shift); *intedge |= ((uint64_t)value << shift); } -#endif /* CONFIG_LPC17_GPIOIRQ */ +#endif /* CONFIG_LPC17_40_GPIOIRQ */ /**************************************************************************** - * Name: lpc17_configinput + * Name: lpc17_40_configinput * * Description: * Configure a GPIO input pin based on bit-encoded description of the pin. * ****************************************************************************/ -static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, +static inline int lpc17_40_configinput(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regval; @@ -578,9 +578,9 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, /* Set as input */ - regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET); + regval = getreg32(fiobase + LPC17_40_FIO_DIR_OFFSET); regval &= ~pinmask; - putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET); + putreg32(regval, fiobase + LPC17_40_FIO_DIR_OFFSET); /* Set up interrupt registers */ @@ -589,88 +589,88 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, { /* Disable any rising edge interrupts */ - regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + regval = getreg32(intbase + LPC17_40_GPIOINT_INTENR_OFFSET); regval &= ~pinmask; - putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET); + putreg32(regval, intbase + LPC17_40_GPIOINT_INTENR_OFFSET); /* Disable any falling edge interrupts */ - regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + regval = getreg32(intbase + LPC17_40_GPIOINT_INTENF_OFFSET); regval &= ~pinmask; - putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET); + putreg32(regval, intbase + LPC17_40_GPIOINT_INTENF_OFFSET); /* Forget about any falling/rising edge interrupt enabled */ -#ifdef CONFIG_LPC17_GPIOIRQ - lpc17_setintedge(port, pin, 0); +#ifdef CONFIG_LPC17_40_GPIOIRQ + lpc17_40_setintedge(port, pin, 0); #endif } /* Set pull-up mode */ - lpc17_setpullup(cfgset, port, pin); + lpc17_40_setpullup(cfgset, port, pin); /* Clear opendrain */ - lpc17_clropendrain(port, pin); + lpc17_40_clropendrain(port, pin); /* Set input polarity */ if ((cfgset & GPIO_INVERT) != 0) { - lpc17_setinvertinput(port, pin); + lpc17_40_setinvertinput(port, pin); } /* Set input hysteresis */ - lpc17_sethysteresis(cfgset, port, pin); + lpc17_40_sethysteresis(cfgset, port, pin); /* Set input filtering */ - lpc17_setfilter(cfgset, port, pin); + lpc17_40_setfilter(cfgset, port, pin); /* Configure as GPIO */ - lpc17_setpinfunction(port, pin, IOCON_FUNC_GPIO); + lpc17_40_setpinfunction(port, pin, IOCON_FUNC_GPIO); return OK; } /**************************************************************************** - * Name: lpc17_configinterrupt + * Name: lpc17_40_configinterrupt * * Description: * Configure a GPIO interrupt pin based on bit-encoded description of the pin. * ****************************************************************************/ -static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port, +static inline int lpc17_40_configinterrupt(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { /* First, configure the port as a generic input so that we have a known * starting point and consistent behavior during the re-configuration. */ - (void)lpc17_configinput(cfgset, port, pin); + (void)lpc17_40_configinput(cfgset, port, pin); /* Then just remember the rising/falling edge interrupt enabled */ DEBUGASSERT(port == 0 || port == 2); -#ifdef CONFIG_LPC17_GPIOIRQ - lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); +#ifdef CONFIG_LPC17_40_GPIOIRQ + lpc17_40_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); #endif return OK; } /**************************************************************************** - * Name: lpc17_configoutput + * Name: lpc17_40_configoutput * * Description: * Configure a GPIO output pin based on bit-encoded description of the pin. * ****************************************************************************/ -static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, +static inline int lpc17_40_configoutput(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t fiobase; @@ -680,14 +680,14 @@ static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, * starting point and consistent behavior during the re-configuration. */ - (void)lpc17_configinput(DEFAULT_INPUT, port, pin); + (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin); /* Now, reconfigure the pin as an output */ fiobase = g_fiobase[port]; - regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET); + regval = getreg32(fiobase + LPC17_40_FIO_DIR_OFFSET); regval |= (1 << pin); - putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET); + putreg32(regval, fiobase + LPC17_40_FIO_DIR_OFFSET); /* Check for open drain output */ @@ -697,26 +697,26 @@ static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, * meaning if the port is an open drain output. */ - lpc17_setpullup(cfgset, port, pin); + lpc17_40_setpullup(cfgset, port, pin); /* Select open drain output */ - lpc17_setopendrain(port, pin); + lpc17_40_setopendrain(port, pin); } /* Set output slew rate */ - lpc17_setslewmode(cfgset, port, pin); + lpc17_40_setslewmode(cfgset, port, pin); /* Set the initial value of the output */ - lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + lpc17_40_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); return OK; } /**************************************************************************** - * Name: lpc17_configalternate + * Name: lpc17_40_configalternate * * Description: * Configure a GPIO alternate function pin based on bit-encoded description @@ -724,7 +724,7 @@ static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, * ****************************************************************************/ -static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, +static int lpc17_40_configalternate(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin, uint32_t alt) { uint32_t i2cmode; @@ -733,23 +733,23 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, * starting point and consistent behavior during the re-configuration. */ - (void)lpc17_configinput(DEFAULT_INPUT, port, pin); + (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin); /* Set pull-up mode */ - lpc17_setpullup(cfgset, port, pin); + lpc17_40_setpullup(cfgset, port, pin); /* Check for analog mode */ if ((cfgset & GPIO_MODE_ANALOG) != 0) { - lpc17_setmodeanalog(port, pin); + lpc17_40_setmodeanalog(port, pin); /* Check for DAC output enable */ if ((cfgset & GPIO_DACEN) != 0) { - lpc17_setdacenable(port, pin); + lpc17_40_setdacenable(port, pin); } } @@ -763,7 +763,7 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, /* Set I2C Modes */ - lpc17_seti2cmode(port, pin, i2cmode); + lpc17_40_seti2cmode(port, pin, i2cmode); } /* Check for open drain output */ @@ -772,16 +772,16 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, { /* Select open drain output */ - lpc17_setopendrain(port, pin); + lpc17_40_setopendrain(port, pin); } /* Set output slew rate */ - lpc17_setslewmode(cfgset, port, pin); + lpc17_40_setslewmode(cfgset, port, pin); /* Select the alternate pin */ - lpc17_setpinfunction(port, pin, alt); + lpc17_40_setpinfunction(port, pin, alt); return OK; } @@ -791,14 +791,14 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, ****************************************************************************/ /**************************************************************************** - * Name: lpc17_configgpio + * Name: lpc17_40_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * ****************************************************************************/ -int lpc17_configgpio(lpc17_pinset_t cfgset) +int lpc17_40_configgpio(lpc17_40_pinset_t cfgset) { unsigned int port; unsigned int pin; @@ -821,45 +821,45 @@ int lpc17_configgpio(lpc17_pinset_t cfgset) switch (cfgset & GPIO_FUNC_MASK) { case GPIO_INPUT: /* GPIO input pin */ - ret = lpc17_configinput(cfgset, port, pin); + ret = lpc17_40_configinput(cfgset, port, pin); break; case GPIO_INTFE: /* GPIO interrupt falling edge */ case GPIO_INTRE: /* GPIO interrupt rising edge */ case GPIO_INTBOTH: /* GPIO interrupt both edges */ - ret = lpc17_configinterrupt(cfgset, port, pin); + ret = lpc17_40_configinterrupt(cfgset, port, pin); break; case GPIO_OUTPUT: /* GPIO outpout pin */ - ret = lpc17_configoutput(cfgset, port, pin); + ret = lpc17_40_configoutput(cfgset, port, pin); break; case GPIO_ALT1: /* Alternate function 1 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1); break; case GPIO_ALT2: /* Alternate function 2 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2); break; case GPIO_ALT3: /* Alternate function 3 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3); break; case GPIO_ALT4: /* Alternate function 4 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT4); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT4); break; case GPIO_ALT5: /* Alternate function 5 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT5); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT5); break; case GPIO_ALT6: /* Alternate function 6 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT6); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT6); break; case GPIO_ALT7: /* Alternate function 7 */ - ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT7); + ret = lpc17_40_configalternate(cfgset, port, pin, IOCON_FUNC_ALT7); break; default: @@ -871,14 +871,14 @@ int lpc17_configgpio(lpc17_pinset_t cfgset) } /**************************************************************************** - * Name: lpc17_gpiowrite + * Name: lpc17_40_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) +void lpc17_40_gpiowrite(lpc17_40_pinset_t pinset, bool value) { uint32_t fiobase; uint32_t offset; @@ -900,11 +900,11 @@ void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) if (value) { - offset = LPC17_FIO_SET_OFFSET; + offset = LPC17_40_FIO_SET_OFFSET; } else { - offset = LPC17_FIO_CLR_OFFSET; + offset = LPC17_40_FIO_CLR_OFFSET; } putreg32((1 << pin), fiobase + offset); @@ -912,14 +912,14 @@ void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) } /**************************************************************************** - * Name: lpc17_gpioread + * Name: lpc17_40_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool lpc17_gpioread(lpc17_pinset_t pinset) +bool lpc17_40_gpioread(lpc17_40_pinset_t pinset) { uint32_t fiobase; unsigned int port; @@ -935,7 +935,7 @@ bool lpc17_gpioread(lpc17_pinset_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0); + return ((getreg32(fiobase + LPC17_40_FIO_PIN_OFFSET) & (1 << pin)) != 0); } return false; diff --git a/arch/arm/src/lpc17xx/lpc178x_gpio.h b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h similarity index 96% rename from arch/arm/src/lpc17xx/lpc178x_gpio.h rename to arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h index 2ddfd6ce6bc..3db6b18e207 100644 --- a/arch/arm/src/lpc17xx/lpc178x_gpio.h +++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc178x_gpio.h + * arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC178X_GPIO_H -#define __ARCH_ARM_SRC_LPC17XX_LPC178X_GPIO_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC178X_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC178X_GPIO_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Bit-encoded input to lpc17_configgpio() ******************************************/ +/* Bit-encoded input to lpc17_40_configgpio() ******************************************/ /* Encoding: TTTT TTTT FFFF MMOV PPPN NNNN * @@ -197,7 +197,7 @@ * Public Types ************************************************************************************/ -typedef uint32_t lpc17_pinset_t; +typedef uint32_t lpc17_40_pinset_t; /************************************************************************************ * Public Data @@ -222,4 +222,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC178X_GPIO_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC178X_GPIO_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_adc.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_adc.c similarity index 83% rename from arch/arm/src/lpc17xx/lpc17_adc.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_adc.c index b7d22b393b1..c09512813fb 100644 --- a/arch/arm/src/lpc17xx/lpc17_adc.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_adc.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_adc.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_adc.c * * Copyright (C) 2011 Li Zhuoyi. All rights reserved. * Copyright (C) 2016 Gregory Nutt. All rights reserved. @@ -63,26 +63,26 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_adc.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_adc.h" -#if defined(CONFIG_LPC17_ADC) +#if defined(CONFIG_LPC17_40_ADC) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_LPC17_ADC0_MASK -# define CONFIG_LPC17_ADC0_MASK 0x01 +#ifndef CONFIG_LPC17_40_ADC0_MASK +# define CONFIG_LPC17_40_ADC0_MASK 0x01 #endif -#ifndef CONFIG_LPC17_ADC0_SPS -# define CONFIG_LPC17_ADC0_SPS 1000 +#ifndef CONFIG_LPC17_40_ADC0_SPS +# define CONFIG_LPC17_40_ADC0_SPS 1000 #endif -#ifndef CONFIG_LPC17_ADC0_AVERAGE -# define CONFIG_LPC17_ADC0_AVERAGE 200 +#ifndef CONFIG_LPC17_40_ADC0_AVERAGE +# define CONFIG_LPC17_40_ADC0_AVERAGE 200 #endif /**************************************************************************** @@ -132,9 +132,9 @@ static const struct adc_ops_s g_adcops = static struct up_dev_s g_adcpriv = { - .sps = CONFIG_LPC17_ADC0_SPS, - .mask = CONFIG_LPC17_ADC0_MASK, - .irq = LPC17_IRQ_ADC, + .sps = CONFIG_LPC17_40_ADC0_SPS, + .mask = CONFIG_LPC17_40_ADC0_MASK, + .irq = LPC17_40_IRQ_ADC, }; static struct adc_dev_s g_adcdev = @@ -205,24 +205,24 @@ static void adc_reset(FAR struct adc_dev_s *dev) flags = enter_critical_section(); - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCADC; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Power up before we access hardware */ - putreg32(ADC_CR_PDN, LPC17_ADC_CR); + putreg32(ADC_CR_PDN, LPC17_40_ADC_CR); - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_ADC_MASK; regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_ADC_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); -#ifdef CONFIG_LPC17_ADC_BURSTMODE - clkdiv = LPC17_CCLK / 3 / 65 / priv->sps; +#ifdef CONFIG_LPC17_40_ADC_BURSTMODE + clkdiv = LPC17_40_CCLK / 3 / 65 / priv->sps; -//putreg32(0x04, LPC17_ADC_INTEN); /* Enable only last channel interrupt */ - putreg32(0x100, LPC17_ADC_INTEN); /* Enable only global interrupt */ +//putreg32(0x04, LPC17_40_ADC_INTEN); /* Enable only last channel interrupt */ + putreg32(0x100, LPC17_40_ADC_INTEN); /* Enable only global interrupt */ putreg32((priv->mask) | /* Select channels 0 to 7 on ADC0 */ // (clkdiv) << 8) | /* CLKDIV = divisor to make the samples @@ -236,55 +236,55 @@ static void adc_reset(FAR struct adc_dev_s *dev) (1 << 26) | (0 << 25) | (0 << 24) | /* START = at MAT0 signal */ (1 << 27), /* EDGE = 1 (CAP/MAT signal rising * trigger A/D conversion) */ - LPC17_ADC_CR); + LPC17_40_ADC_CR); -#else /* CONFIG_LPC17_ADC_BURSTMODE */ +#else /* CONFIG_LPC17_40_ADC_BURSTMODE */ - clkdiv = LPC17_CCLK / 8 / 65 / priv->sps; + clkdiv = LPC17_40_CCLK / 8 / 65 / priv->sps; clkdiv <<= 8; clkdiv &= 0xff00; - putreg32(ADC_CR_PDN | ADC_CR_BURST | clkdiv | priv->mask, LPC17_ADC_CR); + putreg32(ADC_CR_PDN | ADC_CR_BURST | clkdiv | priv->mask, LPC17_40_ADC_CR); -#endif /* CONFIG_LPC17_ADC_BURSTMODE */ +#endif /* CONFIG_LPC17_40_ADC_BURSTMODE */ if ((priv->mask & 0x01) != 0) { - lpc17_configgpio(GPIO_AD0p0); + lpc17_40_configgpio(GPIO_AD0p0); } if ((priv->mask & 0x02) != 0) { - lpc17_configgpio(GPIO_AD0p1); + lpc17_40_configgpio(GPIO_AD0p1); } if ((priv->mask & 0x04) != 0) { - lpc17_configgpio(GPIO_AD0p2); + lpc17_40_configgpio(GPIO_AD0p2); } if ((priv->mask & 0x08) != 0) { - lpc17_configgpio(GPIO_AD0p3); + lpc17_40_configgpio(GPIO_AD0p3); } if ((priv->mask & 0x10) != 0) { - lpc17_configgpio(GPIO_AD0p4); + lpc17_40_configgpio(GPIO_AD0p4); } if ((priv->mask & 0x20) != 0) { - lpc17_configgpio(GPIO_AD0p5); + lpc17_40_configgpio(GPIO_AD0p5); } if ((priv->mask & 0x40) != 0) { - lpc17_configgpio(GPIO_AD0p6); + lpc17_40_configgpio(GPIO_AD0p6); } if ((priv->mask & 0x80) != 0) { - lpc17_configgpio(GPIO_AD0p7); + lpc17_40_configgpio(GPIO_AD0p7); } leave_critical_section(flags); @@ -338,7 +338,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) * level of the NVIC. */ - putreg32(0, LPC17_ADC_INTEN); + putreg32(0, LPC17_40_ADC_INTEN); up_disable_irq(priv->irq); /* Then detach the ADC interrupt handler. */ @@ -360,28 +360,28 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) if (enable) { -#ifndef CONFIG_LPC17_ADC_BURSTMODE -#ifdef CONFIG_LPC17_ADC_CHANLIST +#ifndef CONFIG_LPC17_40_ADC_BURSTMODE +#ifdef CONFIG_LPC17_40_ADC_CHANLIST /* Trigger interrupt at the end of conversion on the last A/D channel * in the channel list. */ - putreg32(ADC_INTEN_CHAN(g_adc_chanlist[CONFIG_LPC17_ADC_NCHANNELS - 1]), - LPC17_ADC_INTEN); + putreg32(ADC_INTEN_CHAN(g_adc_chanlist[CONFIG_LPC17_40_ADC_NCHANNELS - 1]), + LPC17_40_ADC_INTEN); #else /* Trigger interrupt using the global DONE flag. */ - putreg32(ADC_INTEN_GLOBAL, LPC17_ADC_INTEN); + putreg32(ADC_INTEN_GLOBAL, LPC17_40_ADC_INTEN); #endif -#else /* CONFIG_LPC17_ADC_BURSTMODE */ +#else /* CONFIG_LPC17_40_ADC_BURSTMODE */ /* Enable only global interrupt */ - putreg32(0x100, LPC17_ADC_INTEN); -#endif /* CONFIG_LPC17_ADC_BURSTMODE */ + putreg32(0x100, LPC17_40_ADC_INTEN); +#endif /* CONFIG_LPC17_40_ADC_BURSTMODE */ } else { - putreg32(0, LPC17_ADC_INTEN); + putreg32(0, LPC17_40_ADC_INTEN); } } @@ -410,8 +410,8 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) static int adc_interrupt(int irq, void *context, FAR void *arg) { -#ifndef CONFIG_LPC17_ADC_BURSTMODE -#ifdef CONFIG_LPC17_ADC_CHANLIST +#ifndef CONFIG_LPC17_40_ADC_BURSTMODE +#ifdef CONFIG_LPC17_40_ADC_CHANLIST FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv; uint32_t regval; @@ -419,18 +419,18 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) int32_t value; int i; - regval = getreg32(LPC17_ADC_GDR); - for (i = 0; i < CONFIG_LPC17_ADC_NCHANNELS; i++) + regval = getreg32(LPC17_40_ADC_GDR); + for (i = 0; i < CONFIG_LPC17_40_ADC_NCHANNELS; i++) { ch = g_adc_chanlist[i]; - regval = getreg32(LPC17_ADC_DR(ch)); + regval = getreg32(LPC17_40_ADC_DR(ch)); if (regval&ADC_DR_DONE) { priv->count[ch]++; priv->buf[ch] += regval & 0xfff0; - if (priv->count[ch] >= CONFIG_LPC17_ADC0_AVERAGE) + if (priv->count[ch] >= CONFIG_LPC17_40_ADC0_AVERAGE) { value = priv->buf[ch] / priv->count[ch]; value <<= 15; @@ -450,12 +450,12 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) unsigned char ch; int32_t value; - regval = getreg32(LPC17_ADC_GDR); + regval = getreg32(LPC17_40_ADC_GDR); ch = (regval >> 24) & 0x07; priv->buf[ch] += regval & 0xfff0; priv->count[ch]++; - if (priv->count[ch] >= CONFIG_LPC17_ADC0_AVERAGE) + if (priv->count[ch] >= CONFIG_LPC17_40_ADC0_AVERAGE) { value = priv->buf[ch] / priv->count[ch]; value <<= 15; @@ -467,19 +467,19 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) return OK; #endif -#else /* CONFIG_LPC17_ADC_BURSTMODE */ +#else /* CONFIG_LPC17_40_ADC_BURSTMODE */ FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv; volatile uint32_t regVal, regVal2, regVal3; /* Verify that an interrupt has actually occured */ - regVal2 = getreg32(LPC17_ADC_STAT); /* Read ADSTAT will clear the interrupt flag */ + regVal2 = getreg32(LPC17_40_ADC_STAT); /* Read ADSTAT will clear the interrupt flag */ if ((regVal2) & (1 << 16)) { if ((priv->mask & 0x01) != 0) { - regVal = getreg32(LPC17_ADC_DR0); + regVal = getreg32(LPC17_40_ADC_DR0); #ifdef CONFIG_ADC_DIRECT_ACCESS /* Store the data value plus the status bits */ @@ -505,7 +505,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x02) != 0) { - regVal = getreg32(LPC17_ADC_DR1); + regVal = getreg32(LPC17_40_ADC_DR1); #ifdef CONFIG_ADC_DIRECT_ACCESS /* Store the data value plus the status bits */ @@ -532,7 +532,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x04) != 0) { - regVal = getreg32(LPC17_ADC_DR2); + regVal = getreg32(LPC17_40_ADC_DR2); #ifdef CONFIG_ADC_DIRECT_ACCESS /* Store the data value plus the status bits */ @@ -559,7 +559,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x08) != 0) { - regVal = getreg32(LPC17_ADC_DR3); + regVal = getreg32(LPC17_40_ADC_DR3); if ((regVal) & (1 << 31)) { adc_receive(priv, 3, (regVal >> 4) & 0xFFF); @@ -568,7 +568,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x10) != 0) { - regVal = getreg32(LPC17_ADC_DR4); + regVal = getreg32(LPC17_40_ADC_DR4); if ((regVal) & (1 << 31)) { adc_receive(priv, 4, (regVal >> 4) & 0xFFF); @@ -577,7 +577,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x20) != 0) { - regVal = getreg32(LPC17_ADC_DR5); + regVal = getreg32(LPC17_40_ADC_DR5); if ((regVal) & (1 << 31)) { adc_receive(priv, 5, (regVal >> 4) & 0xFFF); @@ -586,7 +586,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x40) != 0) { - regVal = getreg32(LPC17_ADC_DR6); + regVal = getreg32(LPC17_40_ADC_DR6); if ((regVal) & (1 << 31)) { adc_receive(priv, 6, (regVal >> 4) & 0xFFF); @@ -595,7 +595,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) if ((priv->mask & 0x80) != 0) { - regVal = getreg32(LPC17_ADC_DR7); + regVal = getreg32(LPC17_40_ADC_DR7); if ((regVal) & (1 << 31)) { adc_receive(priv, 7, (regVal >> 4) & 0xFFF); @@ -612,7 +612,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) #endif /* CONFIG_ADC_WORKER_THREAD */ } - regVal3 = getreg32(LPC17_ADC_GDR); /* Read ADGDR clear the DONE and OVERRUN bits */ + regVal3 = getreg32(LPC17_40_ADC_GDR); /* Read ADGDR clear the DONE and OVERRUN bits */ putreg32((priv->mask) | /* Select channels 0 to 7 on ADC0 */ (32 << 8) | /* CLKDIV = 16 */ (0 << 16) | /* BURST = 1, BURST capture all selected channels */ @@ -621,12 +621,12 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) (1 << 26) | (0 << 25) | (0 << 24) | /* START = at MAT0 signal */ (1 << 27), /* EDGE = 1 (CAP/MAT signal rising trigger A/D * conversion) */ - LPC17_ADC_CR); + LPC17_40_ADC_CR); -//lpc17_gpiowrite(LPCXPRESSO_GPIO0_21, 0); /* Reset pin P0.21 */ +//lpc17_40_gpiowrite(LPCXPRESSO_GPIO0_21, 0); /* Reset pin P0.21 */ //leave_critical_section(saved_state); return OK; -#endif /* CONFIG_LPC17_ADC_BURSTMODE */ +#endif /* CONFIG_LPC17_40_ADC_BURSTMODE */ } /**************************************************************************** @@ -634,7 +634,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_adcinitialize + * Name: lpc17_40_adcinitialize * * Description: * Initialize the adc @@ -644,9 +644,9 @@ static int adc_interrupt(int irq, void *context, FAR void *arg) * ****************************************************************************/ -FAR struct adc_dev_s *lpc17_adcinitialize(void) +FAR struct adc_dev_s *lpc17_40_adcinitialize(void) { return &g_adcdev; } -#endif /* CONFIG_LPC17_ADC */ +#endif /* CONFIG_LPC17_40_ADC */ diff --git a/arch/arm/src/lpc17xx/lpc17_adc.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_adc.h similarity index 79% rename from arch/arm/src/lpc17xx/lpc17_adc.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_adc.h index 09f1b669840..c09a41cb478 100644 --- a/arch/arm/src/lpc17xx/lpc17_adc.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_adc.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_adc.h * * Copyright (C) 2010, 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,31 +33,31 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_ADC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_ADC_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "hardware/lpc17_adc.h" +#include "hardware/lpc17_40_adc.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ -/* If CONFIG_LPC17_ADC_CHANLIST is enabled, then the platform specific code - * must do two things: (1) define CONFIG_LPC17_ADC_NCHANNELS in the +/* If CONFIG_LPC17_40_ADC_CHANLIST is enabled, then the platform specific code + * must do two things: (1) define CONFIG_LPC17_40_ADC_NCHANNELS in the * configuration file and (2) provide an array g_adc_chanlist[] with the * channel numbers matching the ADC0_MASK within the board-specific library. */ -#ifdef CONFIG_LPC17_ADC_CHANLIST -# if !defined(CONFIG_LPC17_ADC_NCHANNELS) -# error "CONFIG_LPC17_ADC_CHANLIST must defined in this configuration" -# elif CONFIG_LPC17_ADC_NCHANNELS < 1 -# error "The value of CONFIG_LPC17_ADC_NCHANNELS is invalid" +#ifdef CONFIG_LPC17_40_ADC_CHANLIST +# if !defined(CONFIG_LPC17_40_ADC_NCHANNELS) +# error "CONFIG_LPC17_40_ADC_CHANLIST must defined in this configuration" +# elif CONFIG_LPC17_40_ADC_NCHANNELS < 1 +# error "The value of CONFIG_LPC17_40_ADC_NCHANNELS is invalid" # endif #endif @@ -81,19 +81,19 @@ extern "C" /* The errata that states: "A/D Global Data register should not be used with * burst mode or hardware triggering". The configuration option - * CONFIG_LPC17_ADC_CHANLIST is a workaround for this errata. If this option + * CONFIG_LPC17_40_ADC_CHANLIST is a workaround for this errata. If this option * is selected, then the ADC driver will grab from the individual channel * registers rather than from the global data register as this is the stated * workaround in the errata. * * If this option is enabled, then the platform specific code must do two - * things: (1) define CONFIG_LPC17_ADC_NCHANNELS in the configuration file + * things: (1) define CONFIG_LPC17_40_ADC_NCHANNELS in the configuration file * and (2) provide an array g_adc_chanlist[] with the channel numbers * matching the ADC0_MASK within the board-specific library. */ -#ifdef CONFIG_LPC17_ADC_CHANLIST -EXTERN uint8_t g_adc_chanlist[CONFIG_LPC17_ADC_NCHANNELS]; +#ifdef CONFIG_LPC17_40_ADC_CHANLIST +EXTERN uint8_t g_adc_chanlist[CONFIG_LPC17_40_ADC_NCHANNELS]; #endif /**************************************************************************** @@ -101,7 +101,7 @@ EXTERN uint8_t g_adc_chanlist[CONFIG_LPC17_ADC_NCHANNELS]; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_adcinitialize + * Name: lpc17_40_adcinitialize * * Description: * Initialize the adc @@ -111,8 +111,8 @@ EXTERN uint8_t g_adc_chanlist[CONFIG_LPC17_ADC_NCHANNELS]; * ****************************************************************************/ -#ifdef CONFIG_LPC17_ADC -FAR struct adc_dev_s *lpc17_adcinitialize(void); +#ifdef CONFIG_LPC17_40_ADC +FAR struct adc_dev_s *lpc17_40_adcinitialize(void); #endif #undef EXTERN @@ -120,4 +120,4 @@ FAR struct adc_dev_s *lpc17_adcinitialize(void); } #endif -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_ADC_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c similarity index 78% rename from arch/arm/src/lpc17xx/lpc17_allocateheap.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c index 14c5508598e..1775ab2b6a6 100644 --- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_allocateheap.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c * * Copyright (C) 2010-2011, 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,11 +52,11 @@ #include "up_arch.h" #include "up_internal.h" -#include "hardware/lpc17_memorymap.h" -#include "lpc17_emacram.h" -#include "lpc17_ohciram.h" -#include "lpc17_mpuinit.h" -#include "lpc17_start.h" +#include "hardware/lpc17_40_memorymap.h" +#include "lpc17_40_emacram.h" +#include "lpc17_40_ohciram.h" +#include "lpc17_40_mpuinit.h" +#include "lpc17_40_start.h" /**************************************************************************** * Pre-processor Definitions @@ -65,23 +65,23 @@ /* Configuration ************************************************************/ /* The configured RAM start address must be the beginning of CPU SRAM */ -#if CONFIG_RAM_START != LPC17_SRAM_BASE -# warning "CONFIG_RAM_START is not at LPC17_SRAM_BASE" +#if CONFIG_RAM_START != LPC17_40_SRAM_BASE +# warning "CONFIG_RAM_START is not at LPC17_40_SRAM_BASE" # undef CONFIG_RAM_START # undef CONFIG_RAM_END -# define CONFIG_RAM_START LPC17_SRAM_BASE -# define CONFIG_RAM_END (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE) +# define CONFIG_RAM_START LPC17_40_SRAM_BASE +# define CONFIG_RAM_END (LPC17_40_SRAM_BASE+LPC17_40_CPUSRAM_SIZE) #endif /* The configured RAM size must be less then or equal to the CPU SRAM size */ -#if CONFIG_RAM_SIZE > LPC17_CPUSRAM_SIZE +#if CONFIG_RAM_SIZE > LPC17_40_CPUSRAM_SIZE # warning "CONFIG_RAM_SIZE is larger than the size of CPU SRAM" # undef CONFIG_RAM_SIZE # undef CONFIG_RAM_END -# define CONFIG_RAM_SIZE LPC17_CPUSRAM_SIZE -# define CONFIG_RAM_END (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE) -#elif CONFIG_RAM_SIZE < LPC17_CPUSRAM_SIZE +# define CONFIG_RAM_SIZE LPC17_40_CPUSRAM_SIZE +# define CONFIG_RAM_END (LPC17_40_SRAM_BASE+LPC17_40_CPUSRAM_SIZE) +#elif CONFIG_RAM_SIZE < LPC17_40_CPUSRAM_SIZE # warning "CONFIG_RAM_END is before end of CPU SRAM... not all of CPU SRAM used" #endif @@ -97,82 +97,82 @@ * end of Bank 0. */ -#undef LPC17_AHB_HEAPBASE /* Assume that nothing is available */ -#undef LPC17_AHB_HEAPSIZE +#undef LPC17_40_AHB_HEAPBASE /* Assume that nothing is available */ +#undef LPC17_40_AHB_HEAPSIZE /* If we have Bank 0, then we may possibly also have Bank 1 */ -#ifdef LPC17_HAVE_BANK0 +#ifdef LPC17_40_HAVE_BANK0 /* We have BANK0 (and, hence, possibly Bank1). Is Bank0 all used for * Ethernet packet buffering? Or is there any part of Bank0 available for * the heap. */ -# ifdef LPC17_BANK0_HEAPSIZE +# ifdef LPC17_40_BANK0_HEAPSIZE /* Some or all of Bank0 is available for the heap. The heap will begin * in bank 1. */ -# define LPC17_AHB_HEAPBASE LPC17_BANK0_HEAPBASE +# define LPC17_40_AHB_HEAPBASE LPC17_40_BANK0_HEAPBASE /* Is Bank1 present? Has there available heap memory in Bank 1? */ -# if defined(LPC17_HAVE_BANK1) && defined(LPC17_BANK1_HEAPSIZE) +# if defined(LPC17_40_HAVE_BANK1) && defined(LPC17_40_BANK1_HEAPSIZE) /* Yes... the heap space available is the unused memory at the end * of Bank0 plus the unused memory at the beginning of Bank 1. */ -# define LPC17_AHB_HEAPSIZE (LPC17_BANK0_HEAPSIZE + LPC17_BANK1_HEAPSIZE) +# define LPC17_40_AHB_HEAPSIZE (LPC17_40_BANK0_HEAPSIZE + LPC17_40_BANK1_HEAPSIZE) # else /* No... the heap space available is only the unused memory at the * end of Bank 0. */ -# define LPC17_AHB_HEAPSIZE LPC17_BANK0_HEAPSIZE +# define LPC17_40_AHB_HEAPSIZE LPC17_40_BANK0_HEAPSIZE -# endif /* LPC17_HAVE_BANK1 && LPC17_BANK1_HEAPSIZE */ -# else /* !LPC17_BANK0_HEAPSIZE */ +# endif /* LPC17_40_HAVE_BANK1 && LPC17_40_BANK1_HEAPSIZE */ +# else /* !LPC17_40_BANK0_HEAPSIZE */ /* We have Bank 0, but no memory is available for the heap there. * Do we have Bank 1? Is any heap memory available in Bank 1? */ -# if defined(LPC17_HAVE_BANK1) && defined(LPC17_BANK1_HEAPSIZE) +# if defined(LPC17_40_HAVE_BANK1) && defined(LPC17_40_BANK1_HEAPSIZE) /* Yes... the heap space available is the unused memory at the * beginning of Bank1. */ -# define LPC17_AHB_HEAPBASE LPC17_BANK1_HEAPBASE -# define LPC17_AHB_HEAPSIZE LPC17_BANK1_HEAPSIZE +# define LPC17_40_AHB_HEAPBASE LPC17_40_BANK1_HEAPBASE +# define LPC17_40_AHB_HEAPSIZE LPC17_40_BANK1_HEAPSIZE -# endif /* LPC17_HAVE_BANK1 && LPC17_BANK1_HEAPSIZE */ -# endif /* LPC17_BANK0_HEAPSIZE */ -#endif /* LPC17_HAVE_BANK0 */ +# endif /* LPC17_40_HAVE_BANK1 && LPC17_40_BANK1_HEAPSIZE */ +# endif /* LPC17_40_BANK0_HEAPSIZE */ +#endif /* LPC17_40_HAVE_BANK0 */ /* Sanity checking */ -#if !defined(CONFIG_LPC17_EXTDRAMHEAP) && !defined(CONFIG_LPC17_EXTSRAM0HEAP) -# define LPC17_EXT_MM_REGIONS 0 -#elif defined(CONFIG_LPC17_EXTDRAMHEAP) && defined(CONFIG_LPC17_EXTSRAM0HEAP) -# define LPC17_EXT_MM_REGIONS 2 +#if !defined(CONFIG_LPC17_40_EXTDRAMHEAP) && !defined(CONFIG_LPC17_40_EXTSRAM0HEAP) +# define LPC17_40_EXT_MM_REGIONS 0 +#elif defined(CONFIG_LPC17_40_EXTDRAMHEAP) && defined(CONFIG_LPC17_40_EXTSRAM0HEAP) +# define LPC17_40_EXT_MM_REGIONS 2 #else -# define LPC17_EXT_MM_REGIONS 1 +# define LPC17_40_EXT_MM_REGIONS 1 #endif -#ifdef LPC17_AHB_HEAPBASE -# if CONFIG_MM_REGIONS < 2 + LPC17_EXT_MM_REGIONS +#ifdef LPC17_40_AHB_HEAPBASE +# if CONFIG_MM_REGIONS < 2 + LPC17_40_EXT_MM_REGIONS # warning "CONFIG_MM_REGIONS < 2: Available AHB SRAM Bank(s) not included in HEAP" # endif -# if (CONFIG_MM_REGIONS > 2 + LPC17_EXT_MM_REGIONS) +# if (CONFIG_MM_REGIONS > 2 + LPC17_40_EXT_MM_REGIONS) # warning "CONFIG_MM_REGIONS > 2: Are additional regions handled by application?" # endif #else -# if CONFIG_MM_REGIONS > 1 + LPC17_EXT_MM_REGIONS +# if CONFIG_MM_REGIONS > 1 + LPC17_40_EXT_MM_REGIONS # warning "CONFIG_MM_REGIONS > 1: This configuration has no available AHB SRAM Bank0/1" # warning "CONFIG_MM_REGIONS > 1: Are additional regions handled by application?" # endif @@ -248,10 +248,10 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - lpc17_mpu_uheap((uintptr_t)ubase, usize); + lpc17_40_mpu_uheap((uintptr_t)ubase, usize); -#elif CONFIG_MM_REGIONS >= 3 && defined(CONFIG_LPC17_EXTDRAM) && \ - defined(CONFIG_LPC17_EXTDRAMHEAP) +#elif CONFIG_MM_REGIONS >= 3 && defined(CONFIG_LPC17_40_EXTDRAM) && \ + defined(CONFIG_LPC17_40_EXTDRAMHEAP) /* We are going to allocate a DRAM heap. In the case where a bootloader * is used (and has initialized SDRAM), it is possible that .data, .bss, * and the IDLE stack reside in SDRAM. @@ -364,38 +364,38 @@ void up_addregion(void) * Is any memory available in AHB SRAM for the heap? */ -#ifdef LPC17_AHB_HEAPBASE +#ifdef LPC17_40_AHB_HEAPBASE #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Yes.. allow user-mode access to the AHB SRAM user heap memory */ -#if defined(LPC17_BANK0_HEAPBASE) && defined(LPC17_BANK0_HEAPSIZE) - lpc17_mpu_uheap((uintptr_t)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE); +#if defined(LPC17_40_BANK0_HEAPBASE) && defined(LPC17_40_BANK0_HEAPSIZE) + lpc17_40_mpu_uheap((uintptr_t)LPC17_40_BANK0_HEAPBASE, LPC17_40_BANK0_HEAPSIZE); #endif -#if defined(LPC17_BANK1_HEAPBASE) && defined(LPC17_BANK1_HEAPSIZE) - lpc17_mpu_uheap((uintptr_t)LPC17_BANK1_HEAPBASE, LPC17_BANK1_HEAPSIZE); +#if defined(LPC17_40_BANK1_HEAPBASE) && defined(LPC17_40_BANK1_HEAPSIZE) + lpc17_40_mpu_uheap((uintptr_t)LPC17_40_BANK1_HEAPBASE, LPC17_40_BANK1_HEAPSIZE); #endif #endif /* CONFIG_BUILD_PROTECTED && CONFIG_MM_KERNEL_HEAP */ /* Add the AHB SRAM user heap region. */ - kumm_addregion((FAR void *)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE); + kumm_addregion((FAR void *)LPC17_40_AHB_HEAPBASE, LPC17_40_AHB_HEAPSIZE); #endif #if CONFIG_MM_REGIONS >= 3 -#if defined(CONFIG_LPC17_EXTDRAM) && defined(CONFIG_LPC17_EXTDRAMHEAP) +#if defined(CONFIG_LPC17_40_EXTDRAM) && defined(CONFIG_LPC17_40_EXTDRAMHEAP) { /* Memory may be reserved at the beginning of DRAM for other purposes * (for example for video framebuffers). Memory can similar be - * reserved at the end of DRAM using LPC17_EXTDRAMSIZE. The amount to - * be added to the heap will be from DRAM_BASE + LPC17_EXTDRAMHEAP_OFFSET - * through DRAM_BASE + LPC17_EXTDRAMSIZE where (DRAM_BASE is the base + * reserved at the end of DRAM using LPC17_40_EXTDRAMSIZE. The amount to + * be added to the heap will be from DRAM_BASE + LPC17_40_EXTDRAMHEAP_OFFSET + * through DRAM_BASE + LPC17_40_EXTDRAMSIZE where (DRAM_BASE is the base * address of CS0). */ - uintptr_t dram_end = LPC17_EXTDRAM_CS0 + CONFIG_LPC17_EXTDRAMSIZE; + uintptr_t dram_end = LPC17_40_EXTDRAM_CS0 + CONFIG_LPC17_40_EXTDRAMSIZE; uintptr_t dram_start; uintptr_t heap_size; @@ -403,7 +403,7 @@ void up_addregion(void) * stack lie in SDRAM? */ - if (g_idle_topstack >= LPC17_EXTDRAM_CS0 && + if (g_idle_topstack >= LPC17_40_EXTDRAM_CS0 && g_idle_topstack < dram_end) { /* Yes, then the SDRAM heap starts in SDRAM after the IDLE stack */ @@ -416,7 +416,7 @@ void up_addregion(void) * the beginning of DRAM). */ - dram_start = LPC17_EXTDRAM_CS0 + CONFIG_LPC17_EXTDRAMHEAP_OFFSET; + dram_start = LPC17_40_EXTDRAM_CS0 + CONFIG_LPC17_40_EXTDRAMHEAP_OFFSET; } heap_size = dram_end - dram_start; @@ -429,7 +429,7 @@ void up_addregion(void) * region if dram_start is not at the beginning of CS0. */ - lpc17_mpu_uheap(dram_start, heap_size); + lpc17_40_mpu_uheap(dram_start, heap_size); #endif /* Add external DRAM heap memory to the user heap */ @@ -438,17 +438,17 @@ void up_addregion(void) } #endif -#if !defined(CONFIG_LPC17_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4) -#if defined(CONFIG_LPC17_EXTSRAM0) && defined(CONFIG_LPC17_EXTSRAM0HEAP) +#if !defined(CONFIG_LPC17_40_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4) +#if defined(CONFIG_LPC17_40_EXTSRAM0) && defined(CONFIG_LPC17_40_EXTSRAM0HEAP) #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to external SRAM heap memory */ - lpc17_mpu_uheap((uintptr_t)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE); + lpc17_40_mpu_uheap((uintptr_t)LPC17_40_EXTSRAM_CS0, CONFIG_LPC17_40_EXTSRAM0SIZE); #endif /* Add external SRAM heap memory to the user heap */ - kumm_addregion((FAR void *)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE); + kumm_addregion((FAR void *)LPC17_40_EXTSRAM_CS0, CONFIG_LPC17_40_EXTSRAM0SIZE); #endif #endif #endif /* CONFIG_MM_REGIONS >= 3 */ diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c similarity index 81% rename from arch/arm/src/lpc17xx/lpc17_can.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_can.c index 3d3069b0b55..2c596559806 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_can.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_can.c * * Copyright (C) 2011 Li Zhuoyi. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved. @@ -63,111 +63,111 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_can.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_can.h" -#if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) +#if defined(CONFIG_LPC17_40_CAN1) || defined(CONFIG_LPC17_40_CAN2) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ -#ifdef CONFIG_LPC17_CAN1 +#ifdef CONFIG_LPC17_40_CAN1 /* A CAN bit rate must be provided */ -# ifndef CONFIG_LPC17_CAN1_BAUD -# error "CONFIG_LPC17_CAN1_BAUD is not defined" +# ifndef CONFIG_LPC17_40_CAN1_BAUD +# error "CONFIG_LPC17_40_CAN1_BAUD is not defined" # endif /* If no divsor is provided, use a divisor of 4 */ -# ifndef CONFIG_LPC17_CAN1_DIVISOR -# define CONFIG_LPC17_CAN1_DIVISOR 4 +# ifndef CONFIG_LPC17_40_CAN1_DIVISOR +# define CONFIG_LPC17_40_CAN1_DIVISOR 4 # endif /* Get the SYSCON_PCLKSEL value for CAN1 the implements this divisor */ -# if CONFIG_LPC17_CAN1_DIVISOR == 1 +# if CONFIG_LPC17_40_CAN1_DIVISOR == 1 # define CAN1_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK -# elif CONFIG_LPC17_CAN1_DIVISOR == 2 +# elif CONFIG_LPC17_40_CAN1_DIVISOR == 2 # define CAN1_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK2 -# elif CONFIG_LPC17_CAN1_DIVISOR == 4 +# elif CONFIG_LPC17_40_CAN1_DIVISOR == 4 # define CAN1_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK4 -# elif CONFIG_LPC17_CAN1_DIVISOR == 6 +# elif CONFIG_LPC17_40_CAN1_DIVISOR == 6 # define CAN1_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK6 # else -# error "Unsupported value of CONFIG_LPC17_CAN1_DIVISOR" +# error "Unsupported value of CONFIG_LPC17_40_CAN1_DIVISOR" # endif #endif -#ifdef CONFIG_LPC17_CAN2 +#ifdef CONFIG_LPC17_40_CAN2 /* A CAN bit rate must be provided */ -# ifndef CONFIG_LPC17_CAN2_BAUD -# error "CONFIG_LPC17_CAN2_BAUD is not defined" +# ifndef CONFIG_LPC17_40_CAN2_BAUD +# error "CONFIG_LPC17_40_CAN2_BAUD is not defined" # endif /* If no divsor is provided, use a divisor of 4 */ -# ifndef CONFIG_LPC17_CAN2_DIVISOR -# define CONFIG_LPC17_CAN2_DIVISOR 4 +# ifndef CONFIG_LPC17_40_CAN2_DIVISOR +# define CONFIG_LPC17_40_CAN2_DIVISOR 4 # endif /* Get the SYSCON_PCLKSEL value for CAN2 the implements this divisor */ -# if CONFIG_LPC17_CAN2_DIVISOR == 1 +# if CONFIG_LPC17_40_CAN2_DIVISOR == 1 # define CAN2_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK -# elif CONFIG_LPC17_CAN2_DIVISOR == 2 +# elif CONFIG_LPC17_40_CAN2_DIVISOR == 2 # define CAN2_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK2 -# elif CONFIG_LPC17_CAN2_DIVISOR == 4 +# elif CONFIG_LPC17_40_CAN2_DIVISOR == 4 # define CAN2_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK4 -# elif CONFIG_LPC17_CAN2_DIVISOR == 6 +# elif CONFIG_LPC17_40_CAN2_DIVISOR == 6 # define CAN2_CCLK_DIVISOR SYSCON_PCLKSEL_CCLK6 # else -# error "Unsupported value of CONFIG_LPC17_CAN2_DIVISOR" +# error "Unsupported value of CONFIG_LPC17_40_CAN2_DIVISOR" # endif #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_LPC17_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_LPC17_40_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_LPC17_CAN_TSEG1 -# define CONFIG_LPC17_CAN_TSEG1 6 +#ifndef CONFIG_LPC17_40_CAN_TSEG1 +# define CONFIG_LPC17_40_CAN_TSEG1 6 #endif -#if CONFIG_LPC17_CAN_TSEG1 < 1 || CONFIG_LPC17_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# errror "CONFIG_LPC17_CAN_TSEG1 is out of range" +#if CONFIG_LPC17_40_CAN_TSEG1 < 1 || CONFIG_LPC17_40_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# errror "CONFIG_LPC17_40_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_LPC17_CAN_TSEG2 -# define CONFIG_LPC17_CAN_TSEG2 7 +#ifndef CONFIG_LPC17_40_CAN_TSEG2 +# define CONFIG_LPC17_40_CAN_TSEG2 7 #endif -#if CONFIG_LPC17_CAN_TSEG2 < 1 || CONFIG_LPC17_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# errror "CONFIG_LPC17_CAN_TSEG2 is out of range" +#if CONFIG_LPC17_40_CAN_TSEG2 < 1 || CONFIG_LPC17_40_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# errror "CONFIG_LPC17_40_CAN_TSEG2 is out of range" #endif -#define CAN_BIT_QUANTA (CONFIG_LPC17_CAN_TSEG1 + CONFIG_LPC17_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_LPC17_40_CAN_TSEG1 + CONFIG_LPC17_40_CAN_TSEG2 + 1) /* Debug ********************************************************************/ /* Non-standard debug that may be enabled just for testing CAN */ #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_LPC17_CAN_REGDEBUG +# undef CONFIG_LPC17_40_CAN_REGDEBUG #endif /* Timing *******************************************************************/ /* CAN clocking is provided at CCLK divided by the configured divisor */ -#define CAN_CLOCK_FREQUENCY(d) ((uint32_t)LPC17_CCLK / (uint32_t)(d)) +#define CAN_CLOCK_FREQUENCY(d) ((uint32_t)LPC17_40_CCLK / (uint32_t)(d)) /**************************************************************************** * Private Types @@ -186,14 +186,14 @@ struct up_dev_s ****************************************************************************/ /* CAN Register access */ -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static void can_printreg(uint32_t addr, uint32_t value); #endif static uint32_t can_getreg(struct up_dev_s *priv, int offset); static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value); -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static uint32_t can_getcommon(uint32_t addr); static void can_putcommon(uint32_t addr, uint32_t value); #else @@ -241,13 +241,13 @@ static const struct can_ops_s g_canops = .co_txempty = lpc17can_txempty, }; -#ifdef CONFIG_LPC17_CAN1 +#ifdef CONFIG_LPC17_40_CAN1 static struct up_dev_s g_can1priv = { .port = 1, - .divisor = CONFIG_LPC17_CAN1_DIVISOR, - .baud = CONFIG_LPC17_CAN1_BAUD, - .base = LPC17_CAN1_BASE, + .divisor = CONFIG_LPC17_40_CAN1_DIVISOR, + .baud = CONFIG_LPC17_40_CAN1_BAUD, + .base = LPC17_40_CAN1_BASE, }; static struct can_dev_s g_can1dev = @@ -257,13 +257,13 @@ static struct can_dev_s g_can1dev = }; #endif -#ifdef CONFIG_LPC17_CAN2 +#ifdef CONFIG_LPC17_40_CAN2 static struct up_dev_s g_can2priv = { .port = 2, - .divisor = CONFIG_LPC17_CAN2_DIVISOR, - .baud = CONFIG_LPC17_CAN2_BAUD, - .base = LPC17_CAN2_BASE, + .divisor = CONFIG_LPC17_40_CAN2_DIVISOR, + .baud = CONFIG_LPC17_40_CAN2_BAUD, + .base = LPC17_40_CAN2_BASE, }; static struct can_dev_s g_can2dev = @@ -291,7 +291,7 @@ static struct can_dev_s g_can2dev = * ****************************************************************************/ -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static void can_printreg(uint32_t addr, uint32_t value) { static uint32_t prevaddr = 0; @@ -355,7 +355,7 @@ static void can_printreg(uint32_t addr, uint32_t value) * ****************************************************************************/ -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static uint32_t can_getreg(struct up_dev_s *priv, int offset) { uint32_t addr; @@ -391,7 +391,7 @@ static uint32_t can_getreg(struct up_dev_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) { uint32_t addr = priv->base + offset; @@ -425,7 +425,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) * ****************************************************************************/ -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static uint32_t can_getcommon(uint32_t addr) { uint32_t value; @@ -453,7 +453,7 @@ static uint32_t can_getcommon(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_LPC17_CAN_REGDEBUG +#ifdef CONFIG_LPC17_40_CAN_REGDEBUG static void can_putcommon(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -493,10 +493,10 @@ static void lpc17can_reset(FAR struct can_dev_s *dev) /* Disable the CAN and stop ongong transmissions */ - can_putreg(priv, LPC17_CAN_MOD_OFFSET, CAN_MOD_RM); /* Enter Reset Mode */ - can_putreg(priv, LPC17_CAN_IER_OFFSET, 0); /* Disable interrupts */ - can_putreg(priv, LPC17_CAN_GSR_OFFSET, 0); /* Clear status bits */ - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_AT); /* Abort transmission */ + can_putreg(priv, LPC17_40_CAN_MOD_OFFSET, CAN_MOD_RM); /* Enter Reset Mode */ + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, 0); /* Disable interrupts */ + can_putreg(priv, LPC17_40_CAN_GSR_OFFSET, 0); /* Clear status bits */ + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_AT); /* Abort transmission */ /* Set bit timing */ @@ -509,11 +509,11 @@ static void lpc17can_reset(FAR struct can_dev_s *dev) /* Restart the CAN */ #ifdef CONFIG_CAN_LOOPBACK - can_putreg(priv, LPC17_CAN_MOD_OFFSET, CAN_MOD_STM); /* Leave Reset Mode, enter Test Mode */ + can_putreg(priv, LPC17_40_CAN_MOD_OFFSET, CAN_MOD_STM); /* Leave Reset Mode, enter Test Mode */ #else - can_putreg(priv, LPC17_CAN_MOD_OFFSET, 0); /* Leave Reset Mode */ + can_putreg(priv, LPC17_40_CAN_MOD_OFFSET, 0); /* Leave Reset Mode */ #endif - can_putcommon(LPC17_CANAF_AFMR, CANAF_AFMR_ACCBP); /* All RX messages accepted */ + can_putcommon(LPC17_40_CANAF_AFMR, CANAF_AFMR_ACCBP); /* All RX messages accepted */ leave_critical_section(flags); } @@ -543,10 +543,10 @@ static int lpc17can_setup(FAR struct can_dev_s *dev) caninfo("CAN%d\n", priv->port); - ret = irq_attach(LPC17_IRQ_CAN, can12_interrupt, NULL); + ret = irq_attach(LPC17_40_IRQ_CAN, can12_interrupt, NULL); if (ret == OK) { - up_enable_irq(LPC17_IRQ_CAN); + up_enable_irq(LPC17_40_IRQ_CAN); } return ret; @@ -575,8 +575,8 @@ static void lpc17can_shutdown(FAR struct can_dev_s *dev) caninfo("CAN%d\n", priv->port); #endif - up_disable_irq(LPC17_IRQ_CAN); - irq_detach(LPC17_IRQ_CAN); + up_disable_irq(LPC17_40_IRQ_CAN); + irq_detach(LPC17_40_IRQ_CAN); } /**************************************************************************** @@ -606,7 +606,7 @@ static void lpc17can_rxint(FAR struct can_dev_s *dev, bool enable) */ flags = enter_critical_section(); - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); if (enable) { regval |= CAN_IER_RIE; @@ -616,7 +616,7 @@ static void lpc17can_rxint(FAR struct can_dev_s *dev, bool enable) regval &= ~CAN_IER_RIE; } - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); leave_critical_section(flags); } @@ -657,9 +657,9 @@ static void lpc17can_txint(FAR struct can_dev_s *dev, bool enable) /* Disable all TX interrupts */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval &= ~(CAN_IER_TIE1 | CAN_IER_TIE2 | CAN_IER_TIE3); - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); leave_critical_section(flags); } @@ -769,7 +769,7 @@ static int lpc17can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) /* Pick a transmit buffer */ - regval = can_getreg(priv, LPC17_CAN_SR_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_SR_OFFSET); if ((regval & CAN_SR_TBS1) != 0) { /* Make sure that buffer 1 TX interrupts are enabled BEFORE sending the @@ -781,23 +781,23 @@ static int lpc17can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) * following is safe because interrupts are disabled here. */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval |= CAN_IER_TIE1; - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); /* Set up the transfer */ - can_putreg(priv, LPC17_CAN_TFI1_OFFSET, tfi); - can_putreg(priv, LPC17_CAN_TID1_OFFSET, tid); - can_putreg(priv, LPC17_CAN_TDA1_OFFSET, *(uint32_t *)&msg->cm_data[0]); - can_putreg(priv, LPC17_CAN_TDB1_OFFSET, *(uint32_t *)&msg->cm_data[4]); + can_putreg(priv, LPC17_40_CAN_TFI1_OFFSET, tfi); + can_putreg(priv, LPC17_40_CAN_TID1_OFFSET, tid); + can_putreg(priv, LPC17_40_CAN_TDA1_OFFSET, *(uint32_t *)&msg->cm_data[0]); + can_putreg(priv, LPC17_40_CAN_TDB1_OFFSET, *(uint32_t *)&msg->cm_data[4]); /* Send the message */ #ifdef CONFIG_CAN_LOOPBACK - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_SRR); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_SRR); #else - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_TR); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_TR); #endif } else if ((regval & CAN_SR_TBS2) != 0) @@ -811,23 +811,23 @@ static int lpc17can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) * following is safe because interrupts are disabled here. */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval |= CAN_IER_TIE2; - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); /* Set up the transfer */ - can_putreg(priv, LPC17_CAN_TFI2_OFFSET, tfi); - can_putreg(priv, LPC17_CAN_TID2_OFFSET, tid); - can_putreg(priv, LPC17_CAN_TDA2_OFFSET, *(uint32_t *)&msg->cm_data[0]); - can_putreg(priv, LPC17_CAN_TDB2_OFFSET, *(uint32_t *)&msg->cm_data[4]); + can_putreg(priv, LPC17_40_CAN_TFI2_OFFSET, tfi); + can_putreg(priv, LPC17_40_CAN_TID2_OFFSET, tid); + can_putreg(priv, LPC17_40_CAN_TDA2_OFFSET, *(uint32_t *)&msg->cm_data[0]); + can_putreg(priv, LPC17_40_CAN_TDB2_OFFSET, *(uint32_t *)&msg->cm_data[4]); /* Send the message */ #ifdef CONFIG_CAN_LOOPBACK - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_SRR); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_SRR); #else - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_TR); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_TR); #endif } else if ((regval & CAN_SR_TBS3) != 0) @@ -841,23 +841,23 @@ static int lpc17can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) * following is safe because interrupts are disabled here. */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval |= CAN_IER_TIE3; - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); /* Set up the transfer */ - can_putreg(priv, LPC17_CAN_TFI3_OFFSET, tfi); - can_putreg(priv, LPC17_CAN_TID3_OFFSET, tid); - can_putreg(priv, LPC17_CAN_TDA3_OFFSET, *(uint32_t *)&msg->cm_data[0]); - can_putreg(priv, LPC17_CAN_TDB3_OFFSET, *(uint32_t *)&msg->cm_data[4]); + can_putreg(priv, LPC17_40_CAN_TFI3_OFFSET, tfi); + can_putreg(priv, LPC17_40_CAN_TID3_OFFSET, tid); + can_putreg(priv, LPC17_40_CAN_TDA3_OFFSET, *(uint32_t *)&msg->cm_data[0]); + can_putreg(priv, LPC17_40_CAN_TDB3_OFFSET, *(uint32_t *)&msg->cm_data[4]); /* Send the message */ #ifdef CONFIG_CAN_LOOPBACK - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB3 | CAN_CMR_SRR); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_STB3 | CAN_CMR_SRR); #else - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB3 | CAN_CMR_TR); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_STB3 | CAN_CMR_TR); #endif } else @@ -887,7 +887,7 @@ static int lpc17can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) static bool lpc17can_txready(FAR struct can_dev_s *dev) { FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; - uint32_t regval = can_getreg(priv, LPC17_CAN_SR_OFFSET); + uint32_t regval = can_getreg(priv, LPC17_40_CAN_SR_OFFSET); return ((regval & (CAN_SR_TBS1 | CAN_SR_TBS2 | CAN_SR_TBS3)) != 0); } @@ -912,7 +912,7 @@ static bool lpc17can_txready(FAR struct can_dev_s *dev) static bool lpc17can_txempty(FAR struct can_dev_s *dev) { FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; - uint32_t regval = can_getreg(priv, LPC17_CAN_GSR_OFFSET); + uint32_t regval = can_getreg(priv, LPC17_40_CAN_GSR_OFFSET); return ((regval & CAN_GSR_TBS) != 0); } @@ -941,21 +941,21 @@ static void can_interrupt(FAR struct can_dev_s *dev) /* Read the interrupt and capture register (also clearing most status bits) */ - regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_ICR_OFFSET); caninfo("CAN%d ICR: %08x\n", priv->port, regval); /* Check for a receive interrupt */ if ((regval & CAN_ICR_RI) != 0) { - rfs = can_getreg(priv, LPC17_CAN_RFS_OFFSET); - rid = can_getreg(priv, LPC17_CAN_RID_OFFSET); - data[0] = can_getreg(priv, LPC17_CAN_RDA_OFFSET); - data[1] = can_getreg(priv, LPC17_CAN_RDB_OFFSET); + rfs = can_getreg(priv, LPC17_40_CAN_RFS_OFFSET); + rid = can_getreg(priv, LPC17_40_CAN_RID_OFFSET); + data[0] = can_getreg(priv, LPC17_40_CAN_RDA_OFFSET); + data[1] = can_getreg(priv, LPC17_40_CAN_RDB_OFFSET); /* Release the receive buffer */ - can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_RRB); + can_putreg(priv, LPC17_40_CAN_CMR_OFFSET, CAN_CMR_RRB); /* Construct the CAN header */ @@ -989,9 +989,9 @@ static void can_interrupt(FAR struct can_dev_s *dev) { /* Disable all further TX buffer 1 interrupts */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval &= ~CAN_IER_TIE1; - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); /* Indicate that the TX is done and a new TX buffer is available */ @@ -1004,9 +1004,9 @@ static void can_interrupt(FAR struct can_dev_s *dev) { /* Disable all further TX buffer 2 interrupts */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval &= ~CAN_IER_TIE2; - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); /* Indicate that the TX is done and a new TX buffer is available */ @@ -1019,9 +1019,9 @@ static void can_interrupt(FAR struct can_dev_s *dev) { /* Disable all further TX buffer 3 interrupts */ - regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval = can_getreg(priv, LPC17_40_CAN_IER_OFFSET); regval &= ~CAN_IER_TIE3; - can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + can_putreg(priv, LPC17_40_CAN_IER_OFFSET, regval); /* Indicate that the TX is done and a new TX buffer is available */ @@ -1051,10 +1051,10 @@ static int can12_interrupt(int irq, void *context, FAR void *arg) caninfo("irq: %d\n", irq); -#ifdef CONFIG_LPC17_CAN1 +#ifdef CONFIG_LPC17_40_CAN1 can_interrupt(&g_can1dev); #endif -#ifdef CONFIG_LPC17_CAN2 +#ifdef CONFIG_LPC17_40_CAN2 can_interrupt(&g_can2dev); #endif @@ -1107,7 +1107,7 @@ static int can12_interrupt(int irq, void *context, FAR void *arg) * Tq = brp * Tcan * * Where: - * Tcan is the period of the APB clock (PCLK = CCLK / CONFIG_LPC17_CAN1_DIVISOR). + * Tcan is the period of the APB clock (PCLK = CCLK / CONFIG_LPC17_40_CAN1_DIVISOR). * * Input Parameters: * priv - A reference to the CAN block status @@ -1164,15 +1164,15 @@ static int can_bittiming(struct up_dev_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_LPC17_CAN_TSEG1, ts2 is - * CONFIG_LPC17_CAN_TSEG2 and we calculate brp to achieve CAN_BIT_QUANTA quanta + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_LPC17_40_CAN_TSEG1, ts2 is + * CONFIG_LPC17_40_CAN_TSEG2 and we calculate brp to achieve CAN_BIT_QUANTA quanta * in the bit time */ else { - ts1 = CONFIG_LPC17_CAN_TSEG1; - ts2 = CONFIG_LPC17_CAN_TSEG2; + ts1 = CONFIG_LPC17_40_CAN_TSEG1; + ts2 = CONFIG_LPC17_40_CAN_TSEG2; brp = (nclks + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >=1 && brp <= CAN_BTR_BRP_MAX); } @@ -1188,7 +1188,7 @@ static int can_bittiming(struct up_dev_s *priv) ((ts2 - 1) << CAN_BTR_TSEG2_SHIFT) | ((sjw - 1) << CAN_BTR_SJW_SHIFT)); -#ifdef CONFIG_LPC17_CAN_SAM +#ifdef CONFIG_LPC17_40_CAN_SAM /* The bus is sampled 3 times (recommended for low to medium speed buses * to spikes on the bus-line). */ @@ -1197,7 +1197,7 @@ static int can_bittiming(struct up_dev_s *priv) #endif caninfo("Setting CANxBTR= 0x%08x\n", btr); - can_putreg(priv, LPC17_CAN_BTR_OFFSET, btr); /* Set bit timing */ + can_putreg(priv, LPC17_40_CAN_BTR_OFFSET, btr); /* Set bit timing */ return OK; } @@ -1205,7 +1205,7 @@ static int can_bittiming(struct up_dev_s *priv) * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: lpc17_caninitialize + * Name: lpc17_40_caninitialize * * Description: * Initialize the selected can port @@ -1218,7 +1218,7 @@ static int can_bittiming(struct up_dev_s *priv) * ****************************************************************************/ -FAR struct can_dev_s *lpc17_caninitialize(int port) +FAR struct can_dev_s *lpc17_40_caninitialize(int port) { FAR struct can_dev_s *candev; irqstate_t flags; @@ -1228,67 +1228,67 @@ FAR struct can_dev_s *lpc17_caninitialize(int port) flags = enter_critical_section(); -#ifdef CONFIG_LPC17_CAN1 +#ifdef CONFIG_LPC17_40_CAN1 if (port == 1) { /* Enable power to the CAN module */ - regval = can_getcommon(LPC17_SYSCON_PCONP); + regval = can_getcommon(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCCAN1; - can_putcommon(LPC17_SYSCON_PCONP, regval); + can_putcommon(LPC17_40_SYSCON_PCONP, regval); /* Enable clocking to the CAN module (not necessary... already done * in low level clock configuration logic). */ -#ifdef LPC178x - regval = can_getcommon(LPC17_SYSCON_PCLKSEL); +#ifdef LPC178x_40xx + regval = can_getcommon(LPC17_40_SYSCON_PCLKSEL); regval &= SYSCON_PCLKSEL_PCLKDIV_MASK regval >>= SYSCON_PCLKSEL_PCLKDIV_SHIFT; g_can1pri.divisor = regval; #else - regval = can_getcommon(LPC17_SYSCON_PCLKSEL0); + regval = can_getcommon(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_CAN1_MASK; regval |= (CAN1_CCLK_DIVISOR << SYSCON_PCLKSEL0_CAN1_SHIFT); - can_putcommon(LPC17_SYSCON_PCLKSEL0, regval); + can_putcommon(LPC17_40_SYSCON_PCLKSEL0, regval); #endif /* Configure CAN GPIO pins */ - lpc17_configgpio(GPIO_CAN1_RD); - lpc17_configgpio(GPIO_CAN1_TD); + lpc17_40_configgpio(GPIO_CAN1_RD); + lpc17_40_configgpio(GPIO_CAN1_TD); candev = &g_can1dev; } else #endif -#ifdef CONFIG_LPC17_CAN2 +#ifdef CONFIG_LPC17_40_CAN2 if (port == 2) { /* Enable power to the CAN module */ - regval = can_getcommon(LPC17_SYSCON_PCONP); + regval = can_getcommon(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCCAN2; - can_putcommon(LPC17_SYSCON_PCONP, regval); + can_putcommon(LPC17_40_SYSCON_PCONP, regval); /* Enable clocking to the CAN module (not necessary... already done * in low level clock configuration logic). */ -#ifdef LPC178x - regval = can_getcommon(LPC17_SYSCON_PCLKSEL); +#ifdef LPC178x_40xx + regval = can_getcommon(LPC17_40_SYSCON_PCLKSEL); regval &= SYSCON_PCLKSEL_PCLKDIV_MASK; regval >>= SYSCON_PCLKSEL_PCLKDIV_SHIFT; g_can2priv.divisor = regval; #else - regval = can_getcommon(LPC17_SYSCON_PCLKSEL0); + regval = can_getcommon(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_CAN2_MASK; regval |= (CAN2_CCLK_DIVISOR << SYSCON_PCLKSEL0_CAN2_SHIFT); - can_putcommon(LPC17_SYSCON_PCLKSEL0, regval); + can_putcommon(LPC17_40_SYSCON_PCLKSEL0, regval); #endif /* Configure CAN GPIO pins */ - lpc17_configgpio(GPIO_CAN2_RD); - lpc17_configgpio(GPIO_CAN2_TD); + lpc17_40_configgpio(GPIO_CAN2_RD); + lpc17_40_configgpio(GPIO_CAN2_TD); candev = &g_can2dev; } diff --git a/arch/arm/src/lpc17xx/lpc17_can.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.h similarity index 88% rename from arch/arm/src/lpc17xx/lpc17_can.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_can.h index 271339ff054..cbbc752c821 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_can.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_can.h * * Copyright (C) 2010-2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CAN_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CAN_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "hardware/lpc17_can.h" +#include "hardware/lpc17_40_can.h" /**************************************************************************** * Pre-processor Definitions @@ -66,7 +66,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: lpc17_caninitialize + * Name: lpc17_40_caninitialize * * Description: * Initialize the selected can port @@ -79,9 +79,9 @@ extern "C" * ****************************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2)) +#if defined(CONFIG_CAN) && (defined(CONFIG_LPC17_40_CAN1) || defined(CONFIG_LPC17_40_CAN2)) struct can_dev_s; -FAR struct can_dev_s *lpc17_caninitialize(int port); +FAR struct can_dev_s *lpc17_40_caninitialize(int port); #endif #ifdef __cplusplus @@ -89,4 +89,4 @@ FAR struct can_dev_s *lpc17_caninitialize(int port); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CAN_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.c similarity index 82% rename from arch/arm/src/lpc17xx/lpc17_clockconfig.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.c index 97ef496f0df..87ba4346c87 100644 --- a/arch/arm/src/lpc17xx/lpc17_clockconfig.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.c @@ -1,6 +1,6 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_clockconfig.c - * arch/arm/src/chip/lpc17_clockconfig.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.c + * arch/arm/src/chip/lpc17_40_clockconfig.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -41,26 +41,26 @@ #include /* This file is only a thin shell that includes the correct clock - * configuration logic for the selected LPC17xx family. The correct file + * configuration logic for the selected LPC17xx/LPC40xx family. The correct file * cannot be selected by the make system because it needs the intelligence - * that only exists in chip.h that can associate an LPC17xx part number with - * an LPC17xx family. + * that only exists in chip.h that can associate an LPC17xx/LPC40xx part number with + * an LPC17xx/LPC40xx family. * - * The LPC176x and LPC178x system control block is *nearly* identical but - * we have found that the LPC178x is more sensitive to the ordering of + * The LPC176x and LPC178x_40xx system control block is *nearly* identical but + * we have found that the LPC178x_40xx is more sensitive to the ordering of * certain operations. So, although the hardware seems very similar, the - * safer thing to do is to separate the LPC176x and LPC178x into separate + * safer thing to do is to separate the LPC176x and LPC178x_40xx into separate * files. */ -#include +#include #if defined(LPC176x) # include "chip/lpc176x_clockconfig.c" -#elif defined(LPC178x) -# include "chip/lpc178x_clockconfig.c" +#elif defined(LPC178x_40xx) +# include "chip/lpc178x_40xx_clockconfig.c" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /**************************************************************************** diff --git a/arch/arm/src/lpc17xx/lpc17_clockconfig.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.h similarity index 89% rename from arch/arm/src/lpc17xx/lpc17_clockconfig.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.h index ffc9fa88dd5..b2e778cbf90 100644 --- a/arch/arm/src/lpc17xx/lpc17_clockconfig.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_clockconfig.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_clockconfig.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CLOCKCONFIG_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_CLOCKCONFIG_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CLOCKCONFIG_H /************************************************************************************ * Included Files @@ -65,20 +65,20 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: lpc17_clockconfig + * Name: lpc17_40_clockconfig * * Description: - * Called to initialize the LPC17XX. This does whatever setup is needed to put the + * Called to initialize the LPC17XX_40XX. This does whatever setup is needed to put the * MCU in a usable state. This includes the initialization of clocking using the * settings in board.h. * ************************************************************************************/ -void lpc17_clockconfig(void); +void lpc17_40_clockconfig(void); #ifdef __cplusplus } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CLOCKCONFIG_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CLOCKCONFIG_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_clrpend.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.c similarity index 87% rename from arch/arm/src/lpc17xx/lpc17_clrpend.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.c index 7a5552b3975..55546b66465 100644 --- a/arch/arm/src/lpc17xx/lpc17_clrpend.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.c @@ -1,6 +1,6 @@ /**************************************************************************** - * arch/arm/src/lpc17/lpc17_clrpend.c - * arch/arm/src/chip/lpc17_clrpend.c + * arch/arm/src/lpc17/lpc17_40_clrpend.c + * arch/arm/src/chip/lpc17_40_clrpend.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,7 +44,7 @@ #include "nvic.h" #include "up_arch.h" -#include "lpc17_clrpend.h" +#include "lpc17_40_clrpend.h" /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_clrpend + * Name: lpc17_40_clrpend * * Description: * Clear a pending interrupt at the NVIC. This does not seem to be required @@ -75,23 +75,23 @@ * interrupt definitely needs it! * * I keep it in a separate file so that it will not increase the footprint - * on LPC17xx platforms that do not need this function. + * on LPC17xx/LPC40xx platforms that do not need this function. * ****************************************************************************/ -void lpc17_clrpend(int irq) +void lpc17_40_clrpend(int irq) { /* Check for external interrupt */ - if (irq >= LPC17_IRQ_EXTINT) + if (irq >= LPC17_40_IRQ_EXTINT) { - if (irq < (LPC17_IRQ_EXTINT+32)) + if (irq < (LPC17_40_IRQ_EXTINT+32)) { - putreg32(1 << (irq - LPC17_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + putreg32(1 << (irq - LPC17_40_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); } - else if (irq < LPC17_IRQ_NIRQS) + else if (irq < LPC17_40_IRQ_NIRQS) { - putreg32(1 << (irq - LPC17_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); + putreg32(1 << (irq - LPC17_40_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); } } } diff --git a/arch/arm/src/lpc17xx/lpc17_clrpend.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.h similarity index 92% rename from arch/arm/src/lpc17xx/lpc17_clrpend.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.h index d7bf5b90dc5..6e00a63e5b9 100644 --- a/arch/arm/src/lpc17xx/lpc17_clrpend.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_clrpend.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_clrpend.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CLRPEND_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_CLRPEND_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CLRPEND_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CLRPEND_H /************************************************************************************ * Included Files @@ -65,7 +65,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: lpc17_clrpend + * Name: lpc17_40_clrpend * * Description: * Clear a pending interrupt at the NVIC. This does not seem to be required @@ -74,11 +74,11 @@ extern "C" * ************************************************************************************/ -void lpc17_clrpend(int irq); +void lpc17_40_clrpend(int irq); #ifdef __cplusplus } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CLRPEND_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_CLRPEND_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_dac.c similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_dac.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_dac.c index 301dc4133f1..19a09a3e9ca 100644 --- a/arch/arm/src/lpc17xx/lpc17_dac.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_dac.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_dac.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_dac.c * * Copyright (C) 2011 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi @@ -62,12 +62,12 @@ #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "hardware/lpc17_pinconfig.h" -#include "lpc17_gpio.h" -#include "lpc17_dac.h" +#include "hardware/lpc17_40_syscon.h" +#include "hardware/lpc17_40_pinconfig.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_dac.h" -#ifdef CONFIG_LPC17_DAC +#ifdef CONFIG_LPC17_40_DAC /**************************************************************************** * Private Types @@ -120,14 +120,14 @@ static void dac_reset(FAR struct dac_dev_s *dev) flags = enter_critical_section(); - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_DAC_MASK; regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_DAC_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); - //putreg32(DAC_CTRL_DBLBUFEN, LPC17_DAC_CTRL); ? + //putreg32(DAC_CTRL_DBLBUFEN, LPC17_40_DAC_CTRL); ? - lpc17_configgpio(GPIO_AOUT); + lpc17_40_configgpio(GPIO_AOUT); leave_critical_section(flags); } @@ -163,7 +163,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) * speed profile in bit 16) */ - putreg32(((((msg->am_data) << 6) | 0x10000) & 0xffff), LPC17_DAC_CR); + putreg32(((((msg->am_data) << 6) | 0x10000) & 0xffff), LPC17_40_DAC_CR); dac_txdone(&g_dacdev); return 0; } @@ -181,7 +181,7 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_dacinitialize + * Name: lpc17_40_dacinitialize * * Description: * Initialize the DAC @@ -191,10 +191,10 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -FAR struct dac_dev_s *lpc17_dacinitialize(void) +FAR struct dac_dev_s *lpc17_40_dacinitialize(void) { return &g_dacdev; } -#endif /* CONFIG_LPC17_DAC */ +#endif /* CONFIG_LPC17_40_DAC */ diff --git a/arch/arm/src/lpc17xx/lpc17_dac.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_dac.h similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_dac.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_dac.h index a27b6a66d17..924a6fb5b17 100644 --- a/arch/arm/src/lpc17xx/lpc17_dac.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_dac.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_dac.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_dac.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_DAC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_DAC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_DAC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_DAC_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_dac.h" +#include "hardware/lpc17_40_dac.h" /************************************************************************************ * Pre-processor Definitions @@ -66,7 +66,7 @@ extern "C" ************************************************************************************/ /**************************************************************************** - * Name: lpc17_dacinitialize + * Name: lpc17_40_dacinitialize * * Description: * Initialize the DAC @@ -76,8 +76,8 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_LPC17_DAC -FAR struct dac_dev_s *lpc17_dacinitialize(void); +#ifdef CONFIG_LPC17_40_DAC +FAR struct dac_dev_s *lpc17_40_dacinitialize(void); #endif #ifdef __cplusplus @@ -85,4 +85,4 @@ FAR struct dac_dev_s *lpc17_dacinitialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_DAC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_DAC_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_emacram.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_emacram.h similarity index 58% rename from arch/arm/src/lpc17xx/lpc17_emacram.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_emacram.h index f68e62734e4..37abaa63904 100644 --- a/arch/arm/src/lpc17xx/lpc17_emacram.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_emacram.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_emacram.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_emacram.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_EMACRAM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_EMACRAM_H /************************************************************************************ * Included Files @@ -42,47 +42,47 @@ #include #include "chip.h" -#include "hardware/lpc17_ethernet.h" -#include "hardware/lpc17_memorymap.h" +#include "hardware/lpc17_40_ethernet.h" +#include "hardware/lpc17_40_memorymap.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ /* Default, no-EMAC Case ************************************************************/ /* Assume that all of AHB SRAM will be available for heap. If this is not true, then - * LPC17_BANK0_HEAPSIZE will be undefined and redefined below. + * LPC17_40_BANK0_HEAPSIZE will be undefined and redefined below. */ -#undef LPC17_BANK0_HEAPBASE -#undef LPC17_BANK0_HEAPSIZE -#ifdef LPC17_HAVE_BANK0 -# define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0 -# define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE +#undef LPC17_40_BANK0_HEAPBASE +#undef LPC17_40_BANK0_HEAPSIZE +#ifdef LPC17_40_HAVE_BANK0 +# define LPC17_40_BANK0_HEAPBASE LPC17_40_SRAM_BANK0 +# define LPC17_40_BANK0_HEAPSIZE LPC17_40_BANK0_SIZE #endif -/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have +/* Is networking enabled? Is the LPC17xx/LPC40xx Ethernet device enabled? Does this chip have * and Ethernet controller? Yes... then we will replace the above default definitions. */ -#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0 +#if defined(CONFIG_NET) && defined(CONFIG_LPC17_40_ETHERNET) && LPC17_40_NETHCONTROLLERS > 0 /* EMAC RAM Configuration ***********************************************************/ /* Is AHB SRAM available? */ -#ifndef LPC17_HAVE_BANK0 +#ifndef LPC17_40_HAVE_BANK0 # error "AHB SRAM Bank0 is not available for EMAC RAM" #endif /* Number of Tx descriptors */ -#ifndef CONFIG_LPC17_ETH_NTXDESC -# define CONFIG_LPC17_ETH_NTXDESC 13 +#ifndef CONFIG_LPC17_40_ETH_NTXDESC +# define CONFIG_LPC17_40_ETH_NTXDESC 13 #endif /* Number of Rx descriptors */ -#ifndef CONFIG_LPC17_ETH_NRXDESC -# define CONFIG_LPC17_ETH_NRXDESC 13 +#ifndef CONFIG_LPC17_40_ETH_NRXDESC +# define CONFIG_LPC17_40_ETH_NRXDESC 13 #endif /* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC. @@ -90,15 +90,15 @@ * words. */ -#ifndef CONFIG_LPC17_EMACRAM_SIZE -# define CONFIG_LPC17_EMACRAM_SIZE LPC17_BANK0_SIZE +#ifndef CONFIG_LPC17_40_EMACRAM_SIZE +# define CONFIG_LPC17_40_EMACRAM_SIZE LPC17_40_BANK0_SIZE #endif -#if CONFIG_LPC17_EMACRAM_SIZE > LPC17_BANK0_SIZE +#if CONFIG_LPC17_40_EMACRAM_SIZE > LPC17_40_BANK0_SIZE # error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0" #endif -#if (CONFIG_LPC17_EMACRAM_SIZE & 3) != 0 +#if (CONFIG_LPC17_40_EMACRAM_SIZE & 3) != 0 # error "EMAC RAM size must be in multiples of 32-bit words" #endif @@ -106,11 +106,11 @@ * could be added to the heap. */ -#undef LPC17_BANK0_HEAPBASE -#undef LPC17_BANK0_HEAPSIZE -#if CONFIG_LPC17_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128) -# define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_LPC17_EMACRAM_SIZE) -# define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_LPC17_EMACRAM_SIZE) +#undef LPC17_40_BANK0_HEAPBASE +#undef LPC17_40_BANK0_HEAPSIZE +#if CONFIG_LPC17_40_EMACRAM_SIZE < (LPC17_40_BANK0_SIZE-128) +# define LPC17_40_BANK0_HEAPBASE (LPC17_40_SRAM_BANK0 + CONFIG_LPC17_40_EMACRAM_SIZE) +# define LPC17_40_BANK0_HEAPSIZE (LPC17_40_BANK0_SIZE - CONFIG_LPC17_40_EMACRAM_SIZE) #endif /* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx @@ -118,15 +118,15 @@ * is controllable. */ -#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0 -#define LPC17_EMACRAM_SIZE CONFIG_LPC17_EMACRAM_SIZE +#define LPC17_40_EMACRAM_BASE LPC17_40_SRAM_BANK0 +#define LPC17_40_EMACRAM_SIZE CONFIG_LPC17_40_EMACRAM_SIZE /* Descriptor Memory Layout *********************************************************/ /* EMAC DMA RAM and descriptor definitions. The configured number of descriptors * will determine the organization and the size of the descriptor and status tables. * There is a complex interaction between the maximum packet size (CONFIG_NET_ETH_PKTSIZE) - * and the number of Rx and Tx descriptors that can be supported (CONFIG_LPC17_ETH_NRXDESC - * and CONFIG_LPC17_ETH_NTXDESC): Small buffers -> more packets. This is something that + * and the number of Rx and Tx descriptors that can be supported (CONFIG_LPC17_40_ETH_NRXDESC + * and CONFIG_LPC17_40_ETH_NTXDESC): Small buffers -> more packets. This is something that * needs to be tuned for you system. * * For a 16Kb SRAM region, here is the relationship: @@ -138,50 +138,50 @@ * 15,756 is not well aligned.). */ -#define LPC17_TXDESCTAB_SIZE (CONFIG_LPC17_ETH_NTXDESC*LPC17_TXDESC_SIZE) -#define LPC17_TXSTATTAB_SIZE (CONFIG_LPC17_ETH_NTXDESC*LPC17_TXSTAT_SIZE) -#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE) +#define LPC17_40_TXDESCTAB_SIZE (CONFIG_LPC17_40_ETH_NTXDESC*LPC17_40_TXDESC_SIZE) +#define LPC17_40_TXSTATTAB_SIZE (CONFIG_LPC17_40_ETH_NTXDESC*LPC17_40_TXSTAT_SIZE) +#define LPC17_40_TXTAB_SIZE (LPC17_40_TXDESCTAB_SIZE+LPC17_40_TXSTATTAB_SIZE) -#define LPC17_RXDESCTAB_SIZE (CONFIG_LPC17_ETH_NRXDESC*LPC17_RXDESC_SIZE) -#define LPC17_RXSTATTAB_SIZE (CONFIG_LPC17_ETH_NRXDESC*LPC17_RXSTAT_SIZE) -#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE) +#define LPC17_40_RXDESCTAB_SIZE (CONFIG_LPC17_40_ETH_NRXDESC*LPC17_40_RXDESC_SIZE) +#define LPC17_40_RXSTATTAB_SIZE (CONFIG_LPC17_40_ETH_NRXDESC*LPC17_40_RXSTAT_SIZE) +#define LPC17_40_RXTAB_SIZE (LPC17_40_RXDESCTAB_SIZE+LPC17_40_RXSTATTAB_SIZE) -#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE) +#define LPC17_40_DESCTAB_SIZE (LPC17_40_TXTAB_SIZE+LPC17_40_RXTAB_SIZE) /* Descriptor table memory organization. Descriptor tables are packed at * the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for * packet memory. */ -#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) -#define LPC17_TXDESC_BASE LPC17_DESC_BASE -#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE) -#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE) -#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE) +#define LPC17_40_DESC_BASE (LPC17_40_EMACRAM_BASE+LPC17_40_EMACRAM_SIZE-LPC17_40_DESCTAB_SIZE) +#define LPC17_40_TXDESC_BASE LPC17_40_DESC_BASE +#define LPC17_40_TXSTAT_BASE (LPC17_40_TXDESC_BASE+LPC17_40_TXDESCTAB_SIZE) +#define LPC17_40_RXDESC_BASE (LPC17_40_TXSTAT_BASE+LPC17_40_TXSTATTAB_SIZE) +#define LPC17_40_RXSTAT_BASE (LPC17_40_RXDESC_BASE + LPC17_40_RXDESCTAB_SIZE) /* Now carve up the beginning of SRAM for packet memory. The size of a * packet buffer is related to the size of the MTU. We'll round sizes up * to multiples of 256 bytes. */ -#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE -#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) -#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE) +#define LPC17_40_PKTMEM_BASE LPC17_40_EMACRAM_BASE +#define LPC17_40_PKTMEM_SIZE (LPC17_40_EMACRAM_SIZE-LPC17_40_DESCTAB_SIZE) +#define LPC17_40_PKTMEM_END (LPC17_40_EMACRAM_BASE+LPC17_40_PKTMEM_SIZE) -#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE + 3) & ~3) -#define LPC17_NTXPKTS CONFIG_LPC17_ETH_NTXDESC -#define LPC17_NRXPKTS CONFIG_LPC17_ETH_NRXDESC +#define LPC17_40_MAXPACKET_SIZE ((CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE + 3) & ~3) +#define LPC17_40_NTXPKTS CONFIG_LPC17_40_ETH_NTXDESC +#define LPC17_40_NRXPKTS CONFIG_LPC17_40_ETH_NRXDESC -#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE) -#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE) -#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE) +#define LPC17_40_TXBUFFER_SIZE (LPC17_40_NTXPKTS * LPC17_40_MAXPACKET_SIZE) +#define LPC17_40_RXBUFFER_SIZE (LPC17_40_NRXPKTS * LPC17_40_MAXPACKET_SIZE) +#define LPC17_40_BUFFER_SIZE (LPC17_40_TXBUFFER_SIZE + LPC17_40_RXBUFFER_SIZE) -#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE -#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE -#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE) -#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE) +#define LPC17_40_BUFFER_BASE LPC17_40_PKTMEM_BASE +#define LPC17_40_TXBUFFER_BASE LPC17_40_BUFFER_BASE +#define LPC17_40_RXBUFFER_BASE (LPC17_40_TXBUFFER_BASE + LPC17_40_TXBUFFER_SIZE) +#define LPC17_40_BUFFER_END (LPC17_40_BUFFER_BASE + LPC17_40_BUFFER_SIZE) -#if LPC17_BUFFER_END > LPC17_PKTMEM_END +#if LPC17_40_BUFFER_END > LPC17_40_PKTMEM_END # error "Packet memory overlaps descriptor tables" #endif @@ -197,5 +197,5 @@ * Public Functions ************************************************************************************/ -#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */ +#endif /* CONFIG_NET && CONFIG_LPC17_40_ETHERNET && LPC17_40_NETHCONTROLLERS > 0*/ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_EMACRAM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_emc.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_emc.c similarity index 84% rename from arch/arm/src/lpc17xx/lpc17_emc.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_emc.c index ca24d060bd5..c12898c35ef 100644 --- a/arch/arm/src/lpc17xx/lpc17_emc.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_emc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17/lpc17_emc.c + * arch/arm/src/lpc17/lpc17_40_emc.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -45,9 +45,9 @@ #include "up_arch.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_emc.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_emc.h" /**************************************************************************** * Pre-processor Definitions @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -static const lpc17_pinset_t g_emcctrl[] = +static const lpc17_40_pinset_t g_emcctrl[] = { GPIO_EMC_OE, GPIO_EMC_WE, GPIO_EMC_BLS0, GPIO_EMC_BLS1, GPIO_EMC_BLS2, GPIO_EMC_BLS3, @@ -72,9 +72,9 @@ static const lpc17_pinset_t g_emcctrl[] = GPIO_EMC_CKE0, GPIO_EMC_CKE1, GPIO_EMC_CKE2, GPIO_EMC_CKE3, GPIO_EMC_DQM0, GPIO_EMC_DQM1, GPIO_EMC_DQM2, GPIO_EMC_DQM3, }; -#define EMC_NCTRL (sizeof(g_emcctrl) / sizeof(lpc17_pinset_t)) +#define EMC_NCTRL (sizeof(g_emcctrl) / sizeof(lpc17_40_pinset_t)) -static const lpc17_pinset_t g_emcdata[] = +static const lpc17_40_pinset_t g_emcdata[] = { GPIO_EMC_D0, GPIO_EMC_D1, GPIO_EMC_D2, GPIO_EMC_D3, GPIO_EMC_D4, GPIO_EMC_D5, GPIO_EMC_D6, GPIO_EMC_D7, @@ -93,10 +93,10 @@ static const lpc17_pinset_t g_emcdata[] = #ifdef BOARD_NDATA # define EMC_NDATA BOARD_NDATA #else -# define EMC_NDATA (sizeof(g_emcdata) / sizeof(lpc17_pinset_t)) +# define EMC_NDATA (sizeof(g_emcdata) / sizeof(lpc17_40_pinset_t)) #endif -static const lpc17_pinset_t g_emcaddr[] = +static const lpc17_40_pinset_t g_emcaddr[] = { GPIO_EMC_A0, GPIO_EMC_A1, GPIO_EMC_A2, GPIO_EMC_A3, GPIO_EMC_A4, GPIO_EMC_A5, GPIO_EMC_A6, GPIO_EMC_A7, @@ -114,7 +114,7 @@ static const lpc17_pinset_t g_emcaddr[] = #ifdef BOARD_NADDR # define EMC_NADDR BOARD_NADDR #else -# define EMC_NADDR (sizeof(g_emcaddr) / sizeof(lpc17_pinset_t)) +# define EMC_NADDR (sizeof(g_emcaddr) / sizeof(lpc17_40_pinset_t)) #endif /**************************************************************************** @@ -123,7 +123,7 @@ static const lpc17_pinset_t g_emcaddr[] = /***************************************************************************** * Name: - * lpc17_running_from_sdram + * lpc17_40_running_from_sdram * * Descriptions: * Check whether currently execution from SDRAM. @@ -133,13 +133,13 @@ static const lpc17_pinset_t g_emcaddr[] = * ****************************************************************************/ -static int lpc17_running_from_sdram(void) +static int lpc17_40_running_from_sdram(void) { - uint32_t extdram_bank_size = LPC17_EXTDRAM_CS3 - LPC17_EXTDRAM_CS2; - uint32_t extdram_end = LPC17_EXTDRAM_CS3 + extdram_bank_size; + uint32_t extdram_bank_size = LPC17_40_EXTDRAM_CS3 - LPC17_40_EXTDRAM_CS2; + uint32_t extdram_end = LPC17_40_EXTDRAM_CS3 + extdram_bank_size; - if (((uint32_t)lpc17_running_from_sdram >= LPC17_EXTDRAM_CS0) && - ((uint32_t)lpc17_running_from_sdram < extdram_end)) + if (((uint32_t)lpc17_40_running_from_sdram >= LPC17_40_EXTDRAM_CS0) && + ((uint32_t)lpc17_40_running_from_sdram < extdram_end)) { return 1; } @@ -154,7 +154,7 @@ static int lpc17_running_from_sdram(void) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_emcinitialize + * Name: lpc17_40_emcinitialize * * Description: * Initialize EMC clocking and pin configuration. This function should be @@ -163,16 +163,16 @@ static int lpc17_running_from_sdram(void) * ****************************************************************************/ -void lpc17_emcinitialize(void) +void lpc17_40_emcinitialize(void) { uint32_t regval; int i; /* Enable clocking for the EMC */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCEMC; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Set EMC delay values: * @@ -189,7 +189,7 @@ void lpc17_emcinitialize(void) * (CLKOUT1DLY+1) * 250 picoseconds. */ - if (lpc17_running_from_sdram()) + if (lpc17_40_running_from_sdram()) { return; } @@ -198,32 +198,32 @@ void lpc17_emcinitialize(void) SYSCON_EMCDLYCTL_FBCLKDLY(BOARD_FBCLKDLY) | SYSCON_EMCDLYCTL_CLKOUT0DLY(BOARD_CLKOUT0DLY) | SYSCON_EMCDLYCTL_CLKOUT1DLY(BOARD_CLKOUT1DLY); - putreg32(regval, LPC17_SYSCON_EMCDLYCTL); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); /* Enable the EMC */ - putreg32(EMC_CONTROL_E, LPC17_EMC_CONTROL); - putreg32(0, LPC17_EMC_CONFIG); + putreg32(EMC_CONTROL_E, LPC17_40_EMC_CONTROL); + putreg32(0, LPC17_40_EMC_CONFIG); /* Configure EMC pins */ /* Control signals */ for (i = 0; i < EMC_NCTRL; i++) { - lpc17_configgpio(g_emcctrl[i]); + lpc17_40_configgpio(g_emcctrl[i]); } /* Data lines */ for (i = 0; i < EMC_NDATA; i++) { - lpc17_configgpio(g_emcdata[i]); + lpc17_40_configgpio(g_emcdata[i]); } /* Address lines */ for (i = 0; i < EMC_NADDR; i++) { - lpc17_configgpio(g_emcaddr[i]); + lpc17_40_configgpio(g_emcaddr[i]); } } diff --git a/arch/arm/src/lpc17xx/lpc17_emc.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_emc.h similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_emc.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_emc.h index 4b020762fe1..454faf40bb4 100644 --- a/arch/arm/src/lpc17xx/lpc17_emc.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_emc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_emc.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_emc.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_EMC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_EMC_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "hardware/lpc17_emc.h" +#include "hardware/lpc17_40_emc.h" /**************************************************************************** * Pre-processor Definitions @@ -60,7 +60,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_emcinitialize + * Name: lpc17_40_emcinitialize * * Description: * Initialize EMC clocking and pin configuration. This function should be @@ -69,6 +69,6 @@ * ****************************************************************************/ -void lpc17_emcinitialize(void); +void lpc17_40_emcinitialize(void); -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_EMC_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c similarity index 73% rename from arch/arm/src/lpc17xx/lpc17_ethernet.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c index de08bb75cd8..239960f9615 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_ethernet.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c * * Copyright (C) 2010-2015, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -38,7 +38,7 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) +#if defined(CONFIG_NET) && defined(CONFIG_LPC17_40_ETHERNET) #include #include @@ -65,17 +65,17 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_ethernet.h" -#include "lpc17_emacram.h" -#include "lpc17_clrpend.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ethernet.h" +#include "lpc17_40_emacram.h" +#include "lpc17_40_clrpend.h" #include /* Does this chip have an Ethernet controller? */ -#if LPC17_NETHCONTROLLERS > 0 +#if LPC17_40_NETHCONTROLLERS > 0 /**************************************************************************** * Pre-processor Definitions @@ -100,31 +100,31 @@ #define ETHWORK LPWORK -/* CONFIG_LPC17_NINTERFACES determines the number of physical interfaces +/* CONFIG_LPC17_40_NINTERFACES determines the number of physical interfaces * that will be supported -- unless it is more than actually supported by the * hardware! */ -#if !defined(CONFIG_LPC17_NINTERFACES) || CONFIG_LPC17_NINTERFACES > LPC17_NETHCONTROLLERS -# undef CONFIG_LPC17_NINTERFACES -# define CONFIG_LPC17_NINTERFACES LPC17_NETHCONTROLLERS +#if !defined(CONFIG_LPC17_40_NINTERFACES) || CONFIG_LPC17_40_NINTERFACES > LPC17_40_NETHCONTROLLERS +# undef CONFIG_LPC17_40_NINTERFACES +# define CONFIG_LPC17_40_NINTERFACES LPC17_40_NETHCONTROLLERS #endif /* The logic here has a few hooks for support for multiple interfaces, but * that capability is not yet in place (and I won't worry about it until I get - * the first multi-interface LPC17xx). + * the first multi-interface LPC17xx/LPC40xx). */ -#if CONFIG_LPC17_NINTERFACES > 1 +#if CONFIG_LPC17_40_NINTERFACES > 1 # warning "Only a single ethernet controller is supported" -# undef CONFIG_LPC17_NINTERFACES -# define CONFIG_LPC17_NINTERFACES 1 +# undef CONFIG_LPC17_40_NINTERFACES +# define CONFIG_LPC17_40_NINTERFACES 1 #endif /* If IGMP is enabled, then accept multi-cast frames. */ -#if defined(CONFIG_NET_MCASTGROUP) && !defined(CONFIG_LPC17_MULTICAST) -# define CONFIG_LPC17_MULTICAST 1 +#if defined(CONFIG_NET_MCASTGROUP) && !defined(CONFIG_LPC17_40_MULTICAST) +# define CONFIG_LPC17_40_MULTICAST 1 #endif #define PKTBUF_SIZE (MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE) @@ -133,7 +133,7 @@ /* Register debug -- can only happen of CONFIG_DEBUG_NET_INFO is selected */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_LPC17_NET_REGDEBUG +# undef CONFIG_LPC17_40_NET_REGDEBUG #endif /* CONFIG_NET_DUMPPACKET will dump the contents of each packet to the @@ -145,20 +145,20 @@ #endif #ifdef CONFIG_NET_DUMPPACKET -# define lpc17_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) +# define lpc17_40_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) #else -# define lpc17_dumppacket(m,a,n) +# define lpc17_40_dumppacket(m,a,n) #endif /* Timing *******************************************************************/ /* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ -#define LPC17_WDDELAY (1*CLK_TCK) +#define LPC17_40_WDDELAY (1*CLK_TCK) /* TX timeout = 1 minute */ -#define LPC17_TXTIMEOUT (60*CLK_TCK) +#define LPC17_40_TXTIMEOUT (60*CLK_TCK) /* Interrupts ***************************************************************/ @@ -181,63 +181,63 @@ /* Select PHY-specific values. Add more PHYs as needed. */ #if defined(CONFIG_ETH0_PHY_KS8721) -# define LPC17_PHYNAME "KS8721" -# define LPC17_PHYID1 MII_PHYID1_KS8721 -# define LPC17_PHYID2 MII_PHYID2_KS8721 -# define LPC17_HAVE_PHY 1 +# define LPC17_40_PHYNAME "KS8721" +# define LPC17_40_PHYID1 MII_PHYID1_KS8721 +# define LPC17_40_PHYID2 MII_PHYID2_KS8721 +# define LPC17_40_HAVE_PHY 1 #elif defined(CONFIG_ETH0_PHY_KSZ8041) -# define LPC17_PHYNAME "KSZ8041" -# define LPC17_PHYID1 MII_PHYID1_KSZ8041 -# define LPC17_PHYID2 MII_PHYID2_KSZ8041 -# define LPC17_HAVE_PHY 1 +# define LPC17_40_PHYNAME "KSZ8041" +# define LPC17_40_PHYID1 MII_PHYID1_KSZ8041 +# define LPC17_40_PHYID2 MII_PHYID2_KSZ8041 +# define LPC17_40_HAVE_PHY 1 #elif defined(CONFIG_ETH0_PHY_DP83848C) -# define LPC17_PHYNAME "DP83848C" -# define LPC17_PHYID1 MII_PHYID1_DP83848C -# define LPC17_PHYID2 MII_PHYID2_DP83848C -# define LPC17_HAVE_PHY 1 +# define LPC17_40_PHYNAME "DP83848C" +# define LPC17_40_PHYID1 MII_PHYID1_DP83848C +# define LPC17_40_PHYID2 MII_PHYID2_DP83848C +# define LPC17_40_HAVE_PHY 1 #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define LPC17_PHYNAME "LAN8720" -# define LPC17_PHYID1 MII_PHYID1_LAN8720 -# define LPC17_PHYID2 MII_PHYID2_LAN8720 -# define LPC17_HAVE_PHY 1 +# define LPC17_40_PHYNAME "LAN8720" +# define LPC17_40_PHYID1 MII_PHYID1_LAN8720 +# define LPC17_40_PHYID2 MII_PHYID2_LAN8720 +# define LPC17_40_HAVE_PHY 1 #elif defined(CONFIG_ETH0_PHY_KSZ8081) -# define LPC17_PHYNAME "KSZ8081" -# define LPC17_PHYID1 MII_PHYID1_KSZ8081 -# define LPC17_PHYID2 MII_PHYID2_KSZ8081 -# define LPC17_HAVE_PHY 1 +# define LPC17_40_PHYNAME "KSZ8081" +# define LPC17_40_PHYID1 MII_PHYID1_KSZ8081 +# define LPC17_40_PHYID2 MII_PHYID2_KSZ8081 +# define LPC17_40_HAVE_PHY 1 #else # warning "No PHY specified!" -# undef LPC17_HAVE_PHY +# undef LPC17_40_HAVE_PHY #endif #define MII_BIG_TIMEOUT 666666 /* These definitions are used to remember the speed/duplex settings */ -#define LPC17_SPEED_MASK 0x01 -#define LPC17_SPEED_100 0x01 -#define LPC17_SPEED_10 0x00 +#define LPC17_40_SPEED_MASK 0x01 +#define LPC17_40_SPEED_100 0x01 +#define LPC17_40_SPEED_10 0x00 -#define LPC17_DUPLEX_MASK 0x02 -#define LPC17_DUPLEX_FULL 0x02 -#define LPC17_DUPLEX_HALF 0x00 +#define LPC17_40_DUPLEX_MASK 0x02 +#define LPC17_40_DUPLEX_FULL 0x02 +#define LPC17_40_DUPLEX_HALF 0x00 -#define LPC17_10BASET_HD (LPC17_SPEED_10 | LPC17_DUPLEX_HALF) -#define LPC17_10BASET_FD (LPC17_SPEED_10 | LPC17_DUPLEX_FULL) -#define LPC17_100BASET_HD (LPC17_SPEED_100 | LPC17_DUPLEX_HALF) -#define LPC17_100BASET_FD (LPC17_SPEED_100 | LPC17_DUPLEX_FULL) +#define LPC17_40_10BASET_HD (LPC17_40_SPEED_10 | LPC17_40_DUPLEX_HALF) +#define LPC17_40_10BASET_FD (LPC17_40_SPEED_10 | LPC17_40_DUPLEX_FULL) +#define LPC17_40_100BASET_HD (LPC17_40_SPEED_100 | LPC17_40_DUPLEX_HALF) +#define LPC17_40_100BASET_FD (LPC17_40_SPEED_100 | LPC17_40_DUPLEX_FULL) -#ifdef CONFIG_LPC17_PHY_SPEED100 -# ifdef CONFIG_LPC17_PHY_FDUPLEX -# define LPC17_MODE_DEFLT LPC17_100BASET_FD +#ifdef CONFIG_LPC17_40_PHY_SPEED100 +# ifdef CONFIG_LPC17_40_PHY_FDUPLEX +# define LPC17_40_MODE_DEFLT LPC17_40_100BASET_FD # else -# define LPC17_MODE_DEFLT LPC17_100BASET_HD +# define LPC17_40_MODE_DEFLT LPC17_40_100BASET_HD # endif #else -# ifdef CONFIG_LPC17_PHY_FDUPLEX -# define LPC17_MODE_DEFLT LPC17_10BASET_FD +# ifdef CONFIG_LPC17_40_PHY_FDUPLEX +# define LPC17_40_MODE_DEFLT LPC17_40_10BASET_FD # else -# define LPC17_MODE_DEFLT LPC17_10BASET_HD +# define LPC17_40_MODE_DEFLT LPC17_40_10BASET_HD # endif #endif @@ -279,17 +279,17 @@ * Private Types ****************************************************************************/ -/* The lpc17_driver_s encapsulates all state information for a single hardware +/* The lpc17_40_driver_s encapsulates all state information for a single hardware * interface */ -struct lpc17_driver_s +struct lpc17_40_driver_s { /* The following fields would only be necessary on chips that support * multiple Ethernet controllers. */ -#if CONFIG_LPC17_NINTERFACES > 1 +#if CONFIG_LPC17_40_NINTERFACES > 1 uint32_t lp_base; /* Ethernet controller base address */ int lp_irq; /* Ethernet controller IRQ */ #endif @@ -297,7 +297,7 @@ struct lpc17_driver_s bool lp_ifup; /* true:ifup false:ifdown */ bool lp_mode; /* speed/duplex */ bool lp_txpending; /* There is a pending Tx in lp_dev */ -#ifdef LPC17_HAVE_PHY +#ifdef LPC17_40_HAVE_PHY uint8_t lp_phyaddr; /* PHY device address */ #endif uint32_t lp_inten; /* Shadow copy of INTEN register */ @@ -320,11 +320,11 @@ struct lpc17_driver_s /* A single packet buffer per interface is used */ -static uint8_t g_pktbuf[PKTBUF_SIZE * CONFIG_LPC17_NINTERFACES]; +static uint8_t g_pktbuf[PKTBUF_SIZE * CONFIG_LPC17_40_NINTERFACES]; /* Array of ethernet driver status structures */ -static struct lpc17_driver_s g_ethdrvr[CONFIG_LPC17_NINTERFACES]; +static struct lpc17_40_driver_s g_ethdrvr[CONFIG_LPC17_40_NINTERFACES]; /* ENET pins are on P1[0,1,4,6,8,9,10,14,15] + MDC on P1[16] or P2[8] and * MDIO on P1[17] or P2[9]. The board.h file will define GPIO_ENET_MDC and @@ -345,131 +345,131 @@ static const uint16_t g_enetpins[GPIO_NENET_PINS] = /* Register operations */ -#ifdef CONFIG_LPC17_NET_REGDEBUG -static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t lpc17_getreg(uint32_t addr); -static void lpc17_putreg(uint32_t val, uint32_t addr); +#ifdef CONFIG_LPC17_40_NET_REGDEBUG +static void lpc17_40_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t lpc17_40_getreg(uint32_t addr); +static void lpc17_40_putreg(uint32_t val, uint32_t addr); #else -# define lpc17_getreg(addr) getreg32(addr) -# define lpc17_putreg(val,addr) putreg32(val,addr) +# define lpc17_40_getreg(addr) getreg32(addr) +# define lpc17_40_putreg(val,addr) putreg32(val,addr) #endif /* Common TX logic */ -static int lpc17_txdesc(struct lpc17_driver_s *priv); -static int lpc17_transmit(struct lpc17_driver_s *priv); -static int lpc17_txpoll(struct net_driver_s *dev); +static int lpc17_40_txdesc(struct lpc17_40_driver_s *priv); +static int lpc17_40_transmit(struct lpc17_40_driver_s *priv); +static int lpc17_40_txpoll(struct net_driver_s *dev); /* Interrupt handling */ -static void lpc17_response(struct lpc17_driver_s *priv); +static void lpc17_40_response(struct lpc17_40_driver_s *priv); -static void lpc17_txdone_work(FAR void *arg); -static void lpc17_rxdone_work(FAR void *arg); -static int lpc17_interrupt(int irq, void *context, FAR void *arg); +static void lpc17_40_txdone_work(FAR void *arg); +static void lpc17_40_rxdone_work(FAR void *arg); +static int lpc17_40_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ -static void lpc17_txtimeout_work(FAR void *arg); -static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...); +static void lpc17_40_txtimeout_work(FAR void *arg); +static void lpc17_40_txtimeout_expiry(int argc, uint32_t arg, ...); -static void lpc17_poll_work(FAR void *arg); -static void lpc17_poll_expiry(int argc, uint32_t arg, ...); +static void lpc17_40_poll_work(FAR void *arg); +static void lpc17_40_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ #ifdef CONFIG_NET_ICMPv6 -static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv); +static void lpc17_40_ipv6multicast(FAR struct lpc17_40_driver_s *priv); #endif -static int lpc17_ifup(struct net_driver_s *dev); -static int lpc17_ifdown(struct net_driver_s *dev); +static int lpc17_40_ifup(struct net_driver_s *dev); +static int lpc17_40_ifdown(struct net_driver_s *dev); -static void lpc17_txavail_work(FAR void *arg); -static int lpc17_txavail(struct net_driver_s *dev); +static void lpc17_40_txavail_work(FAR void *arg); +static int lpc17_40_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -static uint32_t lpc17_calcethcrc(const uint8_t *data, size_t length); -static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac); +static uint32_t lpc17_40_calcethcrc(const uint8_t *data, size_t length); +static int lpc17_40_addmac(struct net_driver_s *dev, const uint8_t *mac); #endif #ifdef CONFIG_NET_MCASTGROUP -static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac); +static int lpc17_40_rmmac(struct net_driver_s *dev, const uint8_t *mac); #endif #ifdef CONFIG_NETDEV_IOCTL -static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, +static int lpc17_40_eth_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg); #endif /* Initialization functions */ -#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) -static void lpc17_showpins(void); +#if defined(CONFIG_LPC17_40_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) +static void lpc17_40_showpins(void); #else -# define lpc17_showpins() +# define lpc17_40_showpins() #endif /* PHY initialization functions */ -#ifdef LPC17_HAVE_PHY -# ifdef CONFIG_LPC17_NET_REGDEBUG -static void lpc17_showmii(uint8_t phyaddr, const char *msg); +#ifdef LPC17_40_HAVE_PHY +# ifdef CONFIG_LPC17_40_NET_REGDEBUG +static void lpc17_40_showmii(uint8_t phyaddr, const char *msg); # else -# define lpc17_showmii(phyaddr,msg) +# define lpc17_40_showmii(phyaddr,msg) # endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) -static int lpc17_phyintenable(FAR struct lpc17_driver_s *priv); +static int lpc17_40_phyintenable(FAR struct lpc17_40_driver_s *priv); #endif -static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, +static void lpc17_40_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata); -static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr); -static inline int lpc17_phyreset(uint8_t phyaddr); -# ifdef CONFIG_LPC17_PHY_AUTONEG -static inline int lpc17_phyautoneg(uint8_t phyaddr); +static uint16_t lpc17_40_phyread(uint8_t phyaddr, uint8_t regaddr); +static inline int lpc17_40_phyreset(uint8_t phyaddr); +# ifdef CONFIG_LPC17_40_PHY_AUTONEG +static inline int lpc17_40_phyautoneg(uint8_t phyaddr); # endif -static int lpc17_phymode(uint8_t phyaddr, uint8_t mode); -static inline int lpc17_phyinit(struct lpc17_driver_s *priv); +static int lpc17_40_phymode(uint8_t phyaddr, uint8_t mode); +static inline int lpc17_40_phyinit(struct lpc17_40_driver_s *priv); #else -# define lpc17_phyinit(priv) +# define lpc17_40_phyinit(priv) #endif /* EMAC Initialization functions */ -static inline void lpc17_txdescinit(struct lpc17_driver_s *priv); -static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv); -static void lpc17_macmode(uint8_t mode); -static void lpc17_ethreset(struct lpc17_driver_s *priv); +static inline void lpc17_40_txdescinit(struct lpc17_40_driver_s *priv); +static inline void lpc17_40_rxdescinit(struct lpc17_40_driver_s *priv); +static void lpc17_40_macmode(uint8_t mode); +static void lpc17_40_ethreset(struct lpc17_40_driver_s *priv); /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: lpc17_printreg + * Name: lpc17_40_printreg * * Description: - * Print the contents of an LPC17xx register operation + * Print the contents of an LPC17xx/LPC40xx register operation * ****************************************************************************/ -#ifdef CONFIG_LPC17_NET_REGDEBUG -static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_LPC17_40_NET_REGDEBUG +static void lpc17_40_printreg(uint32_t addr, uint32_t val, bool iswrite) { ninfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif /**************************************************************************** - * Name: lpc17_checkreg + * Name: lpc17_40_checkreg * * Description: - * Get the contents of an LPC17xx register + * Get the contents of an LPC17xx/LPC40xx register * ****************************************************************************/ -#ifdef CONFIG_LPC17_NET_REGDEBUG -static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_LPC17_40_NET_REGDEBUG +static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -500,7 +500,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* Yes.. Just one */ - lpc17_printreg(prevaddr, preval, prevwrite); + lpc17_40_printreg(prevaddr, preval, prevwrite); } else { @@ -519,21 +519,21 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) /* Show the new regisgter access */ - lpc17_printreg(addr, val, iswrite); + lpc17_40_printreg(addr, val, iswrite); } } #endif /**************************************************************************** - * Name: lpc17_getreg + * Name: lpc17_40_getreg * * Description: - * Get the contents of an LPC17xx register + * Get the contents of an LPC17xx/LPC40xx register * ****************************************************************************/ -#ifdef CONFIG_LPC17_NET_REGDEBUG -static uint32_t lpc17_getreg(uint32_t addr) +#ifdef CONFIG_LPC17_40_NET_REGDEBUG +static uint32_t lpc17_40_getreg(uint32_t addr) { /* Read the value from the register */ @@ -541,25 +541,25 @@ static uint32_t lpc17_getreg(uint32_t addr) /* Check if we need to print this value */ - lpc17_checkreg(addr, val, false); + lpc17_40_checkreg(addr, val, false); return val; } #endif /**************************************************************************** - * Name: lpc17_putreg + * Name: lpc17_40_putreg * * Description: - * Set the contents of an LPC17xx register to a value + * Set the contents of an LPC17xx/LPC40xx register to a value * ****************************************************************************/ -#ifdef CONFIG_LPC17_NET_REGDEBUG -static void lpc17_putreg(uint32_t val, uint32_t addr) +#ifdef CONFIG_LPC17_40_NET_REGDEBUG +static void lpc17_40_putreg(uint32_t val, uint32_t addr) { /* Check if we need to print this value */ - lpc17_checkreg(addr, val, true); + lpc17_40_checkreg(addr, val, true); /* Write the value */ @@ -568,7 +568,7 @@ static void lpc17_putreg(uint32_t val, uint32_t addr) #endif /**************************************************************************** - * Function: lpc17_txdesc + * Function: lpc17_40_txdesc * * Description: * Check if a free TX descriptor is available. @@ -586,15 +586,15 @@ static void lpc17_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static int lpc17_txdesc(struct lpc17_driver_s *priv) +static int lpc17_40_txdesc(struct lpc17_40_driver_s *priv) { unsigned int prodidx; unsigned int considx; /* Get the next producer index */ - prodidx = lpc17_getreg(LPC17_ETH_TXPRODIDX) & ETH_TXPRODIDX_MASK; - if (++prodidx >= CONFIG_LPC17_ETH_NTXDESC) + prodidx = lpc17_40_getreg(LPC17_40_ETH_TXPRODIDX) & ETH_TXPRODIDX_MASK; + if (++prodidx >= CONFIG_LPC17_40_ETH_NTXDESC) { /* Wrap back to index zero */ @@ -605,12 +605,12 @@ static int lpc17_txdesc(struct lpc17_driver_s *priv) * are no available Tx descriptors. */ - considx = lpc17_getreg(LPC17_ETH_TXCONSIDX) & ETH_TXCONSIDX_MASK; + considx = lpc17_40_getreg(LPC17_40_ETH_TXCONSIDX) & ETH_TXCONSIDX_MASK; return prodidx != considx ? OK : -EAGAIN; } /**************************************************************************** - * Function: lpc17_transmit + * Function: lpc17_40_transmit * * Description: * Start hardware transmission. Called either from the txdone interrupt @@ -629,7 +629,7 @@ static int lpc17_txdesc(struct lpc17_driver_s *priv) * ****************************************************************************/ -static int lpc17_transmit(struct lpc17_driver_s *priv) +static int lpc17_40_transmit(struct lpc17_40_driver_s *priv) { uint32_t *txdesc; void *txbuffer; @@ -640,23 +640,23 @@ static int lpc17_transmit(struct lpc17_driver_s *priv) * must have assured that there is no transmission in progress. */ - DEBUGASSERT(lpc17_txdesc(priv) == OK); + DEBUGASSERT(lpc17_40_txdesc(priv) == OK); /* Increment statistics and dump the packet *if so configured) */ NETDEV_TXPACKETS(&priv->lp_dev); - lpc17_dumppacket("Transmit packet", + lpc17_40_dumppacket("Transmit packet", priv->lp_dev.d_buf, priv->lp_dev.d_len); /* Get the current producer index */ - prodidx = lpc17_getreg(LPC17_ETH_TXPRODIDX) & ETH_TXPRODIDX_MASK; + prodidx = lpc17_40_getreg(LPC17_40_ETH_TXPRODIDX) & ETH_TXPRODIDX_MASK; /* Get the packet address from the descriptor and set the descriptor control * fields. */ - txdesc = (uint32_t *)(LPC17_TXDESC_BASE + (prodidx << 3)); + txdesc = (uint32_t *)(LPC17_40_TXDESC_BASE + (prodidx << 3)); txbuffer = (void *)*txdesc++; *txdesc = TXDESC_CONTROL_INT | TXDESC_CONTROL_LAST | TXDESC_CONTROL_CRC | (priv->lp_dev.d_len - 1); @@ -672,34 +672,34 @@ static int lpc17_transmit(struct lpc17_driver_s *priv) * DMA memory. This could eliminate the following, costly memcpy. */ - DEBUGASSERT(priv->lp_dev.d_len <= LPC17_MAXPACKET_SIZE); + DEBUGASSERT(priv->lp_dev.d_len <= LPC17_40_MAXPACKET_SIZE); memcpy(txbuffer, priv->lp_dev.d_buf, priv->lp_dev.d_len); /* Bump the producer index, making the packet available for transmission. */ - if (++prodidx >= CONFIG_LPC17_ETH_NTXDESC) + if (++prodidx >= CONFIG_LPC17_40_ETH_NTXDESC) { /* Wrap back to index zero */ prodidx = 0; } - lpc17_putreg(prodidx, LPC17_ETH_TXPRODIDX); + lpc17_40_putreg(prodidx, LPC17_40_ETH_TXPRODIDX); /* Enable Tx interrupts */ priv->lp_inten |= ETH_TXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->lp_txtimeout, LPC17_TXTIMEOUT, lpc17_txtimeout_expiry, + (void)wd_start(priv->lp_txtimeout, LPC17_40_TXTIMEOUT, lpc17_40_txtimeout_expiry, 1, (uint32_t)priv); return OK; } /**************************************************************************** - * Function: lpc17_txpoll + * Function: lpc17_40_txpoll * * Description: * The transmitter is available, check if the network layer has any @@ -723,9 +723,9 @@ static int lpc17_transmit(struct lpc17_driver_s *priv) * ****************************************************************************/ -static int lpc17_txpoll(struct net_driver_s *dev) +static int lpc17_40_txpoll(struct net_driver_s *dev) { - struct lpc17_driver_s *priv = (struct lpc17_driver_s *)dev->d_private; + struct lpc17_40_driver_s *priv = (struct lpc17_40_driver_s *)dev->d_private; int ret = OK; /* If the polling resulted in data that should be sent out on the network, @@ -762,13 +762,13 @@ static int lpc17_txpoll(struct net_driver_s *dev) * at least one more packet in the descriptor list. */ - lpc17_transmit(priv); + lpc17_40_transmit(priv); /* Check if there is room in the device to hold another packet. If not, * return any non-zero value to terminate the poll. */ - ret = lpc17_txdesc(priv); + ret = lpc17_40_txdesc(priv); } } @@ -780,7 +780,7 @@ static int lpc17_txpoll(struct net_driver_s *dev) } /**************************************************************************** - * Function: lpc17_response + * Function: lpc17_40_response * * Description: * While processing an RxDone event, higher logic decides to send a packet, @@ -803,18 +803,18 @@ static int lpc17_txpoll(struct net_driver_s *dev) * ****************************************************************************/ -static void lpc17_response(struct lpc17_driver_s *priv) +static void lpc17_40_response(struct lpc17_40_driver_s *priv) { int ret; /* Check if there is room in the device to hold another packet. */ - ret = lpc17_txdesc(priv); + ret = lpc17_40_txdesc(priv); if (ret == OK) { /* Yes.. queue the packet now. */ - lpc17_transmit(priv); + lpc17_40_transmit(priv); } else { @@ -826,12 +826,12 @@ static void lpc17_response(struct lpc17_driver_s *priv) priv->lp_txpending = true; priv->lp_inten &= ~ETH_RXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); } } /**************************************************************************** - * Function: lpc17_rxdone_work + * Function: lpc17_40_rxdone_work * * Description: * Perform Rx interrupt handling logic outside of the interrupt handler (on @@ -847,9 +847,9 @@ static void lpc17_response(struct lpc17_driver_s *priv) * ****************************************************************************/ -static void lpc17_rxdone_work(FAR void *arg) +static void lpc17_40_rxdone_work(FAR void *arg) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)arg; irqstate_t flags; uint32_t *rxstat; bool fragment; @@ -867,8 +867,8 @@ static void lpc17_rxdone_work(FAR void *arg) /* Get the current producer and consumer indices */ - considx = lpc17_getreg(LPC17_ETH_RXCONSIDX) & ETH_RXCONSIDX_MASK; - prodidx = lpc17_getreg(LPC17_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; + considx = lpc17_40_getreg(LPC17_40_ETH_RXCONSIDX) & ETH_RXCONSIDX_MASK; + prodidx = lpc17_40_getreg(LPC17_40_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; /* Loop while there are incoming packets to be processed, that is, while * the producer index is not equal to the consumer index. @@ -883,7 +883,7 @@ static void lpc17_rxdone_work(FAR void *arg) /* Get the Rx status and packet length (-4+1) */ - rxstat = (uint32_t *)(LPC17_RXSTAT_BASE + (considx << 3)); + rxstat = (uint32_t *)(LPC17_40_RXSTAT_BASE + (considx << 3)); pktlen = (*rxstat & RXSTAT_INFO_RXSIZE_MASK) - 3; /* Check for errors. NOTE: The DMA engine reports bogus length errors, @@ -930,7 +930,7 @@ static void lpc17_rxdone_work(FAR void *arg) /* Get the Rx buffer address from the Rx descriptor */ - rxdesc = (uint32_t *)(LPC17_RXDESC_BASE + (considx << 3)); + rxdesc = (uint32_t *)(LPC17_40_RXDESC_BASE + (considx << 3)); rxbuffer = (void *)*rxdesc; /* Copy the data data from the EMAC DMA RAM to priv->lp_dev.d_buf. @@ -945,7 +945,7 @@ static void lpc17_rxdone_work(FAR void *arg) memcpy(priv->lp_dev.d_buf, rxbuffer, pktlen); priv->lp_dev.d_len = pktlen; - lpc17_dumppacket("Received packet", + lpc17_40_dumppacket("Received packet", priv->lp_dev.d_buf, priv->lp_dev.d_len); #ifdef CONFIG_NET_PKT @@ -995,7 +995,7 @@ static void lpc17_rxdone_work(FAR void *arg) /* And send the packet */ - lpc17_response(priv); + lpc17_40_response(priv); } } else @@ -1034,7 +1034,7 @@ static void lpc17_rxdone_work(FAR void *arg) /* And send the packet */ - lpc17_response(priv); + lpc17_40_response(priv); } } else @@ -1052,7 +1052,7 @@ static void lpc17_rxdone_work(FAR void *arg) if (priv->lp_dev.d_len > 0) { - lpc17_response(priv); + lpc17_40_response(priv); } } else @@ -1068,15 +1068,15 @@ static void lpc17_rxdone_work(FAR void *arg) * might also have gotten bumped up by the hardware). */ - if (++considx >= CONFIG_LPC17_ETH_NRXDESC) + if (++considx >= CONFIG_LPC17_40_ETH_NRXDESC) { /* Wrap back to index zero */ considx = 0; } - lpc17_putreg(considx, LPC17_ETH_RXCONSIDX); - prodidx = lpc17_getreg(LPC17_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; + lpc17_40_putreg(considx, LPC17_40_ETH_RXCONSIDX); + prodidx = lpc17_40_getreg(LPC17_40_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; } net_unlock(); @@ -1089,7 +1089,7 @@ static void lpc17_rxdone_work(FAR void *arg) if (!priv->lp_txpending) { priv->lp_inten |= ETH_RXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); } leave_critical_section(flags); @@ -1097,7 +1097,7 @@ static void lpc17_rxdone_work(FAR void *arg) /**************************************************************************** - * Function: lpc17_txdone_work + * Function: lpc17_40_txdone_work * * Description: * Perform Tx interrupt handling logic outside of the interrupt handler (on @@ -1111,16 +1111,16 @@ static void lpc17_rxdone_work(FAR void *arg) * ****************************************************************************/ -static void lpc17_txdone_work(FAR void *arg) +static void lpc17_40_txdone_work(FAR void *arg) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)arg; /* Verify that the hardware is ready to send another packet. Since a Tx * just completed, this must be the case. */ DEBUGASSERT(priv); - DEBUGASSERT(lpc17_txdesc(priv) == OK); + DEBUGASSERT(lpc17_40_txdesc(priv) == OK); /* Check if there is a pending Tx transfer that was scheduled by Rx handling * while the Tx logic was busy. If so, processing that pending Tx now. @@ -1133,24 +1133,24 @@ static void lpc17_txdone_work(FAR void *arg) priv->lp_txpending = false; - lpc17_transmit(priv); + lpc17_40_transmit(priv); priv->lp_inten |= ETH_RXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); } /* Otherwise poll the network layer for new XMIT data */ else { - (void)devif_poll(&priv->lp_dev, lpc17_txpoll); + (void)devif_poll(&priv->lp_dev, lpc17_40_txpoll); } net_unlock(); } /**************************************************************************** - * Function: lpc17_interrupt + * Function: lpc17_40_interrupt * * Description: * Hardware interrupt handler @@ -1166,12 +1166,12 @@ static void lpc17_txdone_work(FAR void *arg) * ****************************************************************************/ -static int lpc17_interrupt(int irq, void *context, FAR void *arg) +static int lpc17_40_interrupt(int irq, void *context, FAR void *arg) { - register struct lpc17_driver_s *priv; + register struct lpc17_40_driver_s *priv; uint32_t status; -#if CONFIG_LPC17_NINTERFACES > 1 +#if CONFIG_LPC17_40_NINTERFACES > 1 # error "A mechanism to associate and interface with an IRQ is needed" #else priv = &g_ethdrvr[0]; @@ -1179,17 +1179,17 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Get the interrupt status (zero means no interrupts pending). */ - status = lpc17_getreg(LPC17_ETH_INTST); + status = lpc17_40_getreg(LPC17_40_ETH_INTST); if (status != 0) { /* Clear all pending interrupts */ - lpc17_putreg(status, LPC17_ETH_INTCLR); + lpc17_40_putreg(status, LPC17_40_ETH_INTCLR); /* Handle each pending interrupt **************************************/ /* Check for Wake-Up on Lan *******************************************/ -#ifdef CONFIG_LPC17_ETH_WOL +#ifdef CONFIG_LPC17_40_ETH_WOL if ((status & ETH_INT_WKUP) != 0) { # warning "Missing logic" @@ -1223,14 +1223,14 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* ifup() will reset the EMAC and bring it back up */ - (void)lpc17_ifup(&priv->lp_dev); + (void)lpc17_40_ifup(&priv->lp_dev); } else { /* Check for receive events ***************************************/ /* RX ERROR -- Triggered on receive errors: AlignmentError, * RangeError, LengthError, SymbolError, CRCError or NoDescriptor - * or Overrun. NOTE: (1) We will still need to call lpc17_rxdone_process + * or Overrun. NOTE: (1) We will still need to call lpc17_40_rxdone_process * on RX errors to bump the considx over the bad packet. (2) The * DMA engine reports bogus length errors, making this a pretty * useless (as well as annoying) check anyway. @@ -1262,20 +1262,20 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) */ priv->lp_inten &= ~ETH_RXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); /* Schedule RX-related work to be performed on the work thread, * perhaps cancelling any pending RX work. */ - work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, + work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_40_rxdone_work, priv, 0); } /* Check for Tx events ********************************************/ /* TX ERROR -- Triggered on transmit errors: LateCollision, * ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. - * NOTE: We will still need to call lpc17_txdone_process() in order to + * NOTE: We will still need to call lpc17_40_txdone_process() in order to * clean up after the failed transmit. */ @@ -1312,11 +1312,11 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Disable further Tx interrupts. Tx interrupts may be * re-enabled again depending upon the actions of - * lpc17_txdone_process() + * lpc17_40_txdone_process() */ priv->lp_inten &= ~ETH_TXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); /* Cancel any pending TX done work (to prevent overruns and also * to avoid race conditions with the TX timeout work) @@ -1328,7 +1328,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) * perhaps cancelling any pending TX work. */ - work_queue(ETHWORK, &priv->lp_txwork, (worker_t)lpc17_txdone_work, + work_queue(ETHWORK, &priv->lp_txwork, (worker_t)lpc17_40_txdone_work, priv, 0); } } @@ -1337,10 +1337,10 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Clear the pending interrupt */ #if 0 /* Apparently not necessary */ -# if CONFIG_LPC17_NINTERFACES > 1 - lpc17_clrpend(priv->irq); +# if CONFIG_LPC17_40_NINTERFACES > 1 + lpc17_40_clrpend(priv->irq); # else - lpc17_clrpend(LPC17_IRQ_ETH); + lpc17_40_clrpend(LPC17_40_IRQ_ETH); # endif #endif @@ -1348,7 +1348,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) } /**************************************************************************** - * Function: lpc17_txtimeout_work + * Function: lpc17_40_txtimeout_work * * Description: * Perform TX timeout related work from the worker thread @@ -1364,9 +1364,9 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) * ****************************************************************************/ -static void lpc17_txtimeout_work(FAR void *arg) +static void lpc17_40_txtimeout_work(FAR void *arg) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)arg; /* Increment statistics and dump debug info */ @@ -1378,18 +1378,18 @@ static void lpc17_txtimeout_work(FAR void *arg) * it back up. */ - (void)lpc17_ifup(&priv->lp_dev); + (void)lpc17_40_ifup(&priv->lp_dev); /* Then poll the network layer for new XMIT data */ - (void)devif_poll(&priv->lp_dev, lpc17_txpoll); + (void)devif_poll(&priv->lp_dev, lpc17_40_txpoll); } net_unlock(); } /**************************************************************************** - * Function: lpc17_txtimeout_expiry + * Function: lpc17_40_txtimeout_expiry * * Description: * Our TX watchdog timed out. Called from the timer interrupt handler. @@ -1407,16 +1407,16 @@ static void lpc17_txtimeout_work(FAR void *arg) * ****************************************************************************/ -static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...) +static void lpc17_40_txtimeout_expiry(int argc, uint32_t arg, ...) { - struct lpc17_driver_s *priv = (struct lpc17_driver_s *)arg; + struct lpc17_40_driver_s *priv = (struct lpc17_40_driver_s *)arg; /* Disable further Tx interrupts. Tx interrupts may be re-enabled again - * depending upon the actions of lpc17_poll_process() + * depending upon the actions of lpc17_40_poll_process() */ priv->lp_inten &= ~ETH_TXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + lpc17_40_putreg(priv->lp_inten, LPC17_40_ETH_INTEN); /* Is the single TX work structure available? If not, then there is * pending TX work to be done this must be a false alarm TX timeout. @@ -1426,12 +1426,12 @@ static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(ETHWORK, &priv->lp_txwork, lpc17_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->lp_txwork, lpc17_40_txtimeout_work, priv, 0); } } /**************************************************************************** - * Function: lpc17_poll_work + * Function: lpc17_40_poll_work * * Description: * Perform periodic polling from the worker thread @@ -1447,9 +1447,9 @@ static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...) * ****************************************************************************/ -static void lpc17_poll_work(FAR void *arg) +static void lpc17_40_poll_work(FAR void *arg) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)arg; unsigned int prodidx; unsigned int considx; @@ -1458,14 +1458,14 @@ static void lpc17_poll_work(FAR void *arg) */ net_lock(); - if (lpc17_txdesc(priv) == OK) + if (lpc17_40_txdesc(priv) == OK) { /* If so, update TCP timing states and poll the network layer for new * XMIT data. Hmmm.. might be bug here. Does this mean if there is a * transmit in progress, we will missing TCP time state updates? */ - (void)devif_timer(&priv->lp_dev, lpc17_txpoll); + (void)devif_timer(&priv->lp_dev, lpc17_40_txpoll); } /* Simulate a fake receive to relaunch the data exchanges when a receive @@ -1474,24 +1474,24 @@ static void lpc17_poll_work(FAR void *arg) /* Get the current producer and consumer indices */ - considx = lpc17_getreg(LPC17_ETH_RXCONSIDX) & ETH_RXCONSIDX_MASK; - prodidx = lpc17_getreg(LPC17_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; + considx = lpc17_40_getreg(LPC17_40_ETH_RXCONSIDX) & ETH_RXCONSIDX_MASK; + prodidx = lpc17_40_getreg(LPC17_40_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; if (considx != prodidx) { - work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, + work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_40_rxdone_work, priv, 0); } /* Setup the watchdog poll timer again */ - (void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_poll_expiry, + (void)wd_start(priv->lp_txpoll, LPC17_40_WDDELAY, lpc17_40_poll_expiry, 1, priv); net_unlock(); } /**************************************************************************** - * Function: lpc17_poll_expiry + * Function: lpc17_40_poll_expiry * * Description: * Periodic timer handler. Called from the timer interrupt handler. @@ -1508,19 +1508,19 @@ static void lpc17_poll_work(FAR void *arg) * ****************************************************************************/ -static void lpc17_poll_expiry(int argc, uint32_t arg, ...) +static void lpc17_40_poll_expiry(int argc, uint32_t arg, ...) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)arg; DEBUGASSERT(arg); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(ETHWORK, &priv->lp_pollwork, lpc17_poll_work, priv, 0); + work_queue(ETHWORK, &priv->lp_pollwork, lpc17_40_poll_work, priv, 0); } /**************************************************************************** - * Function: lpc17_ipv6multicast + * Function: lpc17_40_ipv6multicast * * Description: * Configure the IPv6 multicast MAC address. @@ -1536,7 +1536,7 @@ static void lpc17_poll_expiry(int argc, uint32_t arg, ...) ****************************************************************************/ #ifdef CONFIG_NET_ICMPv6 -static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv) +static void lpc17_40_ipv6multicast(FAR struct lpc17_40_driver_s *priv) { struct net_driver_s *dev; uint16_t tmp16; @@ -1569,7 +1569,7 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv) ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - (void)lpc17_addmac(dev, mac); + (void)lpc17_40_addmac(dev, mac); #ifdef CONFIG_NET_ICMPv6_AUTOCONF /* Add the IPv6 all link-local nodes Ethernet address. This is the @@ -1577,7 +1577,7 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv) * packets. */ - (void)lpc17_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet); + (void)lpc17_40_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet); #endif /* CONFIG_NET_ICMPv6_AUTOCONF */ #ifdef CONFIG_NET_ICMPv6_ROUTER @@ -1586,14 +1586,14 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv) * packets. */ - (void)lpc17_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet); + (void)lpc17_40_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet); #endif /* CONFIG_NET_ICMPv6_ROUTER */ } #endif /* CONFIG_NET_ICMPv6 */ /**************************************************************************** - * Function: lpc17_ifup + * Function: lpc17_40_ifup * * Description: * NuttX Callback: Bring up the Ethernet interface when an IP address is @@ -1609,9 +1609,9 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv) * ****************************************************************************/ -static int lpc17_ifup(struct net_driver_s *dev) +static int lpc17_40_ifup(struct net_driver_s *dev) { - struct lpc17_driver_s *priv = (struct lpc17_driver_s *)dev->d_private; + struct lpc17_40_driver_s *priv = (struct lpc17_40_driver_s *)dev->d_private; uint32_t regval; int ret; @@ -1621,14 +1621,14 @@ static int lpc17_ifup(struct net_driver_s *dev) /* Reset the Ethernet controller (again) */ - lpc17_ethreset(priv); + lpc17_40_ethreset(priv); /* Initialize the PHY and wait for the link to be established */ - ret = lpc17_phyinit(priv); + ret = lpc17_40_phyinit(priv); if (ret != 0) { - nerr("ERROR: lpc17_phyinit failed: %d\n", ret); + nerr("ERROR: lpc17_40_phyinit failed: %d\n", ret); return ret; } @@ -1636,36 +1636,36 @@ static int lpc17_ifup(struct net_driver_s *dev) regval = (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[5] << 8 | (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[4]; - lpc17_putreg(regval, LPC17_ETH_SA0); + lpc17_40_putreg(regval, LPC17_40_ETH_SA0); regval = (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[3] << 8 | (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[2]; - lpc17_putreg(regval, LPC17_ETH_SA1); + lpc17_40_putreg(regval, LPC17_40_ETH_SA1); regval = (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[1] << 8 | (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[0]; - lpc17_putreg(regval, LPC17_ETH_SA2); + lpc17_40_putreg(regval, LPC17_40_ETH_SA2); #ifdef CONFIG_NET_ICMPv6 /* Set up the IPv6 multicast address */ - lpc17_ipv6multicast(priv); + lpc17_40_ipv6multicast(priv); #endif /* Initialize Ethernet interface for the PHY setup */ - lpc17_macmode(priv->lp_mode); + lpc17_40_macmode(priv->lp_mode); /* Initialize EMAC DMA memory -- descriptors, status, packet buffers, etc. */ - lpc17_txdescinit(priv); - lpc17_rxdescinit(priv); + lpc17_40_txdescinit(priv); + lpc17_40_rxdescinit(priv); /* Configure to pass all received frames */ - regval = lpc17_getreg(LPC17_ETH_MAC1); + regval = lpc17_40_getreg(LPC17_40_ETH_MAC1); regval |= ETH_MAC1_PARF; - lpc17_putreg(regval, LPC17_ETH_MAC1); + lpc17_40_putreg(regval, LPC17_40_ETH_MAC1); /* Set up RX filter and configure to accept broadcast addresses, multicast * addresses, and perfect station address matches. We should also accept @@ -1676,33 +1676,33 @@ static int lpc17_ifup(struct net_driver_s *dev) */ regval = ETH_RXFLCTRL_PERFEN | ETH_RXFLCTRL_BCASTEN; -#ifdef CONFIG_LPC17_MULTICAST +#ifdef CONFIG_LPC17_40_MULTICAST regval |= (ETH_RXFLCTRL_MCASTEN | ETH_RXFLCTRL_UCASTEN); #endif -#ifdef CONFIG_LPC17_ETH_HASH +#ifdef CONFIG_LPC17_40_ETH_HASH regval |= (ETH_RXFLCTRL_MCASTHASHEN | ETH_RXFLCTRL_UCASTHASHEN); #endif - lpc17_putreg(regval, LPC17_ETH_RXFLCTRL); + lpc17_40_putreg(regval, LPC17_40_ETH_RXFLCTRL); /* Clear any pending interrupts (shouldn't be any) */ - lpc17_putreg(0xffffffff, LPC17_ETH_INTCLR); + lpc17_40_putreg(0xffffffff, LPC17_40_ETH_INTCLR); /* Enable Ethernet interrupts. The way we do this depends on whether or * not Wakeup on Lan (WoL) has been configured. */ -#ifdef CONFIG_LPC17_ETH_WOL +#ifdef CONFIG_LPC17_40_ETH_WOL /* Configure WoL: Clear all receive filter WoLs and enable the perfect * match WoL interrupt. We will wait until the Wake-up to finish * bringing things up. */ - lpc17_putreg(0xffffffff, LPC17_ETH_RXFLWOLCLR); - lpc17_putreg(ETH_RXFLCTRL_RXFILEN, LPC17_ETH_RXFLCTRL); + lpc17_40_putreg(0xffffffff, LPC17_40_ETH_RXFLWOLCLR); + lpc17_40_putreg(ETH_RXFLCTRL_RXFILEN, LPC17_40_ETH_RXFLCTRL); priv->lp_inten = ETH_INT_WKUP; - lpc17_putreg(ETH_INT_WKUP, LPC17_ETH_INTEN); + lpc17_40_putreg(ETH_INT_WKUP, LPC17_40_ETH_INTEN); #else /* Otherwise, enable all Rx interrupts. Tx interrupts, SOFTINT and WoL are * excluded. Tx interrupts will not be enabled until there is data to be @@ -1710,7 +1710,7 @@ static int lpc17_ifup(struct net_driver_s *dev) */ priv->lp_inten = ETH_RXINTS; - lpc17_putreg(ETH_RXINTS, LPC17_ETH_INTEN); + lpc17_40_putreg(ETH_RXINTS, LPC17_40_ETH_INTEN); #endif /* Enable Rx. "Enabling of the receive function is located in two places. @@ -1721,23 +1721,23 @@ static int lpc17_ifup(struct net_driver_s *dev) * path in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register." */ - regval = lpc17_getreg(LPC17_ETH_CMD); + regval = lpc17_40_getreg(LPC17_40_ETH_CMD); regval |= ETH_CMD_RXEN; - lpc17_putreg(regval, LPC17_ETH_CMD); + lpc17_40_putreg(regval, LPC17_40_ETH_CMD); - regval = lpc17_getreg(LPC17_ETH_MAC1); + regval = lpc17_40_getreg(LPC17_40_ETH_MAC1); regval |= ETH_MAC1_RE; - lpc17_putreg(regval, LPC17_ETH_MAC1); + lpc17_40_putreg(regval, LPC17_40_ETH_MAC1); /* Enable Tx */ - regval = lpc17_getreg(LPC17_ETH_CMD); + regval = lpc17_40_getreg(LPC17_40_ETH_CMD); regval |= ETH_CMD_TXEN; - lpc17_putreg(regval, LPC17_ETH_CMD); + lpc17_40_putreg(regval, LPC17_40_ETH_CMD); /* Set and activate a timer process */ - (void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_poll_expiry, 1, + (void)wd_start(priv->lp_txpoll, LPC17_40_WDDELAY, lpc17_40_poll_expiry, 1, (uint32_t)priv); /* Finally, make the interface up and enable the Ethernet interrupt at @@ -1745,16 +1745,16 @@ static int lpc17_ifup(struct net_driver_s *dev) */ priv->lp_ifup = true; -#if CONFIG_LPC17_NINTERFACES > 1 +#if CONFIG_LPC17_40_NINTERFACES > 1 up_enable_irq(priv->irq); #else - up_enable_irq(LPC17_IRQ_ETH); + up_enable_irq(LPC17_40_IRQ_ETH); #endif return OK; } /**************************************************************************** - * Function: lpc17_ifdown + * Function: lpc17_40_ifdown * * Description: * NuttX Callback: Stop the interface. @@ -1769,15 +1769,15 @@ static int lpc17_ifup(struct net_driver_s *dev) * ****************************************************************************/ -static int lpc17_ifdown(struct net_driver_s *dev) +static int lpc17_40_ifdown(struct net_driver_s *dev) { - struct lpc17_driver_s *priv = (struct lpc17_driver_s *)dev->d_private; + struct lpc17_40_driver_s *priv = (struct lpc17_40_driver_s *)dev->d_private; irqstate_t flags; /* Disable the Ethernet interrupt */ flags = enter_critical_section(); - up_disable_irq(LPC17_IRQ_ETH); + up_disable_irq(LPC17_40_IRQ_ETH); /* Cancel the TX poll timer and TX timeout timers */ @@ -1786,14 +1786,14 @@ static int lpc17_ifdown(struct net_driver_s *dev) /* Reset the device and mark it as down. */ - lpc17_ethreset(priv); + lpc17_40_ethreset(priv); priv->lp_ifup = false; leave_critical_section(flags); return OK; } /**************************************************************************** - * Function: lpc17_txavail_work + * Function: lpc17_40_txavail_work * * Description: * Perform an out-of-cycle poll on the worker thread. @@ -1809,9 +1809,9 @@ static int lpc17_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static void lpc17_txavail_work(FAR void *arg) +static void lpc17_40_txavail_work(FAR void *arg) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)arg; /* Ignore the notification if the interface is not yet up */ @@ -1820,11 +1820,11 @@ static void lpc17_txavail_work(FAR void *arg) { /* Check if there is room in the hardware to hold another outgoing packet. */ - if (lpc17_txdesc(priv) == OK) + if (lpc17_40_txdesc(priv) == OK) { /* If so, then poll the network layer for new XMIT data */ - (void)devif_poll(&priv->lp_dev, lpc17_txpoll); + (void)devif_poll(&priv->lp_dev, lpc17_40_txpoll); } } @@ -1832,7 +1832,7 @@ static void lpc17_txavail_work(FAR void *arg) } /**************************************************************************** - * Function: lpc17_txavail + * Function: lpc17_40_txavail * * Description: * Driver callback invoked when new TX data is available. This is a @@ -1850,9 +1850,9 @@ static void lpc17_txavail_work(FAR void *arg) * ****************************************************************************/ -static int lpc17_txavail(struct net_driver_s *dev) +static int lpc17_40_txavail(struct net_driver_s *dev) { - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)dev->d_private; + FAR struct lpc17_40_driver_s *priv = (FAR struct lpc17_40_driver_s *)dev->d_private; /* Is our single poll work structure available? It may not be if there * are pending polling actions and we will have to ignore the Tx @@ -1864,14 +1864,14 @@ static int lpc17_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(ETHWORK, &priv->lp_pollwork, lpc17_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->lp_pollwork, lpc17_40_txavail_work, priv, 0); } return OK; } /**************************************************************************** - * Function: lpc17_calcethcrc + * Function: lpc17_40_calcethcrc * * Description: * Function to calculate the CRC used by LPC17 to check an Ethernet frame @@ -1901,7 +1901,7 @@ static int lpc17_txavail(struct net_driver_s *dev) ****************************************************************************/ #if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -static uint32_t lpc17_calcethcrc(const uint8_t *data, size_t length) +static uint32_t lpc17_40_calcethcrc(const uint8_t *data, size_t length) { char byte; int crc; @@ -1964,7 +1964,7 @@ static uint32_t lpc17_calcethcrc(const uint8_t *data, size_t length) #endif /* CONFIG_NET_MCASTGROUP || CONFIG_NET_ICMPv6 */ /**************************************************************************** - * Function: lpc17_addmac + * Function: lpc17_40_addmac * * Description: * NuttX Callback: Add the specified MAC address to the hardware multicast @@ -1982,7 +1982,7 @@ static uint32_t lpc17_calcethcrc(const uint8_t *data, size_t length) ****************************************************************************/ #if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac) +static int lpc17_40_addmac(struct net_driver_s *dev, const uint8_t *mac) { uintptr_t regaddr; uint32_t regval; @@ -2002,24 +2002,24 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac) * is 1, the frame is accepted. */ - crc = lpc17_calcethcrc(mac, 6); + crc = lpc17_40_calcethcrc(mac, 6); ndx = (crc >> 23) & 0x3f; /* Add the MAC address to the hardware multicast hash table */ if (ndx > 31) { - regaddr = LPC17_ETH_HASHFLH; /* Hash filter table MSBs register */ + regaddr = LPC17_40_ETH_HASHFLH; /* Hash filter table MSBs register */ ndx -= 32; } else { - regaddr = LPC17_ETH_HASHFLL; /* Hash filter table LSBs register */ + regaddr = LPC17_40_ETH_HASHFLL; /* Hash filter table LSBs register */ } - regval = lpc17_getreg(regaddr); + regval = lpc17_40_getreg(regaddr); regval |= 1 << ndx; - lpc17_putreg(regval, regaddr); + lpc17_40_putreg(regval, regaddr); /* Enabled multicast address filtering in the RxFilterControl register: * @@ -2029,17 +2029,17 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac) * imperfect hash filter are accepted. */ - regval = lpc17_getreg(LPC17_ETH_RXFLCTRL); + regval = lpc17_40_getreg(LPC17_40_ETH_RXFLCTRL); regval &= ~ETH_RXFLCTRL_UCASTHASHEN; regval |= ETH_RXFLCTRL_MCASTHASHEN; - lpc17_putreg(regval, LPC17_ETH_RXFLCTRL); + lpc17_40_putreg(regval, LPC17_40_ETH_RXFLCTRL); return OK; } #endif /* CONFIG_NET_MCASTGROUP || CONFIG_NET_ICMPv6 */ /**************************************************************************** - * Function: lpc17_rmmac + * Function: lpc17_40_rmmac * * Description: * NuttX Callback: Remove the specified MAC address from the hardware multicast @@ -2057,7 +2057,7 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac) ****************************************************************************/ #ifdef CONFIG_NET_MCASTGROUP -static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) +static int lpc17_40_rmmac(struct net_driver_s *dev, const uint8_t *mac) { uintptr_t regaddr1; uintptr_t regaddr2; @@ -2078,32 +2078,32 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) * is 1, the frame is accepted. */ - crc = lpc17_calcethcrc(mac, 6); + crc = lpc17_40_calcethcrc(mac, 6); ndx = (crc >> 23) & 0x3f; /* Remove the MAC address to the hardware multicast hash table */ if (ndx > 31) { - regaddr1 = LPC17_ETH_HASHFLH; /* Hash filter table MSBs register */ - regaddr2 = LPC17_ETH_HASHFLL; /* Hash filter table LSBs register */ + regaddr1 = LPC17_40_ETH_HASHFLH; /* Hash filter table MSBs register */ + regaddr2 = LPC17_40_ETH_HASHFLL; /* Hash filter table LSBs register */ ndx -= 32; } else { - regaddr1 = LPC17_ETH_HASHFLL; /* Hash filter table LSBs register */ - regaddr2 = LPC17_ETH_HASHFLH; /* Hash filter table MSBs register */ + regaddr1 = LPC17_40_ETH_HASHFLL; /* Hash filter table LSBs register */ + regaddr2 = LPC17_40_ETH_HASHFLH; /* Hash filter table MSBs register */ } - regval = lpc17_getreg(regaddr1); + regval = lpc17_40_getreg(regaddr1); regval &= ~(1 << ndx); - lpc17_putreg(regval, regaddr1); + lpc17_40_putreg(regval, regaddr1); /* If there are no longer addresses being filtered , disable multicast * filtering. */ - if (regval == 0 && lpc17_getreg(regaddr2) == 0) + if (regval == 0 && lpc17_40_getreg(regaddr2) == 0) { /* AcceptUnicastHashEn: When set to ’1’, unicast frames that pass the * imperfect hash filter are accepted. @@ -2111,9 +2111,9 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) * imperfect hash filter are accepted. */ - regval = lpc17_getreg(LPC17_ETH_RXFLCTRL); + regval = lpc17_40_getreg(LPC17_40_ETH_RXFLCTRL); regval &= ~(ETH_RXFLCTRL_UCASTHASHEN | ETH_RXFLCTRL_MCASTHASHEN); - lpc17_putreg(regval, LPC17_ETH_RXFLCTRL); + lpc17_40_putreg(regval, LPC17_40_ETH_RXFLCTRL); } return OK; @@ -2121,7 +2121,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) #endif /**************************************************************************** - * Name: lpc17_eth_ioctl + * Name: lpc17_40_eth_ioctl * * Description: * Handle network IOCTL commands directed to this device. @@ -2140,11 +2140,11 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) ****************************************************************************/ #ifdef CONFIG_NETDEV_IOCTL -static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, +static int lpc17_40_eth_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_NETDEV_PHY_IOCTL - struct lpc17_driver_s *priv = (struct lpc17_driver_s *)dev->d_private; + struct lpc17_40_driver_s *priv = (struct lpc17_40_driver_s *)dev->d_private; #endif int ret; @@ -2163,7 +2163,7 @@ static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, { /* Enable PHY link up/down interrupts */ - ret = lpc17_phyintenable(priv); + ret = lpc17_40_phyintenable(priv); } } break; @@ -2179,7 +2179,7 @@ static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, case SIOCGMIIREG: /* Get register from MII PHY */ { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->val_out = lpc17_phyread(priv->lp_phyaddr, req->reg_num); + req->val_out = lpc17_40_phyread(priv->lp_phyaddr, req->reg_num); ret = OK; } break; @@ -2187,7 +2187,7 @@ static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, case SIOCSMIIREG: /* Set register in MII PHY */ { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - lpc17_phywrite(priv->lp_phyaddr, req->reg_num, req->val_in); + lpc17_40_phywrite(priv->lp_phyaddr, req->reg_num, req->val_in); ret = OK; } break; @@ -2195,15 +2195,16 @@ static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, default: nerr("ERROR: Unrecognized IOCTL command: %d\n", command); - return -ENOTTY; /* Special return value for this case */ + ret = -ENOTTY; /* Special return value for this case */ + break; } - return OK; + return ret; } #endif /**************************************************************************** - * Function: lpc17_phyintenable + * Function: lpc17_40_phyintenable * * Description: * Enable link up/down PHY interrupts. The interrupt protocol is like @@ -2223,15 +2224,15 @@ static int lpc17_eth_ioctl(struct net_driver_s *dev, int cmd, ****************************************************************************/ #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) -static int lpc17_phyintenable(struct lpc17_driver_s *priv) +static int lpc17_40_phyintenable(struct lpc17_40_driver_s *priv) { uint16_t phyval; - phyval = lpc17_phyread(priv->lp_phyaddr, MII_INT_REG); + phyval = lpc17_40_phyread(priv->lp_phyaddr, MII_INT_REG); /* Enable link up/down interrupts */ - lpc17_phywrite(priv->lp_phyaddr, MII_INT_REG, + lpc17_40_phywrite(priv->lp_phyaddr, MII_INT_REG, (phyval & ~MII_INT_CLREN) | MII_INT_SETEN); return OK; @@ -2239,7 +2240,7 @@ static int lpc17_phyintenable(struct lpc17_driver_s *priv) #endif /**************************************************************************** - * Name: lpc17_showpins + * Name: lpc17_40_showpins * * Description: * Dump GPIO registers @@ -2254,16 +2255,16 @@ static int lpc17_phyintenable(struct lpc17_driver_s *priv) * ****************************************************************************/ -#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) -static void lpc17_showpins(void) +#if defined(CONFIG_LPC17_40_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) +static void lpc17_40_showpins(void) { - lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]"); - lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN16, "P1[16-31]"); + lpc17_40_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]"); + lpc17_40_dumpgpio(GPIO_PORT1 | GPIO_PIN16, "P1[16-31]"); } #endif /**************************************************************************** - * Name: lpc17_showmii + * Name: lpc17_40_showmii * * Description: * Dump PHY MII registers @@ -2278,23 +2279,23 @@ static void lpc17_showpins(void) * ****************************************************************************/ -#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(LPC17_HAVE_PHY) -static void lpc17_showmii(uint8_t phyaddr, const char *msg) +#if defined(CONFIG_LPC17_40_NET_REGDEBUG) && defined(LPC17_40_HAVE_PHY) +static void lpc17_40_showmii(uint8_t phyaddr, const char *msg) { - ninfo("PHY " LPC17_PHYNAME ": %s\n", msg); - ninfo(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR)); - ninfo(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR)); - ninfo(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE)); - ninfo(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA)); - ninfo(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION)); + ninfo("PHY " LPC17_40_PHYNAME ": %s\n", msg); + ninfo(" MCR: %04x\n", lpc17_40_phyread(phyaddr, MII_MCR)); + ninfo(" MSR: %04x\n", lpc17_40_phyread(phyaddr, MII_MSR)); + ninfo(" ADVERTISE: %04x\n", lpc17_40_phyread(phyaddr, MII_ADVERTISE)); + ninfo(" LPA: %04x\n", lpc17_40_phyread(phyaddr, MII_LPA)); + ninfo(" EXPANSION: %04x\n", lpc17_40_phyread(phyaddr, MII_EXPANSION)); #ifdef CONFIG_ETH0_PHY_KS8721 - ninfo(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR)); + ninfo(" 10BTCR: %04x\n", lpc17_40_phyread(phyaddr, MII_KS8721_10BTCR)); #endif } #endif /**************************************************************************** - * Function: lpc17_phywrite + * Function: lpc17_40_phywrite * * Description: * Write a value to an MII PHY register @@ -2311,8 +2312,8 @@ static void lpc17_showmii(uint8_t phyaddr, const char *msg) * ****************************************************************************/ -#ifdef LPC17_HAVE_PHY -static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata) +#ifdef LPC17_40_HAVE_PHY +static void lpc17_40_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata) { uint32_t regval; @@ -2320,24 +2321,24 @@ static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata) regval = ((uint32_t)phyaddr << ETH_MADR_PHYADDR_SHIFT) | ((uint32_t)regaddr << ETH_MADR_REGADDR_SHIFT); - lpc17_putreg(regval, LPC17_ETH_MADR); + lpc17_40_putreg(regval, LPC17_40_ETH_MADR); /* Set up to write */ - lpc17_putreg(ETH_MCMD_WRITE, LPC17_ETH_MCMD); + lpc17_40_putreg(ETH_MCMD_WRITE, LPC17_40_ETH_MCMD); /* Write the register data to the PHY */ - lpc17_putreg((uint32_t)phydata, LPC17_ETH_MWTD); + lpc17_40_putreg((uint32_t)phydata, LPC17_40_ETH_MWTD); /* Wait for the PHY command to complete */ - while ((lpc17_getreg(LPC17_ETH_MIND) & ETH_MIND_BUSY) != 0); + while ((lpc17_40_getreg(LPC17_40_ETH_MIND) & ETH_MIND_BUSY) != 0); } #endif /**************************************************************************** - * Function: lpc17_phyread + * Function: lpc17_40_phyread * * Description: * Read a value from an MII PHY register @@ -2353,36 +2354,36 @@ static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata) * ****************************************************************************/ -#ifdef LPC17_HAVE_PHY -static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr) +#ifdef LPC17_40_HAVE_PHY +static uint16_t lpc17_40_phyread(uint8_t phyaddr, uint8_t regaddr) { uint32_t regval; - lpc17_putreg(0, LPC17_ETH_MCMD); + lpc17_40_putreg(0, LPC17_40_ETH_MCMD); /* Set PHY address and PHY register address */ regval = ((uint32_t)phyaddr << ETH_MADR_PHYADDR_SHIFT) | ((uint32_t)regaddr << ETH_MADR_REGADDR_SHIFT); - lpc17_putreg(regval, LPC17_ETH_MADR); + lpc17_40_putreg(regval, LPC17_40_ETH_MADR); /* Set up to read */ - lpc17_putreg(ETH_MCMD_READ, LPC17_ETH_MCMD); + lpc17_40_putreg(ETH_MCMD_READ, LPC17_40_ETH_MCMD); /* Wait for the PHY command to complete */ - while ((lpc17_getreg(LPC17_ETH_MIND) & (ETH_MIND_BUSY | ETH_MIND_NVALID)) != 0); - lpc17_putreg(0, LPC17_ETH_MCMD); + while ((lpc17_40_getreg(LPC17_40_ETH_MIND) & (ETH_MIND_BUSY | ETH_MIND_NVALID)) != 0); + lpc17_40_putreg(0, LPC17_40_ETH_MCMD); /* Return the PHY register data */ - return (uint16_t)(lpc17_getreg(LPC17_ETH_MRDD) & ETH_MRDD_MASK); + return (uint16_t)(lpc17_40_getreg(LPC17_40_ETH_MRDD) & ETH_MRDD_MASK); } #endif /**************************************************************************** - * Function: lpc17_phyreset + * Function: lpc17_40_phyreset * * Description: * Reset the PHY @@ -2397,15 +2398,15 @@ static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr) * ****************************************************************************/ -#ifdef LPC17_HAVE_PHY -static inline int lpc17_phyreset(uint8_t phyaddr) +#ifdef LPC17_40_HAVE_PHY +static inline int lpc17_40_phyreset(uint8_t phyaddr) { int32_t timeout; uint16_t phyreg; /* Reset the PHY. Needs a minimal 50uS delay after reset. */ - lpc17_phywrite(phyaddr, MII_MCR, MII_MCR_RESET); + lpc17_40_phywrite(phyaddr, MII_MCR, MII_MCR_RESET); /* Wait for a minimum of 50uS no matter what */ @@ -2417,7 +2418,7 @@ static inline int lpc17_phyreset(uint8_t phyaddr) for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--) { - phyreg = lpc17_phyread(phyaddr, MII_MCR); + phyreg = lpc17_40_phyread(phyaddr, MII_MCR); if ((phyreg & MII_MCR_RESET) == 0) { return OK; @@ -2430,7 +2431,7 @@ static inline int lpc17_phyreset(uint8_t phyaddr) #endif /**************************************************************************** - * Function: lpc17_phyautoneg + * Function: lpc17_40_phyautoneg * * Description: * Enable auto-negotiation. @@ -2446,15 +2447,15 @@ static inline int lpc17_phyreset(uint8_t phyaddr) * ****************************************************************************/ -#if defined(LPC17_HAVE_PHY) && defined(CONFIG_LPC17_PHY_AUTONEG) -static inline int lpc17_phyautoneg(uint8_t phyaddr) +#if defined(LPC17_40_HAVE_PHY) && defined(CONFIG_LPC17_40_PHY_AUTONEG) +static inline int lpc17_40_phyautoneg(uint8_t phyaddr) { int32_t timeout; uint16_t phyreg; /* Start auto-negotiation */ - lpc17_phywrite(phyaddr, MII_MCR, MII_MCR_ANENABLE | MII_MCR_ANRESTART); + lpc17_40_phywrite(phyaddr, MII_MCR, MII_MCR_ANENABLE | MII_MCR_ANRESTART); /* Wait for autonegotiation to complete */ @@ -2462,7 +2463,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr) { /* Check if auto-negotiation has completed */ - phyreg = lpc17_phyread(phyaddr, MII_MSR); + phyreg = lpc17_40_phyread(phyaddr, MII_MSR); if ((phyreg & MII_MSR_ANEGCOMPLETE) != 0) { /* Yes.. return success */ @@ -2477,7 +2478,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr) #endif /**************************************************************************** - * Function: lpc17_phymode + * Function: lpc17_40_phymode * * Description: * Set the PHY to operate at a selected speed/duplex mode. @@ -2493,8 +2494,8 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr) * ****************************************************************************/ -#ifdef LPC17_HAVE_PHY -static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) +#ifdef LPC17_40_HAVE_PHY +static int lpc17_40_phymode(uint8_t phyaddr, uint8_t mode) { int32_t timeout; uint16_t phyreg; @@ -2515,17 +2516,17 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) */ phyreg = 0; - if ((mode & LPC17_SPEED_MASK) == LPC17_SPEED_100) + if ((mode & LPC17_40_SPEED_MASK) == LPC17_40_SPEED_100) { phyreg = MII_MCR_SPEED100; } - if ((mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL) + if ((mode & LPC17_40_DUPLEX_MASK) == LPC17_40_DUPLEX_FULL) { phyreg |= MII_MCR_FULLDPLX; } - lpc17_phywrite(phyaddr, MII_MCR, phyreg); + lpc17_40_phywrite(phyaddr, MII_MCR, phyreg); /* Then wait for the link to be established */ @@ -2537,7 +2538,7 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) */ #if defined(CONFIG_ETH0_PHY_DP83848C) && !defined(CONFIG_ARCH_BOARD_MBED) - phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS); + phyreg = lpc17_40_phyread(phyaddr, MII_DP83848C_STS); if ((phyreg & 0x0001) != 0) { /* Yes.. return success */ @@ -2545,7 +2546,7 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) return OK; } #else - phyreg = lpc17_phyread(phyaddr, MII_MSR); + phyreg = lpc17_40_phyread(phyaddr, MII_MSR); if ((phyreg & MII_MSR_LINKSTATUS) != 0) { /* Yes.. return success */ @@ -2561,7 +2562,7 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) #endif /**************************************************************************** - * Function: lpc17_phyinit + * Function: lpc17_40_phyinit * * Description: * Initialize the PHY @@ -2577,8 +2578,8 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) * ****************************************************************************/ -#ifdef LPC17_HAVE_PHY -static inline int lpc17_phyinit(struct lpc17_driver_s *priv) +#ifdef LPC17_40_HAVE_PHY +static inline int lpc17_40_phyinit(struct lpc17_40_driver_s *priv) { unsigned int phyaddr; uint16_t phyreg; @@ -2589,13 +2590,13 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) * preamble, no scan increment. */ - lpc17_putreg(ETH_MCFG_CLKSEL_DIV, LPC17_ETH_MCFG); - lpc17_putreg(0, LPC17_ETH_MCMD); + lpc17_40_putreg(ETH_MCFG_CLKSEL_DIV, LPC17_40_ETH_MCFG); + lpc17_40_putreg(0, LPC17_40_ETH_MCMD); /* Enter RMII mode and select 100 MBPS support */ - lpc17_putreg(ETH_CMD_RMII, LPC17_ETH_CMD); - lpc17_putreg(ETH_SUPP_SPEED, LPC17_ETH_SUPP); + lpc17_40_putreg(ETH_CMD_RMII, LPC17_40_ETH_CMD); + lpc17_40_putreg(ETH_SUPP_SPEED, LPC17_40_ETH_SUPP); /* Find PHY Address. Because the controller has a pull-up and the * PHY has pull-down resistors on RXD lines some times the PHY @@ -2608,21 +2609,21 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) * PHY address. */ - phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1); + phyreg = (unsigned int)lpc17_40_phyread(phyaddr, MII_PHYID1); ninfo("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); /* Compare OUI bits 3-18 */ - if (phyreg == LPC17_PHYID1) + if (phyreg == LPC17_40_PHYID1) { - phyreg = lpc17_phyread(phyaddr, MII_PHYID2); + phyreg = lpc17_40_phyread(phyaddr, MII_PHYID2); ninfo("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg); /* Compare OUI bits 19-24 and the 6-bit model number (ignoring the * 4-bit revision number). */ - if ((phyreg & 0xfff0) == (LPC17_PHYID2 & 0xfff0)) + if ((phyreg & 0xfff0) == (LPC17_40_PHYID2 & 0xfff0)) { break; } @@ -2646,38 +2647,38 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) /* Reset the PHY */ - ret = lpc17_phyreset(phyaddr); + ret = lpc17_40_phyreset(phyaddr); if (ret < 0) { return ret; } - lpc17_showmii(phyaddr, "After reset"); + lpc17_40_showmii(phyaddr, "After reset"); /* Check for preamble suppression support */ - phyreg = lpc17_phyread(phyaddr, MII_MSR); + phyreg = lpc17_40_phyread(phyaddr, MII_MSR); if ((phyreg & MII_MSR_MFRAMESUPPRESS) != 0) { /* The PHY supports preamble suppression */ - regval = lpc17_getreg(LPC17_ETH_MCFG); + regval = lpc17_40_getreg(LPC17_40_ETH_MCFG); regval |= ETH_MCFG_SUPPRE; - lpc17_putreg(regval, LPC17_ETH_MCFG); + lpc17_40_putreg(regval, LPC17_40_ETH_MCFG); } /* Are we configured to do auto-negotiation? */ -#ifdef CONFIG_LPC17_PHY_AUTONEG +#ifdef CONFIG_LPC17_40_PHY_AUTONEG /* Setup the Auto-negotiation advertisement: 100 or 10, and HD or FD */ - lpc17_phywrite(phyaddr, MII_ADVERTISE, + lpc17_40_phywrite(phyaddr, MII_ADVERTISE, (MII_ADVERTISE_100BASETXFULL | MII_ADVERTISE_100BASETXHALF | MII_ADVERTISE_10BASETXFULL | MII_ADVERTISE_10BASETXHALF | MII_ADVERTISE_CSMA)); /* Then perform the auto-negotiation */ - ret = lpc17_phyautoneg(phyaddr); + ret = lpc17_40_phyautoneg(phyaddr); if (ret < 0) { return ret; @@ -2685,7 +2686,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) #else /* Set up the fixed PHY configuration */ - ret = lpc17_phymode(phyaddr, LPC17_MODE_DEFLT); + ret = lpc17_40_phymode(phyaddr, LPC17_40_MODE_DEFLT); if (ret < 0) { return ret; @@ -2694,31 +2695,31 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) /* The link is established */ - lpc17_showmii(phyaddr, "After link established"); + lpc17_40_showmii(phyaddr, "After link established"); /* Check configuration */ #if defined(CONFIG_ETH0_PHY_KS8721) - phyreg = lpc17_phyread(phyaddr, MII_KS8721_10BTCR); + phyreg = lpc17_40_phyread(phyaddr, MII_KS8721_10BTCR); switch (phyreg & KS8721_10BTCR_MODE_MASK) { case KS8721_10BTCR_MODE_10BTHD: /* 10BASE-T half duplex */ - priv->lp_mode = LPC17_10BASET_HD; - lpc17_putreg(0, LPC17_ETH_SUPP); + priv->lp_mode = LPC17_40_10BASET_HD; + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); break; case KS8721_10BTCR_MODE_100BTHD: /* 100BASE-T half duplex */ - priv->lp_mode = LPC17_100BASET_HD; + priv->lp_mode = LPC17_40_100BASET_HD; break; case KS8721_10BTCR_MODE_10BTFD: /* 10BASE-T full duplex */ - priv->lp_mode = LPC17_10BASET_FD; - lpc17_putreg(0, LPC17_ETH_SUPP); + priv->lp_mode = LPC17_40_10BASET_FD; + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); break; case KS8721_10BTCR_MODE_100BTFD: /* 100BASE-T full duplex */ - priv->lp_mode = LPC17_100BASET_FD; + priv->lp_mode = LPC17_40_100BASET_FD; break; default: @@ -2727,26 +2728,26 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) } #elif defined(CONFIG_ETH0_PHY_KSZ8041) - phyreg = lpc17_phyread(phyaddr, MII_KSZ8041_PHYCTRL2); + phyreg = lpc17_40_phyread(phyaddr, MII_KSZ8041_PHYCTRL2); switch (phyreg & MII_PHYCTRL2_MODE_MASK) { case MII_PHYCTRL2_MODE_10HDX: /* 10BASE-T half duplex */ - priv->lp_mode = LPC17_10BASET_HD; - lpc17_putreg(0, LPC17_ETH_SUPP); + priv->lp_mode = LPC17_40_10BASET_HD; + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); break; case MII_PHYCTRL2_MODE_100HDX: /* 100BASE-T half duplex */ - priv->lp_mode = LPC17_100BASET_HD; + priv->lp_mode = LPC17_40_100BASET_HD; break; case MII_PHYCTRL2_MODE_10FDX: /* 10BASE-T full duplex */ - priv->lp_mode = LPC17_10BASET_FD; - lpc17_putreg(0, LPC17_ETH_SUPP); + priv->lp_mode = LPC17_40_10BASET_FD; + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); break; case MII_PHYCTRL2_MODE_100FDX: /* 100BASE-T full duplex */ - priv->lp_mode = LPC17_100BASET_FD; + priv->lp_mode = LPC17_40_100BASET_FD; break; default: @@ -2754,26 +2755,26 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) return -ENODEV; } #elif defined(CONFIG_ETH0_PHY_KSZ8081) - phyreg = lpc17_phyread(phyaddr, MII_KSZ8081_PHYCTRL1); + phyreg = lpc17_40_phyread(phyaddr, MII_KSZ8081_PHYCTRL1); switch (phyreg & MII_PHYCTRL1_MODE_MASK) { case MII_PHYCTRL1_MODE_10HDX: /* 10BASE-T half duplex */ - priv->lp_mode = LPC17_10BASET_HD; - lpc17_putreg(0, LPC17_ETH_SUPP); + priv->lp_mode = LPC17_40_10BASET_HD; + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); break; case MII_PHYCTRL1_MODE_100HDX: /* 100BASE-T half duplex */ - priv->lp_mode = LPC17_100BASET_HD; + priv->lp_mode = LPC17_40_100BASET_HD; break; case MII_PHYCTRL1_MODE_10FDX: /* 10BASE-T full duplex */ - priv->lp_mode = LPC17_10BASET_FD; - lpc17_putreg(0, LPC17_ETH_SUPP); + priv->lp_mode = LPC17_40_10BASET_FD; + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); break; case MII_PHYCTRL1_MODE_100FDX: /* 100BASE-T full duplex */ - priv->lp_mode = LPC17_100BASET_FD; + priv->lp_mode = LPC17_40_100BASET_FD; break; default: @@ -2781,26 +2782,26 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) return -ENODEV; } #elif defined(CONFIG_ETH0_PHY_DP83848C) - phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS); + phyreg = lpc17_40_phyread(phyaddr, MII_DP83848C_STS); /* Configure for full/half duplex mode and speed */ switch (phyreg & 0x0006) { case 0x0000: - priv->lp_mode = LPC17_100BASET_HD; + priv->lp_mode = LPC17_40_100BASET_HD; break; case 0x0002: - priv->lp_mode = LPC17_10BASET_HD; + priv->lp_mode = LPC17_40_10BASET_HD; break; case 0x0004: - priv->lp_mode = LPC17_100BASET_FD; + priv->lp_mode = LPC17_40_100BASET_FD; break; case 0x0006: - priv->lp_mode = LPC17_10BASET_FD; + priv->lp_mode = LPC17_40_10BASET_FD; break; default: @@ -2814,15 +2815,15 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) uint16_t lpa; up_udelay(500); - advertise = lpc17_phyread(phyaddr, MII_ADVERTISE); - lpa = lpc17_phyread(phyaddr, MII_LPA); + advertise = lpc17_40_phyread(phyaddr, MII_ADVERTISE); + lpa = lpc17_40_phyread(phyaddr, MII_LPA); /* Check for 100BASETX full duplex */ if ((advertise & MII_ADVERTISE_100BASETXFULL) != 0 && (lpa & MII_LPA_100BASETXFULL) != 0) { - priv->lp_mode = LPC17_100BASET_FD; + priv->lp_mode = LPC17_40_100BASET_FD; } /* Check for 100BASETX half duplex */ @@ -2830,7 +2831,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) else if ((advertise & MII_ADVERTISE_100BASETXHALF) != 0 && (lpa & MII_LPA_100BASETXHALF) != 0) { - priv->lp_mode = LPC17_100BASET_HD; + priv->lp_mode = LPC17_40_100BASET_HD; } /* Check for 10BASETX full duplex */ @@ -2838,7 +2839,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) else if ((advertise & MII_ADVERTISE_10BASETXFULL) != 0 && (lpa & MII_LPA_10BASETXFULL) != 0) { - priv->lp_mode = LPC17_10BASET_FD; + priv->lp_mode = LPC17_40_10BASET_FD; } /* Check for 10BASETX half duplex */ @@ -2846,7 +2847,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) else if ((advertise & MII_ADVERTISE_10BASETXHALF) != 0 && (lpa & MII_LPA_10BASETXHALF) != 0) { - priv->lp_mode = LPC17_10BASET_HD; + priv->lp_mode = LPC17_40_10BASET_HD; } else { @@ -2860,34 +2861,34 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) #endif ninfo("%dBase-T %s duplex\n", - (priv->lp_mode & LPC17_SPEED_MASK) == LPC17_SPEED_100 ? 100 : 10, - (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half"); + (priv->lp_mode & LPC17_40_SPEED_MASK) == LPC17_40_SPEED_100 ? 100 : 10, + (priv->lp_mode & LPC17_40_DUPLEX_MASK) == LPC17_40_DUPLEX_FULL ?"full" : "half"); /* Disable auto-configuration. Set the fixed speed/duplex mode. * (probably more than little redundant). * * REVISIT: Revisit the following CONFIG_PHY_CEMENT_DISABLE work-around. - * It is should not needed if CONFIG_LPC17_PHY_AUTONEG is defined and is known + * It is should not needed if CONFIG_LPC17_40_PHY_AUTONEG is defined and is known * cause a problem for at least one PHY (DP83848I PHY). It might be * safe just to remove this elided coded for all PHYs. */ #ifndef CONFIG_PHY_CEMENT_DISABLE - ret = lpc17_phymode(phyaddr, priv->lp_mode); + ret = lpc17_40_phymode(phyaddr, priv->lp_mode); #endif - lpc17_showmii(phyaddr, "After final configuration"); + lpc17_40_showmii(phyaddr, "After final configuration"); return ret; } #else -static inline int lpc17_phyinit(struct lpc17_driver_s *priv) +static inline int lpc17_40_phyinit(struct lpc17_40_driver_s *priv) { - priv->lp_mode = LPC17_MODE_DEFLT; + priv->lp_mode = LPC17_40_MODE_DEFLT; return OK; } #endif /**************************************************************************** - * Function: lpc17_txdescinit + * Function: lpc17_40_txdescinit * * Description: * Initialize the EMAC Tx descriptor table @@ -2904,7 +2905,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) * ****************************************************************************/ -static inline void lpc17_txdescinit(struct lpc17_driver_s *priv) +static inline void lpc17_40_txdescinit(struct lpc17_40_driver_s *priv) { uint32_t *txdesc; uint32_t *txstat; @@ -2913,37 +2914,37 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv) /* Configure Tx descriptor and status tables */ - lpc17_putreg(LPC17_TXDESC_BASE, LPC17_ETH_TXDESC); - lpc17_putreg(LPC17_TXSTAT_BASE, LPC17_ETH_TXSTAT); - lpc17_putreg(CONFIG_LPC17_ETH_NTXDESC-1, LPC17_ETH_TXDESCRNO); + lpc17_40_putreg(LPC17_40_TXDESC_BASE, LPC17_40_ETH_TXDESC); + lpc17_40_putreg(LPC17_40_TXSTAT_BASE, LPC17_40_ETH_TXSTAT); + lpc17_40_putreg(CONFIG_LPC17_40_ETH_NTXDESC-1, LPC17_40_ETH_TXDESCRNO); /* Initialize Tx descriptors and link to packet buffers */ - txdesc = (uint32_t *)LPC17_TXDESC_BASE; - pktaddr = LPC17_TXBUFFER_BASE; + txdesc = (uint32_t *)LPC17_40_TXDESC_BASE; + pktaddr = LPC17_40_TXBUFFER_BASE; - for (i = 0; i < CONFIG_LPC17_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_LPC17_40_ETH_NTXDESC; i++) { *txdesc++ = pktaddr; - *txdesc++ = (TXDESC_CONTROL_INT | (LPC17_MAXPACKET_SIZE - 1)); - pktaddr += LPC17_MAXPACKET_SIZE; + *txdesc++ = (TXDESC_CONTROL_INT | (LPC17_40_MAXPACKET_SIZE - 1)); + pktaddr += LPC17_40_MAXPACKET_SIZE; } /* Initialize Tx status */ - txstat = (uint32_t *)LPC17_TXSTAT_BASE; - for (i = 0; i < CONFIG_LPC17_ETH_NTXDESC; i++) + txstat = (uint32_t *)LPC17_40_TXSTAT_BASE; + for (i = 0; i < CONFIG_LPC17_40_ETH_NTXDESC; i++) { *txstat++ = 0; } /* Point to first Tx descriptor */ - lpc17_putreg(0, LPC17_ETH_TXPRODIDX); + lpc17_40_putreg(0, LPC17_40_ETH_TXPRODIDX); } /**************************************************************************** - * Function: lpc17_rxdescinit + * Function: lpc17_40_rxdescinit * * Description: * Initialize the EMAC Rx descriptor table @@ -2960,7 +2961,7 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv) * ****************************************************************************/ -static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv) +static inline void lpc17_40_rxdescinit(struct lpc17_40_driver_s *priv) { uint32_t *rxdesc; uint32_t *rxstat; @@ -2969,26 +2970,26 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv) /* Configure Rx descriptor and status tables */ - lpc17_putreg(LPC17_RXDESC_BASE, LPC17_ETH_RXDESC); - lpc17_putreg(LPC17_RXSTAT_BASE, LPC17_ETH_RXSTAT); - lpc17_putreg(CONFIG_LPC17_ETH_NRXDESC-1, LPC17_ETH_RXDESCNO); + lpc17_40_putreg(LPC17_40_RXDESC_BASE, LPC17_40_ETH_RXDESC); + lpc17_40_putreg(LPC17_40_RXSTAT_BASE, LPC17_40_ETH_RXSTAT); + lpc17_40_putreg(CONFIG_LPC17_40_ETH_NRXDESC-1, LPC17_40_ETH_RXDESCNO); /* Initialize Rx descriptors and link to packet buffers */ - rxdesc = (uint32_t *)LPC17_RXDESC_BASE; - pktaddr = LPC17_RXBUFFER_BASE; + rxdesc = (uint32_t *)LPC17_40_RXDESC_BASE; + pktaddr = LPC17_40_RXBUFFER_BASE; - for (i = 0; i < CONFIG_LPC17_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_LPC17_40_ETH_NRXDESC; i++) { *rxdesc++ = pktaddr; - *rxdesc++ = (RXDESC_CONTROL_INT | (LPC17_MAXPACKET_SIZE - 1)); - pktaddr += LPC17_MAXPACKET_SIZE; + *rxdesc++ = (RXDESC_CONTROL_INT | (LPC17_40_MAXPACKET_SIZE - 1)); + pktaddr += LPC17_40_MAXPACKET_SIZE; } /* Initialize Rx status */ - rxstat = (uint32_t *)LPC17_RXSTAT_BASE; - for (i = 0; i < CONFIG_LPC17_ETH_NRXDESC; i++) + rxstat = (uint32_t *)LPC17_40_RXSTAT_BASE; + for (i = 0; i < CONFIG_LPC17_40_ETH_NRXDESC; i++) { *rxstat++ = 0; *rxstat++ = 0; @@ -2996,11 +2997,11 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv) /* Point to first Rx descriptor */ - lpc17_putreg(0, LPC17_ETH_RXCONSIDX); + lpc17_40_putreg(0, LPC17_40_ETH_RXCONSIDX); } /**************************************************************************** - * Function: lpc17_macmode + * Function: lpc17_40_macmode * * Description: * Set the MAC to operate at a selected speed/duplex mode. @@ -3015,59 +3016,59 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv) * ****************************************************************************/ -#ifdef LPC17_HAVE_PHY -static void lpc17_macmode(uint8_t mode) +#ifdef LPC17_40_HAVE_PHY +static void lpc17_40_macmode(uint8_t mode) { uint32_t regval; /* Set up for full or half duplex operation */ - if ((mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL) + if ((mode & LPC17_40_DUPLEX_MASK) == LPC17_40_DUPLEX_FULL) { /* Set the back-to-back inter-packet gap */ - lpc17_putreg(21, LPC17_ETH_IPGT); + lpc17_40_putreg(21, LPC17_40_ETH_IPGT); /* Set MAC to operate in full duplex mode with CRC and Pad enabled */ - regval = lpc17_getreg(LPC17_ETH_MAC2); + regval = lpc17_40_getreg(LPC17_40_ETH_MAC2); regval |= (ETH_MAC2_FD | ETH_MAC2_CRCEN | ETH_MAC2_PADCRCEN); - lpc17_putreg(regval, LPC17_ETH_MAC2); + lpc17_40_putreg(regval, LPC17_40_ETH_MAC2); /* Select full duplex operation for ethernet controller */ - regval = lpc17_getreg(LPC17_ETH_CMD); + regval = lpc17_40_getreg(LPC17_40_ETH_CMD); regval |= (ETH_CMD_FD | ETH_CMD_RMII | ETH_CMD_PRFRAME); - lpc17_putreg(regval, LPC17_ETH_CMD); + lpc17_40_putreg(regval, LPC17_40_ETH_CMD); } else { /* Set the back-to-back inter-packet gap */ - lpc17_putreg(18, LPC17_ETH_IPGT); + lpc17_40_putreg(18, LPC17_40_ETH_IPGT); /* Set MAC to operate in half duplex mode with CRC and Pad enabled */ - regval = lpc17_getreg(LPC17_ETH_MAC2); + regval = lpc17_40_getreg(LPC17_40_ETH_MAC2); regval &= ~ETH_MAC2_FD; regval |= (ETH_MAC2_CRCEN | ETH_MAC2_PADCRCEN); - lpc17_putreg(regval, LPC17_ETH_MAC2); + lpc17_40_putreg(regval, LPC17_40_ETH_MAC2); /* Select half duplex operation for ethernet controller */ - regval = lpc17_getreg(LPC17_ETH_CMD); + regval = lpc17_40_getreg(LPC17_40_ETH_CMD); regval &= ~ETH_CMD_FD; regval |= (ETH_CMD_RMII | ETH_CMD_PRFRAME); - lpc17_putreg(regval, LPC17_ETH_CMD); + lpc17_40_putreg(regval, LPC17_40_ETH_CMD); } - /* This is currently done in lpc17_phyinit(). That doesn't + /* This is currently done in lpc17_40_phyinit(). That doesn't * seem like the right place. It should be done here. */ #if 0 - regval = lpc17_getreg(LPC17_ETH_SUPP); - if ((mode & LPC17_SPEED_MASK) == LPC17_SPEED_100) + regval = lpc17_40_getreg(LPC17_40_ETH_SUPP); + if ((mode & LPC17_40_SPEED_MASK) == LPC17_40_SPEED_100) { regval |= ETH_SUPP_SPEED; } @@ -3075,13 +3076,13 @@ static void lpc17_macmode(uint8_t mode) { regval &= ~ETH_SUPP_SPEED; } - lpc17_putreg(regval, LPC17_ETH_SUPP); + lpc17_40_putreg(regval, LPC17_40_ETH_SUPP); #endif } #endif /**************************************************************************** - * Function: lpc17_ethreset + * Function: lpc17_40_ethreset * * Description: * Configure and reset the Ethernet module, leaving it in a disabled state. @@ -3096,7 +3097,7 @@ static void lpc17_macmode(uint8_t mode) * ****************************************************************************/ -static void lpc17_ethreset(struct lpc17_driver_s *priv) +static void lpc17_40_ethreset(struct lpc17_40_driver_s *priv) { irqstate_t flags; @@ -3106,35 +3107,35 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv) /* Put the MAC into the reset state */ - lpc17_putreg((ETH_MAC1_TXRST | ETH_MAC1_MCSTXRST | ETH_MAC1_RXRST | + lpc17_40_putreg((ETH_MAC1_TXRST | ETH_MAC1_MCSTXRST | ETH_MAC1_RXRST | ETH_MAC1_MCSRXRST | ETH_MAC1_SIMRST | ETH_MAC1_SOFTRST), - LPC17_ETH_MAC1); + LPC17_40_ETH_MAC1); /* Disable RX/RX, clear modes, reset all control registers */ - lpc17_putreg((ETH_CMD_REGRST | ETH_CMD_TXRST | ETH_CMD_RXRST), - LPC17_ETH_CMD); + lpc17_40_putreg((ETH_CMD_REGRST | ETH_CMD_TXRST | ETH_CMD_RXRST), + LPC17_40_ETH_CMD); /* Take the MAC out of the reset state */ up_udelay(50); - lpc17_putreg(0, LPC17_ETH_MAC1); + lpc17_40_putreg(0, LPC17_40_ETH_MAC1); /* The RMII bit must be set on initialization (I'm not sure this needs * to be done here but... oh well). */ - lpc17_putreg(ETH_CMD_RMII, LPC17_ETH_CMD); + lpc17_40_putreg(ETH_CMD_RMII, LPC17_40_ETH_CMD); /* Set other misc configuration-related registers to default values */ - lpc17_putreg(0, LPC17_ETH_MAC2); - lpc17_putreg(0, LPC17_ETH_SUPP); - lpc17_putreg(0, LPC17_ETH_TEST); + lpc17_40_putreg(0, LPC17_40_ETH_MAC2); + lpc17_40_putreg(0, LPC17_40_ETH_SUPP); + lpc17_40_putreg(0, LPC17_40_ETH_TEST); - lpc17_putreg(18, LPC17_ETH_IPGR); - lpc17_putreg(((15 << ETH_CLRT_RMAX_SHIFT) | (55 << ETH_CLRT_COLWIN_SHIFT)), - LPC17_ETH_CLRT); + lpc17_40_putreg(18, LPC17_40_ETH_IPGR); + lpc17_40_putreg(((15 << ETH_CLRT_RMAX_SHIFT) | (55 << ETH_CLRT_COLWIN_SHIFT)), + LPC17_40_ETH_CLRT); /* Set the Maximum Frame size register. "This field resets to the value * 0x0600, which represents a maximum receive frame of 1536 octets. An @@ -3143,15 +3144,15 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv) * restriction is desired, program this 16-bit field." */ - lpc17_putreg(LPC17_MAXPACKET_SIZE, LPC17_ETH_MAXF); + lpc17_40_putreg(LPC17_40_MAXPACKET_SIZE, LPC17_40_ETH_MAXF); /* Disable all Ethernet controller interrupts */ - lpc17_putreg(0, LPC17_ETH_INTEN); + lpc17_40_putreg(0, LPC17_40_ETH_INTEN); /* Clear any pending interrupts (shouldn't be any) */ - lpc17_putreg(0xffffffff, LPC17_ETH_INTCLR); + lpc17_40_putreg(0xffffffff, LPC17_40_ETH_INTCLR); leave_critical_section(flags); } @@ -3160,7 +3161,7 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv) ****************************************************************************/ /**************************************************************************** - * Function: lpc17_ethinitialize + * Function: lpc17_40_ethinitialize * * Description: * Initialize one Ethernet controller and driver structure. @@ -3175,35 +3176,35 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv) * ****************************************************************************/ -#if CONFIG_LPC17_NINTERFACES > 1 || defined(CONFIG_NETDEV_LATEINIT) -int lpc17_ethinitialize(int intf) +#if CONFIG_LPC17_40_NINTERFACES > 1 || defined(CONFIG_NETDEV_LATEINIT) +int lpc17_40_ethinitialize(int intf) #else -static inline int lpc17_ethinitialize(int intf) +static inline int lpc17_40_ethinitialize(int intf) #endif { - struct lpc17_driver_s *priv; + struct lpc17_40_driver_s *priv; uint8_t *pktbuf; uint32_t regval; int ret; int i; - DEBUGASSERT(intf < CONFIG_LPC17_NINTERFACES); + DEBUGASSERT(intf < CONFIG_LPC17_40_NINTERFACES); priv = &g_ethdrvr[intf]; /* Turn on the ethernet MAC clock */ - regval = lpc17_getreg(LPC17_SYSCON_PCONP); + regval = lpc17_40_getreg(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCENET; - lpc17_putreg(regval, LPC17_SYSCON_PCONP); + lpc17_40_putreg(regval, LPC17_40_SYSCON_PCONP); /* Configure all GPIO pins needed by ENET */ for (i = 0; i < GPIO_NENET_PINS; i++) { - (void)lpc17_configgpio(g_enetpins[i]); + (void)lpc17_40_configgpio(g_enetpins[i]); } - lpc17_showpins(); + lpc17_40_showpins(); /* Select the packet buffer */ @@ -3211,21 +3212,21 @@ static inline int lpc17_ethinitialize(int intf) /* Initialize the driver structure */ - memset(priv, 0, sizeof(struct lpc17_driver_s)); + memset(priv, 0, sizeof(struct lpc17_40_driver_s)); priv->lp_dev.d_buf = pktbuf; /* Single packet buffer */ - priv->lp_dev.d_ifup = lpc17_ifup; /* I/F down callback */ - priv->lp_dev.d_ifdown = lpc17_ifdown; /* I/F up (new IP address) callback */ - priv->lp_dev.d_txavail = lpc17_txavail; /* New TX data callback */ + priv->lp_dev.d_ifup = lpc17_40_ifup; /* I/F down callback */ + priv->lp_dev.d_ifdown = lpc17_40_ifdown; /* I/F up (new IP address) callback */ + priv->lp_dev.d_txavail = lpc17_40_txavail; /* New TX data callback */ #ifdef CONFIG_NET_MCASTGROUP - priv->lp_dev.d_addmac = lpc17_addmac; /* Add multicast MAC address */ - priv->lp_dev.d_rmmac = lpc17_rmmac; /* Remove multicast MAC address */ + priv->lp_dev.d_addmac = lpc17_40_addmac; /* Add multicast MAC address */ + priv->lp_dev.d_rmmac = lpc17_40_rmmac; /* Remove multicast MAC address */ #endif #ifdef CONFIG_NETDEV_IOCTL - priv->lp_dev.d_ioctl = lpc17_eth_ioctl; /* Handle network IOCTL commands */ + priv->lp_dev.d_ioctl = lpc17_40_eth_ioctl; /* Handle network IOCTL commands */ #endif priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */ -#if CONFIG_LPC17_NINTERFACES > 1 +#if CONFIG_LPC17_40_NINTERFACES > 1 # error "A mechanism to associate base address an IRQ with an interface is needed" priv->lp_base = ??; /* Ethernet controller base address */ priv->lp_irq = ??; /* Ethernet controller IRQ number */ @@ -3238,17 +3239,17 @@ static inline int lpc17_ethinitialize(int intf) /* Reset the Ethernet controller and leave in the ifdown statue. The * Ethernet controller will be properly re-initialized each time - * lpc17_ifup() is called. + * lpc17_40_ifup() is called. */ - lpc17_ifdown(&priv->lp_dev); + lpc17_40_ifdown(&priv->lp_dev); /* Attach the IRQ to the driver */ -#if CONFIG_LPC17_NINTERFACES > 1 - ret = irq_attach(priv->irq, lpc17_interrupt, NULL); +#if CONFIG_LPC17_40_NINTERFACES > 1 + ret = irq_attach(priv->irq, lpc17_40_interrupt, NULL); #else - ret = irq_attach(LPC17_IRQ_ETH, lpc17_interrupt, NULL); + ret = irq_attach(LPC17_40_IRQ_ETH, lpc17_40_interrupt, NULL); #endif if (ret != 0) { @@ -3274,11 +3275,11 @@ static inline int lpc17_ethinitialize(int intf) * ****************************************************************************/ -#if CONFIG_LPC17_NINTERFACES == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if CONFIG_LPC17_40_NINTERFACES == 1 && !defined(CONFIG_NETDEV_LATEINIT) void up_netinitialize(void) { - (void)lpc17_ethinitialize(0); + (void)lpc17_40_ethinitialize(0); } #endif -#endif /* LPC17_NETHCONTROLLERS > 0 */ -#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET */ +#endif /* LPC17_40_NETHCONTROLLERS > 0 */ +#endif /* CONFIG_NET && CONFIG_LPC17_40_ETHERNET */ diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.h similarity index 91% rename from arch/arm/src/lpc17xx/lpc17_ethernet.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.h index 9aebf2d7e78..1151aaac9c6 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_ethernet.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_ETHERNET_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_ETHERNET_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_ethernet.h" +#include "hardware/lpc17_40_ethernet.h" /************************************************************************************ * Pre-processor Definitions @@ -70,4 +70,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_ETHERNET_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c similarity index 72% rename from arch/arm/src/lpc17xx/lpc17_gpdma.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c index 9de5338a867..45b09804ece 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_gpdma.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c * * Copyright (C) 2010, 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -55,10 +55,10 @@ #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpdma.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpdma.h" -#ifdef CONFIG_LPC17_GPDMA +#ifdef CONFIG_LPC17_40_GPDMA /**************************************************************************** * Pre-processor Definitions @@ -69,7 +69,7 @@ ****************************************************************************/ /* This structure represents the state of one DMA channel */ -struct lpc17_dmach_s +struct lpc17_40_dmach_s { uint8_t chn; /* The DMA channel number */ bool inuse; /* True: The channel is in use */ @@ -81,13 +81,13 @@ struct lpc17_dmach_s /* This structure represents the state of the LPC17 DMA block */ -struct lpc17_gpdma_s +struct lpc17_40_gpdma_s { sem_t exclsem; /* For exclusive access to the DMA channel list */ /* This is the state of each DMA channel */ - struct lpc17_dmach_s dmach[LPC17_NDMACH]; + struct lpc17_40_dmach_s dmach[LPC17_40_NDMACH]; }; /**************************************************************************** @@ -99,7 +99,7 @@ struct lpc17_gpdma_s ****************************************************************************/ /* The state of the LPC17 DMA block */ -static struct lpc17_gpdma_s g_gpdma; +static struct lpc17_40_gpdma_s g_gpdma; /**************************************************************************** * Public Data @@ -121,7 +121,7 @@ volatile uint8_t g_dma_inprogress; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_dmainprogress + * Name: lpc17_40_dmainprogress * * Description: * Another DMA has started. Increment the g_dma_inprogress counter. @@ -131,28 +131,28 @@ volatile uint8_t g_dma_inprogress; * ****************************************************************************/ -static void lpc17_dmainprogress(struct lpc17_dmach_s *dmach) +static void lpc17_40_dmainprogress(struct lpc17_40_dmach_s *dmach) { irqstate_t flags; /* Increment the DMA in progress counter */ flags = enter_critical_section(); - DEBUGASSERT(!dmach->inprogress && g_dma_inprogress < LPC17_NDMACH); + DEBUGASSERT(!dmach->inprogress && g_dma_inprogress < LPC17_40_NDMACH); g_dma_inprogress++; dmach->inprogress = true; leave_critical_section(flags); } /**************************************************************************** - * Name: lpc17_dmadone + * Name: lpc17_40_dmadone * * Description: * A DMA has completed. Decrement the g_dma_inprogress counter. * - * This function is called only from lpc17_dmastop which, in turn, will be + * This function is called only from lpc17_40_dmastop which, in turn, will be * called either by the user directly, by the user indirectly via - * lpc17_dmafree(), or from gpdma_interrupt when the transfer completes. + * lpc17_40_dmafree(), or from gpdma_interrupt when the transfer completes. * * NOTE: In the first two cases, we must be able to handle the case where * there is no DMA in progress and gracefully ignore the call. @@ -162,7 +162,7 @@ static void lpc17_dmainprogress(struct lpc17_dmach_s *dmach) * ****************************************************************************/ -static void lpc17_dmadone(struct lpc17_dmach_s *dmach) +static void lpc17_40_dmadone(struct lpc17_40_dmach_s *dmach) { irqstate_t flags; @@ -192,7 +192,7 @@ static void lpc17_dmadone(struct lpc17_dmach_s *dmach) static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) { - struct lpc17_dmach_s *dmach; + struct lpc17_40_dmach_s *dmach; uint32_t regval; uint32_t chbit; int result; @@ -200,7 +200,7 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) /* Check each DMA channel */ - for (i = 0; i < LPC17_NDMACH; i++) + for (i = 0; i < LPC17_40_NDMACH; i++) { chbit = DMACH((uint32_t)i); @@ -210,7 +210,7 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) * either the error or terminal count interrupt requests. */ - regval = getreg32(LPC17_DMA_INTST); + regval = getreg32(LPC17_40_DMA_INTST); if ((regval & chbit) != 0) { /* Yes.. Is this channel assigned? Is there a callback function? */ @@ -220,7 +220,7 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) { /* Yes.. did an error occur? */ - regval = getreg32(LPC17_DMA_INTERRST); + regval = getreg32(LPC17_40_DMA_INTERRST); if ((regval & chbit) != 0) { /* Yes.. report error status */ @@ -234,7 +234,7 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) { /* Let's make sure it is the terminal transfer event. */ - regval = getreg32(LPC17_DMA_INTTCST); + regval = getreg32(LPC17_40_DMA_INTTCST); if ((regval & chbit) != 0) { result = OK; @@ -257,7 +257,7 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) * this channel, and clear any pending interrupts. */ - lpc17_dmastop((DMA_HANDLE)dmach); + lpc17_40_dmastop((DMA_HANDLE)dmach); } } @@ -288,27 +288,27 @@ void weak_function up_dma_initialize(void) /* Enable clocking to the GPDMA block */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCGPDMA; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Reset all channel configurations */ - for (i = 0; i < LPC17_NDMACH; i++) + for (i = 0; i < LPC17_40_NDMACH; i++) { - putreg32(0, LPC17_DMACH_CONFIG(i)); + putreg32(0, LPC17_40_DMACH_CONFIG(i)); } /* Clear all DMA interrupts */ - putreg32(DMACH_ALL, LPC17_DMA_INTTCCLR); - putreg32(DMACH_ALL, LPC17_DMA_INTERRCLR); + putreg32(DMACH_ALL, LPC17_40_DMA_INTTCCLR); + putreg32(DMACH_ALL, LPC17_40_DMA_INTERRCLR); /* Initialize the DMA state structure */ nxsem_init(&g_gpdma.exclsem, 0, 1); - for (i = 0; i < LPC17_NDMACH; i++) + for (i = 0; i < LPC17_40_NDMACH; i++) { g_gpdma.dmach[i].chn = i; /* Channel number */ g_gpdma.dmach[i].inuse = false; /* Channel is not in-use */ @@ -316,19 +316,19 @@ void weak_function up_dma_initialize(void) /* Attach and enable the common interrupt handler */ - ret = irq_attach(LPC17_IRQ_GPDMA, gpdma_interrupt, NULL); + ret = irq_attach(LPC17_40_IRQ_GPDMA, gpdma_interrupt, NULL); if (ret == OK) { - up_enable_irq(LPC17_IRQ_GPDMA); + up_enable_irq(LPC17_40_IRQ_GPDMA); } /* Enable the DMA controller (for little endian operation) */ - putreg32(DMA_CONFIG_E, LPC17_DMA_CONFIG); + putreg32(DMA_CONFIG_E, LPC17_40_DMA_CONFIG); } /**************************************************************************** - * Name: lpc17_dmaconfigure + * Name: lpc17_40_dmaconfigure * * Description: * Configure a DMA request. Each DMA request may have two different DMA @@ -339,11 +339,11 @@ void weak_function up_dma_initialize(void) * ****************************************************************************/ -void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate) +void lpc17_40_dmaconfigure(uint8_t dmarequest, bool alternate) { uint32_t regval; - DEBUGASSERT(dmarequest < LPC17_NDMAREQ); + DEBUGASSERT(dmarequest < LPC17_40_NDMAREQ); #ifdef LPC176x /* For the LPC176x family, only request numbers 8-15 have DMASEL bits */ @@ -358,7 +358,7 @@ void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate) /* Set or clear the DMASEL bit corresponding to the request number */ - regval = getreg32(LPC17_SYSCON_DMAREQSEL); + regval = getreg32(LPC17_40_SYSCON_DMAREQSEL); if (alternate) { @@ -369,11 +369,11 @@ void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate) regval &= ~(1 << dmarequest); } - putreg32(regval, LPC17_SYSCON_DMAREQSEL); + putreg32(regval, LPC17_40_SYSCON_DMAREQSEL); } /**************************************************************************** - * Name: lpc17_dmachannel + * Name: lpc17_40_dmachannel * * Description: * Allocate a DMA channel. This function sets aside a DMA channel and @@ -386,9 +386,9 @@ void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate) * ****************************************************************************/ -DMA_HANDLE lpc17_dmachannel(void) +DMA_HANDLE lpc17_40_dmachannel(void) { - struct lpc17_dmach_s *dmach = NULL; + struct lpc17_40_dmach_s *dmach = NULL; int ret; int i; @@ -403,7 +403,7 @@ DMA_HANDLE lpc17_dmachannel(void) /* Find an available DMA channel */ - for (i = 0; i < LPC17_NDMACH; i++) + for (i = 0; i < LPC17_40_NDMACH; i++) { if (!g_gpdma.dmach[i].inuse) { @@ -422,11 +422,11 @@ DMA_HANDLE lpc17_dmachannel(void) } /**************************************************************************** - * Name: lpc17_dmafree + * Name: lpc17_40_dmafree * * Description: * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until lpc17_dmachannel() is called again to re-gain + * NEVER be used again until lpc17_40_dmachannel() is called again to re-gain * a valid handle. * * Returned Value: @@ -434,15 +434,15 @@ DMA_HANDLE lpc17_dmachannel(void) * ****************************************************************************/ -void lpc17_dmafree(DMA_HANDLE handle) +void lpc17_40_dmafree(DMA_HANDLE handle) { - struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; + struct lpc17_40_dmach_s *dmach = (DMA_HANDLE)handle; DEBUGASSERT(dmach && dmach->inuse); /* Make sure that the DMA channel was properly stopped */ - lpc17_dmastop(handle); + lpc17_40_dmastop(handle); /* Mark the channel available. This is an atomic operation and needs no * special protection. @@ -452,17 +452,17 @@ void lpc17_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: lpc17_dmasetup + * Name: lpc17_40_dmasetup * * Description: * Configure DMA for one transfer. * ****************************************************************************/ -int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, +int lpc17_40_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, uint32_t srcaddr, uint32_t destaddr, size_t nxfrs) { - struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; + struct lpc17_40_dmach_s *dmach = (DMA_HANDLE)handle; uint32_t chbit; uint32_t regval; uint32_t base; @@ -470,12 +470,12 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, DEBUGASSERT(dmach && dmach->inuse && nxfrs < 4096); chbit = DMACH((uint32_t)dmach->chn); - base = LPC17_DMACH_BASE((uint32_t)dmach->chn); + base = LPC17_40_DMACH_BASE((uint32_t)dmach->chn); /* Put the channel in a known state. Zero disables everything */ - putreg32(0, base + LPC17_DMACH_CONTROL_OFFSET); - putreg32(0, base + LPC17_DMACH_CONFIG_OFFSET); + putreg32(0, base + LPC17_40_DMACH_CONTROL_OFFSET); + putreg32(0, base + LPC17_40_DMACH_CONFIG_OFFSET); /* "Programming a DMA channel * @@ -483,7 +483,7 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, * has the highest priority and DMA channel 7 the lowest priority. */ - regval = getreg32(LPC17_DMA_ENBLDCHNS); + regval = getreg32(LPC17_40_DMA_ENBLDCHNS); if ((regval & chbit) != 0) { /* There is an active DMA on this channel! */ @@ -496,23 +496,23 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, * channel operation might have left interrupt active. */ - putreg32(chbit, LPC17_DMA_INTTCCLR); - putreg32(chbit, LPC17_DMA_INTERRCLR); + putreg32(chbit, LPC17_40_DMA_INTTCCLR); + putreg32(chbit, LPC17_40_DMA_INTERRCLR); /* 3. "Write the source address into the DMACCxSrcAddr register. */ - putreg32(srcaddr, base + LPC17_DMACH_SRCADDR_OFFSET); + putreg32(srcaddr, base + LPC17_40_DMACH_SRCADDR_OFFSET); /* 4. "Write the destination address into the DMACCxDestAddr register. */ - putreg32(destaddr, base + LPC17_DMACH_DESTADDR_OFFSET); + putreg32(destaddr, base + LPC17_40_DMACH_DESTADDR_OFFSET); /* 5. "Write the address of the next LLI into the DMACCxLLI register. If * the transfer comprises of a single packet of data then 0 must be * written into this register. */ - putreg32(0, base + LPC17_DMACH_LLI_OFFSET); + putreg32(0, base + LPC17_40_DMACH_LLI_OFFSET); /* 6. "Write the control information into the DMACCxControl register." * @@ -523,9 +523,9 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, regval = control & ~(DMACH_CONTROL_XFRSIZE_MASK | DMACH_CONTROL_I); regval |= ((uint32_t)nxfrs << DMACH_CONTROL_XFRSIZE_SHIFT); - putreg32(regval, base + LPC17_DMACH_CONTROL_OFFSET); + putreg32(regval, base + LPC17_40_DMACH_CONTROL_OFFSET); - /* Save the number of transfer to perform for lpc17_dmastart */ + /* Save the number of transfer to perform for lpc17_40_dmastart */ dmach->nxfrs = (uint16_t)nxfrs; @@ -539,22 +539,22 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, regval = config & (DMACH_CONFIG_SRCPER_MASK | DMACH_CONFIG_DSTPER_MASK | DMACH_CONFIG_XFRTYPE_MASK); - putreg32(regval, base + LPC17_DMACH_CONFIG_OFFSET); + putreg32(regval, base + LPC17_40_DMACH_CONFIG_OFFSET); return OK; } /**************************************************************************** - * Name: lpc17_dmastart + * Name: lpc17_40_dmastart * * Description: * Start the DMA transfer * ****************************************************************************/ -int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) +int lpc17_40_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) { - struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; + struct lpc17_40_dmach_s *dmach = (DMA_HANDLE)handle; uint32_t regval; uint32_t chbit; uint32_t base; @@ -567,59 +567,59 @@ int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) dmach->arg = arg; /* Increment the count of DMAs in-progress. This count will be - * decremented when lpc17_dmastop() is called, either by the user, - * indirectly via lpc17_dmafree(), or from gpdma_interrupt when the + * decremented when lpc17_40_dmastop() is called, either by the user, + * indirectly via lpc17_40_dmafree(), or from gpdma_interrupt when the * transfer completes. */ - lpc17_dmainprogress(dmach); + lpc17_40_dmainprogress(dmach); /* Clear any pending DMA interrupts */ chbit = DMACH((uint32_t)dmach->chn); - putreg32(chbit, LPC17_DMA_INTTCCLR); - putreg32(chbit, LPC17_DMA_INTERRCLR); + putreg32(chbit, LPC17_40_DMA_INTTCCLR); + putreg32(chbit, LPC17_40_DMA_INTERRCLR); /* Enable terminal count interrupt. Note that we need to restore the * number transfers. That is because the value has a different meaning * when it is read. */ - base = LPC17_DMACH_BASE((uint32_t)dmach->chn); - regval = getreg32(base + LPC17_DMACH_CONTROL_OFFSET); + base = LPC17_40_DMACH_BASE((uint32_t)dmach->chn); + regval = getreg32(base + LPC17_40_DMACH_CONTROL_OFFSET); regval &= ~DMACH_CONTROL_XFRSIZE_MASK; regval |= (DMACH_CONTROL_I | ((uint32_t)dmach->nxfrs << DMACH_CONTROL_XFRSIZE_SHIFT)); - putreg32(regval, base + LPC17_DMACH_CONTROL_OFFSET); + putreg32(regval, base + LPC17_40_DMACH_CONTROL_OFFSET); /* Enable the channel and unmask terminal count and error interrupts. * According to the user manual, zero masks and one unmasks (hence, * these are really enables). */ - regval = getreg32(base + LPC17_DMACH_CONFIG_OFFSET); + regval = getreg32(base + LPC17_40_DMACH_CONFIG_OFFSET); regval |= (DMACH_CONFIG_E | DMACH_CONFIG_IE | DMACH_CONFIG_ITC); - putreg32(regval, base + LPC17_DMACH_CONFIG_OFFSET); + putreg32(regval, base + LPC17_40_DMACH_CONFIG_OFFSET); return OK; } /**************************************************************************** - * Name: lpc17_dmastop + * Name: lpc17_40_dmastop * * Description: - * Cancel the DMA. After lpc17_dmastop() is called, the DMA channel is - * reset and lpc17_dmasetup() must be called before lpc17_dmastart() can be + * Cancel the DMA. After lpc17_40_dmastop() is called, the DMA channel is + * reset and lpc17_40_dmasetup() must be called before lpc17_40_dmastart() can be * called again * * This function will be called either by the user directly, by the user - * indirectly via lpc17_dmafree(), or from gpdma_interrupt when the + * indirectly via lpc17_40_dmafree(), or from gpdma_interrupt when the * transfer completes. * ****************************************************************************/ -void lpc17_dmastop(DMA_HANDLE handle) +void lpc17_40_dmastop(DMA_HANDLE handle) { - struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; + struct lpc17_40_dmach_s *dmach = (DMA_HANDLE)handle; uint32_t regaddr; uint32_t regval; uint32_t chbit; @@ -631,7 +631,7 @@ void lpc17_dmastop(DMA_HANDLE handle) * enable bit. Any outstanding data in the FIFO’s is lost. */ - regaddr = LPC17_DMACH_CONFIG((uint32_t)dmach->chn); + regaddr = LPC17_40_DMACH_CONFIG((uint32_t)dmach->chn); regval = getreg32(regaddr); regval &= ~(DMACH_CONFIG_E | DMACH_CONFIG_IE | DMACH_CONFIG_ITC); putreg32(regval, regaddr); @@ -639,16 +639,16 @@ void lpc17_dmastop(DMA_HANDLE handle) /* Clear any pending interrupts for this channel */ chbit = DMACH((uint32_t)dmach->chn); - putreg32(chbit, LPC17_DMA_INTTCCLR); - putreg32(chbit, LPC17_DMA_INTERRCLR); + putreg32(chbit, LPC17_40_DMA_INTTCCLR); + putreg32(chbit, LPC17_40_DMA_INTERRCLR); /* Decrement the count of DMAs in progress */ - lpc17_dmadone(dmach); + lpc17_40_dmadone(dmach); } /**************************************************************************** - * Name: lpc17_dmasample + * Name: lpc17_40_dmasample * * Description: * Sample DMA register contents @@ -656,41 +656,41 @@ void lpc17_dmastop(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG__DEBUG_DMA_INFO -void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs) +void lpc17_40_dmasample(DMA_HANDLE handle, struct lpc17_40_dmaregs_s *regs) { - struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; + struct lpc17_40_dmach_s *dmach = (DMA_HANDLE)handle; uint32_t base; DEBUGASSERT(dmach); /* Sample the global DMA registers */ - regs->gbl.intst = getreg32(LPC17_DMA_INTST); - regs->gbl.inttcst = getreg32(LPC17_DMA_INTTCST); - regs->gbl.interrst = getreg32(LPC17_DMA_INTERRST); - regs->gbl.rawinttcst = getreg32(LPC17_DMA_RAWINTTCST); - regs->gbl.rawinterrst = getreg32(LPC17_DMA_RAWINTERRST); - regs->gbl.enbldchns = getreg32(LPC17_DMA_ENBLDCHNS); - regs->gbl.softbreq = getreg32(LPC17_DMA_SOFTBREQ); - regs->gbl.softsreq = getreg32(LPC17_DMA_SOFTSREQ); - regs->gbl.softlbreq = getreg32(LPC17_DMA_SOFTLBREQ); - regs->gbl.softlsreq = getreg32(LPC17_DMA_SOFTLSREQ); - regs->gbl.config = getreg32(LPC17_DMA_CONFIG); - regs->gbl.sync = getreg32(LPC17_DMA_SYNC); + regs->gbl.intst = getreg32(LPC17_40_DMA_INTST); + regs->gbl.inttcst = getreg32(LPC17_40_DMA_INTTCST); + regs->gbl.interrst = getreg32(LPC17_40_DMA_INTERRST); + regs->gbl.rawinttcst = getreg32(LPC17_40_DMA_RAWINTTCST); + regs->gbl.rawinterrst = getreg32(LPC17_40_DMA_RAWINTERRST); + regs->gbl.enbldchns = getreg32(LPC17_40_DMA_ENBLDCHNS); + regs->gbl.softbreq = getreg32(LPC17_40_DMA_SOFTBREQ); + regs->gbl.softsreq = getreg32(LPC17_40_DMA_SOFTSREQ); + regs->gbl.softlbreq = getreg32(LPC17_40_DMA_SOFTLBREQ); + regs->gbl.softlsreq = getreg32(LPC17_40_DMA_SOFTLSREQ); + regs->gbl.config = getreg32(LPC17_40_DMA_CONFIG); + regs->gbl.sync = getreg32(LPC17_40_DMA_SYNC); /* Sample the DMA channel registers */ - base = LPC17_DMACH_BASE((uint32_t)dmach->chn); - regs->ch.srcaddr = getreg32(base + LPC17_DMACH_SRCADDR_OFFSET); - regs->ch.destaddr = getreg32(base + LPC17_DMACH_DESTADDR_OFFSET); - regs->ch.lli = getreg32(base + LPC17_DMACH_LLI_OFFSET); - regs->ch.control = getreg32(base + LPC17_DMACH_CONTROL_OFFSET); - regs->ch.config = getreg32(base + LPC17_DMACH_CONFIG_OFFSET); + base = LPC17_40_DMACH_BASE((uint32_t)dmach->chn); + regs->ch.srcaddr = getreg32(base + LPC17_40_DMACH_SRCADDR_OFFSET); + regs->ch.destaddr = getreg32(base + LPC17_40_DMACH_DESTADDR_OFFSET); + regs->ch.lli = getreg32(base + LPC17_40_DMACH_LLI_OFFSET); + regs->ch.control = getreg32(base + LPC17_40_DMACH_CONTROL_OFFSET); + regs->ch.config = getreg32(base + LPC17_40_DMACH_CONFIG_OFFSET); } #endif /* CONFIG__DEBUG_DMA_INFO */ /**************************************************************************** - * Name: lpc17_dmadump + * Name: lpc17_40_dmadump * * Description: * Dump previously sampled DMA register contents @@ -698,10 +698,10 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs) ****************************************************************************/ #ifdef CONFIG__DEBUG_DMA_INFO -void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, +void lpc17_40_dmadump(DMA_HANDLE handle, const struct lpc17_40_dmaregs_s *regs, const char *msg) { - struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; + struct lpc17_40_dmach_s *dmach = (DMA_HANDLE)handle; uint32_t base; DEBUGASSERT(dmach); @@ -710,47 +710,47 @@ void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, dmainfo("Global GPDMA Registers: %s\n", msg); dmainfo(" INTST[%08x]: %08x\n", - LPC17_DMA_INTST, regs->gbl.intst); + LPC17_40_DMA_INTST, regs->gbl.intst); dmainfo(" INTTCST[%08x]: %08x\n", - LPC17_DMA_INTTCST, regs->gbl.inttcst); + LPC17_40_DMA_INTTCST, regs->gbl.inttcst); dmainfo(" INTERRST[%08x]: %08x\n", - LPC17_DMA_INTERRST, regs->gbl.interrst); + LPC17_40_DMA_INTERRST, regs->gbl.interrst); dmainfo(" RAWINTTCST[%08x]: %08x\n", - LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst); + LPC17_40_DMA_RAWINTTCST, regs->gbl.rawinttcst); dmainfo(" RAWINTERRST[%08x]: %08x\n", - LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst); + LPC17_40_DMA_RAWINTERRST, regs->gbl.rawinterrst); dmainfo(" ENBLDCHNS[%08x]: %08x\n", - LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns); + LPC17_40_DMA_ENBLDCHNS, regs->gbl.enbldchns); dmainfo(" SOFTBREQ[%08x]: %08x\n", - LPC17_DMA_SOFTBREQ, regs->gbl.softbreq); + LPC17_40_DMA_SOFTBREQ, regs->gbl.softbreq); dmainfo(" SOFTSREQ[%08x]: %08x\n", - LPC17_DMA_SOFTSREQ, regs->gbl.softsreq); + LPC17_40_DMA_SOFTSREQ, regs->gbl.softsreq); dmainfo(" SOFTLBREQ[%08x]: %08x\n", - LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq); + LPC17_40_DMA_SOFTLBREQ, regs->gbl.softlbreq); dmainfo(" SOFTLSREQ[%08x]: %08x\n", - LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq); + LPC17_40_DMA_SOFTLSREQ, regs->gbl.softlsreq); dmainfo(" CONFIG[%08x]: %08x\n", - LPC17_DMA_CONFIG, regs->gbl.config); + LPC17_40_DMA_CONFIG, regs->gbl.config); dmainfo(" SYNC[%08x]: %08x\n", - LPC17_DMA_SYNC, regs->gbl.sync); + LPC17_40_DMA_SYNC, regs->gbl.sync); /* Dump the DMA channel registers */ - base = LPC17_DMACH_BASE((uint32_t)dmach->chn); + base = LPC17_40_DMACH_BASE((uint32_t)dmach->chn); dmainfo("Channel GPDMA Registers: %d\n", dmach->chn); dmainfo(" SRCADDR[%08x]: %08x\n", - base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr); + base + LPC17_40_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr); dmainfo(" DESTADDR[%08x]: %08x\n", - base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr); + base + LPC17_40_DMACH_DESTADDR_OFFSET, regs->ch.destaddr); dmainfo(" LLI[%08x]: %08x\n", - base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli); + base + LPC17_40_DMACH_LLI_OFFSET, regs->ch.lli); dmainfo(" CONTROL[%08x]: %08x\n", - base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control); + base + LPC17_40_DMACH_CONTROL_OFFSET, regs->ch.control); dmainfo(" CONFIG[%08x]: %08x\n", - base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config); + base + LPC17_40_DMACH_CONFIG_OFFSET, regs->ch.config); } #endif /* CONFIG__DEBUG_DMA_INFO */ -#endif /* CONFIG_LPC17_GPDMA */ +#endif /* CONFIG_LPC17_40_GPDMA */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h similarity index 82% rename from arch/arm/src/lpc17xx/lpc17_gpdma.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h index 3c93379a9d8..013f8c55731 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_gpdma.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_GPDMA_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_GPDMA_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "hardware/lpc17_gpdma.h" +#include "hardware/lpc17_40_gpdma.h" /**************************************************************************** * Pre-processor Definitions @@ -51,14 +51,14 @@ * Public Types ****************************************************************************/ -#ifdef CONFIG_LPC17_GPDMA +#ifdef CONFIG_LPC17_40_GPDMA /* DMA_HANDLE is an opaque reference to an allocated DMA channel */ typedef FAR void *DMA_HANDLE; -/* dma_callback_t a function pointer provided to lpc17_dmastart. This +/* dma_callback_t a function pointer provided to lpc17_40_dmastart. This * function is called at the completion of the DMA transfer. 'arg' is the - * same 'arg' value that was provided when lpc17_dmastart() was called and + * same 'arg' value that was provided when lpc17_40_dmastart() was called and * result indicates the result of the transfer: Zero indicates a successful * transfers. On failure, a negated errno is returned indicating the general * nature of the DMA faiure. @@ -69,7 +69,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ #ifdef CONFIG__DEBUG_DMA_INFO -struct lpc17_dmaglobalregs_s +struct lpc17_40_dmaglobalregs_s { /* Global Registers */ @@ -87,7 +87,7 @@ struct lpc17_dmaglobalregs_s uint32_t sync; /* DMA Synchronization Register */ }; -struct lpc17_dmachanregs_s +struct lpc17_40_dmachanregs_s { /* Channel Registers */ @@ -98,15 +98,15 @@ struct lpc17_dmachanregs_s uint32_t config; /* DMA Channel Configuration Register */ }; -struct lpc17_dmaregs_s +struct lpc17_40_dmaregs_s { /* Global Registers */ - struct lpc17_dmaglobalregs_s gbl; + struct lpc17_40_dmaglobalregs_s gbl; /* Channel Registers */ - struct lpc17_dmachanregs_s ch; + struct lpc17_40_dmachanregs_s ch; }; #endif /* CONFIG__DEBUG_DMA_INFO */ @@ -141,7 +141,7 @@ EXTERN volatile uint8_t g_dma_inprogress; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_dmaconfigure + * Name: lpc17_40_dmaconfigure * * Description: * Configure a DMA request. Each DMA request may have two different DMA @@ -152,10 +152,10 @@ EXTERN volatile uint8_t g_dma_inprogress; * ****************************************************************************/ -void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate); +void lpc17_40_dmaconfigure(uint8_t dmarequest, bool alternate); /**************************************************************************** - * Name: lpc17_dmachannel + * Name: lpc17_40_dmachannel * * Description: * Allocate a DMA channel. This function sets aside a DMA channel and @@ -168,14 +168,14 @@ void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate); * ****************************************************************************/ -DMA_HANDLE lpc17_dmachannel(void); +DMA_HANDLE lpc17_40_dmachannel(void); /**************************************************************************** - * Name: lpc17_dmafree + * Name: lpc17_40_dmafree * * Description: * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until lpc17_dmachannel() is called again to re-gain + * NEVER be used again until lpc17_40_dmachannel() is called again to re-gain * a valid handle. * * Returned Value: @@ -183,43 +183,43 @@ DMA_HANDLE lpc17_dmachannel(void); * ****************************************************************************/ -void lpc17_dmafree(DMA_HANDLE handle); +void lpc17_40_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: lpc17_dmasetup + * Name: lpc17_40_dmasetup * * Description: * Configure DMA for one transfer. * ****************************************************************************/ -int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, +int lpc17_40_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, uint32_t srcaddr, uint32_t destaddr, size_t nxfrs); /**************************************************************************** - * Name: lpc17_dmastart + * Name: lpc17_40_dmastart * * Description: * Start the DMA transfer * ****************************************************************************/ -int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); +int lpc17_40_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); /**************************************************************************** - * Name: lpc17_dmastop + * Name: lpc17_40_dmastop * * Description: - * Cancel the DMA. After lpc17_dmastop() is called, the DMA channel is - * reset and lpc17_dmasetup() must be called before lpc17_dmastart() can be + * Cancel the DMA. After lpc17_40_dmastop() is called, the DMA channel is + * reset and lpc17_40_dmasetup() must be called before lpc17_40_dmastart() can be * called again * ****************************************************************************/ -void lpc17_dmastop(DMA_HANDLE handle); +void lpc17_40_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: lpc17_dmasample + * Name: lpc17_40_dmasample * * Description: * Sample DMA register contents @@ -227,13 +227,13 @@ void lpc17_dmastop(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG__DEBUG_DMA_INFO -void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs); +void lpc17_40_dmasample(DMA_HANDLE handle, struct lpc17_40_dmaregs_s *regs); #else -# define lpc17_dmasample(handle,regs) +# define lpc17_40_dmasample(handle,regs) #endif /**************************************************************************** - * Name: lpc17_dmadump + * Name: lpc17_40_dmadump * * Description: * Dump previously sampled DMA register contents @@ -241,10 +241,10 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs); ****************************************************************************/ #ifdef CONFIG__DEBUG_DMA_INFO -void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, +void lpc17_40_dmadump(DMA_HANDLE handle, const struct lpc17_40_dmaregs_s *regs, const char *msg); #else -# define lpc17_dmadump(handle,regs,msg) +# define lpc17_40_dmadump(handle,regs,msg) #endif #undef EXTERN @@ -253,5 +253,5 @@ void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_LPC17_GPDMA */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */ +#endif /* CONFIG_LPC17_40_GPDMA */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_GPDMA_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_gpio.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c index 34f0aefcd6a..4a69d487d90 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_gpio.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c * * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -41,19 +41,19 @@ #include /* This file is only a thin shell that includes the correct GPIO logic for - * the selected LPC17xx family. The correct file cannot be selected by the + * the selected LPC17xx/LPC40xx family. The correct file cannot be selected by the * make system because it needs the intelligence that only exists in chip.h - * that can associate an LPC17xx part number with an LPC17xx family. + * that can associate an LPC17xx/LPC40xx part number with an LPC17xx/LPC40xx family. */ -#include +#include #if defined(LPC176x) # include "lpc176x_gpio.c" -#elif defined(LPC178x) -# include "lpc178x_gpio.c" +#elif defined(LPC178x_40xx) +# include "lpc178x_40xx_gpio.c" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /**************************************************************************** diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.h similarity index 78% rename from arch/arm/src/lpc17xx/lpc17_gpio.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.h index b794c3055b1..53227c606eb 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_gpio.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_GPIO_H /************************************************************************************ * Included Files @@ -47,20 +47,20 @@ # include #endif -#include +#include -#include "hardware/lpc17_gpio.h" -#include "hardware/lpc17_pinconn.h" -#include "hardware/lpc17_pinconfig.h" +#include "hardware/lpc17_40_gpio.h" +#include "hardware/lpc17_40_pinconn.h" +#include "hardware/lpc17_40_pinconfig.h" -/* Include the GPIO definitions for the selected LPC17xx family. */ +/* Include the GPIO definitions for the selected LPC17xx/LPC40xx family. */ #if defined(LPC176x) # include "lpc176x_gpio.h" -#elif defined(LPC178x) -# include "lpc178x_gpio.h" +#elif defined(LPC178x_40xx) +# include "lpc178x_40xx_gpio.h" #else -# error "Unrecognized LPC17xx family" +# error "Unrecognized LPC17xx/LPC40xx family" #endif /************************************************************************************ @@ -85,11 +85,11 @@ extern "C" #define EXTERN extern #endif -/* These tables have global scope only because they are shared between lpc17_gpio.c, - * lpc17_gpioint.c, and lpc17_gpiodbg.c +/* These tables have global scope only because they are shared between lpc17_40_gpio.c, + * lpc17_40_gpioint.c, and lpc17_40_gpiodbg.c */ -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ EXTERN uint64_t g_intedge0; EXTERN uint64_t g_intedge2; #endif @@ -102,79 +102,79 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS]; ****************************************************************************/ /************************************************************************************ - * Name: lpc17_gpioirqinitialize + * Name: lpc17_40_gpioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for GPIO pins. * ************************************************************************************/ -#ifdef CONFIG_LPC17_GPIOIRQ -void lpc17_gpioirqinitialize(void); +#ifdef CONFIG_LPC17_40_GPIOIRQ +void lpc17_40_gpioirqinitialize(void); #else -# define lpc17_gpioirqinitialize() +# define lpc17_40_gpioirqinitialize() #endif /************************************************************************************ - * Name: lpc17_configgpio + * Name: lpc17_40_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * ************************************************************************************/ -int lpc17_configgpio(lpc17_pinset_t cfgset); +int lpc17_40_configgpio(lpc17_40_pinset_t cfgset); /************************************************************************************ - * Name: lpc17_gpiowrite + * Name: lpc17_40_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ************************************************************************************/ -void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value); +void lpc17_40_gpiowrite(lpc17_40_pinset_t pinset, bool value); /************************************************************************************ - * Name: lpc17_gpioread + * Name: lpc17_40_gpioread * * Description: * Read one or zero from the selected GPIO pin * ************************************************************************************/ -bool lpc17_gpioread(lpc17_pinset_t pinset); +bool lpc17_40_gpioread(lpc17_40_pinset_t pinset); /************************************************************************************ - * Name: lpc17_gpioirqenable + * Name: lpc17_40_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * ************************************************************************************/ -#ifdef CONFIG_LPC17_GPIOIRQ -void lpc17_gpioirqenable(int irq); +#ifdef CONFIG_LPC17_40_GPIOIRQ +void lpc17_40_gpioirqenable(int irq); #else -# define lpc17_gpioirqenable(irq) +# define lpc17_40_gpioirqenable(irq) #endif /************************************************************************************ - * Name: lpc17_gpioirqdisable + * Name: lpc17_40_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * ************************************************************************************/ -#ifdef CONFIG_LPC17_GPIOIRQ -void lpc17_gpioirqdisable(int irq); +#ifdef CONFIG_LPC17_40_GPIOIRQ +void lpc17_40_gpioirqdisable(int irq); #else -# define lpc17_gpioirqdisable(irq) +# define lpc17_40_gpioirqdisable(irq) #endif /************************************************************************************ - * Function: lpc17_dumpgpio + * Function: lpc17_40_dumpgpio * * Description: * Dump all GPIO registers associated with the base address of the provided pinset. @@ -182,9 +182,9 @@ void lpc17_gpioirqdisable(int irq); ************************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO -int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg); +int lpc17_40_dumpgpio(lpc17_40_pinset_t pinset, const char *msg); #else -# define lpc17_dumpgpio(p,m) +# define lpc17_40_dumpgpio(p,m) #endif #ifdef __cplusplus @@ -192,4 +192,4 @@ int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_GPIO_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpiodbg.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpiodbg.c similarity index 79% rename from arch/arm/src/lpc17xx/lpc17_gpiodbg.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_gpiodbg.c index 00d0f8fade2..a9f9e6e3dc1 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpiodbg.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpiodbg.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_gpiodbg.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_gpiodbg.c * * Copyright (C) 2010-2011, 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,7 +52,7 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #ifdef CONFIG_DEBUG_GPIO_INFO @@ -61,7 +61,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_pinsel + * Name: lpc17_40_pinsel * * Description: * Get the address of the PINSEL register corresponding to this port and @@ -70,7 +70,7 @@ ****************************************************************************/ #ifdef LPC176x -static uint32_t lpc17_pinsel(unsigned int port, unsigned int pin) +static uint32_t lpc17_40_pinsel(unsigned int port, unsigned int pin) { if (pin < 16) { @@ -84,7 +84,7 @@ static uint32_t lpc17_pinsel(unsigned int port, unsigned int pin) #endif /* LPC176x */ /**************************************************************************** - * Name: lpc17_pinmode + * Name: lpc17_40_pinmode * * Description: * Get the address of the PINMODE register corresponding to this port and @@ -93,7 +93,7 @@ static uint32_t lpc17_pinsel(unsigned int port, unsigned int pin) ****************************************************************************/ #ifdef LPC176x -static uint32_t lpc17_pinmode(unsigned int port, unsigned int pin) +static uint32_t lpc17_40_pinmode(unsigned int port, unsigned int pin) { if (pin < 16) { @@ -111,21 +111,21 @@ static uint32_t lpc17_pinmode(unsigned int port, unsigned int pin) ****************************************************************************/ /**************************************************************************** - * Function: lpc17_dumpgpio + * Function: lpc17_40_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg) +int lpc17_40_dumpgpio(lpc17_40_pinset_t pinset, const char *msg) { irqstate_t flags; uint32_t base; #if defined(LPC176x) uint32_t pinsel; uint32_t pinmode; -#elif defined(LPC178x) +#elif defined(LPC178x_40xx) uint32_t iocon; #endif /* LPC176x */ unsigned int port; @@ -137,10 +137,10 @@ int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg) pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; #if defined(LPC176x) - pinsel = lpc17_pinsel(port, pin); - pinmode = lpc17_pinmode(port, pin); -#elif defined(LPC178x) - iocon = LPC17_IOCON_P(port, pin); + pinsel = lpc17_40_pinsel(port, pin); + pinmode = lpc17_40_pinmode(port, pin); +#elif defined(LPC178x_40xx) + iocon = LPC17_40_IOCON_P(port, pin); #endif /* LPC176x */ /* The following requires exclusive access to the GPIO registers */ @@ -155,24 +155,24 @@ int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg) pinsel, pinsel ? getreg32(pinsel) : 0, pinmode, pinmode ? getreg32(pinmode) : 0, g_odmode[port], getreg32(g_odmode[port])); -#elif defined(LPC178x) +#elif defined(LPC178x_40xx) gpioinfo(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon)); #endif base = g_fiobase[port]; gpioinfo(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n", - base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET), - base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET), - base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET)); + base+LPC17_40_FIO_DIR_OFFSET, getreg32(base+LPC17_40_FIO_DIR_OFFSET), + base+LPC17_40_FIO_MASK_OFFSET, getreg32(base+LPC17_40_FIO_MASK_OFFSET), + base+LPC17_40_FIO_PIN_OFFSET, getreg32(base+LPC17_40_FIO_PIN_OFFSET)); base = g_intbase[port]; gpioinfo(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n", - LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS), - base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET), - base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET)); + LPC17_40_GPIOINT_IOINTSTATUS, getreg32(LPC17_40_GPIOINT_IOINTSTATUS), + base+LPC17_40_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_40_GPIOINT_INTSTATR_OFFSET), + base+LPC17_40_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_40_GPIOINT_INTSTATF_OFFSET)); gpioinfo(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n", - base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET), - base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET)); + base+LPC17_40_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_40_GPIOINT_INTENR_OFFSET), + base+LPC17_40_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_40_GPIOINT_INTENF_OFFSET)); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/lpc17xx/lpc17_gpioint.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c similarity index 64% rename from arch/arm/src/lpc17xx/lpc17_gpioint.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c index fded5b5b51c..d621052ea8e 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpioint.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_gpioint.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c * * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,9 +49,9 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ /**************************************************************************** * Pre-processor Definitions @@ -74,14 +74,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_getintedge + * Name: lpc17_40_getintedge * * Description: * Get the stored interrupt edge configuration. * ****************************************************************************/ -static unsigned int lpc17_getintedge(unsigned int port, unsigned int pin) +static unsigned int lpc17_40_getintedge(unsigned int port, unsigned int pin) { uint64_t *intedge; @@ -106,14 +106,14 @@ static unsigned int lpc17_getintedge(unsigned int port, unsigned int pin) } /**************************************************************************** - * Name: lpc17_setintedge + * Name: lpc17_40_setintedge * * Description: * Set the edge interrupt enabled bits for this pin. * ****************************************************************************/ -static void lpc17_setintedge(uint32_t intbase, unsigned int pin, +static void lpc17_40_setintedge(uint32_t intbase, unsigned int pin, unsigned int edges) { irqstate_t flags; @@ -125,7 +125,7 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin, /* Set/clear the rising edge enable bit */ - regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + regval = getreg32(intbase + LPC17_40_GPIOINT_INTENR_OFFSET); if ((edges & 2) != 0) { regval |= GPIOINT(pin); @@ -135,11 +135,11 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin, regval &= ~GPIOINT(pin); } - putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET); + putreg32(regval, intbase + LPC17_40_GPIOINT_INTENR_OFFSET); /* Set/clear the falling edge enable bit */ - regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + regval = getreg32(intbase + LPC17_40_GPIOINT_INTENF_OFFSET); if ((edges & 1) != 0) { regval |= GPIOINT(pin); @@ -149,38 +149,38 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin, regval &= ~GPIOINT(pin); } - putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET); + putreg32(regval, intbase + LPC17_40_GPIOINT_INTENF_OFFSET); leave_critical_section(flags); } /**************************************************************************** - * Name: lpc17_irq2port + * Name: lpc17_40_irq2port * * Description: * Given an IRQ number, return the GPIO port number (0 or 2) of the interrupt. * ****************************************************************************/ -static int lpc17_irq2port(int irq) +static int lpc17_40_irq2port(int irq) { /* Set 1: * LPC176x: 12 interrupts p0.0-p0.11 - * LPC178x: 16 interrupts p0.0-p0.15 + * LPC178x_40xx: 16 interrupts p0.0-p0.15 */ - if (irq >= LPC17_VALID_FIRST0L && - irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L)) + if (irq >= LPC17_40_VALID_FIRST0L && + irq < (LPC17_40_VALID_FIRST0L + LPC17_40_VALID_NIRQS0L)) { return 0; } /* Set 2: * LPC176x: 16 interrupts p0.15-p0.30 - * LPC178x: 16 interrupts p0.16-p0.31 + * LPC178x_40xx: 16 interrupts p0.16-p0.31 */ - else if (irq >= LPC17_VALID_FIRST0H && - irq < (LPC17_VALID_FIRST0H + LPC17_VALID_NIRQS0H)) + else if (irq >= LPC17_40_VALID_FIRST0H && + irq < (LPC17_40_VALID_FIRST0H + LPC17_40_VALID_NIRQS0H)) { return 0; } @@ -190,29 +190,29 @@ static int lpc17_irq2port(int irq) * LPC17x: 14 interrupts p2.0-p2.13 */ - else if (irq >= LPC17_VALID_FIRST2 && - irq < (LPC17_VALID_FIRST2 + LPC17_VALID_NIRQS2)) + else if (irq >= LPC17_40_VALID_FIRST2 && + irq < (LPC17_40_VALID_FIRST2 + LPC17_40_VALID_NIRQS2)) { return 2; } -#elif defined (LPC178x) +#elif defined (LPC178x_40xx) /* Set 3: * LPC18x: 16 interrupts p2.0-p2.15 */ - else if (irq >= LPC17_VALID_FIRST2L && - irq < (LPC17_VALID_FIRST2L + LPC17_VALID_NIRQS2L)) + else if (irq >= LPC17_40_VALID_FIRST2L && + irq < (LPC17_40_VALID_FIRST2L + LPC17_40_VALID_NIRQS2L)) { return 2; } /* Set 4: - * LPC178x: 16 interrupts p2.16-p2.31 + * LPC178x_40xx: 16 interrupts p2.16-p2.31 */ - else if (irq >= LPC17_VALID_FIRST2H && - irq < (LPC17_VALID_FIRST2H + LPC17_VALID_NIRQS2H)) + else if (irq >= LPC17_40_VALID_FIRST2H && + irq < (LPC17_40_VALID_FIRST2H + LPC17_40_VALID_NIRQS2H)) { return 2; } @@ -223,94 +223,94 @@ static int lpc17_irq2port(int irq) } /**************************************************************************** - * Name: lpc17_irq2pin + * Name: lpc17_40_irq2pin * * Description: * Given an IRQ number, return the GPIO pin number (0..31) of the interrupt. * ****************************************************************************/ -static int lpc17_irq2pin(int irq) +static int lpc17_40_irq2pin(int irq) { /* Set 1: * LPC17x: 12 interrupts p0.0-p0.11 * LPC18x: 16 interrupts p0.0-p0.15 * - * See arch/arm/include/lpc17xx/irq.h: - * LPC17_VALID_SHIFT0L 0 - Bit 0 is thre first bit in the group of + * See arch/arm/include/lpc17xx_40xx/irq.h: + * LPC17_40_VALID_SHIFT0L 0 - Bit 0 is thre first bit in the group of * 12/16 interrupts - * LPC17_VALID_FIRST0L irq - IRQ number associated with p0.0 - * LPC17_VALID_NIRQS0L 12/16 - Number of interrupt bits in the group + * LPC17_40_VALID_FIRST0L irq - IRQ number associated with p0.0 + * LPC17_40_VALID_NIRQS0L 12/16 - Number of interrupt bits in the group */ - if (irq >= LPC17_VALID_FIRST0L && - irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L)) + if (irq >= LPC17_40_VALID_FIRST0L && + irq < (LPC17_40_VALID_FIRST0L + LPC17_40_VALID_NIRQS0L)) { - return irq - LPC17_VALID_FIRST0L + LPC17_VALID_SHIFT0L; + return irq - LPC17_40_VALID_FIRST0L + LPC17_40_VALID_SHIFT0L; } /* Set 2: * LPC176x: 16 interrupts p0.15-p0.30 - * LPC178x: 16 interrupts p0.16-p0.31 + * LPC178x_40xx: 16 interrupts p0.16-p0.31 * - * LPC17_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group + * LPC17_40_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group * of 16 interrupts - * LPC17_VALID_FIRST0L irq - IRQ number associated with p0.15/16 - * LPC17_VALID_NIRQS0L 16 - 16 interrupt bits in the group + * LPC17_40_VALID_FIRST0L irq - IRQ number associated with p0.15/16 + * LPC17_40_VALID_NIRQS0L 16 - 16 interrupt bits in the group */ - else if (irq >= LPC17_VALID_FIRST0H && - irq < (LPC17_VALID_FIRST0H + LPC17_VALID_NIRQS0H)) + else if (irq >= LPC17_40_VALID_FIRST0H && + irq < (LPC17_40_VALID_FIRST0H + LPC17_40_VALID_NIRQS0H)) { - return irq - LPC17_VALID_FIRST0H + LPC17_VALID_SHIFT0H; + return irq - LPC17_40_VALID_FIRST0H + LPC17_40_VALID_SHIFT0H; } #if defined(LPC176x) /* Set 3: * LPC17x: 14 interrupts p2.0-p2.13 * - * LPC17_VALID_SHIFT2 0 - Bit 0 is the first bit in a group of 14 + * LPC17_40_VALID_SHIFT2 0 - Bit 0 is the first bit in a group of 14 * interrupts - * LPC17_VALID_FIRST2 irq - IRQ number associated with p2.0 - * LPC17_VALID_NIRQS2 14 - 14 interrupt bits in the group + * LPC17_40_VALID_FIRST2 irq - IRQ number associated with p2.0 + * LPC17_40_VALID_NIRQS2 14 - 14 interrupt bits in the group */ - else if (irq >= LPC17_VALID_FIRST2 && - irq < (LPC17_VALID_FIRST2 + LPC17_VALID_NIRQS2)) + else if (irq >= LPC17_40_VALID_FIRST2 && + irq < (LPC17_40_VALID_FIRST2 + LPC17_40_VALID_NIRQS2)) { - return irq - LPC17_VALID_FIRST2 + LPC17_VALID_SHIFT2; + return irq - LPC17_40_VALID_FIRST2 + LPC17_40_VALID_SHIFT2; } -#elif defined(LPC178x) +#elif defined(LPC178x_40xx) /* Set 3: * LPC18x: 16 interrupts p2.0-p2.15 * - * LPC17_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 16 + * LPC17_40_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 16 * interrupts - * LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0 - * LPC17_VALID_NIRQS2L 16 - 16 interrupt bits in the group + * LPC17_40_VALID_FIRST2L irq - IRQ number associated with p2.0 + * LPC17_40_VALID_NIRQS2L 16 - 16 interrupt bits in the group */ - else if (irq >= LPC17_VALID_FIRST2L && - irq < (LPC17_VALID_FIRST2L + LPC17_VALID_NIRQS2L)) + else if (irq >= LPC17_40_VALID_FIRST2L && + irq < (LPC17_40_VALID_FIRST2L + LPC17_40_VALID_NIRQS2L)) { - return irq - LPC17_VALID_FIRST2L + LPC17_VALID_SHIFT2L; + return irq - LPC17_40_VALID_FIRST2L + LPC17_40_VALID_SHIFT2L; } /* Set 3: * LPC18x: 16 interrupts p2.16-p2.31 * - * LPC17_VALID_SHIFT2L 16 - Bit 16 is the first bit in a group of 16 + * LPC17_40_VALID_SHIFT2L 16 - Bit 16 is the first bit in a group of 16 * interrupts - * LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0 - * LPC17_VALID_NIRQS2L 16 - 16 interrupt bits in the group + * LPC17_40_VALID_FIRST2L irq - IRQ number associated with p2.0 + * LPC17_40_VALID_NIRQS2L 16 - 16 interrupt bits in the group */ - else if (irq >= LPC17_VALID_FIRST2H && - irq < (LPC17_VALID_FIRST2H + LPC17_VALID_NIRQS2H)) + else if (irq >= LPC17_40_VALID_FIRST2H && + irq < (LPC17_40_VALID_FIRST2H + LPC17_40_VALID_NIRQS2H)) { - return irq - LPC17_VALID_FIRST2H + LPC17_VALID_SHIFT2H; + return irq - LPC17_40_VALID_FIRST2H + LPC17_40_VALID_SHIFT2H; } #endif @@ -319,14 +319,14 @@ static int lpc17_irq2pin(int irq) } /**************************************************************************** - * Name: lpc17_gpiodemux + * Name: lpc17_40_gpiodemux * * Description: * Demux all interrupts on one GPIO interrupt status register. * ****************************************************************************/ -static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, +static void lpc17_40_gpiodemux(uint32_t intbase, uint32_t intmask, int irqbase, void *context) { uint32_t intstatr; @@ -339,11 +339,11 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, * interrupts that are enabled. */ - intstatr = getreg32(intbase + LPC17_GPIOINT_INTSTATR_OFFSET); - intstatr &= getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + intstatr = getreg32(intbase + LPC17_40_GPIOINT_INTSTATR_OFFSET); + intstatr &= getreg32(intbase + LPC17_40_GPIOINT_INTENR_OFFSET); - intstatf = getreg32(intbase + LPC17_GPIOINT_INTSTATF_OFFSET); - intstatf &= getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + intstatf = getreg32(intbase + LPC17_40_GPIOINT_INTSTATF_OFFSET); + intstatf &= getreg32(intbase + LPC17_40_GPIOINT_INTENF_OFFSET); /* And get the OR of the enabled interrupt sources. We do not make any * distinction between rising and falling edges (but the hardware does support @@ -372,7 +372,7 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, { /* Clear the interrupt status */ - putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET); + putreg32(bit, intbase + LPC17_40_GPIOINT_INTCLR_OFFSET); /* And dispatch the interrupt */ @@ -392,7 +392,7 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, } /**************************************************************************** - * Name: lpc17_gpiointerrupt + * Name: lpc17_40_gpiointerrupt * * Description: * Handle the GPIO interrupt. For the LPC176x family, that interrupt could @@ -402,18 +402,18 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, * ****************************************************************************/ -static int lpc17_gpiointerrupt(int irq, void *context, FAR void *arg) +static int lpc17_40_gpiointerrupt(int irq, void *context, FAR void *arg) { /* Get the GPIO interrupt status */ - uint32_t intstatus = getreg32(LPC17_GPIOINT_IOINTSTATUS); + uint32_t intstatus = getreg32(LPC17_40_GPIOINT_IOINTSTATUS); /* Check for an interrupt on GPIO0 */ if ((intstatus & GPIOINT_IOINTSTATUS_P0INT) != 0) { - lpc17_gpiodemux(LPC17_GPIOINT0_BASE, LPC17_VALID_GPIOINT0, - LPC17_VALID_FIRST0L, context); + lpc17_40_gpiodemux(LPC17_40_GPIOINT0_BASE, LPC17_40_VALID_GPIOINT0, + LPC17_40_VALID_FIRST0L, context); } #if defined(LPC176x) @@ -421,17 +421,17 @@ static int lpc17_gpiointerrupt(int irq, void *context, FAR void *arg) if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0) { - lpc17_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2, - LPC17_VALID_FIRST2, context); + lpc17_40_gpiodemux(LPC17_40_GPIOINT2_BASE, LPC17_40_VALID_GPIOINT2, + LPC17_40_VALID_FIRST2, context); } -#elif defined(LPC178x) +#elif defined(LPC178x_40xx) /* Check for an interrupt on GPIO2 */ if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0) { - lpc17_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2, - LPC17_VALID_FIRST2L, context); + lpc17_40_gpiodemux(LPC17_40_GPIOINT2_BASE, LPC17_40_VALID_GPIOINT2, + LPC17_40_VALID_FIRST2L, context); } #endif @@ -444,7 +444,7 @@ static int lpc17_gpiointerrupt(int irq, void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_gpioirqinitialize + * Name: lpc17_40_gpioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -452,14 +452,14 @@ static int lpc17_gpiointerrupt(int irq, void *context, FAR void *arg) * ****************************************************************************/ -void lpc17_gpioirqinitialize(void) +void lpc17_40_gpioirqinitialize(void) { /* Disable all GPIO interrupts */ - putreg32(0, LPC17_GPIOINT0_INTENR); - putreg32(0, LPC17_GPIOINT0_INTENF); - putreg32(0, LPC17_GPIOINT2_INTENR); - putreg32(0, LPC17_GPIOINT2_INTENF); + putreg32(0, LPC17_40_GPIOINT0_INTENR); + putreg32(0, LPC17_40_GPIOINT0_INTENF); + putreg32(0, LPC17_40_GPIOINT2_INTENR); + putreg32(0, LPC17_40_GPIOINT2_INTENF); /* Attach and enable the GPIO IRQ. */ @@ -468,33 +468,33 @@ void lpc17_gpioirqinitialize(void) * position in the NVIC with External Interrupt 3 */ - (void)irq_attach(LPC17_IRQ_EINT3, lpc17_gpiointerrupt, NULL); - up_enable_irq(LPC17_IRQ_EINT3); + (void)irq_attach(LPC17_40_IRQ_EINT3, lpc17_40_gpiointerrupt, NULL); + up_enable_irq(LPC17_40_IRQ_EINT3); -#elif defined(LPC178x) - /* the LPC178x family has a single, dedicated interrupt for GPIO0 and +#elif defined(LPC178x_40xx) + /* the LPC178x/40xx family has a single, dedicated interrupt for GPIO0 and * GPIO2. */ - (void)irq_attach(LPC17_IRQ_GPIO, lpc17_gpiointerrupt, NULL); - up_enable_irq(LPC17_IRQ_GPIO); + (void)irq_attach(LPC17_40_IRQ_GPIO, lpc17_40_gpiointerrupt, NULL); + up_enable_irq(LPC17_40_IRQ_GPIO); #endif } /**************************************************************************** - * Name: lpc17_gpioirqenable + * Name: lpc17_40_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * ****************************************************************************/ -void lpc17_gpioirqenable(int irq) +void lpc17_40_gpioirqenable(int irq) { /* Map the IRQ number to a port number */ - int port = lpc17_irq2port(irq); + int port = lpc17_40_irq2port(irq); if (port >= 0) { /* The IRQ number does correspond to an interrupt port. Now get the base @@ -506,26 +506,26 @@ void lpc17_gpioirqenable(int irq) { /* And get the pin number associated with the port */ - unsigned int pin = lpc17_irq2pin(irq); - unsigned int edges = lpc17_getintedge(port, pin); - lpc17_setintedge(intbase, pin, edges); + unsigned int pin = lpc17_40_irq2pin(irq); + unsigned int edges = lpc17_40_getintedge(port, pin); + lpc17_40_setintedge(intbase, pin, edges); } } } /**************************************************************************** - * Name: lpc17_gpioirqdisable + * Name: lpc17_40_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * ****************************************************************************/ -void lpc17_gpioirqdisable(int irq) +void lpc17_40_gpioirqdisable(int irq) { /* Map the IRQ number to a port number */ - int port = lpc17_irq2port(irq); + int port = lpc17_40_irq2port(irq); if (port >= 0) { /* The IRQ number does correspond to an interrupt port. Now get the base @@ -537,10 +537,10 @@ void lpc17_gpioirqdisable(int irq) { /* And get the pin number associated with the port */ - unsigned int pin = lpc17_irq2pin(irq); - lpc17_setintedge(intbase, pin, 0); + unsigned int pin = lpc17_40_irq2pin(irq); + lpc17_40_setintedge(intbase, pin, 0); } } } -#endif /* CONFIG_LPC17_GPIOIRQ */ +#endif /* CONFIG_LPC17_40_GPIOIRQ */ diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c similarity index 66% rename from arch/arm/src/lpc17xx/lpc17_i2c.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c index d89c2c7f60b..be28ac617a1 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_i2c.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c * * Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -70,11 +70,11 @@ #include "up_internal.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_i2c.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_i2c.h" -#if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2) +#if defined(CONFIG_LPC17_40_I2C0) || defined(CONFIG_LPC17_40_I2C1) || defined(CONFIG_LPC17_40_I2C2) /**************************************************************************** * Pre-processor Definitions @@ -85,26 +85,26 @@ # define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 #endif -#ifndef CONFIG_LPC17_I2C0_FREQUENCY -# define CONFIG_LPC17_I2C0_FREQUENCY 100000 +#ifndef CONFIG_LPC17_40_I2C0_FREQUENCY +# define CONFIG_LPC17_40_I2C0_FREQUENCY 100000 #endif -#ifndef CONFIG_LPC17_I2C1_FREQUENCY -# define CONFIG_LPC17_I2C1_FREQUENCY 100000 +#ifndef CONFIG_LPC17_40_I2C1_FREQUENCY +# define CONFIG_LPC17_40_I2C1_FREQUENCY 100000 #endif -#ifndef CONFIG_LPC17_I2C2_FREQUENCY -# define CONFIG_LPC17_I2C2_FREQUENCY 100000 +#ifndef CONFIG_LPC17_40_I2C2_FREQUENCY +# define CONFIG_LPC17_40_I2C2_FREQUENCY 100000 #endif #define I2C_TIMEOUT (20 * 1000/CONFIG_USEC_PER_TICK) /* 20 mS */ -#define LPC17_I2C1_FREQUENCY 400000 +#define LPC17_40_I2C1_FREQUENCY 400000 /**************************************************************************** * Private Types ****************************************************************************/ -struct lpc17_i2cdev_s +struct lpc17_40_i2cdev_s { struct i2c_master_s dev; /* Generic I2C device */ unsigned int base; /* Base address of registers */ @@ -127,53 +127,53 @@ struct lpc17_i2cdev_s * Private Function Prototypes ****************************************************************************/ -static int lpc17_i2c_start(struct lpc17_i2cdev_s *priv); -static void lpc17_i2c_stop(struct lpc17_i2cdev_s *priv); -static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg); -static void lpc17_i2c_timeout(int argc, uint32_t arg, ...); -static void lpc17_i2c_setfrequency(struct lpc17_i2cdev_s *priv, +static int lpc17_40_i2c_start(struct lpc17_40_i2cdev_s *priv); +static void lpc17_40_i2c_stop(struct lpc17_40_i2cdev_s *priv); +static int lpc17_40_i2c_interrupt(int irq, FAR void *context, void *arg); +static void lpc17_40_i2c_timeout(int argc, uint32_t arg, ...); +static void lpc17_40_i2c_setfrequency(struct lpc17_40_i2cdev_s *priv, uint32_t frequency); -static void lpc17_stopnext(struct lpc17_i2cdev_s *priv); +static void lpc17_40_stopnext(struct lpc17_40_i2cdev_s *priv); /* I2C device operations */ -static int lpc17_i2c_transfer(FAR struct i2c_master_s *dev, +static int lpc17_40_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int lpc17_i2c_reset(FAR struct i2c_master_s * dev); +static int lpc17_40_i2c_reset(FAR struct i2c_master_s * dev); #endif /**************************************************************************** * Private Data ****************************************************************************/ -#ifdef CONFIG_LPC17_I2C0 -static struct lpc17_i2cdev_s g_i2c0dev; +#ifdef CONFIG_LPC17_40_I2C0 +static struct lpc17_40_i2cdev_s g_i2c0dev; #endif -#ifdef CONFIG_LPC17_I2C1 -static struct lpc17_i2cdev_s g_i2c1dev; +#ifdef CONFIG_LPC17_40_I2C1 +static struct lpc17_40_i2cdev_s g_i2c1dev; #endif -#ifdef CONFIG_LPC17_I2C2 -static struct lpc17_i2cdev_s g_i2c2dev; +#ifdef CONFIG_LPC17_40_I2C2 +static struct lpc17_40_i2cdev_s g_i2c2dev; #endif -struct i2c_ops_s lpc17_i2c_ops = +struct i2c_ops_s lpc17_40_i2c_ops = { - .transfer = lpc17_i2c_transfer + .transfer = lpc17_40_i2c_transfer #ifdef CONFIG_I2C_RESET - , .reset = lpc17_i2c_reset + , .reset = lpc17_40_i2c_reset #endif }; /**************************************************************************** - * Name: lpc17_i2c_setfrequency + * Name: lpc17_40_i2c_setfrequency * * Description: * Set the frequency for the next transfer * ****************************************************************************/ -static void lpc17_i2c_setfrequency(struct lpc17_i2cdev_s *priv, +static void lpc17_40_i2c_setfrequency(struct lpc17_40_i2cdev_s *priv, uint32_t frequency) { if (frequency != priv->frequency) @@ -182,19 +182,19 @@ static void lpc17_i2c_setfrequency(struct lpc17_i2cdev_s *priv, { /* Asymetric per 400Khz I2C spec */ - putreg32(LPC17_CCLK / (83 + 47) * 47 / frequency, - priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32(LPC17_CCLK / (83 + 47) * 83 / frequency, - priv->base + LPC17_I2C_SCLL_OFFSET); + putreg32(LPC17_40_CCLK / (83 + 47) * 47 / frequency, + priv->base + LPC17_40_I2C_SCLH_OFFSET); + putreg32(LPC17_40_CCLK / (83 + 47) * 83 / frequency, + priv->base + LPC17_40_I2C_SCLL_OFFSET); } else { /* 50/50 mark space ratio */ - putreg32(LPC17_CCLK / 100 * 50 / frequency, - priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32(LPC17_CCLK / 100 * 50 / frequency, - priv->base + LPC17_I2C_SCLL_OFFSET); + putreg32(LPC17_40_CCLK / 100 * 50 / frequency, + priv->base + LPC17_40_I2C_SCLH_OFFSET); + putreg32(LPC17_40_CCLK / 100 * 50 / frequency, + priv->base + LPC17_40_I2C_SCLL_OFFSET); } priv->frequency = frequency; @@ -202,20 +202,20 @@ static void lpc17_i2c_setfrequency(struct lpc17_i2cdev_s *priv, } /**************************************************************************** - * Name: lpc17_i2c_start + * Name: lpc17_40_i2c_start * * Description: * Perform a I2C transfer start * ****************************************************************************/ -static int lpc17_i2c_start(struct lpc17_i2cdev_s *priv) +static int lpc17_40_i2c_start(struct lpc17_40_i2cdev_s *priv) { putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, - priv->base + LPC17_I2C_CONCLR_OFFSET); - putreg32(I2C_CONSET_STA, priv->base + LPC17_I2C_CONSET_OFFSET); + priv->base + LPC17_40_I2C_CONCLR_OFFSET); + putreg32(I2C_CONSET_STA, priv->base + LPC17_40_I2C_CONSET_OFFSET); - (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc17_i2c_timeout, 1, + (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc17_40_i2c_timeout, 1, (uint32_t)priv); nxsem_wait(&priv->wait); @@ -225,35 +225,35 @@ static int lpc17_i2c_start(struct lpc17_i2cdev_s *priv) } /**************************************************************************** - * Name: lpc17_i2c_stop + * Name: lpc17_40_i2c_stop * * Description: * Perform a I2C transfer stop * ****************************************************************************/ -static void lpc17_i2c_stop(struct lpc17_i2cdev_s *priv) +static void lpc17_40_i2c_stop(struct lpc17_40_i2cdev_s *priv) { if (priv->state != 0x38) { putreg32(I2C_CONSET_STO | I2C_CONSET_AA, - priv->base + LPC17_I2C_CONSET_OFFSET); + priv->base + LPC17_40_I2C_CONSET_OFFSET); } nxsem_post(&priv->wait); } /**************************************************************************** - * Name: lpc17_i2c_timeout + * Name: lpc17_40_i2c_timeout * * Description: * Watchdog timer for timeout of I2C operation * ****************************************************************************/ -static void lpc17_i2c_timeout(int argc, uint32_t arg, ...) +static void lpc17_40_i2c_timeout(int argc, uint32_t arg, ...) { - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *)arg; + struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *)arg; irqstate_t flags = enter_critical_section(); priv->state = 0xff; @@ -262,17 +262,17 @@ static void lpc17_i2c_timeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Name: lpc17_i2c_transfer + * Name: lpc17_40_i2c_transfer * * Description: * Perform a sequence of I2C transfers * ****************************************************************************/ -static int lpc17_i2c_transfer(FAR struct i2c_master_s *dev, +static int lpc17_40_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count) { - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *)dev; + struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *)dev; int ret; DEBUGASSERT(dev != NULL && msgs != NULL && count > 0); @@ -294,50 +294,50 @@ static int lpc17_i2c_transfer(FAR struct i2c_master_s *dev, * each message segment. */ - lpc17_i2c_setfrequency(priv, msgs->frequency); + lpc17_40_i2c_setfrequency(priv, msgs->frequency); /* Perform the transfer */ - ret = lpc17_i2c_start(priv); + ret = lpc17_40_i2c_start(priv); nxsem_post(&priv->mutex); return ret; } /**************************************************************************** - * Name: lpc17_stopnext + * Name: lpc17_40_stopnext * * Description: * Check if we need to issue STOP at the next message * ****************************************************************************/ -static void lpc17_stopnext(struct lpc17_i2cdev_s *priv) +static void lpc17_40_stopnext(struct lpc17_40_i2cdev_s *priv) { priv->nmsg--; if (priv->nmsg > 0) { priv->msgs++; - putreg32(I2C_CONSET_STA, priv->base + LPC17_I2C_CONSET_OFFSET); + putreg32(I2C_CONSET_STA, priv->base + LPC17_40_I2C_CONSET_OFFSET); } else { - lpc17_i2c_stop(priv); + lpc17_40_i2c_stop(priv); } } /**************************************************************************** - * Name: lpc17_i2c_interrupt + * Name: lpc17_40_i2c_interrupt * * Description: * The I2C Interrupt Handler * ****************************************************************************/ -static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) +static int lpc17_40_i2c_interrupt(int irq, FAR void *context, void *arg) { - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *)arg; + struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *)arg; struct i2c_msg_s *msg; uint32_t state; @@ -345,7 +345,7 @@ static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) /* Reference UM10360 19.10.5 */ - state = getreg32(priv->base + LPC17_I2C_STAT_OFFSET); + state = getreg32(priv->base + LPC17_40_I2C_STAT_OFFSET); msg = priv->msgs; priv->state = state; @@ -359,18 +359,18 @@ static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ) ? I2C_READADDR8(msg->addr) : - I2C_WRITEADDR8(msg->addr), priv->base + LPC17_I2C_DAT_OFFSET); + I2C_WRITEADDR8(msg->addr), priv->base + LPC17_40_I2C_DAT_OFFSET); /* Clear start bit */ - putreg32(I2C_CONCLR_STAC, priv->base + LPC17_I2C_CONCLR_OFFSET); + putreg32(I2C_CONCLR_STAC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); break; /* Write cases */ case 0x18: /* SLA+W has been transmitted; ACK has been received */ priv->wrcnt = 0; - putreg32(msg->buffer[0], priv->base + LPC17_I2C_DAT_OFFSET); /* put first byte */ + putreg32(msg->buffer[0], priv->base + LPC17_40_I2C_DAT_OFFSET); /* put first byte */ break; case 0x28: /* Data byte in DAT has been transmitted; ACK has been received. */ @@ -378,11 +378,11 @@ static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) if (priv->wrcnt < msg->length) { - putreg32(msg->buffer[priv->wrcnt], priv->base + LPC17_I2C_DAT_OFFSET); /* Put next byte */ + putreg32(msg->buffer[priv->wrcnt], priv->base + LPC17_40_I2C_DAT_OFFSET); /* Put next byte */ } else { - lpc17_stopnext(priv); + lpc17_40_stopnext(priv); } break; @@ -392,41 +392,41 @@ static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) priv->rdcnt = 0; if (msg->length > 1) { - putreg32(I2C_CONSET_AA, priv->base + LPC17_I2C_CONSET_OFFSET); /* Set ACK next read */ + putreg32(I2C_CONSET_AA, priv->base + LPC17_40_I2C_CONSET_OFFSET); /* Set ACK next read */ } else { - putreg32(I2C_CONCLR_AAC, priv->base + LPC17_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */ + putreg32(I2C_CONCLR_AAC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */ } break; case 0x50: /* Data byte has been received; ACK has been returned. */ priv->rdcnt++; - msg->buffer[priv->rdcnt - 1] = getreg32(priv->base + LPC17_I2C_BUFR_OFFSET); + msg->buffer[priv->rdcnt - 1] = getreg32(priv->base + LPC17_40_I2C_BUFR_OFFSET); if (priv->rdcnt >= (msg->length - 1)) { - putreg32(I2C_CONCLR_AAC, priv->base + LPC17_I2C_CONCLR_OFFSET); /* Do not ACK any more */ + putreg32(I2C_CONCLR_AAC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); /* Do not ACK any more */ } break; case 0x58: /* Data byte has been received; NACK has been returned. */ - msg->buffer[priv->rdcnt] = getreg32(priv->base + LPC17_I2C_BUFR_OFFSET); - lpc17_stopnext(priv); + msg->buffer[priv->rdcnt] = getreg32(priv->base + LPC17_40_I2C_BUFR_OFFSET); + lpc17_40_stopnext(priv); break; default: - lpc17_i2c_stop(priv); + lpc17_40_i2c_stop(priv); break; } - putreg32(I2C_CONCLR_SIC, priv->base + LPC17_I2C_CONCLR_OFFSET); /* clear interrupt */ + putreg32(I2C_CONCLR_SIC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); /* clear interrupt */ return OK; } /************************************************************************************ - * Name: lpc17_i2c_reset + * Name: lpc17_40_i2c_reset * * Description: * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. @@ -440,7 +440,7 @@ static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) ************************************************************************************/ #ifdef CONFIG_I2C_RESET -static int lpc17_i2c_reset(FAR struct i2c_master_s * dev) +static int lpc17_40_i2c_reset(FAR struct i2c_master_s * dev) { return OK; } @@ -451,16 +451,16 @@ static int lpc17_i2c_reset(FAR struct i2c_master_s * dev) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_i2cbus_initialize + * Name: lpc17_40_i2cbus_initialize * * Description: * Initialise an I2C device * ****************************************************************************/ -struct i2c_master_s *lpc17_i2cbus_initialize(int port) +struct i2c_master_s *lpc17_40_i2cbus_initialize(int port) { - struct lpc17_i2cdev_s *priv; + struct lpc17_40_i2cdev_s *priv; if (port > 1) { @@ -473,90 +473,90 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) flags = enter_critical_section(); -#ifdef CONFIG_LPC17_I2C0 +#ifdef CONFIG_LPC17_40_I2C0 if (port == 0) { priv = &g_i2c0dev; - priv->base = LPC17_I2C0_BASE; - priv->irqid = LPC17_IRQ_I2C0; + priv->base = LPC17_40_I2C0_BASE; + priv->irqid = LPC17_40_IRQ_I2C0; /* Enable clocking */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCI2C0; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_I2C0_MASK; regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); /* Pin configuration */ - lpc17_configgpio(GPIO_I2C0_SCL); - lpc17_configgpio(GPIO_I2C0_SDA); + lpc17_40_configgpio(GPIO_I2C0_SCL); + lpc17_40_configgpio(GPIO_I2C0_SDA); /* Set default frequency */ - lpc17_i2c_setfrequency(priv, CONFIG_LPC17_I2C0_FREQUENCY); + lpc17_40_i2c_setfrequency(priv, CONFIG_LPC17_40_I2C0_FREQUENCY); } else #endif -#ifdef CONFIG_LPC17_I2C1 +#ifdef CONFIG_LPC17_40_I2C1 if (port == 1) { priv = &g_i2c1dev; - priv->base = LPC17_I2C1_BASE; - priv->irqid = LPC17_IRQ_I2C1; + priv->base = LPC17_40_I2C1_BASE; + priv->irqid = LPC17_40_IRQ_I2C1; /* Enable clocking */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCI2C1; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~SYSCON_PCLKSEL1_I2C1_MASK; regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); /* Pin configuration */ - lpc17_configgpio(GPIO_I2C1_SCL); - lpc17_configgpio(GPIO_I2C1_SDA); + lpc17_40_configgpio(GPIO_I2C1_SCL); + lpc17_40_configgpio(GPIO_I2C1_SDA); /* Set default frequency */ - lpc17_i2c_setfrequency(priv, CONFIG_LPC17_I2C1_FREQUENCY); + lpc17_40_i2c_setfrequency(priv, CONFIG_LPC17_40_I2C1_FREQUENCY); } else #endif -#ifdef CONFIG_LPC17_I2C2 +#ifdef CONFIG_LPC17_40_I2C2 if (port == 2) { priv = &g_i2c2dev; - priv->base = LPC17_I2C2_BASE; - priv->irqid = LPC17_IRQ_I2C2; + priv->base = LPC17_40_I2C2_BASE; + priv->irqid = LPC17_40_IRQ_I2C2; /* Enable clocking */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCI2C2; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~SYSCON_PCLKSEL1_I2C2_MASK; regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); /* Pin configuration */ - lpc17_configgpio(GPIO_I2C2_SCL); - lpc17_configgpio(GPIO_I2C2_SDA); + lpc17_40_configgpio(GPIO_I2C2_SCL); + lpc17_40_configgpio(GPIO_I2C2_SDA); /* Set default frequency */ - lpc17_i2c_setfrequency(priv, CONFIG_LPC17_I2C2_FREQUENCY); + lpc17_40_i2c_setfrequency(priv, CONFIG_LPC17_40_I2C2_FREQUENCY); } else #endif @@ -566,7 +566,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) leave_critical_section(flags); - putreg32(I2C_CONSET_I2EN, priv->base + LPC17_I2C_CONSET_OFFSET); + putreg32(I2C_CONSET_I2EN, priv->base + LPC17_40_I2C_CONSET_OFFSET); /* Initialize semaphores */ @@ -586,7 +586,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, lpc17_i2c_interrupt, priv); + irq_attach(priv->irqid, lpc17_40_i2c_interrupt, priv); /* Enable Interrupt Handler */ @@ -594,25 +594,25 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) /* Install our operations */ - priv->dev.ops = &lpc17_i2c_ops; + priv->dev.ops = &lpc17_40_i2c_ops; return &priv->dev; } /**************************************************************************** - * Name: lpc17_i2cbus_uninitialize + * Name: lpc17_40_i2cbus_uninitialize * * Description: * Uninitialise an I2C device * ****************************************************************************/ -int lpc17_i2cbus_uninitialize(FAR struct i2c_master_s * dev) +int lpc17_40_i2cbus_uninitialize(FAR struct i2c_master_s * dev) { - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *) dev; /* Disable I2C */ - putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC17_I2C_CONCLR_OFFSET); + putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); /* Reset data structures */ @@ -634,4 +634,4 @@ int lpc17_i2cbus_uninitialize(FAR struct i2c_master_s * dev) return OK; } -#endif /* CONFIG_LPC17_I2C0 || CONFIG_LPC17_I2C1 || CONFIG_LPC17_I2C2 */ +#endif /* CONFIG_LPC17_40_I2C0 || CONFIG_LPC17_40_I2C1 || CONFIG_LPC17_40_I2C2 */ diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.h similarity index 86% rename from arch/arm/src/lpc17xx/lpc17_i2c.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.h index 3595c880dbf..e900c6e7e17 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_i2c.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_I2C_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_I2C_H /**************************************************************************** * Included Files @@ -42,14 +42,14 @@ #include #include -#include "hardware/lpc17_i2c.h" +#include "hardware/lpc17_40_i2c.h" /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: lpc17_i2cbus_initialize + * Name: lpc17_40_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -65,16 +65,16 @@ * ****************************************************************************/ -FAR struct i2c_master_s *lpc17_i2cbus_initialize(int port); +FAR struct i2c_master_s *lpc17_40_i2cbus_initialize(int port); /**************************************************************************** - * Name: lpc17_i2cbus_uninitialize + * Name: lpc17_40_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the lpc17_i2cbus_initialize() + * Device structure as returned by the lpc17_40_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -82,6 +82,6 @@ FAR struct i2c_master_s *lpc17_i2cbus_initialize(int port); * ****************************************************************************/ -int lpc17_i2cbus_uninitialize(FAR struct i2c_master_s *dev); +int lpc17_40_i2cbus_uninitialize(FAR struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_I2C_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_i2s.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2s.h similarity index 91% rename from arch/arm/src/lpc17xx/lpc17_i2s.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_i2s.h index 49a02dbec5d..033a022a4c8 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2s.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2s.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_i2s.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_i2s.h * * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H -#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_LPC17_40_I2S_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_LPC17_40_I2S_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "hardware/lpc17_i2s.h" +#include "hardware/lpc17_40_i2s.h" /**************************************************************************** * Pre-processor Definitions @@ -59,4 +59,4 @@ * Public Functions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_LPC17_40_I2S_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_idle.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_idle.c similarity index 97% rename from arch/arm/src/lpc17xx/lpc17_idle.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_idle.c index 5600ed9367f..7a4a59c27ed 100644 --- a/arch/arm/src/lpc17xx/lpc17_idle.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17/lpc17_idle.c + * arch/arm/src/lpc17/lpc17_40_idle.c * * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,7 +44,7 @@ #include #include "up_internal.h" -#include "lpc17_gpdma.h" +#include "lpc17_40_gpdma.h" /**************************************************************************** * Pre-processor Definitions @@ -106,7 +106,7 @@ void up_idle(void) * disabled in order to save power." */ -#ifdef CONFIG_LPC17_GPDMA +#ifdef CONFIG_LPC17_40_GPDMA if (g_dma_inprogress == 0) #endif { diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c similarity index 82% rename from arch/arm/src/lpc17xx/lpc17_irq.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c index c15d33baf9b..a6bbdb41548 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17/lpc17_irq.c + * arch/arm/src/lpc17/lpc17_40_irq.c * * Copyright (C) 2010-2011, 2013-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,8 +52,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" -#include "lpc17_clrpend.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_clrpend.h" /**************************************************************************** * Pre-processor Definitions @@ -96,7 +96,7 @@ extern uint32_t _vectors[]; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_dumpnvic + * Name: lpc17_40_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -104,7 +104,7 @@ extern uint32_t _vectors[]; ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void lpc17_dumpnvic(const char *msg, int irq) +static void lpc17_40_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -135,12 +135,12 @@ static void lpc17_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define lpc17_dumpnvic(msg, irq) +# define lpc17_40_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: lpc17_nmi, lpc17_busfault, lpc17_usagefault, lpc17_pendsv, - * lpc17_dbgmonitor, lpc17_pendsv, lpc17_reserved + * Name: lpc17_40_nmi, lpc17_40_busfault, lpc17_40_usagefault, lpc17_40_pendsv, + * lpc17_40_dbgmonitor, lpc17_40_pendsv, lpc17_40_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -150,7 +150,7 @@ static void lpc17_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int lpc17_nmi(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -158,7 +158,7 @@ static int lpc17_nmi(int irq, FAR void *context, FAR void *arg) return 0; } -static int lpc17_busfault(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault recived\n"); @@ -166,7 +166,7 @@ static int lpc17_busfault(int irq, FAR void *context, FAR void *arg) return 0; } -static int lpc17_usagefault(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received\n"); @@ -174,7 +174,7 @@ static int lpc17_usagefault(int irq, FAR void *context, FAR void *arg) return 0; } -static int lpc17_pendsv(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -182,7 +182,7 @@ static int lpc17_pendsv(int irq, FAR void *context, FAR void *arg) return 0; } -static int lpc17_dbgmonitor(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -190,7 +190,7 @@ static int lpc17_dbgmonitor(int irq, FAR void *context, FAR void *arg) return 0; } -static int lpc17_reserved(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -200,7 +200,7 @@ static int lpc17_reserved(int irq, FAR void *context, FAR void *arg) #endif /**************************************************************************** - * Name: lpc17_prioritize_syscall + * Name: lpc17_40_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -209,7 +209,7 @@ static int lpc17_reserved(int irq, FAR void *context, FAR void *arg) ****************************************************************************/ #ifdef CONFIG_ARMV7M_USEBASEPRI -static inline void lpc17_prioritize_syscall(int priority) +static inline void lpc17_40_prioritize_syscall(int priority) { uint32_t regval; @@ -223,7 +223,7 @@ static inline void lpc17_prioritize_syscall(int priority) #endif /**************************************************************************** - * Name: lpc17_irqinfo + * Name: lpc17_40_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -231,24 +231,24 @@ static inline void lpc17_prioritize_syscall(int priority) * ****************************************************************************/ -static int lpc17_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int lpc17_40_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { - DEBUGASSERT(irq >= LPC17_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= LPC17_40_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= LPC17_IRQ_EXTINT) + if (irq >= LPC17_40_IRQ_EXTINT) { - if (irq < (LPC17_IRQ_EXTINT+32)) + if (irq < (LPC17_40_IRQ_EXTINT+32)) { *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << (irq - LPC17_IRQ_EXTINT); + *bit = 1 << (irq - LPC17_40_IRQ_EXTINT); } - else if (irq < LPC17_IRQ_NIRQS) + else if (irq < LPC17_40_IRQ_NIRQS) { *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - LPC17_IRQ_EXTINT - 32); + *bit = 1 << (irq - LPC17_40_IRQ_EXTINT - 32); } else { @@ -261,19 +261,19 @@ static int lpc17_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == LPC17_IRQ_MEMFAULT) + if (irq == LPC17_40_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == LPC17_IRQ_BUSFAULT) + else if (irq == LPC17_40_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == LPC17_IRQ_USAGEFAULT) + else if (irq == LPC17_40_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == LPC17_IRQ_SYSTICK) + else if (irq == LPC17_40_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -372,16 +372,16 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(LPC17_IRQ_SVCALL, up_svcall, NULL); - irq_attach(LPC17_IRQ_HARDFAULT, up_hardfault, NULL); + irq_attach(LPC17_40_IRQ_SVCALL, up_svcall, NULL); + irq_attach(LPC17_40_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(LPC17_40_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - lpc17_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + lpc17_40_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -389,32 +389,32 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(LPC17_IRQ_MEMFAULT, up_memfault, NULL); - up_enable_irq(LPC17_IRQ_MEMFAULT); + irq_attach(LPC17_40_IRQ_MEMFAULT, up_memfault, NULL); + up_enable_irq(LPC17_40_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(LPC17_IRQ_NMI, lpc17_nmi, NULL); + irq_attach(LPC17_40_IRQ_NMI, lpc17_40_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(LPC17_IRQ_MEMFAULT, up_memfault, NULL); + irq_attach(LPC17_40_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault, NULL); - irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault, NULL); - irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv, NULL); - irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor, NULL); - irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved, NULL); + irq_attach(LPC17_40_IRQ_BUSFAULT, lpc17_40_busfault, NULL); + irq_attach(LPC17_40_IRQ_USAGEFAULT, lpc17_40_usagefault, NULL); + irq_attach(LPC17_40_IRQ_PENDSV, lpc17_40_pendsv, NULL); + irq_attach(LPC17_40_IRQ_DBGMONITOR, lpc17_40_dbgmonitor, NULL); + irq_attach(LPC17_40_IRQ_RESERVED, lpc17_40_reserved, NULL); #endif - lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS); + lpc17_40_dumpnvic("initial", LPC17_40_IRQ_NIRQS); /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ -#ifdef CONFIG_LPC17_GPIOIRQ - lpc17_gpioirqinitialize(); +#ifdef CONFIG_LPC17_40_GPIOIRQ + lpc17_40_gpioirqinitialize(); #endif /* And finally, enable interrupts */ @@ -438,7 +438,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (lpc17_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (lpc17_40_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -446,7 +446,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= LPC17_IRQ_EXTINT) + if (irq >= LPC17_40_IRQ_EXTINT) { putreg32(bit, regaddr); } @@ -457,16 +457,16 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_LPC17_GPIOIRQ - else if (irq >= LPC17_VALID_FIRST0L) +#ifdef CONFIG_LPC17_40_GPIOIRQ + else if (irq >= LPC17_40_VALID_FIRST0L) { /* Maybe it is a (derived) GPIO IRQ */ - lpc17_gpioirqdisable(irq); + lpc17_40_gpioirqdisable(irq); } #endif - lpc17_dumpnvic("disable", irq); + lpc17_40_dumpnvic("disable", irq); } /**************************************************************************** @@ -483,7 +483,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (lpc17_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (lpc17_40_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -491,7 +491,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= LPC17_IRQ_EXTINT) + if (irq >= LPC17_40_IRQ_EXTINT) { putreg32(bit, regaddr); } @@ -502,16 +502,16 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_LPC17_GPIOIRQ - else if (irq >= LPC17_VALID_FIRST0L) +#ifdef CONFIG_LPC17_40_GPIOIRQ + else if (irq >= LPC17_40_VALID_FIRST0L) { /* Maybe it is a (derived) GPIO IRQ */ - lpc17_gpioirqenable(irq); + lpc17_40_gpioirqenable(irq); } #endif - lpc17_dumpnvic("enable", irq); + lpc17_40_dumpnvic("enable", irq); } /**************************************************************************** @@ -525,7 +525,7 @@ void up_enable_irq(int irq) void up_ack_irq(int irq) { #if 0 /* Does not appear to be necessary in most cases */ - lpc17_clrpend(irq); + lpc17_40_clrpend(irq); #endif } @@ -547,10 +547,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && + DEBUGASSERT(irq >= LPC17_40_IRQ_MEMFAULT && irq < LPC17_40_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < LPC17_IRQ_EXTINT) + if (irq < LPC17_40_IRQ_EXTINT) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -563,7 +563,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= LPC17_IRQ_EXTINT; + irq -= LPC17_40_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } @@ -573,7 +573,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - lpc17_dumpnvic("prioritize", irq); + lpc17_40_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c similarity index 68% rename from arch/arm/src/lpc17xx/lpc17_lcd.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c index 9894e05f6cb..1e9c9621299 100644 --- a/arch/arm/src/lpc17xx/lpc17_lcd.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src//lpc17xx/lpc17_lcd.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c * * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,50 +48,50 @@ #include #include "up_arch.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_lcd.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_lcd.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define LPC17_LCD_CLK_PER_LINE \ - (CONFIG_LPC17_LCD_HWIDTH + CONFIG_LPC17_LCD_HPULSE + \ - CONFIG_LPC17_LCD_HFRONTPORCH + CONFIG_LPC17_LCD_HBACKPORCH) -#define LPC17_LCD_LINES_PER_FRAME \ - (CONFIG_LPC17_LCD_VHEIGHT + CONFIG_LPC17_LCD_VPULSE + \ - CONFIG_LPC17_LCD_VFRONTPORCH + CONFIG_LPC17_LCD_VBACKPORCH) -#define LPC17_LCD_PIXEL_CLOCK \ - (LPC17_LCD_CLK_PER_LINE * LPC17_LCD_LINES_PER_FRAME * \ - CONFIG_LPC17_LCD_REFRESH_FREQ) +#define LPC17_40_LCD_CLK_PER_LINE \ + (CONFIG_LPC17_40_LCD_HWIDTH + CONFIG_LPC17_40_LCD_HPULSE + \ + CONFIG_LPC17_40_LCD_HFRONTPORCH + CONFIG_LPC17_40_LCD_HBACKPORCH) +#define LPC17_40_LCD_LINES_PER_FRAME \ + (CONFIG_LPC17_40_LCD_VHEIGHT + CONFIG_LPC17_40_LCD_VPULSE + \ + CONFIG_LPC17_40_LCD_VFRONTPORCH + CONFIG_LPC17_40_LCD_VBACKPORCH) +#define LPC17_40_LCD_PIXEL_CLOCK \ + (LPC17_40_LCD_CLK_PER_LINE * LPC17_40_LCD_LINES_PER_FRAME * \ + CONFIG_LPC17_40_LCD_REFRESH_FREQ) /* Framebuffer characteristics in bytes */ -#if defined(CONFIG_LPC17_LCD_BPP1) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 1 + 7) / 8) -#elif defined(CONFIG_LPC17_LCD_BPP2) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 2 + 7) / 8) -#elif defined(CONFIG_LPC17_LCD_BPP4) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 4 + 7) / 8) -#elif defined(CONFIG_LPC17_LCD_BPP8) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 8 + 7) / 8) -#elif defined(CONFIG_LPC17_LCD_BPP16) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 16 + 7) / 8) -#elif defined(CONFIG_LPC17_LCD_BPP24) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 32 + 7) / 8) -#elif defined(CONFIG_LPC17_LCD_BPP16_565) -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 16 + 7) / 8) -#else /* defined(CONFIG_LPC17_LCD_BPP12_444) */ -# define LPC17_STRIDE ((CONFIG_LPC17_LCD_HWIDTH * 16 + 7) / 8) +#if defined(CONFIG_LPC17_40_LCD_BPP1) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 1 + 7) / 8) +#elif defined(CONFIG_LPC17_40_LCD_BPP2) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 2 + 7) / 8) +#elif defined(CONFIG_LPC17_40_LCD_BPP4) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 4 + 7) / 8) +#elif defined(CONFIG_LPC17_40_LCD_BPP8) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 8 + 7) / 8) +#elif defined(CONFIG_LPC17_40_LCD_BPP16) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 16 + 7) / 8) +#elif defined(CONFIG_LPC17_40_LCD_BPP24) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 32 + 7) / 8) +#elif defined(CONFIG_LPC17_40_LCD_BPP16_565) +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 16 + 7) / 8) +#else /* defined(CONFIG_LPC17_40_LCD_BPP12_444) */ +# define LPC17_40_STRIDE ((CONFIG_LPC17_40_LCD_HWIDTH * 16 + 7) / 8) #endif -#define LPC17_FBSIZE (LPC17_STRIDE * CONFIG_LPC17_LCD_VHEIGHT) +#define LPC17_40_FBSIZE (LPC17_40_STRIDE * CONFIG_LPC17_40_LCD_VHEIGHT) /* Delays */ -#define LPC17_LCD_PWRDIS_DELAY 10000 -#define LPC17_LCD_PWREN_DELAY 10000 +#define LPC17_40_LCD_PWRDIS_DELAY 10000 +#define LPC17_40_LCD_PWREN_DELAY 10000 /**************************************************************************** * Private Types @@ -105,9 +105,9 @@ * configuration of each color plane. */ -static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable, +static int lpc17_40_getvideoinfo(FAR struct fb_vtable_s *vtable, FAR struct fb_videoinfo_s *vinfo); -static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, +static int lpc17_40_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, FAR struct fb_planeinfo_s *pinfo); /* The following is provided only if the video hardware supports RGB color @@ -115,9 +115,9 @@ static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, */ #ifdef CONFIG_FB_CMAP -static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, +static int lpc17_40_getcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap); -static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, +static int lpc17_40_putcmap(FAR struct fb_vtable_s *vtable, FAR const struct fb_cmap_s *cmap); #endif @@ -126,9 +126,9 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, */ #ifdef CONFIG_FB_HWCURSOR -static int lpc17_getcursor(FAR struct fb_vtable_s *vtable, +static int lpc17_40_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursorattrib_s *attrib); -static int lpc17_setcursor(FAR struct fb_vtable_s *vtable, +static int lpc17_40_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcursor_s *settings); #endif @@ -140,9 +140,9 @@ static int lpc17_setcursor(FAR struct fb_vtable_s *vtable, static const struct fb_videoinfo_s g_videoinfo = { - .fmt = LPC17_COLOR_FMT, - .xres = CONFIG_LPC17_LCD_HWIDTH, - .yres = CONFIG_LPC17_LCD_VHEIGHT, + .fmt = LPC17_40_COLOR_FMT, + .xres = CONFIG_LPC17_40_LCD_HWIDTH, + .yres = CONFIG_LPC17_40_LCD_VHEIGHT, .nplanes = 1, }; @@ -150,11 +150,11 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct fb_planeinfo_s g_planeinfo = { - .fbmem = (FAR void *)CONFIG_LPC17_LCD_VRAMBASE, - .fblen = LPC17_FBSIZE, - .stride = LPC17_STRIDE, + .fbmem = (FAR void *)CONFIG_LPC17_40_LCD_VRAMBASE, + .fblen = LPC17_40_FBSIZE, + .stride = LPC17_40_STRIDE, .display = 0, - .bpp = LPC17_BPP, + .bpp = LPC17_40_BPP, }; /* Current cursor position */ @@ -175,15 +175,15 @@ static struct fb_cursorsize_s g_csize; struct fb_vtable_s g_fbobject = { - .getvideoinfo = lpc17_getvideoinfo, - .getplaneinfo = lpc17_getplaneinfo, + .getvideoinfo = lpc17_40_getvideoinfo, + .getplaneinfo = lpc17_40_getplaneinfo, #ifdef CONFIG_FB_CMAP - .getcmap = lpc17_getcmap, - .putcmap = lpc17_putcmap, + .getcmap = lpc17_40_getcmap, + .putcmap = lpc17_40_putcmap, #endif #ifdef CONFIG_FB_HWCURSOR - .getcursor = lpc17_getcursor, - .setcursor = lpc17_setcursor, + .getcursor = lpc17_40_getcursor, + .setcursor = lpc17_40_setcursor, #endif }; @@ -196,10 +196,10 @@ struct fb_vtable_s g_fbobject = ****************************************************************************/ /**************************************************************************** - * Name: lpc17_getvideoinfo + * Name: lpc17_40_getvideoinfo ****************************************************************************/ -static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable, +static int lpc17_40_getvideoinfo(FAR struct fb_vtable_s *vtable, FAR struct fb_videoinfo_s *vinfo) { lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); @@ -214,10 +214,10 @@ static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable, } /**************************************************************************** - * Name: lpc17_getplaneinfo + * Name: lpc17_40_getplaneinfo ****************************************************************************/ -static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, +static int lpc17_40_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, FAR struct fb_planeinfo_s *pinfo) { lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); @@ -232,11 +232,11 @@ static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, } /**************************************************************************** - * Name: lpc17_getcmap + * Name: lpc17_40_getcmap ****************************************************************************/ #ifdef CONFIG_FB_CMAP -static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, +static int lpc17_40_getcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap) { uint32_t *pal; @@ -250,7 +250,7 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, DEBUGASSERT(vtable && cmap && cmap->first < 256 && (cmap->first + cmap->len) < 256); - pal = (uint32_t *)LPC17_LCD_PAL(cmap->first >> 1); + pal = (uint32_t *)LPC17_40_LCD_PAL(cmap->first >> 1); last = cmap->first + cmap->len; /* Handle the case where the first color starts on an odd boundary */ @@ -306,11 +306,11 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, #endif /**************************************************************************** - * Name: lpc17_putcmap + * Name: lpc17_40_putcmap ****************************************************************************/ #ifdef CONFIG_FB_CMAP -static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, +static int lpc17_40_putcmap(FAR struct fb_vtable_s *vtable, FAR const struct fb_cmap_s *cmap) { uint32_t *pal; @@ -324,7 +324,7 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, DEBUGASSERT(vtable && cmap); - pal = (uint32_t *)LPC17_LCD_PAL(cmap->first >> 1); + pal = (uint32_t *)LPC17_40_LCD_PAL(cmap->first >> 1); last = cmap->first + cmap->len; /* Handle the case where the first color starts on an odd boundary */ @@ -376,26 +376,26 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, #endif /**************************************************************************** - * Name: lpc17_getcursor + * Name: lpc17_40_getcursor ****************************************************************************/ #ifdef CONFIG_FB_HWCURSOR -static int lpc17_getcursor(FAR struct fb_vtable_s *vtable, +static int lpc17_40_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursorattrib_s *attrib) { lcdinfo("vtable=%p attrib=%p\n", vtable, attrib); if (vtable && attrib) { #ifdef CONFIG_FB_HWCURSORIMAGE - attrib->fmt = LPC17_COLOR_FMT; + attrib->fmt = LPC17_40_COLOR_FMT; #endif lcdinfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y); attrib->pos = g_cpos; #ifdef CONFIG_FB_HWCURSORSIZE - attrib->mxsize.h = CONFIG_LPC17_LCD_VHEIGHT; - attrib->mxsize.w = CONFIG_LPC17_LCD_HWIDTH; + attrib->mxsize.h = CONFIG_LPC17_40_LCD_VHEIGHT; + attrib->mxsize.w = CONFIG_LPC17_40_LCD_HWIDTH; lcdinfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w); attrib->size = g_csize; @@ -409,11 +409,11 @@ static int lpc17_getcursor(FAR struct fb_vtable_s *vtable, #endif /**************************************************************************** - * Name: lpc17_setcursor + * Name: lpc17_40_setcursor ****************************************************************************/ #ifdef CONFIG_FB_HWCURSOR -static int lpc17_setcursor(FAR struct fb_vtable_s *vtable, +static int lpc17_40_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcursor_s *settings) { lcdinfo("vtable=%p settings=%p\n", vtable, settings); @@ -480,7 +480,7 @@ int up_fbinitialize(int display) regval = ((SYSCON_MATRIXARB_PRI_ICODE(SYSCON_MATRIXARB_PRI_LOW)) | (SYSCON_MATRIXARB_PRI_DCODE(SYSCON_MATRIXARB_PRI_HIGHEST)) | (SYSCON_MATRIXARB_PRI_LCD(SYSCON_MATRIXARB_PRI_HIGHEST))); - putreg32(regval, LPC17_SYSCON_MATRIXARB); + putreg32(regval, LPC17_40_SYSCON_MATRIXARB); /* Configure pins */ /* Video data: @@ -490,94 +490,94 @@ int up_fbinitialize(int display) lcdinfo("Configuring pins\n"); - lpc17_configgpio(GPIO_LCD_VD0); - lpc17_configgpio(GPIO_LCD_VD1); - lpc17_configgpio(GPIO_LCD_VD2); - lpc17_configgpio(GPIO_LCD_VD3); - lpc17_configgpio(GPIO_LCD_VD4); - lpc17_configgpio(GPIO_LCD_VD5); - lpc17_configgpio(GPIO_LCD_VD6); - lpc17_configgpio(GPIO_LCD_VD7); + lpc17_40_configgpio(GPIO_LCD_VD0); + lpc17_40_configgpio(GPIO_LCD_VD1); + lpc17_40_configgpio(GPIO_LCD_VD2); + lpc17_40_configgpio(GPIO_LCD_VD3); + lpc17_40_configgpio(GPIO_LCD_VD4); + lpc17_40_configgpio(GPIO_LCD_VD5); + lpc17_40_configgpio(GPIO_LCD_VD6); + lpc17_40_configgpio(GPIO_LCD_VD7); - lpc17_configgpio(GPIO_LCD_VD8); - lpc17_configgpio(GPIO_LCD_VD9); - lpc17_configgpio(GPIO_LCD_VD10); - lpc17_configgpio(GPIO_LCD_VD11); - lpc17_configgpio(GPIO_LCD_VD12); - lpc17_configgpio(GPIO_LCD_VD13); - lpc17_configgpio(GPIO_LCD_VD14); - lpc17_configgpio(GPIO_LCD_VD15); + lpc17_40_configgpio(GPIO_LCD_VD8); + lpc17_40_configgpio(GPIO_LCD_VD9); + lpc17_40_configgpio(GPIO_LCD_VD10); + lpc17_40_configgpio(GPIO_LCD_VD11); + lpc17_40_configgpio(GPIO_LCD_VD12); + lpc17_40_configgpio(GPIO_LCD_VD13); + lpc17_40_configgpio(GPIO_LCD_VD14); + lpc17_40_configgpio(GPIO_LCD_VD15); -#if LPC17_BPP > 16 - lpc17_configgpio(GPIO_LCD_VD16); - lpc17_configgpio(GPIO_LCD_VD17); - lpc17_configgpio(GPIO_LCD_VD18); - lpc17_configgpio(GPIO_LCD_VD19); - lpc17_configgpio(GPIO_LCD_VD20); - lpc17_configgpio(GPIO_LCD_VD21); - lpc17_configgpio(GPIO_LCD_VD22); - lpc17_configgpio(GPIO_LCD_VD23); +#if LPC17_40_BPP > 16 + lpc17_40_configgpio(GPIO_LCD_VD16); + lpc17_40_configgpio(GPIO_LCD_VD17); + lpc17_40_configgpio(GPIO_LCD_VD18); + lpc17_40_configgpio(GPIO_LCD_VD19); + lpc17_40_configgpio(GPIO_LCD_VD20); + lpc17_40_configgpio(GPIO_LCD_VD21); + lpc17_40_configgpio(GPIO_LCD_VD22); + lpc17_40_configgpio(GPIO_LCD_VD23); #endif /* Other pins */ - lpc17_configgpio(GPIO_LCD_DCLK); - lpc17_configgpio(GPIO_LCD_LP); - lpc17_configgpio(GPIO_LCD_FP); - lpc17_configgpio(GPIO_LCD_ENABM); - lpc17_configgpio(GPIO_LCD_PWR); + lpc17_40_configgpio(GPIO_LCD_DCLK); + lpc17_40_configgpio(GPIO_LCD_LP); + lpc17_40_configgpio(GPIO_LCD_FP); + lpc17_40_configgpio(GPIO_LCD_ENABM); + lpc17_40_configgpio(GPIO_LCD_PWR); /* Turn on LCD clock */ - modifyreg32(LPC17_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD); + modifyreg32(LPC17_40_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD); lcdinfo("Configuring the LCD controller\n"); /* Disable the cursor */ - regval = getreg32(LPC17_LCD_CRSR_CRTL); + regval = getreg32(LPC17_40_LCD_CRSR_CRTL); regval &= ~LCD_CRSR_CTRL_CRSON; - putreg32(regval, LPC17_LCD_CRSR_CRTL); + putreg32(regval, LPC17_40_LCD_CRSR_CRTL); /* Clear any pending interrupts */ - putreg32(LCD_INTCLR_ALL, LPC17_LCD_INTCLR); + putreg32(LCD_INTCLR_ALL, LPC17_40_LCD_INTCLR); /* Disable GLCD controller */ - putreg32(0, LPC17_LCD_CTRL); + putreg32(0, LPC17_40_LCD_CTRL); /* Initialize pixel clock (assuming clock source is the peripheral clock) */ - putreg32(((uint32_t)BOARD_PCLK_FREQUENCY / (uint32_t)LPC17_LCD_PIXEL_CLOCK)+1, - LPC17_SYSCON_LCDCFG); + putreg32(((uint32_t)BOARD_PCLK_FREQUENCY / (uint32_t)LPC17_40_LCD_PIXEL_CLOCK)+1, + LPC17_40_SYSCON_LCDCFG); /* Set the bits per pixel */ - regval = getreg32(LPC17_LCD_CTRL); + regval = getreg32(LPC17_40_LCD_CTRL); regval &= ~LCD_CTRL_LCDBPP_MASK; -#if defined(CONFIG_LPC17_LCD_BPP1) +#if defined(CONFIG_LPC17_40_LCD_BPP1) regval |= LCD_CTRL_LCDBPP_1; /* 1 bpp */ -#elif defined(CONFIG_LPC17_LCD_BPP2) +#elif defined(CONFIG_LPC17_40_LCD_BPP2) regval |= LCD_CTRL_LCDBPP_2; /* 2 bpp */ -#elif defined(CONFIG_LPC17_LCD_BPP4) +#elif defined(CONFIG_LPC17_40_LCD_BPP4) regval |= LCD_CTRL_LCDBPP_4; /* 4 bpp */ -#elif defined(CONFIG_LPC17_LCD_BPP8) +#elif defined(CONFIG_LPC17_40_LCD_BPP8) regval |= LCD_CTRL_LCDBPP_8; /* 8 bpp */ -#elif defined(CONFIG_LPC17_LCD_BPP16) +#elif defined(CONFIG_LPC17_40_LCD_BPP16) regval |= LCD_CTRL_LCDBPP_16; /* 16 bpp */ -#elif defined(CONFIG_LPC17_LCD_BPP24) +#elif defined(CONFIG_LPC17_40_LCD_BPP24) regval |= LCD_CTRL_LCDBPP_24; /* 24-bit TFT panel only */ -#elif defined(CONFIG_LPC17_LCD_BPP16_565) +#elif defined(CONFIG_LPC17_40_LCD_BPP16_565) regval |= LCD_CTRL_LCDBPP_565; /* 16 bpp, 5:6:5 mode */ -#else /* defined(CONFIG_LPC17_LCD_BPP12_444) */ +#else /* defined(CONFIG_LPC17_40_LCD_BPP12_444) */ regval |= LCD_CTRL_LCDBPP_444; /* 12 bpp, 4:4:4 mode */ #endif /* TFT panel */ -#ifdef CONFIG_LPC17_LCD_TFTPANEL +#ifdef CONFIG_LPC17_40_LCD_TFTPANEL regval |= LCD_CTRL_LCDTFT; #endif @@ -591,14 +591,14 @@ int up_fbinitialize(int display) /* Select monochrome or color LCD */ -#ifdef CONFIG_LPC17_LCD_MONOCHROME +#ifdef CONFIG_LPC17_40_LCD_MONOCHROME /* Select monochrome LCD */ regval &= ~LCD_CTRL_BGR; /* Select 4- or 8-bit monochrome interface */ -# if LPC17_BPP > 4 +# if LPC17_40_BPP > 4 regval |= LCD_CTRL_LCDMONO8; # else regval &= ~LCD_CTRL_LCDMONO8; @@ -609,7 +609,7 @@ int up_fbinitialize(int display) regval &= ~(LCD_CTRL_LCDBW | LCD_CTRL_LCDMONO8); -#endif /* CONFIG_LPC17_LCD_MONOCHROME */ +#endif /* CONFIG_LPC17_40_LCD_MONOCHROME */ /* Little endian byte order */ @@ -618,31 +618,31 @@ int up_fbinitialize(int display) /* Little endian pixel order */ regval &= ~LCD_CTRL_BEPO; - putreg32(regval, LPC17_LCD_CTRL); + putreg32(regval, LPC17_40_LCD_CTRL); /* Initialize horizontal timing */ - putreg32(0, LPC17_LCD_TIMH); + putreg32(0, LPC17_40_LCD_TIMH); - regval = (((CONFIG_LPC17_LCD_HWIDTH/16) - 1) << LCD_TIMH_PPL_SHIFT | - (CONFIG_LPC17_LCD_HPULSE - 1) << LCD_TIMH_HSW_SHIFT | - (CONFIG_LPC17_LCD_HFRONTPORCH - 1) << LCD_TIMH_HFP_SHIFT | - (CONFIG_LPC17_LCD_HBACKPORCH - 1) << LCD_TIMH_HBP_SHIFT); - putreg32(regval, LPC17_LCD_TIMH); + regval = (((CONFIG_LPC17_40_LCD_HWIDTH/16) - 1) << LCD_TIMH_PPL_SHIFT | + (CONFIG_LPC17_40_LCD_HPULSE - 1) << LCD_TIMH_HSW_SHIFT | + (CONFIG_LPC17_40_LCD_HFRONTPORCH - 1) << LCD_TIMH_HFP_SHIFT | + (CONFIG_LPC17_40_LCD_HBACKPORCH - 1) << LCD_TIMH_HBP_SHIFT); + putreg32(regval, LPC17_40_LCD_TIMH); /* Initialize vertical timing */ - putreg32(0, LPC17_LCD_TIMV); + putreg32(0, LPC17_40_LCD_TIMV); - regval = ((CONFIG_LPC17_LCD_VHEIGHT - 1) << LCD_TIMV_LPP_SHIFT | - (CONFIG_LPC17_LCD_VPULSE - 1) << LCD_TIMV_VSW_SHIFT | - (CONFIG_LPC17_LCD_VFRONTPORCH) << LCD_TIMV_VFP_SHIFT | - (CONFIG_LPC17_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT); - putreg32(regval, LPC17_LCD_TIMV); + regval = ((CONFIG_LPC17_40_LCD_VHEIGHT - 1) << LCD_TIMV_LPP_SHIFT | + (CONFIG_LPC17_40_LCD_VPULSE - 1) << LCD_TIMV_VSW_SHIFT | + (CONFIG_LPC17_40_LCD_VFRONTPORCH) << LCD_TIMV_VFP_SHIFT | + (CONFIG_LPC17_40_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT); + putreg32(regval, LPC17_40_LCD_TIMV); /* Initialize clock and signal polarity */ - regval = getreg32(LPC17_LCD_POL); + regval = getreg32(LPC17_40_LCD_POL); /* LCDFP pin is active LOW and inactive HIGH */ @@ -658,7 +658,7 @@ int up_fbinitialize(int display) /* Set number of clocks per line */ - regval |= ((CONFIG_LPC17_LCD_HWIDTH-1) << LCD_POL_CPL_SHIFT); + regval |= ((CONFIG_LPC17_40_LCD_HWIDTH-1) << LCD_POL_CPL_SHIFT); /* Bypass internal pixel clock divider */ @@ -671,41 +671,41 @@ int up_fbinitialize(int display) /* Select CCLK for the LCD block clock source */ regval &= ~LCD_POL_CLKSEL; - putreg32(regval, LPC17_LCD_POL); + putreg32(regval, LPC17_40_LCD_POL); /* Frame base address doubleword aligned */ - putreg32(CONFIG_LPC17_LCD_VRAMBASE & ~7, LPC17_LCD_UPBASE); - putreg32(CONFIG_LPC17_LCD_VRAMBASE & ~7, LPC17_LCD_LPBASE); + putreg32(CONFIG_LPC17_40_LCD_VRAMBASE & ~7, LPC17_40_LCD_UPBASE); + putreg32(CONFIG_LPC17_40_LCD_VRAMBASE & ~7, LPC17_40_LCD_LPBASE); /* Clear the display */ - lpc17_lcdclear(CONFIG_LPC17_LCD_BACKCOLOR); + lpc17_40_lcdclear(CONFIG_LPC17_40_LCD_BACKCOLOR); -#ifdef CONFIG_LPC17_LCD_BACKLIGHT +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT /* Turn on the back light */ - lpc17_backlight(true); + lpc17_40_backlight(true); #endif - putreg32(0, LPC17_LCD_INTMSK); + putreg32(0, LPC17_40_LCD_INTMSK); lcdinfo("Enabling the display\n"); - for (i = LPC17_LCD_PWREN_DELAY; i; i--); + for (i = LPC17_40_LCD_PWREN_DELAY; i; i--); /* Enable LCD */ - regval = getreg32(LPC17_LCD_CTRL); + regval = getreg32(LPC17_40_LCD_CTRL); regval |= LCD_CTRL_LCDEN; - putreg32(regval, LPC17_LCD_CTRL); + putreg32(regval, LPC17_40_LCD_CTRL); /* Enable LCD power */ - for (i = LPC17_LCD_PWREN_DELAY; i; i--); + for (i = LPC17_40_LCD_PWREN_DELAY; i; i--); - regval = getreg32(LPC17_LCD_CTRL); + regval = getreg32(LPC17_40_LCD_CTRL); regval |= LCD_CTRL_LCDPWR; - putreg32(regval, LPC17_LCD_CTRL); + putreg32(regval, LPC17_40_LCD_CTRL); return OK; } @@ -765,58 +765,58 @@ void up_fbuninitialize(int display) * worry about mutually exclusive access to the LCD hardware. */ -#ifdef CONFIG_LPC17_LCD_BACKLIGHT +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT /* Turn off the back light */ - lpc17_backlight(false); + lpc17_40_backlight(false); #endif /* Disable the LCD controller */ - regval = getreg32(LPC17_LCD_CTRL); + regval = getreg32(LPC17_40_LCD_CTRL); regval &= ~LCD_CTRL_LCDPWR; - putreg32(regval, LPC17_LCD_CTRL); + putreg32(regval, LPC17_40_LCD_CTRL); - for (i = LPC17_LCD_PWRDIS_DELAY; i; i--); + for (i = LPC17_40_LCD_PWRDIS_DELAY; i; i--); regval &= ~LCD_CTRL_LCDEN; - putreg32(regval, LPC17_LCD_CTRL); + putreg32(regval, LPC17_40_LCD_CTRL); /* Turn off clocking to the LCD. modifyreg32() can do this atomically. */ - modifyreg32(LPC17_SYSCON_PCONP, SYSCON_PCONP_PCLCD, 0); + modifyreg32(LPC17_40_SYSCON_PCONP, SYSCON_PCONP_PCLCD, 0); } /************************************************************************************ - * Name: lpc17_lcdclear + * Name: lpc17_40_lcdclear * * Description: - * This is a non-standard LCD interface just for the LPC17xx. Clearing the display + * This is a non-standard LCD interface just for the LPC17xx/LPC40xx. Clearing the display * in the normal way by writing a sequences of runs that covers the entire display * can be slow. Here the display is cleared by simply setting all VRAM memory to * the specified color. * ************************************************************************************/ -void lpc17_lcdclear(nxgl_mxpixel_t color) +void lpc17_40_lcdclear(nxgl_mxpixel_t color) { int i; -#if LPC17_BPP > 16 - uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE; +#if LPC17_40_BPP > 16 + uint32_t *dest = (uint32_t *)CONFIG_LPC17_40_LCD_VRAMBASE; lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", - color, CONFIG_LPC17_LCD_VRAMBASE, - CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t)); + color, CONFIG_LPC17_40_LCD_VRAMBASE, + CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT * sizeof(uint32_t)); #else - uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE; + uint16_t *dest = (uint16_t *)CONFIG_LPC17_40_LCD_VRAMBASE; lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", - color, CONFIG_LPC17_LCD_VRAMBASE, - CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t)); + color, CONFIG_LPC17_40_LCD_VRAMBASE, + CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT * sizeof(uint16_t)); #endif - for (i = 0; i < (CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT); i++) + for (i = 0; i < (CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT); i++) { *dest++ = color; } diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.h similarity index 56% rename from arch/arm/src/lpc17xx/lpc17_lcd.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.h index 103cf81bca1..9fb70859943 100644 --- a/arch/arm/src/lpc17xx/lpc17_lcd.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_lcd.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_LCD_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_LCD_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_LCD_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_LCD_H /************************************************************************************ * Included Files @@ -46,7 +46,7 @@ #include -#include "hardware/lpc17_lcd.h" +#include "hardware/lpc17_40_lcd.h" /************************************************************************************ * Pre-processor Definitions @@ -55,100 +55,100 @@ /* Base address of the video RAM frame buffer */ -#ifndef CONFIG_LPC17_LCD_VRAMBASE -# define CONFIG_LPC17_LCD_VRAMBASE ((uint32_t)LPC17_EXTDRAM_CS0 + 0x00010000) +#ifndef CONFIG_LPC17_40_LCD_VRAMBASE +# define CONFIG_LPC17_40_LCD_VRAMBASE ((uint32_t)LPC17_40_EXTDRAM_CS0 + 0x00010000) #endif /* LCD refresh rate */ -#ifndef CONFIG_LPC17_LCD_REFRESH_FREQ -# define CONFIG_LPC17_LCD_REFRESH_FREQ (50) /* Hz */ +#ifndef CONFIG_LPC17_40_LCD_REFRESH_FREQ +# define CONFIG_LPC17_40_LCD_REFRESH_FREQ (50) /* Hz */ #endif /* Bits per pixel / color format */ -#undef LPC17_COLOR_FMT -#if defined(CONFIG_LPC17_LCD_BPP1) -# define LPC17_BPP 1 -# define LPC17_COLOR_FMT FB_FMT_Y1 -#elif defined(CONFIG_LPC17_LCD_BPP2) -# define LPC17_BPP 2 -# define LPC17_COLOR_FMT FB_FMT_Y2 -#elif defined(CONFIG_LPC17_LCD_BPP4) -# define LPC17_BPP 4 -# define LPC17_COLOR_FMT FB_FMT_Y4 -#elif defined(CONFIG_LPC17_LCD_BPP8) -# define LPC17_BPP 8 -# define LPC17_COLOR_FMT FB_FMT_Y8 -#elif defined(CONFIG_LPC17_LCD_BPP16) -# define LPC17_BPP 16 -# define LPC17_COLOR_FMT FB_FMT_Y16 -#elif defined(CONFIG_LPC17_LCD_BPP24) -# define LPC17_BPP 32 /* Only 24 of 32 bits used for RGB */ -# define LPC17_COLOR_FMT FB_FMT_RGB24 -# ifndef CONFIG_LPC17_LCD_TFTPANEL +#undef LPC17_40_COLOR_FMT +#if defined(CONFIG_LPC17_40_LCD_BPP1) +# define LPC17_40_BPP 1 +# define LPC17_40_COLOR_FMT FB_FMT_Y1 +#elif defined(CONFIG_LPC17_40_LCD_BPP2) +# define LPC17_40_BPP 2 +# define LPC17_40_COLOR_FMT FB_FMT_Y2 +#elif defined(CONFIG_LPC17_40_LCD_BPP4) +# define LPC17_40_BPP 4 +# define LPC17_40_COLOR_FMT FB_FMT_Y4 +#elif defined(CONFIG_LPC17_40_LCD_BPP8) +# define LPC17_40_BPP 8 +# define LPC17_40_COLOR_FMT FB_FMT_Y8 +#elif defined(CONFIG_LPC17_40_LCD_BPP16) +# define LPC17_40_BPP 16 +# define LPC17_40_COLOR_FMT FB_FMT_Y16 +#elif defined(CONFIG_LPC17_40_LCD_BPP24) +# define LPC17_40_BPP 32 /* Only 24 of 32 bits used for RGB */ +# define LPC17_40_COLOR_FMT FB_FMT_RGB24 +# ifndef CONFIG_LPC17_40_LCD_TFTPANEL # error "24 BPP is only available for a TFT panel" # endif -#elif defined(CONFIG_LPC17_LCD_BPP16_565) -# define LPC17_BPP 16 -# define LPC17_COLOR_FMT FB_FMT_RGB16_565 -#elif defined(CONFIG_LPC17_LCD_BPP12_444) -# define LPC17_BPP 1 2 -# define LPC17_COLOR_FMT FB_FMT_RGB12_444 +#elif defined(CONFIG_LPC17_40_LCD_BPP16_565) +# define LPC17_40_BPP 16 +# define LPC17_40_COLOR_FMT FB_FMT_RGB16_565 +#elif defined(CONFIG_LPC17_40_LCD_BPP12_444) +# define LPC17_40_BPP 1 2 +# define LPC17_40_COLOR_FMT FB_FMT_RGB12_444 #else -# ifndef CONFIG_LPC17_LCD_TFTPANEL +# ifndef CONFIG_LPC17_40_LCD_TFTPANEL # warning "Assuming 24 BPP" -# define LPC17_BPP 24 -# define CONFIG_LPC17_LCD_BPP24 1 -# define LPC17_COLOR_FMT FB_FMT_RGB24 +# define LPC17_40_BPP 24 +# define CONFIG_LPC17_40_LCD_BPP24 1 +# define LPC17_40_COLOR_FMT FB_FMT_RGB24 # else # warning "Assuming 16 BPP 5:6:5" -# define LPC17_BPP 16 -# define CONFIG_LPC17_LCD_BPP16_565 1 -# define LPC17_COLOR_FMT FB_FMT_RGB16_565 +# define LPC17_40_BPP 16 +# define CONFIG_LPC17_40_LCD_BPP16_565 1 +# define LPC17_40_COLOR_FMT FB_FMT_RGB16_565 # endif #endif /* Background color */ -#ifndef CONFIG_LPC17_LCD_BACKCOLOR -# define CONFIG_LPC17_LCD_BACKCOLOR 0 /* Initial background color */ +#ifndef CONFIG_LPC17_40_LCD_BACKCOLOR +# define CONFIG_LPC17_40_LCD_BACKCOLOR 0 /* Initial background color */ #endif /* Horizontal video characteristics */ -#ifndef CONFIG_LPC17_LCD_HWIDTH -# define CONFIG_LPC17_LCD_HWIDTH 480 /* Width in pixels */ +#ifndef CONFIG_LPC17_40_LCD_HWIDTH +# define CONFIG_LPC17_40_LCD_HWIDTH 480 /* Width in pixels */ #endif -#ifndef CONFIG_LPC17_LCD_HPULSE -# define CONFIG_LPC17_LCD_HPULSE 2 +#ifndef CONFIG_LPC17_40_LCD_HPULSE +# define CONFIG_LPC17_40_LCD_HPULSE 2 #endif -#ifndef CONFIG_LPC17_LCD_HFRONTPORCH -# define CONFIG_LPC17_LCD_HFRONTPORCH 5 +#ifndef CONFIG_LPC17_40_LCD_HFRONTPORCH +# define CONFIG_LPC17_40_LCD_HFRONTPORCH 5 #endif -#ifndef CONFIG_LPC17_LCD_HBACKPORCH -# define CONFIG_LPC17_LCD_HBACKPORCH 40 +#ifndef CONFIG_LPC17_40_LCD_HBACKPORCH +# define CONFIG_LPC17_40_LCD_HBACKPORCH 40 #endif /* Vertical video characteristics */ -#ifndef CONFIG_LPC17_LCD_VHEIGHT -# define CONFIG_LPC17_LCD_VHEIGHT 272 /* Height in rows */ +#ifndef CONFIG_LPC17_40_LCD_VHEIGHT +# define CONFIG_LPC17_40_LCD_VHEIGHT 272 /* Height in rows */ #endif -#ifndef CONFIG_LPC17_LCD_VPULSE -# define CONFIG_LPC17_LCD_VPULSE 2 +#ifndef CONFIG_LPC17_40_LCD_VPULSE +# define CONFIG_LPC17_40_LCD_VPULSE 2 #endif -#ifndef CONFIG_LPC17_LCD_VFRONTPORCH -# define CONFIG_LPC17_LCD_VFRONTPORCH 8 +#ifndef CONFIG_LPC17_40_LCD_VFRONTPORCH +# define CONFIG_LPC17_40_LCD_VFRONTPORCH 8 #endif -#ifndef CONFIG_LPC17_LCD_VBACKPORCH -# define CONFIG_LPC17_LCD_VBACKPORCH 8 +#ifndef CONFIG_LPC17_40_LCD_VBACKPORCH +# define CONFIG_LPC17_40_LCD_VBACKPORCH 8 #endif /************************************************************************************ @@ -167,29 +167,29 @@ */ /************************************************************************************ - * Name: lpc17_lcdclear + * Name: lpc17_40_lcdclear * * Description: - * This is a non-standard LCD interface just for the LPC17xx. Clearing the display + * This is a non-standard LCD interface just for the LPC17xx/LPC40xx. Clearing the display * in the normal way by writing a sequences of runs that covers the entire display * can be slow. Here the dispaly is cleared by simply setting all VRAM memory to * the specified color. * ************************************************************************************/ -void lpc17_lcdclear(nxgl_mxpixel_t color); +void lpc17_40_lcdclear(nxgl_mxpixel_t color); /************************************************************************************ - * Name: lpc17_backlight + * Name: lpc17_40_backlight * * Description: - * If CONFIG_LPC17_LCD_BACKLIGHT is defined, then the board-specific logic must + * If CONFIG_LPC17_40_LCD_BACKLIGHT is defined, then the board-specific logic must * provide this interface to turn the backlight on and off. * ************************************************************************************/ -#ifdef CONFIG_LPC17_LCD_BACKLIGHT -void lpc17_backlight(bool blon); +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT +void lpc17_40_backlight(bool blon); #endif -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_LCD_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_LCD_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_lowputc.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c similarity index 83% rename from arch/arm/src/lpc17xx/lpc17_lowputc.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c index 218d1d62574..26915e5717e 100644 --- a/arch/arm/src/lpc17xx/lpc17_lowputc.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_lowputc.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c * * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,12 +47,12 @@ #include "up_internal.h" #include "up_arch.h" -#include "hardware/lpc17_syscon.h" -#include "hardware/lpc17_uart.h" +#include "hardware/lpc17_40_syscon.h" +#include "hardware/lpc17_40_uart.h" -#include "lpc17_gpio.h" -#include "lpc17_lowputc.h" -#include "lpc17_serial.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_lowputc.h" +#include "lpc17_40_serial.h" /**************************************************************************** * Pre-processor Definitions @@ -61,25 +61,25 @@ /* Select UART parameters for the selected console */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC17_UART0_BASE +# define CONSOLE_BASE LPC17_40_UART0_BASE # define CONSOLE_BAUD CONFIG_UART0_BAUD # define CONSOLE_BITS CONFIG_UART0_BITS # define CONSOLE_PARITY CONFIG_UART0_PARITY # define CONSOLE_2STOP CONFIG_UART0_2STOP #elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC17_UART1_BASE +# define CONSOLE_BASE LPC17_40_UART1_BASE # define CONSOLE_BAUD CONFIG_UART1_BAUD # define CONSOLE_BITS CONFIG_UART1_BITS # define CONSOLE_PARITY CONFIG_UART1_PARITY # define CONSOLE_2STOP CONFIG_UART1_2STOP #elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC17_UART2_BASE +# define CONSOLE_BASE LPC17_40_UART2_BASE # define CONSOLE_BAUD CONFIG_UART2_BAUD # define CONSOLE_BITS CONFIG_UART2_BITS # define CONSOLE_PARITY CONFIG_UART2_PARITY # define CONSOLE_2STOP CONFIG_UART2_2STOP #elif defined(CONFIG_UART3_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC17_UART3_BASE +# define CONSOLE_BASE LPC17_40_UART3_BASE # define CONSOLE_BAUD CONFIG_UART3_BAUD # define CONSOLE_BITS CONFIG_UART3_BITS # define CONSOLE_PARITY CONFIG_UART3_PARITY @@ -88,7 +88,7 @@ # if defined(HAVE_CONSOLE) # error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" # endif -# define CONSOLE_BASE LPC17_UART0_BASE +# define CONSOLE_BASE LPC17_40_UART0_BASE # define CONSOLE_BAUD 115200 # define CONSOLE_BITS 8 # define CONSOLE_PARITY 0 @@ -151,7 +151,7 @@ * * PCLK = CCLK / divisor * - * And for the LPC178x, the PCLK is determined by the global divisor setting in + * And for the LPC178x/40xx, the PCLK is determined by the global divisor setting in * the PLKSEL register. * * Ignoring the fractional divider for now. (If you want to extend this driver @@ -159,7 +159,7 @@ * the same peripheral and that logic could easily leveraged here). */ -#ifdef LPC178x +#ifdef LPC178x_40xx /* Use the global PCLK frequency */ # define CONSOLE_NUMERATOR BOARD_PCLK_FREQUENCY @@ -181,9 +181,9 @@ * BAUD <= CCLK / 16 / MinDL */ -# if CONSOLE_BAUD < (LPC17_CCLK / 16 / UART_MINDL) +# if CONSOLE_BAUD < (LPC17_40_CCLK / 16 / UART_MINDL) # define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK -# define CONSOLE_NUMERATOR (LPC17_CCLK) +# define CONSOLE_NUMERATOR (LPC17_40_CCLK) /* Check divisor == 2. This works if: * @@ -196,9 +196,9 @@ * BAUD <= CCLK / 8 / MinDL */ -# elif CONSOLE_BAUD < (LPC17_CCLK / 8 / UART_MINDL) +# elif CONSOLE_BAUD < (LPC17_40_CCLK / 8 / UART_MINDL) # define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2 -# define CONSOLE_NUMERATOR (LPC17_CCLK / 2) +# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 2) /* Check divisor == 4. This works if: * @@ -211,9 +211,9 @@ * BAUD <= CCLK / 4 / MinDL */ -# elif CONSOLE_BAUD < (LPC17_CCLK / 4 / UART_MINDL) +# elif CONSOLE_BAUD < (LPC17_40_CCLK / 4 / UART_MINDL) # define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4 -# define CONSOLE_NUMERATOR (LPC17_CCLK / 4) +# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 4) /* Check divisor == 8. This works if: * @@ -226,11 +226,11 @@ * BAUD <= CCLK / 2 / MinDL */ -# else /* if CONSOLE_BAUD < (LPC17_CCLK / 2 / UART_MINDL) */ +# else /* if CONSOLE_BAUD < (LPC17_40_CCLK / 2 / UART_MINDL) */ # define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8 -# define CONSOLE_NUMERATOR (LPC17_CCLK / 8) +# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 8) # endif -#endif /* LPC178x */ +#endif /* LPC178x_40xx */ /* Then this is the value to use for the DLM and DLL registers */ @@ -273,16 +273,16 @@ void up_lowputc(char ch) #if defined HAVE_UART && defined HAVE_CONSOLE /* Wait for the transmitter to be available */ - while ((getreg32(CONSOLE_BASE+LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) == 0); + while ((getreg32(CONSOLE_BASE+LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) == 0); /* Send the character */ - putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_UART_THR_OFFSET); + putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_40_UART_THR_OFFSET); #endif } /**************************************************************************** - * Name: lpc17_lowsetup + * Name: lpc17_40_lowsetup * * Description: * This performs basic initialization of the UART used for the serial @@ -311,7 +311,7 @@ void up_lowputc(char ch) * ****************************************************************************/ -void lpc17_lowsetup(void) +void lpc17_40_lowsetup(void) { #ifdef HAVE_UART uint32_t regval; @@ -320,7 +320,7 @@ void lpc17_lowsetup(void) * other UARTs */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval &= ~(SYSCON_PCONP_PCUART0 | SYSCON_PCONP_PCUART1 | SYSCON_PCONP_PCUART2 | SYSCON_PCONP_PCUART3); #if defined(CONFIG_UART0_SERIAL_CONSOLE) @@ -332,54 +332,54 @@ void lpc17_lowsetup(void) #elif defined(CONFIG_UART3_SERIAL_CONSOLE) regval |= SYSCON_PCONP_PCUART3; #endif - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Step 2: Enable peripheral clocking for the console UART and disable * clocking for all other UARTs */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~(SYSCON_PCLKSEL0_UART0_MASK | SYSCON_PCLKSEL0_UART1_MASK); #if defined(CONFIG_UART0_SERIAL_CONSOLE) regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART0_SHIFT); #elif defined(CONFIG_UART1_SERIAL_CONSOLE) regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART1_SHIFT); #endif - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~(SYSCON_PCLKSEL1_UART2_MASK | SYSCON_PCLKSEL1_UART3_MASK); #if defined(CONFIG_UART2_SERIAL_CONSOLE) regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART2_SHIFT); #elif defined(CONFIG_UART3_SERIAL_CONSOLE) regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART3_SHIFT); #endif - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); #endif /* Configure UART pins for the selected CONSOLE */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) - lpc17_configgpio(GPIO_UART0_TXD); - lpc17_configgpio(GPIO_UART0_RXD); + lpc17_40_configgpio(GPIO_UART0_TXD); + lpc17_40_configgpio(GPIO_UART0_RXD); #elif defined(CONFIG_UART1_SERIAL_CONSOLE) - lpc17_configgpio(GPIO_UART1_TXD); - lpc17_configgpio(GPIO_UART1_RXD); + lpc17_40_configgpio(GPIO_UART1_TXD); + lpc17_40_configgpio(GPIO_UART1_RXD); #if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) - lpc17_configgpio(GPIO_UART1_CTS); - lpc17_configgpio(GPIO_UART1_DCD); - lpc17_configgpio(GPIO_UART1_DSR); - lpc17_configgpio(GPIO_UART1_DTR); - lpc17_configgpio(GPIO_UART1_RI); - lpc17_configgpio(GPIO_UART1_RTS); + lpc17_40_configgpio(GPIO_UART1_CTS); + lpc17_40_configgpio(GPIO_UART1_DCD); + lpc17_40_configgpio(GPIO_UART1_DSR); + lpc17_40_configgpio(GPIO_UART1_DTR); + lpc17_40_configgpio(GPIO_UART1_RI); + lpc17_40_configgpio(GPIO_UART1_RTS); #endif #elif defined(CONFIG_UART2_SERIAL_CONSOLE) - lpc17_configgpio(GPIO_UART2_TXD); - lpc17_configgpio(GPIO_UART2_RXD); + lpc17_40_configgpio(GPIO_UART2_TXD); + lpc17_40_configgpio(GPIO_UART2_RXD); #elif defined(CONFIG_UART3_SERIAL_CONSOLE) - lpc17_configgpio(GPIO_UART3_TXD); - lpc17_configgpio(GPIO_UART3_RXD); + lpc17_40_configgpio(GPIO_UART3_TXD); + lpc17_40_configgpio(GPIO_UART3_RXD); #endif /* Configure the console (only) */ @@ -389,39 +389,39 @@ void lpc17_lowsetup(void) /* Clear fifos */ putreg32(UART_FCR_RXRST | UART_FCR_TXRST, - CONSOLE_BASE + LPC17_UART_FCR_OFFSET); + CONSOLE_BASE + LPC17_40_UART_FCR_OFFSET); /* Set trigger */ putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8, - CONSOLE_BASE + LPC17_UART_FCR_OFFSET); + CONSOLE_BASE + LPC17_40_UART_FCR_OFFSET); /* Disable FDR (fractional divider), * ignored by baudrate calculation => has to be disabled */ putreg32((1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT), - CONSOLE_BASE + LPC17_UART_FDR_OFFSET); + CONSOLE_BASE + LPC17_40_UART_FDR_OFFSET); /* Set up the LCR and set DLAB=1 */ putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB, - CONSOLE_BASE + LPC17_UART_LCR_OFFSET); + CONSOLE_BASE + LPC17_40_UART_LCR_OFFSET); /* Set the BAUD divisor */ - putreg32(CONSOLE_DL >> 8, CONSOLE_BASE + LPC17_UART_DLM_OFFSET); - putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE + LPC17_UART_DLL_OFFSET); + putreg32(CONSOLE_DL >> 8, CONSOLE_BASE + LPC17_40_UART_DLM_OFFSET); + putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE + LPC17_40_UART_DLL_OFFSET); /* Clear DLAB */ - putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC17_UART_LCR_OFFSET); + putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC17_40_UART_LCR_OFFSET); /* Configure the FIFOs */ putreg32(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | UART_FCR_FIFOEN, - CONSOLE_BASE + LPC17_UART_FCR_OFFSET); + CONSOLE_BASE + LPC17_40_UART_FCR_OFFSET); #endif #endif /* HAVE_UART */ } diff --git a/arch/arm/src/lpc17xx/lpc17_lowputc.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.h similarity index 92% rename from arch/arm/src/lpc17xx/lpc17_lowputc.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.h index b1b226e0353..e93414bf678 100644 --- a/arch/arm/src/lpc17xx/lpc17_lowputc.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_lowputc.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_LOWPUTC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_LOWPUTC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_LOWPUTC_H /************************************************************************************ * Included Files @@ -65,7 +65,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: lpc17_lowsetup + * Name: lpc17_40_lowsetup * * Description: * Called at the very beginning of _start. Performs low level initialization @@ -74,11 +74,11 @@ extern "C" * ************************************************************************************/ -void lpc17_lowsetup(void); +void lpc17_40_lowsetup(void); #ifdef __cplusplus } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_LOWPUTC_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c similarity index 74% rename from arch/arm/src/lpc17xx/lpc17_mcpwm.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c index 997a1b46fac..1fd9a14c5b1 100644 --- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_mcpwm.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c * * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,17 +54,17 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_pwm.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_pwm.h" #include "hardware/lpc176x_pinconfig.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lpc176x_gpio.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_LPC17_MCPWM) +#if defined(CONFIG_LPC17_40_MCPWM) /**************************************************************************** * Pre-processor Definitions @@ -93,7 +93,7 @@ ****************************************************************************/ /* This structure represents the state of one PWM timer */ -struct lpc17_mcpwmtimer_s +struct lpc17_40_mcpwmtimer_s { FAR const struct pwm_ops_s *ops; /* PWM operations */ uint8_t timid; /* Timer ID {0,...,7} */ @@ -110,18 +110,18 @@ struct lpc17_mcpwmtimer_s ****************************************************************************/ /* Register access */ -static uint32_t mcpwm_getreg(struct lpc17_mcpwmtimer_s *priv, int offset); -static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t value); +static uint32_t mcpwm_getreg(struct lpc17_40_mcpwmtimer_s *priv, int offset); +static void mcpwm_putreg(struct lpc17_40_mcpwmtimer_s *priv, int offset, uint32_t value); #ifdef CONFIG_DEBUG_PWM_INFO -static void mcpwm_dumpregs(struct lpc17_mcpwmtimer_s *priv, FAR const char *msg); +static void mcpwm_dumpregs(struct lpc17_40_mcpwmtimer_s *priv, FAR const char *msg); #else # define mcpwm_dumpregs(priv,msg) #endif /* Timer management */ -static int mcpwm_timer(FAR struct lpc17_mcpwmtimer_s *priv, +static int mcpwm_timer(FAR struct lpc17_40_mcpwmtimer_s *priv, FAR const struct pwm_info_s *info); /* PWM driver methods */ @@ -152,14 +152,14 @@ static const struct pwm_ops_s g_pwmops = .ioctl = mcpwm_ioctl, }; -#ifdef CONFIG_LPC17_MCPWM -static struct lpc17_mcpwmtimer_s g_pwm1dev = +#ifdef CONFIG_LPC17_40_MCPWM +static struct lpc17_40_mcpwmtimer_s g_pwm1dev = { .ops = &g_pwmops, .timid = 1, - .channel = CONFIG_LPC17_MCPWM1_PIN, + .channel = CONFIG_LPC17_40_MCPWM1_PIN, .timtype = TIMTYPE_TIM1, - .base = LPC17_MCPWM_BASE, + .base = LPC17_40_MCPWM_BASE, .pincfg = GPIO_MCPWM_MCOA0, .pclk = (1 << 12), }; @@ -184,7 +184,7 @@ static struct lpc17_mcpwmtimer_s g_pwm1dev = * ****************************************************************************/ -static uint32_t mcpwm_getreg(struct lpc17_mcpwmtimer_s *priv, int offset) +static uint32_t mcpwm_getreg(struct lpc17_40_mcpwmtimer_s *priv, int offset) { return getreg32(priv->base + offset); } @@ -204,7 +204,7 @@ static uint32_t mcpwm_getreg(struct lpc17_mcpwmtimer_s *priv, int offset) * ****************************************************************************/ -static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t value) +static void mcpwm_putreg(struct lpc17_40_mcpwmtimer_s *priv, int offset, uint32_t value) { putreg32(value, priv->base + offset); } @@ -224,30 +224,30 @@ static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t v ****************************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv, +static void mcpwm_dumpregs(FAR struct lpc17_40_mcpwmtimer_s *priv, FAR const char *msg) { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - mcpwm_getreg(priv, LPC17_PWM_MR0_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR1_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR3_OFFSET)); -#if defined(CONFIG_LPC17_MCPWM) + mcpwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); +#if defined(CONFIG_LPC17_40_MCPWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - mcpwm_getreg(priv, LPC17_PWM_MR0_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR1_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR3_OFFSET)); + mcpwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET), - mcpwm_getreg(priv, LPC17_PWM_MR3_OFFSET)); + mcpwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + mcpwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); } } #endif @@ -267,7 +267,7 @@ static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv, * ****************************************************************************/ -static int mcpwm_timer(FAR struct lpc17_mcpwmtimer_s *priv, +static int mcpwm_timer(FAR struct lpc17_40_mcpwmtimer_s *priv, FAR const struct pwm_info_s *info) { irqstate_t flags; @@ -275,8 +275,8 @@ static int mcpwm_timer(FAR struct lpc17_mcpwmtimer_s *priv, flags = enter_critical_section(); - putreg32(info->frequency, LPC17_MCPWM_LIM0); /* Set PWMMR0 = number of counts */ - putreg32(info->duty, LPC17_MCPWM_MAT0); /* Set PWM cycle */ + putreg32(info->frequency, LPC17_40_MCPWM_LIM0); /* Set PWMMR0 = number of counts */ + putreg32(info->duty, LPC17_40_MCPWM_MAT0); /* Set PWM cycle */ leave_critical_section(flags); mcpwm_dumpregs(priv, "After starting"); @@ -298,7 +298,7 @@ static int mcpwm_timer(FAR struct lpc17_mcpwmtimer_s *priv, * ****************************************************************************/ -static int mcpwm_interrupt(struct lpc17_mcpwmtimer_s *priv) +static int mcpwm_interrupt(struct lpc17_40_mcpwmtimer_s *priv) { uint16_t regval; @@ -349,7 +349,7 @@ static int mcpwm_tim1interrupt(int irq, void *context) * ****************************************************************************/ -static void mcpwm_set_apb_clock(FAR struct lpc17_mcpwmtimer_s *priv, bool on) +static void mcpwm_set_apb_clock(FAR struct lpc17_40_mcpwmtimer_s *priv, bool on) { uint32_t en_bit; uint32_t regaddr; @@ -358,7 +358,7 @@ static void mcpwm_set_apb_clock(FAR struct lpc17_mcpwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_LPC17_MCPWM +#ifdef CONFIG_LPC17_40_MCPWM case 1: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; @@ -401,7 +401,7 @@ static void mcpwm_set_apb_clock(FAR struct lpc17_mcpwmtimer_s *priv, bool on) static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev; + FAR struct lpc17_40_mcpwmtimer_s *priv = (FAR struct lpc17_40_mcpwmtimer_s *)dev; irqstate_t flags; uint32_t regval; @@ -409,71 +409,71 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) /* Power on the mcpwm peripheral */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCMCPWM; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Select clock for the mcpwm peripheral */ - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~(0x3 << 30); regval |= (0x2 << 30); /* PCLK_MC peripheral clk = CCLK/2 = 50 MHz */ - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); priv->pclk = (0x1 << 12) | (0x1 << 4); - putreg32((1 << 15), LPC17_MCPWM_INTENCLR); /* Disable MCABORT pin interrupt */ - putreg32((1 << 0), LPC17_MCPWM_INTENCLR); /* Disable ILIM0 interrupt */ - putreg32((1 << 1), LPC17_MCPWM_INTENCLR); /* Disable IMAT0 interrupt */ - putreg32((1 << 2), LPC17_MCPWM_INTENCLR); /* Disable ICAP0 interrupt */ - putreg32((1 << 4), LPC17_MCPWM_INTENCLR); /* Disable ILIM1 interrupt */ - putreg32((1 << 5), LPC17_MCPWM_INTENCLR); /* Disable IMAT1 interrupt */ - putreg32((1 << 6), LPC17_MCPWM_INTENCLR); /* Disable ICAP1 interrupt */ - putreg32((1 << 8), LPC17_MCPWM_INTENCLR); /* Disable ILIM2 interrupt */ - putreg32((1 << 9), LPC17_MCPWM_INTENCLR); /* Disable IMAT2 interrupt */ - putreg32((1 << 10), LPC17_MCPWM_INTENCLR); /* Disable ICAP2 interrupt */ + putreg32((1 << 15), LPC17_40_MCPWM_INTENCLR); /* Disable MCABORT pin interrupt */ + putreg32((1 << 0), LPC17_40_MCPWM_INTENCLR); /* Disable ILIM0 interrupt */ + putreg32((1 << 1), LPC17_40_MCPWM_INTENCLR); /* Disable IMAT0 interrupt */ + putreg32((1 << 2), LPC17_40_MCPWM_INTENCLR); /* Disable ICAP0 interrupt */ + putreg32((1 << 4), LPC17_40_MCPWM_INTENCLR); /* Disable ILIM1 interrupt */ + putreg32((1 << 5), LPC17_40_MCPWM_INTENCLR); /* Disable IMAT1 interrupt */ + putreg32((1 << 6), LPC17_40_MCPWM_INTENCLR); /* Disable ICAP1 interrupt */ + putreg32((1 << 8), LPC17_40_MCPWM_INTENCLR); /* Disable ILIM2 interrupt */ + putreg32((1 << 9), LPC17_40_MCPWM_INTENCLR); /* Disable IMAT2 interrupt */ + putreg32((1 << 10), LPC17_40_MCPWM_INTENCLR); /* Disable ICAP2 interrupt */ - putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR); /* Clear all event capture */ + putreg32((0xFFFFFFFF), LPC17_40_MCPWM_CAPCLR); /* Clear all event capture */ /* Configure the output pins */ - lpc17_configgpio(GPIO_MCPWM_MCOA0); - lpc17_configgpio(GPIO_MCPWM_MCOB0); + lpc17_40_configgpio(GPIO_MCPWM_MCOA0); + lpc17_40_configgpio(GPIO_MCPWM_MCOB0); /* Program the timing registers */ - putreg32((1 << 0), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer0 */ - putreg32((1 << 8), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer1 */ - putreg32((1 << 16), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer2 */ + putreg32((1 << 0), LPC17_40_MCPWM_CONCLR); /* Stop MCPWM timer0 */ + putreg32((1 << 8), LPC17_40_MCPWM_CONCLR); /* Stop MCPWM timer1 */ + putreg32((1 << 16), LPC17_40_MCPWM_CONCLR); /* Stop MCPWM timer2 */ - putreg32((1 << 30), LPC17_MCPWM_CONCLR); /* MCPWM not in AC mode */ + putreg32((1 << 30), LPC17_40_MCPWM_CONCLR); /* MCPWM not in AC mode */ - putreg32(1000, LPC17_MCPWM_TC0); /* Count frequency: Fpclk/1000 = 50 MHz/1000 = 50 KHz */ - putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */ - putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */ + putreg32(1000, LPC17_40_MCPWM_TC0); /* Count frequency: Fpclk/1000 = 50 MHz/1000 = 50 KHz */ + putreg32(400, LPC17_40_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */ + putreg32(0, LPC17_40_MCPWM_MAT0); /* Reset the timer */ - putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */ - putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */ - putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */ + putreg32(100000, LPC17_40_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */ + putreg32(50000, LPC17_40_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */ + putreg32(0, LPC17_40_MCPWM_MAT1); /* Reset the timer */ - putreg32(1000, LPC17_MCPWM_TC2); /* Count frequency:Fpclk/1000 = 50 MHz/1000 = 50 KHz */ - putreg32(400, LPC17_MCPWM_LIM2); /* Set the starting duty cycle to 0.25 */ - putreg32(0, LPC17_MCPWM_MAT2); /* Reset the timer */ + putreg32(1000, LPC17_40_MCPWM_TC2); /* Count frequency:Fpclk/1000 = 50 MHz/1000 = 50 KHz */ + putreg32(400, LPC17_40_MCPWM_LIM2); /* Set the starting duty cycle to 0.25 */ + putreg32(0, LPC17_40_MCPWM_MAT2); /* Reset the timer */ - putreg32((1 << 2), LPC17_MCPWM_CONCLR); /* Channel 0 polarity set to default */ - putreg32((1 << 10), LPC17_MCPWM_CONCLR); /* Channel 1 polarity set to default */ - putreg32((1 << 18), LPC17_MCPWM_CONCLR); /* Channel 2 polarity set to default */ + putreg32((1 << 2), LPC17_40_MCPWM_CONCLR); /* Channel 0 polarity set to default */ + putreg32((1 << 10), LPC17_40_MCPWM_CONCLR); /* Channel 1 polarity set to default */ + putreg32((1 << 18), LPC17_40_MCPWM_CONCLR); /* Channel 2 polarity set to default */ - putreg32((1 << 3), LPC17_MCPWM_CONCLR); /* Channel 0 dead time disabled */ - putreg32((1 << 11), LPC17_MCPWM_CONCLR); /* Channel 1 dead time disabled */ - putreg32((1 << 19), LPC17_MCPWM_CONCLR); /* Channel 2 dead time disabled */ + putreg32((1 << 3), LPC17_40_MCPWM_CONCLR); /* Channel 0 dead time disabled */ + putreg32((1 << 11), LPC17_40_MCPWM_CONCLR); /* Channel 1 dead time disabled */ + putreg32((1 << 19), LPC17_40_MCPWM_CONCLR); /* Channel 2 dead time disabled */ - putreg32((1 << 1), LPC17_MCPWM_CONCLR); /* Channel 0 edge aligned */ - putreg32((1 << 9), LPC17_MCPWM_CONCLR); /* Channel 1 edge aligned */ - putreg32((1 << 17), LPC17_MCPWM_CONCLR); /* Channel 2 edge aligned */ + putreg32((1 << 1), LPC17_40_MCPWM_CONCLR); /* Channel 0 edge aligned */ + putreg32((1 << 9), LPC17_40_MCPWM_CONCLR); /* Channel 1 edge aligned */ + putreg32((1 << 17), LPC17_40_MCPWM_CONCLR); /* Channel 2 edge aligned */ - putreg32((0xFFFFFFFF), LPC17_MCPWM_CNTCONCLR); /* All channels in counter mode on PCLK */ + putreg32((0xFFFFFFFF), LPC17_40_MCPWM_CNTCONCLR); /* All channels in counter mode on PCLK */ - putreg32((1 << 0), LPC17_MCPWM_CONSET); /* Start MCPWM timer0 */ + putreg32((1 << 0), LPC17_40_MCPWM_CONSET); /* Start MCPWM timer0 */ leave_critical_section(flags); pwm_dumpgpio(priv->pincfg, "PWM setup"); @@ -498,7 +498,7 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) static int mcpwm_shutdown(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev; + FAR struct lpc17_40_mcpwmtimer_s *priv = (FAR struct lpc17_40_mcpwmtimer_s *)dev; uint32_t pincfg; pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); @@ -526,7 +526,7 @@ static int mcpwm_shutdown(FAR struct pwm_lowerhalf_s *dev) static int mcpwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) { - FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev; + FAR struct lpc17_40_mcpwmtimer_s *priv = (FAR struct lpc17_40_mcpwmtimer_s *)dev; return mcpwm_timer(priv, info); } @@ -551,7 +551,7 @@ static int mcpwm_start(FAR struct pwm_lowerhalf_s *dev, static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev; + FAR struct lpc17_40_mcpwmtimer_s *priv = (FAR struct lpc17_40_mcpwmtimer_s *)dev; uint32_t resetbit; uint32_t regaddr; uint32_t regval; @@ -571,7 +571,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_LPC17_MCPWM +#ifdef CONFIG_LPC17_40_MCPWM case 1: break; #endif @@ -607,7 +607,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev) static int mcpwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO - FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev; + FAR struct lpc17_40_mcpwmtimer_s *priv = (FAR struct lpc17_40_mcpwmtimer_s *)dev; /* There are no platform-specific ioctl commands */ @@ -621,7 +621,7 @@ static int mcpwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long a ****************************************************************************/ /**************************************************************************** - * Name: lpc17_mcpwminitialize + * Name: lpc17_40_mcpwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -637,15 +637,15 @@ static int mcpwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long a * ****************************************************************************/ -FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer) +FAR struct pwm_lowerhalf_s *lpc17_40_mcpwminitialize(int timer) { - FAR struct lpc17_mcpwmtimer_s *lower; + FAR struct lpc17_40_mcpwmtimer_s *lower; pwminfo("TIM%d\n", timer); switch (timer) { -#ifdef CONFIG_LPC17_MCPWM +#ifdef CONFIG_LPC17_40_MCPWM case 0: lower = &g_pwm1dev; @@ -662,4 +662,4 @@ FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer) return (FAR struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_LPC17_TIMn_PWM, n = 1,...,14 */ +#endif /* CONFIG_LPC17_40_TIMn_PWM, n = 1,...,14 */ diff --git a/arch/arm/src/lpc17xx/lpc17_mpuinit.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.c similarity index 94% rename from arch/arm/src/lpc17xx/lpc17_mpuinit.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.c index 46311393c77..33cad4f119b 100644 --- a/arch/arm/src/lpc17xx/lpc17_mpuinit.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_mpuinit.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.c * * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,7 +44,7 @@ #include #include "mpu.h" -#include "lpc17_mpuinit.h" +#include "lpc17_40_mpuinit.h" #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) @@ -65,7 +65,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_mpuinitialize + * Name: lpc17_40_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -73,7 +73,7 @@ * ****************************************************************************/ -void lpc17_mpuinitialize(void) +void lpc17_40_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -98,7 +98,7 @@ void lpc17_mpuinitialize(void) } /**************************************************************************** - * Name: lpc17_mpu_uheap + * Name: lpc17_40_mpu_uheap * * Description: * Map the user-heap region. @@ -107,7 +107,7 @@ void lpc17_mpuinitialize(void) * ****************************************************************************/ -void lpc17_mpu_uheap(uintptr_t start, size_t size) +void lpc17_40_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/lpc17xx/lpc17_mpuinit.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.h similarity index 88% rename from arch/arm/src/lpc17xx/lpc17_mpuinit.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.h index 145789532da..98c4f918501 100644 --- a/arch/arm/src/lpc17xx/lpc17_mpuinit.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_mpuinit.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_mpuinit.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MPUINIT_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_MPUINIT_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_MPUINIT_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_MPUINIT_H /************************************************************************************ * Included Files @@ -59,7 +59,7 @@ ************************************************************************************/ /**************************************************************************** - * Name: lpc17_mpuinitialize + * Name: lpc17_40_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -68,13 +68,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void lpc17_mpuinitialize(void); +void lpc17_40_mpuinitialize(void); #else -# define lpc17_mpuinitialize() +# define lpc17_40_mpuinitialize() #endif /**************************************************************************** - * Name: lpc17_mpu_uheap + * Name: lpc17_40_mpu_uheap * * Description: * Map the user heap region. @@ -82,9 +82,9 @@ void lpc17_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void lpc17_mpu_uheap(uintptr_t start, size_t size); +void lpc17_40_mpu_uheap(uintptr_t start, size_t size); #else -# define lpc17_mpu_uheap(start,size) +# define lpc17_40_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_MPUINIT_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_ohciram.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_ohciram.h similarity index 58% rename from arch/arm/src/lpc17xx/lpc17_ohciram.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_ohciram.h index 7aa894c8e0d..d87d7933042 100644 --- a/arch/arm/src/lpc17xx/lpc17_ohciram.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ohciram.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_ohciram.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_ohciram.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_OHCIRAM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_OHCIRAM_H /************************************************************************************ * Included Files @@ -42,33 +42,33 @@ #include #include "chip.h" -#include "hardware/lpc17_memorymap.h" +#include "hardware/lpc17_40_memorymap.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ /* Default, no-OHCI Case ************************************************************/ /* Assume that all of AHB SRAM will be available for heap. If this is not true, then - * LPC17_BANK1_HEAPSIZE will be undefined but redefined below. + * LPC17_40_BANK1_HEAPSIZE will be undefined but redefined below. */ -#undef LPC17_BANK1_HEAPBASE -#undef LPC17_BANK1_HEAPSIZE -#ifdef LPC17_HAVE_BANK1 -# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 -# define LPC17_BANK1_HEAPSIZE LPC17_BANK1_SIZE +#undef LPC17_40_BANK1_HEAPBASE +#undef LPC17_40_BANK1_HEAPSIZE +#ifdef LPC17_40_HAVE_BANK1 +# define LPC17_40_BANK1_HEAPBASE LPC17_40_SRAM_BANK1 +# define LPC17_40_BANK1_HEAPSIZE LPC17_40_BANK1_SIZE #endif -/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have +/* Is networking enabled? Is the LPC17xx/LPC40xx Ethernet device enabled? Does this chip have * and Ethernet controlloer? Yes... then we will replace the above default definitions. */ -#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_USBHOST) && LPC17_NUSBHOST > 0 +#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_40_USBHOST) && LPC17_40_NUSBHOST > 0 /* OHCI RAM Configuration ***********************************************************/ /* Is AHB SRAM available? */ -#ifndef LPC17_HAVE_BANK1 +#ifndef LPC17_40_HAVE_BANK1 # error "AHB SRAM Bank1 is not available for OHCI RAM" #endif @@ -78,39 +78,39 @@ * bytes. */ -#ifndef CONFIG_LPC17_OHCIRAM_SIZE -# define CONFIG_LPC17_OHCIRAM_SIZE LPC17_BANK1_SIZE +#ifndef CONFIG_LPC17_40_OHCIRAM_SIZE +# define CONFIG_LPC17_40_OHCIRAM_SIZE LPC17_40_BANK1_SIZE #endif -#if CONFIG_LPC17_OHCIRAM_SIZE > LPC17_BANK1_SIZE +#if CONFIG_LPC17_40_OHCIRAM_SIZE > LPC17_40_BANK1_SIZE # error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1" #endif -#if (CONFIG_LPC17_OHCIRAM_SIZE & 0xff) != 0 +#if (CONFIG_LPC17_40_OHCIRAM_SIZE & 0xff) != 0 # error "OHCI RAM size must be in multiples of 256 bytes" #endif /* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */ -#define LPC17_OHCIRAM_END (LPC17_SRAM_BANK1 + LPC17_BANK1_SIZE) -#define LPC17_OHCIRAM_BASE (LPC17_OHCIRAM_END - CONFIG_LPC17_OHCIRAM_SIZE) -#define LPC17_OHCIRAM_SIZE CONFIG_LPC17_OHCIRAM_SIZE +#define LPC17_40_OHCIRAM_END (LPC17_40_SRAM_BANK1 + LPC17_40_BANK1_SIZE) +#define LPC17_40_OHCIRAM_BASE (LPC17_40_OHCIRAM_END - CONFIG_LPC17_40_OHCIRAM_SIZE) +#define LPC17_40_OHCIRAM_SIZE CONFIG_LPC17_40_OHCIRAM_SIZE /* Determine is there is any meaningful space left at the beginning of AHB Bank 1 * that could be added to the heap. */ -#undef LPC17_BANK1_HEAPBASE -#undef LPC17_BANK1_HEAPSIZE -#if LPC17_OHCIRAM_SIZE < (LPC17_BANK1_SIZE-128) -# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 -# define LPC17_BANK1_HEAPSIZE (LPC17_BANK1_SIZE - LPC17_OHCIRAM_SIZE) +#undef LPC17_40_BANK1_HEAPBASE +#undef LPC17_40_BANK1_HEAPSIZE +#if LPC17_40_OHCIRAM_SIZE < (LPC17_40_BANK1_SIZE-128) +# define LPC17_40_BANK1_HEAPBASE LPC17_40_SRAM_BANK1 +# define LPC17_40_BANK1_HEAPSIZE (LPC17_40_BANK1_SIZE - LPC17_40_OHCIRAM_SIZE) #endif /* Numbers and Sizes of Things ******************************************************/ /* Fixed size of the OHCI control area */ -#define LPC17_HCCA_SIZE 256 +#define LPC17_40_HCCA_SIZE 256 /* Fixed endpoint descriptor size. The actual size required by the hardware is only * 16 bytes, however, we set aside an additional 16 bytes for for internal use by @@ -118,7 +118,7 @@ * aligned to 16-byte boundaries. */ -#define LPC17_ED_SIZE 32 +#define LPC17_40_ED_SIZE 32 /* Configurable number of user endpoint descriptors (EDs). This number excludes * the control endpoint that is always allocated. @@ -130,7 +130,7 @@ /* Derived size of user endpoint descriptor (ED) memory. */ -#define LPC17_EDFREE_SIZE (CONFIG_LP17_USBHOST_NEDS * LPC17_ED_SIZE) +#define LPC17_40_EDFREE_SIZE (CONFIG_LP17_USBHOST_NEDS * LPC17_40_ED_SIZE) /* Fixed transfer descriptor size. The actual size required by the hardware is only * 16 bytes, however, we set aside an additional 16 bytes for for internal use by @@ -138,7 +138,7 @@ * aligned to 16-byte boundaries. */ -#define LPC17_TD_SIZE 32 +#define LPC17_40_TD_SIZE 32 /* Configurable number of user transfer descriptors (TDs). */ @@ -152,99 +152,99 @@ /* Derived size of user transfer descriptor (TD) memory. */ -#define LPC17_TDFREE_SIZE (CONFIG_LP17_USBHOST_NTDS * LPC17_TD_SIZE) +#define LPC17_40_TDFREE_SIZE (CONFIG_LP17_USBHOST_NTDS * LPC17_40_TD_SIZE) /* Configurable number of request/descriptor buffers (TDBUFFER) */ -#ifndef CONFIG_LPC17_USBHOST_TDBUFFERS -# define CONFIG_LPC17_USBHOST_TDBUFFERS 2 +#ifndef CONFIG_LPC17_40_USBHOST_TDBUFFERS +# define CONFIG_LPC17_40_USBHOST_TDBUFFERS 2 #endif -#if CONFIG_LPC17_USBHOST_TDBUFFERS < 2 +#if CONFIG_LPC17_40_USBHOST_TDBUFFERS < 2 # error "At least two TD buffers are required" #endif /* Configurable size of a TD buffer */ -#if CONFIG_LPC17_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_LPC17_USBHOST_TDBUFSIZE) -# define CONFIG_LPC17_USBHOST_TDBUFSIZE 128 +#if CONFIG_LPC17_40_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_LPC17_40_USBHOST_TDBUFSIZE) +# define CONFIG_LPC17_40_USBHOST_TDBUFSIZE 128 #endif -#if (CONFIG_LPC17_USBHOST_TDBUFSIZE & 3) != 0 +#if (CONFIG_LPC17_40_USBHOST_TDBUFSIZE & 3) != 0 # error "TD buffer size must be an even number of 32-bit words" #endif -#define LPC17_TBFREE_SIZE (CONFIG_LPC17_USBHOST_TDBUFFERS * CONFIG_LPC17_USBHOST_TDBUFSIZE) +#define LPC17_40_TBFREE_SIZE (CONFIG_LPC17_40_USBHOST_TDBUFFERS * CONFIG_LPC17_40_USBHOST_TDBUFSIZE) /* Configurable size of an IO buffer. The number of IO buffers will be determined * by what is left at the end of the BANK1 memory setup aside of OHCI RAM. */ -#ifndef CONFIG_LPC17_USBHOST_IOBUFSIZE -# define CONFIG_LPC17_USBHOST_IOBUFSIZE 512 +#ifndef CONFIG_LPC17_40_USBHOST_IOBUFSIZE +# define CONFIG_LPC17_40_USBHOST_IOBUFSIZE 512 #endif -#if (CONFIG_LPC17_USBHOST_IOBUFSIZE & 3) != 0 +#if (CONFIG_LPC17_40_USBHOST_IOBUFSIZE & 3) != 0 # error "IO buffer size must be an even number of 32-bit words" #endif /* OHCI Memory Layout ***************************************************************/ /* Example: * Hardware: - * LPC17_SRAM_BANK1 0x20008000 - * LPC17_BANK1_SIZE 16384 + * LPC17_40_SRAM_BANK1 0x20008000 + * LPC17_40_BANK1_SIZE 16384 * * Configuration: - * CONFIG_LPC17_OHCIRAM_SIZE 1536 + * CONFIG_LPC17_40_OHCIRAM_SIZE 1536 * CONFIG_LP17_USBHOST_NEDS 2 * CONFIG_LP17_USBHOST_NTDS 3 - * CONFIG_LPC17_USBHOST_TDBUFFERS 3 - * CONFIG_LPC17_USBHOST_TDBUFSIZE 128 - * CONFIG_LPC17_USBHOST_IOBUFSIZE 512 + * CONFIG_LPC17_40_USBHOST_TDBUFFERS 3 + * CONFIG_LPC17_40_USBHOST_TDBUFSIZE 128 + * CONFIG_LPC17_40_USBHOST_IOBUFSIZE 512 * * Sizes of things - * LPC17_EDFREE_SIZE 64 0x00000040 - * LPC17_TDFREE_SIZE 96 0x00000060 - * LPC17_TBFREE_SIZE 384 0x00000100 - * LPC17_IOFREE_SIZE 512 0x00000200 + * LPC17_40_EDFREE_SIZE 64 0x00000040 + * LPC17_40_TDFREE_SIZE 96 0x00000060 + * LPC17_40_TBFREE_SIZE 384 0x00000100 + * LPC17_40_IOFREE_SIZE 512 0x00000200 * * Memory Layout - * LPC17_OHCIRAM_END (0x20008000 + 16384) = 0x20084000 - * LPC17_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00 - * LPC17_OHCIRAM_SIZE 1280 - * LPC17_BANK1_HEAPBASE 0x20008000 - * LPC17_BANK1_HEAPSIZE (16384 - 1280) = 15104 + * LPC17_40_OHCIRAM_END (0x20008000 + 16384) = 0x20084000 + * LPC17_40_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00 + * LPC17_40_OHCIRAM_SIZE 1280 + * LPC17_40_BANK1_HEAPBASE 0x20008000 + * LPC17_40_BANK1_HEAPSIZE (16384 - 1280) = 15104 * - * LPC17_HCCA_BASE 0x20083a00 -- Communications area - * LPC17_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD - * LPC17_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0 - * LPC17_EDFREE_BASE 0x20083b40 -- Free EDs - * LPC17_TDFREE_BASE 0x20083b80 -- Free TDs - * LPC17_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers - * LPC17_IOFREE_BASE 0x20083d60 -- Free large I/O buffers - * LPC17_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1 + * LPC17_40_HCCA_BASE 0x20083a00 -- Communications area + * LPC17_40_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD + * LPC17_40_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0 + * LPC17_40_EDFREE_BASE 0x20083b40 -- Free EDs + * LPC17_40_TDFREE_BASE 0x20083b80 -- Free TDs + * LPC17_40_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers + * LPC17_40_IOFREE_BASE 0x20083d60 -- Free large I/O buffers + * LPC17_40_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1 * * Wasted memory: 672-512 = 160 bytes */ -#define LPC17_HCCA_BASE (LPC17_OHCIRAM_BASE) -#define LPC17_TDTAIL_ADDR (LPC17_HCCA_BASE + LPC17_HCCA_SIZE) -#define LPC17_EDCTRL_ADDR (LPC17_TDTAIL_ADDR + LPC17_TD_SIZE) -#define LPC17_EDFREE_BASE (LPC17_EDCTRL_ADDR + LPC17_ED_SIZE) -#define LPC17_TDFREE_BASE (LPC17_EDFREE_BASE + LPC17_EDFREE_SIZE) -#define LPC17_TBFREE_BASE (LPC17_TDFREE_BASE + LPC17_TDFREE_SIZE) -#define LPC17_IOFREE_BASE (LPC17_TBFREE_BASE + LPC17_TBFREE_SIZE) +#define LPC17_40_HCCA_BASE (LPC17_40_OHCIRAM_BASE) +#define LPC17_40_TDTAIL_ADDR (LPC17_40_HCCA_BASE + LPC17_40_HCCA_SIZE) +#define LPC17_40_EDCTRL_ADDR (LPC17_40_TDTAIL_ADDR + LPC17_40_TD_SIZE) +#define LPC17_40_EDFREE_BASE (LPC17_40_EDCTRL_ADDR + LPC17_40_ED_SIZE) +#define LPC17_40_TDFREE_BASE (LPC17_40_EDFREE_BASE + LPC17_40_EDFREE_SIZE) +#define LPC17_40_TBFREE_BASE (LPC17_40_TDFREE_BASE + LPC17_40_TDFREE_SIZE) +#define LPC17_40_IOFREE_BASE (LPC17_40_TBFREE_BASE + LPC17_40_TBFREE_SIZE) -#if LPC17_IOFREE_BASE > LPC17_OHCIRAM_END +#if LPC17_40_IOFREE_BASE > LPC17_40_OHCIRAM_END # error "Insufficient OHCI RAM allocated" #endif /* Finally, use the remainder of the allocated OHCI for IO buffers */ -#if CONFIG_LPC17_USBHOST_IOBUFSIZE > 0 -# define LPC17_IOBUFFERS ((LPC17_OHCIRAM_END - LPC17_IOFREE_BASE) / CONFIG_LPC17_USBHOST_IOBUFSIZE) +#if CONFIG_LPC17_40_USBHOST_IOBUFSIZE > 0 +# define LPC17_40_IOBUFFERS ((LPC17_40_OHCIRAM_END - LPC17_40_IOFREE_BASE) / CONFIG_LPC17_40_USBHOST_IOBUFSIZE) #else -# define LPC17_IOBUFFERS 0 +# define LPC17_40_IOBUFFERS 0 #endif /************************************************************************************ @@ -259,5 +259,5 @@ * Public Functions ************************************************************************************/ -#endif /* CONFIG_USBHOST && CONFIG_LPC17_USBHOST && LPC17_NUSBHOST > 0*/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H */ +#endif /* CONFIG_USBHOST && CONFIG_LPC17_40_USBHOST && LPC17_40_NUSBHOST > 0*/ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_OHCIRAM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_progmem.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c similarity index 81% rename from arch/arm/src/lpc17xx/lpc17_progmem.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c index af35b7e4253..d68a4d7a900 100644 --- a/arch/arm/src/lpc17xx/lpc17_progmem.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c @@ -1,5 +1,5 @@ /****************************************************************************** - * arch/arm/src/lpc17xx/lpc17_progmem.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c * * Copyright (C) 2018 Michael Jung. All rights reserved. * Author: Michael Jung @@ -53,16 +53,16 @@ #include #include -#include "lpc17_progmem.h" +#include "lpc17_40_progmem.h" /****************************************************************************** * Private Function Prototypes ******************************************************************************/ -static void lpc17_iap(void *in, void *out); -static uint32_t lpc17_iap_prepare_sector_for_write_operation(uint32_t sector); -static uint32_t lpc17_iap_erase_sector(uint32_t sector); -static uint32_t lpc17_iap_copy_ram_to_flash(void *flash, const void *ram, +static void lpc17_40_iap(void *in, void *out); +static uint32_t lpc17_40_iap_prepare_sector_for_write_operation(uint32_t sector); +static uint32_t lpc17_40_iap_erase_sector(uint32_t sector); +static uint32_t lpc17_40_iap_copy_ram_to_flash(void *flash, const void *ram, size_t count); /****************************************************************************** @@ -70,7 +70,7 @@ static uint32_t lpc17_iap_copy_ram_to_flash(void *flash, const void *ram, ******************************************************************************/ /****************************************************************************** - * Name: lpc17_iap + * Name: lpc17_40_iap * * Description (from UM10360): * For in-application programming the IAP routine should be called with a word @@ -81,19 +81,19 @@ static uint32_t lpc17_iap_copy_ram_to_flash(void *flash, const void *ram, * ******************************************************************************/ -static void lpc17_iap(FAR void *in, FAR void *out) +static void lpc17_40_iap(FAR void *in, FAR void *out) { irqstate_t flags; flags = enter_critical_section(); - ((void (*)(FAR void *, FAR void *))LPC17_IAP_ENTRY_ADDR)(in, out); + ((void (*)(FAR void *, FAR void *))LPC17_40_IAP_ENTRY_ADDR)(in, out); leave_critical_section(flags); } /****************************************************************************** - * Name: lpc17_iap_prepare_sector_for_write_operation + * Name: lpc17_40_iap_prepare_sector_for_write_operation * * Description (from UM10360): * This command must be executed before executing "Copy RAM to Flash" or @@ -103,21 +103,21 @@ static void lpc17_iap(FAR void *in, FAR void *out) * ******************************************************************************/ -static uint32_t lpc17_iap_prepare_sector_for_write_operation(uint32_t sector) +static uint32_t lpc17_40_iap_prepare_sector_for_write_operation(uint32_t sector) { uint32_t inout[3]; - inout[0] = LPC17_IAP_CMD_PREPARE_SECTORS_FOR_WRITE_OPERATION; + inout[0] = LPC17_40_IAP_CMD_PREPARE_SECTORS_FOR_WRITE_OPERATION; inout[1] = sector; inout[2] = sector; - lpc17_iap(inout, inout); + lpc17_40_iap(inout, inout); return inout[0]; } /****************************************************************************** - * Name: lpc17_iap_erase_sector + * Name: lpc17_40_iap_erase_sector * * Description (from UM10360): * This command is used to erase a sector or multiple sectors of on-chip flash @@ -126,22 +126,22 @@ static uint32_t lpc17_iap_prepare_sector_for_write_operation(uint32_t sector) * ******************************************************************************/ -static uint32_t lpc17_iap_erase_sector(uint32_t sector) +static uint32_t lpc17_40_iap_erase_sector(uint32_t sector) { uint32_t inout[4]; - inout[0] = LPC17_IAP_CMD_ERASE_SECTORS; + inout[0] = LPC17_40_IAP_CMD_ERASE_SECTORS; inout[1] = sector; inout[2] = sector; - inout[3] = LPC17_CCLK / 1000; + inout[3] = LPC17_40_CCLK / 1000; - lpc17_iap(inout, inout); + lpc17_40_iap(inout, inout); return inout[0]; } /****************************************************************************** - * Name: lpc17_iap_copy_ram_to_flash + * Name: lpc17_40_iap_copy_ram_to_flash * * Description (from UM10360): * This command is used to program the flash memory. The affected sectors @@ -151,18 +151,18 @@ static uint32_t lpc17_iap_erase_sector(uint32_t sector) * ******************************************************************************/ -static uint32_t lpc17_iap_copy_ram_to_flash(void *flash, const void *ram, +static uint32_t lpc17_40_iap_copy_ram_to_flash(void *flash, const void *ram, size_t count) { uint32_t inout[5]; - inout[0] = LPC17_IAP_CMD_COPY_RAM_TO_FLASH; + inout[0] = LPC17_40_IAP_CMD_COPY_RAM_TO_FLASH; inout[1] = (uint32_t)flash; inout[2] = (uint32_t)ram; inout[3] = (uint32_t)count; - inout[4] = LPC17_CCLK / 1000; + inout[4] = LPC17_40_CCLK / 1000; - lpc17_iap(inout, inout); + lpc17_40_iap(inout, inout); return inout[0]; } @@ -181,7 +181,7 @@ static uint32_t lpc17_iap_copy_ram_to_flash(void *flash, const void *ram, size_t up_progmem_neraseblocks(void) { - return CONFIG_LPC17_PROGMEM_NSECTORS; + return CONFIG_LPC17_40_PROGMEM_NSECTORS; } /****************************************************************************** @@ -207,7 +207,7 @@ bool up_progmem_isuniform(void) size_t up_progmem_pagesize(size_t page) { - return (size_t)LPC17_PROGMEM_PAGE_SIZE; + return (size_t)LPC17_40_PROGMEM_PAGE_SIZE; } /****************************************************************************** @@ -220,7 +220,7 @@ size_t up_progmem_pagesize(size_t page) size_t up_progmem_erasesize(size_t block) { - return (size_t)LPC17_PROGMEM_SECTOR_SIZE; + return (size_t)LPC17_40_PROGMEM_SECTOR_SIZE; } /****************************************************************************** @@ -242,12 +242,12 @@ size_t up_progmem_erasesize(size_t block) ssize_t up_progmem_getpage(size_t addr) { - if (addr >= LPC17_PROGMEM_START_ADDR) + if (addr >= LPC17_40_PROGMEM_START_ADDR) { - addr -= LPC17_PROGMEM_START_ADDR; + addr -= LPC17_40_PROGMEM_START_ADDR; } - return (size_t)(addr / LPC17_PROGMEM_PAGE_SIZE); + return (size_t)(addr / LPC17_40_PROGMEM_PAGE_SIZE); } /****************************************************************************** @@ -266,7 +266,7 @@ ssize_t up_progmem_getpage(size_t addr) size_t up_progmem_getaddress(size_t page) { - return (size_t)(LPC17_PROGMEM_START_ADDR + page * LPC17_PROGMEM_PAGE_SIZE); + return (size_t)(LPC17_40_PROGMEM_START_ADDR + page * LPC17_40_PROGMEM_PAGE_SIZE); } /****************************************************************************** @@ -295,26 +295,26 @@ ssize_t up_progmem_eraseblock(size_t block) { uint32_t rc; - if (block >= CONFIG_LPC17_PROGMEM_NSECTORS) + if (block >= CONFIG_LPC17_40_PROGMEM_NSECTORS) { return -EFAULT; } - rc = lpc17_iap_prepare_sector_for_write_operation((uint32_t)block + - LPC17_PROGMEM_START_SECTOR); - if (rc != LPC17_IAP_RC_CMD_SUCCESS) + rc = lpc17_40_iap_prepare_sector_for_write_operation((uint32_t)block + + LPC17_40_PROGMEM_START_SECTOR); + if (rc != LPC17_40_IAP_RC_CMD_SUCCESS) { return -EIO; } - rc = lpc17_iap_erase_sector((uint32_t)block + LPC17_PROGMEM_START_SECTOR); + rc = lpc17_40_iap_erase_sector((uint32_t)block + LPC17_40_PROGMEM_START_SECTOR); - if (rc != LPC17_IAP_RC_CMD_SUCCESS) + if (rc != LPC17_40_IAP_RC_CMD_SUCCESS) { return -EIO; } - return (ssize_t)LPC17_PROGMEM_SECTOR_SIZE; + return (ssize_t)LPC17_40_PROGMEM_SECTOR_SIZE; } /****************************************************************************** @@ -340,14 +340,14 @@ ssize_t up_progmem_ispageerased(size_t page) const uint8_t *p; int i; - if (page >= CONFIG_LPC17_PROGMEM_NSECTORS) + if (page >= CONFIG_LPC17_40_PROGMEM_NSECTORS) { return -EFAULT; } p = (const uint8_t *)up_progmem_getaddress(page); - for (i = 0; i < LPC17_PROGMEM_SECTOR_SIZE; i++) + for (i = 0; i < LPC17_40_PROGMEM_SECTOR_SIZE; i++) { if (p[i] != 0xffu) { @@ -355,7 +355,7 @@ ssize_t up_progmem_ispageerased(size_t page) } } - return (ssize_t)(LPC17_PROGMEM_SECTOR_SIZE - i); + return (ssize_t)(LPC17_40_PROGMEM_SECTOR_SIZE - i); } /****************************************************************************** @@ -392,24 +392,24 @@ ssize_t up_progmem_write(size_t addr, FAR const void *buf, size_t count) size_t page; uint32_t rc; - if (count % LPC17_PROGMEM_PAGE_SIZE) + if (count % LPC17_40_PROGMEM_PAGE_SIZE) { return -EINVAL; } - page = up_progmem_getpage(addr) / LPC17_PROGMEM_PAGES_PER_SECTOR + - LPC17_PROGMEM_START_SECTOR; + page = up_progmem_getpage(addr) / LPC17_40_PROGMEM_PAGES_PER_SECTOR + + LPC17_40_PROGMEM_START_SECTOR; - rc = lpc17_iap_prepare_sector_for_write_operation((uint32_t)page); + rc = lpc17_40_iap_prepare_sector_for_write_operation((uint32_t)page); - if (rc != LPC17_IAP_RC_CMD_SUCCESS) + if (rc != LPC17_40_IAP_RC_CMD_SUCCESS) { return -EIO; } - rc = lpc17_iap_copy_ram_to_flash((void *)addr, buf, count); + rc = lpc17_40_iap_copy_ram_to_flash((void *)addr, buf, count); - if (rc != LPC17_IAP_RC_CMD_SUCCESS) + if (rc != LPC17_40_IAP_RC_CMD_SUCCESS) { return -EIO; } diff --git a/arch/arm/src/lpc17xx/lpc17_progmem.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h similarity index 58% rename from arch/arm/src/lpc17xx/lpc17_progmem.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h index fd826273c3f..d2b158c3bc0 100644 --- a/arch/arm/src/lpc17xx/lpc17_progmem.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h @@ -1,5 +1,5 @@ /****************************************************************************** - * arch/arm/src/lpc17xx/lpc17_progmem.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c * * Copyright (C) 2018 Michael Jung. All rights reserved. * Author: Michael Jung @@ -33,8 +33,8 @@ * ******************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PROGMEM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_PROGMEM_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_PROGMEM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_PROGMEM_H /****************************************************************************** * See NXP UM10360 LPC176x/5x User manual, Rev 4.1, Chapter 32: LPC176x/5x @@ -61,79 +61,79 @@ /* The first 16 sectors are 4kB in size and thus not supported as progmem. */ -#define LPC17_FLASH_NUM_4K_SECTORS 16 +#define LPC17_40_FLASH_NUM_4K_SECTORS 16 /* The number of 32kB sectors depends on the target device's flash size */ -#define LPC17_FLASH_NUM_32K_SECTORS \ - ((LPC17_FLASH_SIZE - LPC17_FLASH_NUM_4K_SECTORS * 4096) / 32768) +#define LPC17_40_FLASH_NUM_32K_SECTORS \ + ((LPC17_40_FLASH_SIZE - LPC17_40_FLASH_NUM_4K_SECTORS * 4096) / 32768) /* The number of 32kB sectors to be used for progmem is configurable. The * sectors at the end of the flash are used for progmem, the rest is left * for code and data. */ -#define LPC17_PROGMEM_START_SECTOR \ - (LPC17_FLASH_NUM_4K_SECTORS + LPC17_FLASH_NUM_32K_SECTORS - \ - CONFIG_LPC17_PROGMEM_NSECTORS) +#define LPC17_40_PROGMEM_START_SECTOR \ + (LPC17_40_FLASH_NUM_4K_SECTORS + LPC17_40_FLASH_NUM_32K_SECTORS - \ + CONFIG_LPC17_40_PROGMEM_NSECTORS) /* Base address of the flash segment used for progmem. */ -#define LPC17_PROGMEM_START_ADDR \ - (LPC17_FLASH_NUM_4K_SECTORS * 4096 + \ - (LPC17_PROGMEM_START_SECTOR - LPC17_FLASH_NUM_4K_SECTORS) * 32768) +#define LPC17_40_PROGMEM_START_ADDR \ + (LPC17_40_FLASH_NUM_4K_SECTORS * 4096 + \ + (LPC17_40_PROGMEM_START_SECTOR - LPC17_40_FLASH_NUM_4K_SECTORS) * 32768) /* Size of the flash segment used for progmem. */ -#define LPC17_PROGMEM_SIZE (CONFIG_LPC17_PROGMEM_NSECTORS * 32768) +#define LPC17_40_PROGMEM_SIZE (CONFIG_LPC17_40_PROGMEM_NSECTORS * 32768) /* Size of a read/write page. */ -#define LPC17_PROGMEM_PAGE_SIZE 256 +#define LPC17_40_PROGMEM_PAGE_SIZE 256 /* Total number of read/write pages. */ -#define LPC17_PROGMEM_NUM_PAGES (LPC17_PROGMEM_SIZE / LPC17_PROGMEM_PAGE_SIZE) +#define LPC17_40_PROGMEM_NUM_PAGES (LPC17_40_PROGMEM_SIZE / LPC17_40_PROGMEM_PAGE_SIZE) /* Size of an erase page. This driver only supports the 32kB sectors. */ -#define LPC17_PROGMEM_SECTOR_SIZE 32768 +#define LPC17_40_PROGMEM_SECTOR_SIZE 32768 /* Number of read/write pages per erase page. */ -#define LPC17_PROGMEM_PAGES_PER_SECTOR \ - (LPC17_PROGMEM_SECTOR_SIZE / LPC17_PROGMEM_PAGE_SIZE) +#define LPC17_40_PROGMEM_PAGES_PER_SECTOR \ + (LPC17_40_PROGMEM_SECTOR_SIZE / LPC17_40_PROGMEM_PAGE_SIZE) /* LPC17 entry point for In-Application-Programming boot rom service function */ -#define LPC17_IAP_ENTRY_ADDR 0x1fff1ff1 +#define LPC17_40_IAP_ENTRY_ADDR 0x1fff1ff1 /* The IAP Commands required for progmem */ -#define LPC17_IAP_CMD_PREPARE_SECTORS_FOR_WRITE_OPERATION 50 -#define LPC17_IAP_CMD_COPY_RAM_TO_FLASH 51 -#define LPC17_IAP_CMD_ERASE_SECTORS 52 +#define LPC17_40_IAP_CMD_PREPARE_SECTORS_FOR_WRITE_OPERATION 50 +#define LPC17_40_IAP_CMD_COPY_RAM_TO_FLASH 51 +#define LPC17_40_IAP_CMD_ERASE_SECTORS 52 /* IAP return codes */ -#define LPC17_IAP_RC_CMD_SUCCESS 0 -#define LPC17_IAP_RC_INVALID_CMD 1 -#define LPC17_IAP_RC_SCR_ADDR_ERROR 2 -#define LPC17_IAP_RC_DST_ADDR_ERROR 3 -#define LPC17_IAP_RC_SRC_ADDR_NOT_MAPPED 4 -#define LPC17_IAP_RC_DST_ADDR_NOT_MAPPED 5 -#define LPC17_IAP_RC_COUNT_ERROR 6 -#define LPC17_IAP_RC_INVALID_SECTOR 7 -#define LPC17_IAP_RC_SECTOR_NOT_BLANK 8 -#define LPC17_IAP_RC_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION 9 -#define LPC17_IAP_RC_COMPARE_ERROR 10 -#define LPC17_IAP_RC_BUSY 11 -#define LPC17_IAP_RC_PARAM_ERROR 12 -#define LPC17_IAP_RC_ADDR_ERROR 13 -#define LPC17_IAP_RC_ADDR_NOT_MAPPED 14 -#define LPC17_IAP_RC_CMD_LOCKED 15 -#define LPC17_IAP_RC_INVALID_CODE 16 -#define LPC17_IAP_RC_INVALID_BAUD_RATE 17 -#define LPC17_IAP_RC_INVALID_STOP_BIT 18 -#define LPC17_IAP_RC_CODE_READ_PROTECTION_ENABLED 19 +#define LPC17_40_IAP_RC_CMD_SUCCESS 0 +#define LPC17_40_IAP_RC_INVALID_CMD 1 +#define LPC17_40_IAP_RC_SCR_ADDR_ERROR 2 +#define LPC17_40_IAP_RC_DST_ADDR_ERROR 3 +#define LPC17_40_IAP_RC_SRC_ADDR_NOT_MAPPED 4 +#define LPC17_40_IAP_RC_DST_ADDR_NOT_MAPPED 5 +#define LPC17_40_IAP_RC_COUNT_ERROR 6 +#define LPC17_40_IAP_RC_INVALID_SECTOR 7 +#define LPC17_40_IAP_RC_SECTOR_NOT_BLANK 8 +#define LPC17_40_IAP_RC_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION 9 +#define LPC17_40_IAP_RC_COMPARE_ERROR 10 +#define LPC17_40_IAP_RC_BUSY 11 +#define LPC17_40_IAP_RC_PARAM_ERROR 12 +#define LPC17_40_IAP_RC_ADDR_ERROR 13 +#define LPC17_40_IAP_RC_ADDR_NOT_MAPPED 14 +#define LPC17_40_IAP_RC_CMD_LOCKED 15 +#define LPC17_40_IAP_RC_INVALID_CODE 16 +#define LPC17_40_IAP_RC_INVALID_BAUD_RATE 17 +#define LPC17_40_IAP_RC_INVALID_STOP_BIT 18 +#define LPC17_40_IAP_RC_CODE_READ_PROTECTION_ENABLED 19 -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PROGMEM_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_PROGMEM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c similarity index 84% rename from arch/arm/src/lpc17xx/lpc17_pwm.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c index dbbc8de2cd0..a44cfbc3c34 100644 --- a/arch/arm/src/lpc17xx/lpc17_pwm.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_pwm.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,17 +54,17 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_pwm.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_pwm.h" #include "hardware/lpc176x_pinconfig.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lpc176x_gpio.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_LPC17_PWM1) +#if defined(CONFIG_LPC17_40_PWM1) /**************************************************************************** * Pre-processor Definitions @@ -111,7 +111,7 @@ ****************************************************************************/ /* This structure represents the state of one PWM timer */ -struct lpc17_pwmtimer_s +struct lpc17_40_pwmtimer_s { FAR const struct pwm_ops_s *ops; /* PWM operations */ uint8_t timid; /* Timer ID {0,...,7} */ @@ -128,18 +128,18 @@ struct lpc17_pwmtimer_s ****************************************************************************/ /* Register access */ -static uint32_t pwm_getreg(struct lpc17_pwmtimer_s *priv, int offset); -static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value); +static uint32_t pwm_getreg(struct lpc17_40_pwmtimer_s *priv, int offset); +static void pwm_putreg(struct lpc17_40_pwmtimer_s *priv, int offset, uint32_t value); #ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg); +static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv, FAR const char *msg); #else # define pwm_dumpregs(priv,msg) #endif /* Timer management */ -static int pwm_timer(FAR struct lpc17_pwmtimer_s *priv, +static int pwm_timer(FAR struct lpc17_40_pwmtimer_s *priv, FAR const struct pwm_info_s *info); /* PWM driver methods */ @@ -168,14 +168,14 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_LPC17_PWM1 -static struct lpc17_pwmtimer_s g_pwm1dev = +#ifdef CONFIG_LPC17_40_PWM1 +static struct lpc17_40_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, .timid = 1, - .channel = CONFIG_LPC17_PWM1_PIN, + .channel = CONFIG_LPC17_40_PWM1_PIN, .timtype = TIMTYPE_TIM1, - .base = LPC17_PWM1_BASE, + .base = LPC17_40_PWM1_BASE, .pincfg = GPIO_PWM1p1_1, .pclk = (0x1 << 12), }; @@ -200,7 +200,7 @@ static struct lpc17_pwmtimer_s g_pwm1dev = * ****************************************************************************/ -static uint32_t pwm_getreg(struct lpc17_pwmtimer_s *priv, int offset) +static uint32_t pwm_getreg(struct lpc17_40_pwmtimer_s *priv, int offset) { return getreg32(priv->base + offset); } @@ -220,7 +220,7 @@ static uint32_t pwm_getreg(struct lpc17_pwmtimer_s *priv, int offset) * ****************************************************************************/ -static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value) +static void pwm_putreg(struct lpc17_40_pwmtimer_s *priv, int offset, uint32_t value) { putreg32(value, priv->base + offset); } @@ -240,29 +240,29 @@ static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value ****************************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg) +static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv, FAR const char *msg) { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, LPC17_PWM_MR0_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR1_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR2_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR3_OFFSET)); -#if defined(CONFIG_LPC17_PWM1) + pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); +#if defined(CONFIG_LPC17_40_PWM1) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, LPC17_PWM_MR0_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR1_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR2_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR3_OFFSET)); + pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, LPC17_PWM_MR2_OFFSET), - pwm_getreg(priv, LPC17_PWM_MR3_OFFSET)); + pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); } } #endif @@ -282,19 +282,19 @@ static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg) * ****************************************************************************/ -static int pwm_timer(FAR struct lpc17_pwmtimer_s *priv, +static int pwm_timer(FAR struct lpc17_40_pwmtimer_s *priv, FAR const struct pwm_info_s *info) { irqstate_t flags; flags = enter_critical_section(); - putreg32(info->frequency, LPC17_PWM1_MR0); /* Set PWMMR0 = number of counts */ - putreg32(info->duty, LPC17_PWM1_MR1); /* Set PWM cycle */ + putreg32(info->frequency, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */ + putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */ - putreg32(LER0_EN | LER3_EN, LPC17_PWM1_LER); /* Load Shadow register contents */ - putreg32(PWMENA1, LPC17_PWM1_PCR); /* Enable PWM outputs */ - putreg32(TCR_CNT_EN | TCR_PWM_EN, LPC17_PWM1_TCR); /* Enable PWM Timer */ + putreg32(LER0_EN | LER3_EN, LPC17_40_PWM1_LER); /* Load Shadow register contents */ + putreg32(PWMENA1, LPC17_40_PWM1_PCR); /* Enable PWM outputs */ + putreg32(TCR_CNT_EN | TCR_PWM_EN, LPC17_40_PWM1_TCR); /* Enable PWM Timer */ leave_critical_section(flags); pwm_dumpregs(priv, "After starting"); @@ -316,7 +316,7 @@ static int pwm_timer(FAR struct lpc17_pwmtimer_s *priv, * ****************************************************************************/ -static int pwm_interrupt(struct lpc17_pwmtimer_s *priv) +static int pwm_interrupt(struct lpc17_40_pwmtimer_s *priv) { uint16_t regval; @@ -367,7 +367,7 @@ static int pwm_tim1interrupt(int irq, void *context, FAR void *arg) * ****************************************************************************/ -static void pwm_set_apb_clock(FAR struct lpc17_pwmtimer_s *priv, bool on) +static void pwm_set_apb_clock(FAR struct lpc17_40_pwmtimer_s *priv, bool on) { uint32_t en_bit; uint32_t regaddr; @@ -376,7 +376,7 @@ static void pwm_set_apb_clock(FAR struct lpc17_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_LPC17_PWM1 +#ifdef CONFIG_LPC17_40_PWM1 case 1: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; @@ -419,7 +419,7 @@ static void pwm_set_apb_clock(FAR struct lpc17_pwmtimer_s *priv, bool on) static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev; + FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev; irqstate_t flags; uint32_t regval; @@ -427,24 +427,24 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) /* Power on the pwm peripheral */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCPWM1; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Select clock for the pwm peripheral */ - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~(0x3 << 12); /* PCLK_MC peripheral clk = CCLK = 12.5 MHz */ regval |= (0x1 << 12); /* PCLK_MC peripheral clk = CCLK = 12.5 MHz */ - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); priv->pclk = (0x1 << 12); /* Configure the output pin */ - lpc17_configgpio(GPIO_PWM1p1_1); + lpc17_40_configgpio(GPIO_PWM1p1_1); - putreg32(1, LPC17_PWM1_PR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(1 << 1, LPC17_PWM1_MCR); /* Reset on match register MR0 */ + putreg32(1, LPC17_40_PWM1_PR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(1 << 1, LPC17_40_PWM1_MCR); /* Reset on match register MR0 */ leave_critical_section(flags); pwm_dumpgpio(priv->pincfg, "PWM setup"); @@ -469,7 +469,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev; + FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev; uint32_t pincfg; pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); @@ -497,7 +497,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) { - FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev; + FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev; return pwm_timer(priv, info); } @@ -522,7 +522,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev; + FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev; uint32_t resetbit; uint32_t regaddr; uint32_t regval; @@ -542,7 +542,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_LPC17_PWM1 +#ifdef CONFIG_LPC17_40_PWM1 case 1: break; #endif @@ -578,7 +578,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO - FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev; + FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev; /* There are no platform-specific ioctl commands */ @@ -592,7 +592,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg ****************************************************************************/ /**************************************************************************** - * Name: lpc17_pwminitialize + * Name: lpc17_40_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -608,15 +608,15 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg * ****************************************************************************/ -FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer) +FAR struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer) { - FAR struct lpc17_pwmtimer_s *lower; + FAR struct lpc17_40_pwmtimer_s *lower; pwminfo("TIM%d\n", timer); switch (timer) { -#ifdef CONFIG_LPC17_PWM1 +#ifdef CONFIG_LPC17_40_PWM1 case 0: lower = &g_pwm1dev; @@ -633,4 +633,4 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer) return (FAR struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_LPC17_TIMn_PWM, n = 1,...,14 */ +#endif /* CONFIG_LPC17_40_TIMn_PWM, n = 1,...,14 */ diff --git a/arch/arm/src/lpc17xx/lpc17_wdt.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.h similarity index 91% rename from arch/arm/src/lpc17xx/lpc17_wdt.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.h index eb4d60834e3..6bcf499029a 100644 --- a/arch/arm/src/lpc17xx/lpc17_wdt.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_wdt.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,16 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_PWM_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_PWM_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_wdt.h" +#include "hardware/lpc17_40_pwm.h" +#include "hardware/lpc17_40_mcpwm.h" /************************************************************************************ * Pre-processor Definitions @@ -59,4 +60,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_PWM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_rit.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_qei.h similarity index 92% rename from arch/arm/src/lpc17xx/lpc17_rit.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_qei.h index 99611ca5a37..a1758a9637c 100644 --- a/arch/arm/src/lpc17xx/lpc17_rit.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_qei.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_rit.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_qei.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_QEI_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_QEI_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_rit.h" +#include "hardware/lpc17_40_qei.h" /************************************************************************************ * Pre-processor Definitions @@ -59,4 +59,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_QEI_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_rit.h similarity index 92% rename from arch/arm/src/lpc17xx/lpc17_pwm.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_rit.h index 34fba32bdd7..d5d95dc5111 100644 --- a/arch/arm/src/lpc17xx/lpc17_pwm.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_rit.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_pwm.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_rit.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,16 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_RIT_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_RIT_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_pwm.h" -#include "hardware/lpc17_mcpwm.h" +#include "hardware/lpc17_40_rit.h" /************************************************************************************ * Pre-processor Definitions @@ -60,4 +59,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_RIT_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_rtc.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_rtc.h similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_rtc.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_rtc.h index 80523759b67..a43f5323d05 100644 --- a/arch/arm/src/lpc17xx/lpc17_rtc.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_rtc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_rtc.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_rtc.h * * Copyright (C) 2010, 2012-2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_RTC_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_RTC_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_rtc.h" +#include "hardware/lpc17_40_rtc.h" /************************************************************************************ * Pre-processor Definitions @@ -64,7 +64,7 @@ typedef void (*alarmcb_t)(void); ************************************************************************************/ /************************************************************************************ - * Name: lpc17_rtc_setalarm + * Name: lpc17_40_rtc_setalarm * * Description: * Set up an alarm. @@ -80,7 +80,7 @@ typedef void (*alarmcb_t)(void); #ifdef CONFIG_RTC_ALARM struct timespec; -int lpc17_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); +int lpc17_40_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); #endif -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_RTC_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c similarity index 74% rename from arch/arm/src/lpc17xx/lpc17_sdcard.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c index 04e48c44e0a..6f53a902de9 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_sdcard.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c * * Copyright (C) 2013-2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -61,14 +61,14 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_gpdma.h" -#include "lpc17_gpio.h" -#include "lpc17_sdcard.h" +#include "lpc17_40_gpdma.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_sdcard.h" -#include "hardware/lpc17_syscon.h" -#include "hardware/lpc17_pinconfig.h" +#include "hardware/lpc17_40_syscon.h" +#include "hardware/lpc17_40_pinconfig.h" -#ifdef CONFIG_LPC17_SDCARD +#ifdef CONFIG_LPC17_40_SDCARD /**************************************************************************** * Pre-processor Definitions @@ -78,9 +78,9 @@ /* Required system configuration options: * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem - * initialization. Required if CONFIG_LPC17_SDCARD_DMA is enabled. - * CONFIG_LPC17_GPDMA - Enable LPC17XX GPDMA support. Required if - * CONFIG_LPC17_SDCARD_DMA is enabled + * initialization. Required if CONFIG_LPC17_40_SDCARD_DMA is enabled. + * CONFIG_LPC17_40_GPDMA - Enable LPC17XX_40XX GPDMA support. Required if + * CONFIG_LPC17_40_SDCARD_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * * Driver-specific configuration options: @@ -88,24 +88,24 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SD card bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_LPC17_SDCARD_DMA - Enable SD card DMA. This is a marginally optional. + * CONFIG_LPC17_40_SDCARD_DMA - Enable SD card DMA. This is a marginally optional. * For most usages, SD accesses will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. - * CONFIG_LPC17_SDCARD_WIDTH_D1_ONLY - This may be selected to force the + * CONFIG_LPC17_40_SDCARD_WIDTH_D1_ONLY - This may be selected to force the * driver operate with only a single data line (the default is to use * all 4 SD data lines). * CONFIG_DEBUG_MEMCARD_* - Enables some very low-level debug output * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO */ -#ifndef CONFIG_LPC17_SDCARD_DMA +#ifndef CONFIG_LPC17_40_SDCARD_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# ifndef CONFIG_LPC17_GPDMA -# error "CONFIG_LPC17_SDCARD_DMA support requires CONFIG_LPC17_GPDMA" +# ifndef CONFIG_LPC17_40_GPDMA +# error "CONFIG_LPC17_40_SDCARD_DMA support requires CONFIG_LPC17_40_GPDMA" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_LPC17_SDCARD_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_LPC17_40_SDCARD_DMA # endif #endif @@ -120,7 +120,7 @@ * SDCARD_MMCXFR_CLKDIV, and SDCARD_SDXFR_CLKDIV. */ -#define LPC17_CLCKCR_INIT (SDCARD_INIT_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) +#define LPC17_40_CLCKCR_INIT (SDCARD_INIT_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) #define SDCARD_CLOCK_MMCXFR (SDCARD_MMCXFR_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) #define SDCARD_CLOCK_SDXFR (SDCARD_SDXFR_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) #define SDCARD_CLOCK_SDWIDEXFR (SDCARD_SDXFR_CLKDIV | SDCARD_CLOCK_WIDBUS_D4) @@ -214,7 +214,7 @@ /* Register logging support */ #ifdef CONFIG_DEBUG_MEMCARD_INFO -# ifdef CONFIG_LPC17_SDCARD_DMA +# ifdef CONFIG_LPC17_40_SDCARD_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -233,13 +233,13 @@ * Private Types ****************************************************************************/ -/* This structure defines the state of the LPC17XX SD card interface */ +/* This structure defines the state of the LPC17XX_40XX SD card interface */ -struct lpc17_dev_s +struct lpc17_40_dev_s { struct sdio_dev_s dev; /* Standard, base SD card interface */ - /* LPC17XX-specific extensions */ + /* LPC17XX_40XX-specific extensions */ /* Event support */ sem_t waitsem; /* Implements event waiting */ @@ -265,7 +265,7 @@ struct lpc17_dev_s /* DMA data transfer support */ bool widebus; /* Required for DMA support */ -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA volatile uint8_t xfrflags; /* Used to synchronize SD card and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -275,7 +275,7 @@ struct lpc17_dev_s /* Register logging support */ #ifdef CONFIG_DEBUG_MEMCARD_INFO -struct lpc17_sdcard_regs_s +struct lpc17_40_sdcard_regs_s { uint8_t pwr; uint16_t clkcr; @@ -288,11 +288,11 @@ struct lpc17_sdcard_regs_s uint32_t fifocnt; }; -struct lpc17_sampleregs_s +struct lpc17_40_sampleregs_s { - struct lpc17_sdcard_regs_s sdcard; -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_SDCARD_DMA) - struct lpc17_dmaregs_s dma; + struct lpc17_40_sdcard_regs_s sdcard; +#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_40_SDCARD_DMA) + struct lpc17_40_dmaregs_s dma; #endif }; #endif @@ -303,153 +303,153 @@ struct lpc17_sampleregs_s /* Low-level helpers ********************************************************/ -static void lpc17_takesem(struct lpc17_dev_s *priv); -#define lpc17_givesem(priv) (nxsem_post(&priv->waitsem)) -static inline void lpc17_setclock(uint32_t clkcr); -static void lpc17_configwaitints(struct lpc17_dev_s *priv, uint32_t waitmask, +static void lpc17_40_takesem(struct lpc17_40_dev_s *priv); +#define lpc17_40_givesem(priv) (nxsem_post(&priv->waitsem)) +static inline void lpc17_40_setclock(uint32_t clkcr); +static void lpc17_40_configwaitints(struct lpc17_40_dev_s *priv, uint32_t waitmask, sdio_eventset_t waitevents, sdio_eventset_t wkupevents); -static void lpc17_configxfrints(struct lpc17_dev_s *priv, uint32_t xfrmask); -static void lpc17_setpwrctrl(uint32_t pwrctrl); -static inline uint32_t lpc17_getpwrctrl(void); +static void lpc17_40_configxfrints(struct lpc17_40_dev_s *priv, uint32_t xfrmask); +static void lpc17_40_setpwrctrl(uint32_t pwrctrl); +static inline uint32_t lpc17_40_getpwrctrl(void); /* DMA Helpers **************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_sampleinit(void); -static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs); -static void lpc17_sample(struct lpc17_dev_s *priv, int index); -static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg); -static void lpc17_dumpsample(struct lpc17_dev_s *priv, - struct lpc17_sampleregs_s *regs, const char *msg); -static void lpc17_dumpsamples(struct lpc17_dev_s *priv); +static void lpc17_40_sampleinit(void); +static void lpc17_40_sdcard_sample(struct lpc17_40_sdcard_regs_s *regs); +static void lpc17_40_sample(struct lpc17_40_dev_s *priv, int index); +static void lpc17_40_sdcard_dump(struct lpc17_40_sdcard_regs_s *regs, const char *msg); +static void lpc17_40_dumpsample(struct lpc17_40_dev_s *priv, + struct lpc17_40_sampleregs_s *regs, const char *msg); +static void lpc17_40_dumpsamples(struct lpc17_40_dev_s *priv); #else -# define lpc17_sampleinit() -# define lpc17_sample(priv,index) -# define lpc17_dumpsamples(priv) +# define lpc17_40_sampleinit() +# define lpc17_40_sample(priv,index) +# define lpc17_40_dumpsamples(priv) #endif -#ifdef CONFIG_LPC17_SDCARD_DMA -static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status); +#ifdef CONFIG_LPC17_40_SDCARD_DMA +static void lpc17_40_dmacallback(DMA_HANDLE handle, void *arg, int status); #endif /* Data Transfer Helpers ****************************************************/ -static uint8_t lpc17_log2(uint16_t value); -static void lpc17_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl); -static void lpc17_datadisable(void); -static void lpc17_sendfifo(struct lpc17_dev_s *priv); -static void lpc17_recvfifo(struct lpc17_dev_s *priv); -static void lpc17_eventtimeout(int argc, uint32_t arg); -static void lpc17_endwait(struct lpc17_dev_s *priv, sdio_eventset_t wkupevent); -static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupevent); +static uint8_t lpc17_40_log2(uint16_t value); +static void lpc17_40_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl); +static void lpc17_40_datadisable(void); +static void lpc17_40_sendfifo(struct lpc17_40_dev_s *priv); +static void lpc17_40_recvfifo(struct lpc17_40_dev_s *priv); +static void lpc17_40_eventtimeout(int argc, uint32_t arg); +static void lpc17_40_endwait(struct lpc17_40_dev_s *priv, sdio_eventset_t wkupevent); +static void lpc17_40_endtransfer(struct lpc17_40_dev_s *priv, sdio_eventset_t wkupevent); /* Interrupt Handling *******************************************************/ -static int lpc17_interrupt(int irq, void *context, FAR void *arg); +static int lpc17_40_interrupt(int irq, void *context, FAR void *arg); /* SD Card Interface Methods ************************************************/ /* Mutual exclusion */ #ifdef CONFIG_SDIO_MUXBUS -static int lpc17_lock(FAR struct sdio_dev_s *dev, bool lock); +static int lpc17_40_lock(FAR struct sdio_dev_s *dev, bool lock); #endif /* Initialization/setup */ -static void lpc17_reset(FAR struct sdio_dev_s *dev); -static sdio_capset_t lpc17_capabilities(FAR struct sdio_dev_s *dev); -static uint8_t lpc17_status(FAR struct sdio_dev_s *dev); -static void lpc17_widebus(FAR struct sdio_dev_s *dev, bool enable); -static void lpc17_clock(FAR struct sdio_dev_s *dev, +static void lpc17_40_reset(FAR struct sdio_dev_s *dev); +static sdio_capset_t lpc17_40_capabilities(FAR struct sdio_dev_s *dev); +static uint8_t lpc17_40_status(FAR struct sdio_dev_s *dev); +static void lpc17_40_widebus(FAR struct sdio_dev_s *dev, bool enable); +static void lpc17_40_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate); -static int lpc17_attach(FAR struct sdio_dev_s *dev); +static int lpc17_40_attach(FAR struct sdio_dev_s *dev); /* Command/Status/Data Transfer */ -static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, +static int lpc17_40_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg); -static int lpc17_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, +static int lpc17_40_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); -static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, +static int lpc17_40_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, uint32_t nbytes); -static int lpc17_cancel(FAR struct sdio_dev_s *dev); +static int lpc17_40_cancel(FAR struct sdio_dev_s *dev); -static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); -static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, +static int lpc17_40_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); +static int lpc17_40_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort); -static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, +static int lpc17_40_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]); -static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, +static int lpc17_40_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort); -static int lpc17_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, +static int lpc17_40_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl); /* EVENT handler */ -static void lpc17_waitenable(FAR struct sdio_dev_s *dev, +static void lpc17_40_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset); static sdio_eventset_t - lpc17_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout); -static void lpc17_callbackenable(FAR struct sdio_dev_s *dev, + lpc17_40_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout); +static void lpc17_40_callbackenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset); -static int lpc17_registercallback(FAR struct sdio_dev_s *dev, +static int lpc17_40_registercallback(FAR struct sdio_dev_s *dev, worker_t callback, void *arg); /* DMA */ -#ifdef CONFIG_LPC17_SDCARD_DMA -static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, +#ifdef CONFIG_LPC17_40_SDCARD_DMA +static int lpc17_40_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t buflen); -static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, +static int lpc17_40_dmasendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, size_t buflen); #endif /* Initialization/uninitialization/reset ************************************/ -static void lpc17_callback(void *arg); -static void lpc17_default(void); +static void lpc17_40_callback(void *arg); +static void lpc17_40_default(void); /**************************************************************************** * Private Data ****************************************************************************/ -struct lpc17_dev_s g_scard_dev = +struct lpc17_40_dev_s g_scard_dev = { .dev = { #ifdef CONFIG_SDIO_MUXBUS - .lock = lpc17_lock, + .lock = lpc17_40_lock, #endif - .reset = lpc17_reset, - .capabilities = lpc17_capabilities, - .status = lpc17_status, - .widebus = lpc17_widebus, - .clock = lpc17_clock, - .attach = lpc17_attach, - .sendcmd = lpc17_sendcmd, - .recvsetup = lpc17_recvsetup, - .sendsetup = lpc17_sendsetup, - .cancel = lpc17_cancel, - .waitresponse = lpc17_waitresponse, - .recvR1 = lpc17_recvshortcrc, - .recvR2 = lpc17_recvlong, - .recvR3 = lpc17_recvshort, - .recvR4 = lpc17_recvnotimpl, - .recvR5 = lpc17_recvnotimpl, - .recvR6 = lpc17_recvshortcrc, - .recvR7 = lpc17_recvshort, - .waitenable = lpc17_waitenable, - .eventwait = lpc17_eventwait, - .callbackenable = lpc17_callbackenable, - .registercallback = lpc17_registercallback, + .reset = lpc17_40_reset, + .capabilities = lpc17_40_capabilities, + .status = lpc17_40_status, + .widebus = lpc17_40_widebus, + .clock = lpc17_40_clock, + .attach = lpc17_40_attach, + .sendcmd = lpc17_40_sendcmd, + .recvsetup = lpc17_40_recvsetup, + .sendsetup = lpc17_40_sendsetup, + .cancel = lpc17_40_cancel, + .waitresponse = lpc17_40_waitresponse, + .recvR1 = lpc17_40_recvshortcrc, + .recvR2 = lpc17_40_recvlong, + .recvR3 = lpc17_40_recvshort, + .recvR4 = lpc17_40_recvnotimpl, + .recvR5 = lpc17_40_recvnotimpl, + .recvR6 = lpc17_40_recvshortcrc, + .recvR7 = lpc17_40_recvshort, + .waitenable = lpc17_40_waitenable, + .eventwait = lpc17_40_eventwait, + .callbackenable = lpc17_40_callbackenable, + .registercallback = lpc17_40_registercallback, #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_LPC17_SDCARD_DMA - .dmarecvsetup = lpc17_dmarecvsetup, - .dmasendsetup = lpc17_dmasendsetup, +#ifdef CONFIG_LPC17_40_SDCARD_DMA + .dmarecvsetup = lpc17_40_dmarecvsetup, + .dmasendsetup = lpc17_40_dmasendsetup, #else - .dmarecvsetup = lpc17_recvsetup, - .dmasendsetup = lpc17_sendsetup, + .dmarecvsetup = lpc17_40_recvsetup, + .dmasendsetup = lpc17_40_sendsetup, #endif #endif }, @@ -458,7 +458,7 @@ struct lpc17_dev_s g_scard_dev = /* Register logging support */ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static struct lpc17_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; +static struct lpc17_40_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif /**************************************************************************** @@ -469,7 +469,7 @@ static struct lpc17_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; * Low-level Helpers ****************************************************************************/ /**************************************************************************** - * Name: lpc17_takesem + * Name: lpc17_40_takesem * * Description: * Take the wait semaphore (handling false alarm wakeups due to the receipt @@ -483,7 +483,7 @@ static struct lpc17_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; * ****************************************************************************/ -static void lpc17_takesem(struct lpc17_dev_s *priv) +static void lpc17_40_takesem(struct lpc17_40_dev_s *priv) { int ret; @@ -503,7 +503,7 @@ static void lpc17_takesem(struct lpc17_dev_s *priv) } /**************************************************************************** - * Name: lpc17_setclock + * Name: lpc17_40_setclock * * Description: * Modify oft-changed bits in the CLKCR register. Only the following bit- @@ -520,9 +520,9 @@ static void lpc17_takesem(struct lpc17_dev_s *priv) * ****************************************************************************/ -static inline void lpc17_setclock(uint32_t clkcr) +static inline void lpc17_40_setclock(uint32_t clkcr) { - uint32_t regval = getreg32(LPC17_SDCARD_CLOCK); + uint32_t regval = getreg32(LPC17_40_SDCARD_CLOCK); /* Clear CLKDIV, PWRSAV, BYPASS, and WIDBUS bits */ @@ -537,14 +537,14 @@ static inline void lpc17_setclock(uint32_t clkcr) SDCARD_CLOCK_CLKEN); regval |= clkcr; - putreg32(regval, LPC17_SDCARD_CLOCK); + putreg32(regval, LPC17_40_SDCARD_CLOCK); mcinfo("CLKCR: %08x PWR: %08x\n", - getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR)); + getreg32(LPC17_40_SDCARD_CLOCK), getreg32(LPC17_40_SDCARD_PWR)); } /**************************************************************************** - * Name: lpc17_configwaitints + * Name: lpc17_40_configwaitints * * Description: * Enable/disable SD card interrupts needed to suport the wait function @@ -560,7 +560,7 @@ static inline void lpc17_setclock(uint32_t clkcr) * ****************************************************************************/ -static void lpc17_configwaitints(struct lpc17_dev_s *priv, uint32_t waitmask, +static void lpc17_40_configwaitints(struct lpc17_40_dev_s *priv, uint32_t waitmask, sdio_eventset_t waitevents, sdio_eventset_t wkupevent) { @@ -574,15 +574,15 @@ static void lpc17_configwaitints(struct lpc17_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA priv->xfrflags = 0; #endif - putreg32(priv->xfrmask | priv->waitmask, LPC17_SDCARD_MASK0); + putreg32(priv->xfrmask | priv->waitmask, LPC17_40_SDCARD_MASK0); leave_critical_section(flags); } /**************************************************************************** - * Name: lpc17_configxfrints + * Name: lpc17_40_configxfrints * * Description: * Enable SD card interrupts needed to support the data transfer event @@ -596,17 +596,17 @@ static void lpc17_configwaitints(struct lpc17_dev_s *priv, uint32_t waitmask, * ****************************************************************************/ -static void lpc17_configxfrints(struct lpc17_dev_s *priv, uint32_t xfrmask) +static void lpc17_40_configxfrints(struct lpc17_40_dev_s *priv, uint32_t xfrmask) { irqstate_t flags; flags = enter_critical_section(); priv->xfrmask = xfrmask; - putreg32(priv->xfrmask | priv->waitmask, LPC17_SDCARD_MASK0); + putreg32(priv->xfrmask | priv->waitmask, LPC17_40_SDCARD_MASK0); leave_critical_section(flags); } /**************************************************************************** - * Name: lpc17_setpwrctrl + * Name: lpc17_40_setpwrctrl * * Description: * Change the PWRCTRL field of the SD card POWER register to turn the SD card @@ -620,7 +620,7 @@ static void lpc17_configxfrints(struct lpc17_dev_s *priv, uint32_t xfrmask) * ****************************************************************************/ -static void lpc17_setpwrctrl(uint32_t pwrctrl) +static void lpc17_40_setpwrctrl(uint32_t pwrctrl) { uint32_t regval; @@ -628,14 +628,14 @@ static void lpc17_setpwrctrl(uint32_t pwrctrl) * side-effect, clear the OPENDRAIN and ROD bits as well. */ - regval = getreg32(LPC17_SDCARD_PWR); + regval = getreg32(LPC17_40_SDCARD_PWR); regval &= ~(SDCARD_PWR_CTRL_MASK | SDCARD_PWR_OPENDRAIN | SDCARD_PWR_ROD); regval |= pwrctrl; - putreg32(regval, LPC17_SDCARD_PWR); + putreg32(regval, LPC17_40_SDCARD_PWR); } /**************************************************************************** - * Name: lpc17_getpwrctrl + * Name: lpc17_40_getpwrctrl * * Description: * Return the current value of the the PWRCTRL field of the SD card P @@ -650,11 +650,11 @@ static void lpc17_setpwrctrl(uint32_t pwrctrl) * ****************************************************************************/ -static inline uint32_t lpc17_getpwrctrl(void) +static inline uint32_t lpc17_40_getpwrctrl(void) { /* Extract and return the PWRCTRL field of the PWR register. */ - return getreg32(LPC17_SDCARD_PWR) & SDCARD_PWR_CTRL_MASK; + return getreg32(LPC17_40_SDCARD_PWR) & SDCARD_PWR_CTRL_MASK; } /**************************************************************************** @@ -662,7 +662,7 @@ static inline uint32_t lpc17_getpwrctrl(void) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_sampleinit + * Name: lpc17_40_sampleinit * * Description: * Setup prior to collecting DMA samples @@ -670,14 +670,14 @@ static inline uint32_t lpc17_getpwrctrl(void) ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_sampleinit(void) +static void lpc17_40_sampleinit(void) { - memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct lpc17_sampleregs_s)); + memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct lpc17_40_sampleregs_s)); } #endif /**************************************************************************** - * Name: lpc17_sdcard_sample + * Name: lpc17_40_sdcard_sample * * Description: * Sample SD card registers @@ -685,22 +685,22 @@ static void lpc17_sampleinit(void) ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs) +static void lpc17_40_sdcard_sample(struct lpc17_40_sdcard_regs_s *regs) { - regs->pwr = (uint8_t)getreg32(LPC17_SDCARD_PWR); - regs->clkcr = (uint16_t)getreg32(LPC17_SDCARD_CLOCK); - regs->dctrl = (uint16_t)getreg32(LPC17_SDCARD_DCTRL); - regs->dtimer = getreg32(LPC17_SDCARD_DTIMER); - regs->dlen = getreg32(LPC17_SDCARD_DLEN); - regs->dcount = getreg32(LPC17_SDCARD_DCOUNT); - regs->sta = getreg32(LPC17_SDCARD_STATUS); - regs->mask = getreg32(LPC17_SDCARD_MASK0); - regs->fifocnt = getreg32(LPC17_SDCARD_FIFOCNT); + regs->pwr = (uint8_t)getreg32(LPC17_40_SDCARD_PWR); + regs->clkcr = (uint16_t)getreg32(LPC17_40_SDCARD_CLOCK); + regs->dctrl = (uint16_t)getreg32(LPC17_40_SDCARD_DCTRL); + regs->dtimer = getreg32(LPC17_40_SDCARD_DTIMER); + regs->dlen = getreg32(LPC17_40_SDCARD_DLEN); + regs->dcount = getreg32(LPC17_40_SDCARD_DCOUNT); + regs->sta = getreg32(LPC17_40_SDCARD_STATUS); + regs->mask = getreg32(LPC17_40_SDCARD_MASK0); + regs->fifocnt = getreg32(LPC17_40_SDCARD_FIFOCNT); } #endif /**************************************************************************** - * Name: lpc17_sample + * Name: lpc17_40_sample * * Description: * Sample SD card/DMA registers @@ -708,22 +708,22 @@ static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs) ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_sample(struct lpc17_dev_s *priv, int index) +static void lpc17_40_sample(struct lpc17_40_dev_s *priv, int index) { - struct lpc17_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_SDCARD_DMA) + struct lpc17_40_sampleregs_s *regs = &g_sampleregs[index]; +#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_40_SDCARD_DMA) if (priv->dmamode) { - lpc17_dmasample(priv->dma, ®s->dma); + lpc17_40_dmasample(priv->dma, ®s->dma); } #endif - lpc17_sdcard_sample(®s->sdcard); + lpc17_40_sdcard_sample(®s->sdcard); } #endif /**************************************************************************** - * Name: lpc17_sdcard_dump + * Name: lpc17_40_sdcard_dump * * Description: * Dump one register sample @@ -731,23 +731,23 @@ static void lpc17_sample(struct lpc17_dev_s *priv, int index) ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg) +static void lpc17_40_sdcard_dump(struct lpc17_40_sdcard_regs_s *regs, const char *msg) { mcinfo("SD Card Registers: %s\n", msg); - mcinfo(" POWER[%08x]: %08x\n", LPC17_SDCARD_PWR, regs->pwr); - mcinfo(" CLKCR[%08x]: %08x\n", LPC17_SDCARD_CLOCK, regs->clkcr); - mcinfo(" DCTRL[%08x]: %08x\n", LPC17_SDCARD_DCTRL, regs->dctrl); - mcinfo(" DTIMER[%08x]: %08x\n", LPC17_SDCARD_DTIMER, regs->dtimer); - mcinfo(" DLEN[%08x]: %08x\n", LPC17_SDCARD_DLEN, regs->dlen); - mcinfo(" DCOUNT[%08x]: %08x\n", LPC17_SDCARD_DCOUNT, regs->dcount); - mcinfo(" STA[%08x]: %08x\n", LPC17_SDCARD_STATUS, regs->sta); - mcinfo(" MASK[%08x]: %08x\n", LPC17_SDCARD_MASK0, regs->mask); - mcinfo("FIFOCNT[%08x]: %08x\n", LPC17_SDCARD_FIFOCNT, regs->fifocnt); + mcinfo(" POWER[%08x]: %08x\n", LPC17_40_SDCARD_PWR, regs->pwr); + mcinfo(" CLKCR[%08x]: %08x\n", LPC17_40_SDCARD_CLOCK, regs->clkcr); + mcinfo(" DCTRL[%08x]: %08x\n", LPC17_40_SDCARD_DCTRL, regs->dctrl); + mcinfo(" DTIMER[%08x]: %08x\n", LPC17_40_SDCARD_DTIMER, regs->dtimer); + mcinfo(" DLEN[%08x]: %08x\n", LPC17_40_SDCARD_DLEN, regs->dlen); + mcinfo(" DCOUNT[%08x]: %08x\n", LPC17_40_SDCARD_DCOUNT, regs->dcount); + mcinfo(" STA[%08x]: %08x\n", LPC17_40_SDCARD_STATUS, regs->sta); + mcinfo(" MASK[%08x]: %08x\n", LPC17_40_SDCARD_MASK0, regs->mask); + mcinfo("FIFOCNT[%08x]: %08x\n", LPC17_40_SDCARD_FIFOCNT, regs->fifocnt); } #endif /**************************************************************************** - * Name: lpc17_dumpsample + * Name: lpc17_40_dumpsample * * Description: * Dump one register sample @@ -755,21 +755,21 @@ static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg) ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_dumpsample(struct lpc17_dev_s *priv, - struct lpc17_sampleregs_s *regs, const char *msg) +static void lpc17_40_dumpsample(struct lpc17_40_dev_s *priv, + struct lpc17_40_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_SDCARD_DMA) +#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_40_SDCARD_DMA) if (priv->dmamode) { - lpc17_dmadump(priv->dma, ®s->dma, msg); + lpc17_40_dmadump(priv->dma, ®s->dma, msg); } #endif - lpc17_sdcard_dump(®s->sdcard, msg); + lpc17_40_sdcard_dump(®s->sdcard, msg); } #endif /**************************************************************************** - * Name: lpc17_dumpsamples + * Name: lpc17_40_dumpsamples * * Description: * Dump all sampled register data @@ -777,38 +777,38 @@ static void lpc17_dumpsample(struct lpc17_dev_s *priv, ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMCARD_INFO -static void lpc17_dumpsamples(struct lpc17_dev_s *priv) +static void lpc17_40_dumpsamples(struct lpc17_40_dev_s *priv) { - lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_SDCARD_DMA) + lpc17_40_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); +#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_40_SDCARD_DMA) if (priv->dmamode) { - lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable"); + lpc17_40_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable"); } #endif - lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup"); - lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_SDCARD_DMA) + lpc17_40_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup"); + lpc17_40_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); +#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_LPC17_40_SDCARD_DMA) if (priv->dmamode) { - lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback"); + lpc17_40_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback"); } #endif } #endif /**************************************************************************** - * Name: lpc17_dmacallback + * Name: lpc17_40_dmacallback * * Description: * Called when SD card DMA completes * ****************************************************************************/ -#ifdef CONFIG_LPC17_SDCARD_DMA -static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) +#ifdef CONFIG_LPC17_40_SDCARD_DMA +static void lpc17_40_dmacallback(DMA_HANDLE handle, void *arg, int status) { - FAR struct lpc17_dev_s *priv = (FAR struct lpc17_dev_s *)arg; + FAR struct lpc17_40_dev_s *priv = (FAR struct lpc17_40_dev_s *)arg; DEBUGASSERT(priv->dmamode); sdio_eventset_t result; @@ -818,7 +818,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) * Transfer. */ - lpc17_sample((struct lpc17_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); + lpc17_40_sample((struct lpc17_40_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); /* Get the result of the DMA transfer */ @@ -841,7 +841,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) priv->xfrflags |= SDCARD_DMADONE_FLAG; if (priv->xfrflags == SDCARD_ALLDONE || result == SDIOWAIT_ERROR) { - lpc17_endtransfer(priv, result); + lpc17_40_endtransfer(priv, result); } } #endif @@ -851,7 +851,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_log2 + * Name: lpc17_40_log2 * * Description: * Take (approximate) log base 2 of the provided number (Only works if the @@ -859,7 +859,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) * ****************************************************************************/ -static uint8_t lpc17_log2(uint16_t value) +static uint8_t lpc17_40_log2(uint16_t value) { uint8_t log2 = 0; @@ -882,63 +882,63 @@ static uint8_t lpc17_log2(uint16_t value) } /**************************************************************************** - * Name: lpc17_dataconfig + * Name: lpc17_40_dataconfig * * Description: * Configure the SD card data path for the next data transfer * ****************************************************************************/ -static void lpc17_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) +static void lpc17_40_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) { uint32_t regval = 0; /* Enable data path */ - putreg32(timeout, LPC17_SDCARD_DTIMER); /* Set DTIMER */ - putreg32(dlen, LPC17_SDCARD_DLEN); /* Set DLEN */ + putreg32(timeout, LPC17_40_SDCARD_DTIMER); /* Set DTIMER */ + putreg32(dlen, LPC17_40_SDCARD_DLEN); /* Set DLEN */ /* Configure DCTRL DTDIR, DTMODE, and DBLOCKSIZE fields and set the DTEN * field */ - regval = getreg32(LPC17_SDCARD_DCTRL); + regval = getreg32(LPC17_40_SDCARD_DCTRL); regval &= ~(SDCARD_DCTRL_DTDIR | SDCARD_DCTRL_DTMODE | SDCARD_DCTRL_DBLOCKSIZE_MASK); dctrl &= (SDCARD_DCTRL_DTDIR | SDCARD_DCTRL_DTMODE | SDCARD_DCTRL_DBLOCKSIZE_MASK); regval |= (dctrl | SDCARD_DCTRL_DTEN); - putreg32(regval, LPC17_SDCARD_DCTRL); + putreg32(regval, LPC17_40_SDCARD_DCTRL); } /**************************************************************************** - * Name: lpc17_datadisable + * Name: lpc17_40_datadisable * * Description: - * Disable the SD card data path setup by lpc17_dataconfig() and + * Disable the SD card data path setup by lpc17_40_dataconfig() and * disable DMA. * ****************************************************************************/ -static void lpc17_datadisable(void) +static void lpc17_40_datadisable(void) { uint32_t regval; /* Disable the data path */ - putreg32(SDCARD_DTIMER_DATATIMEOUT, LPC17_SDCARD_DTIMER); /* Reset DTIMER */ - putreg32(0, LPC17_SDCARD_DLEN); /* Reset DLEN */ + putreg32(SDCARD_DTIMER_DATATIMEOUT, LPC17_40_SDCARD_DTIMER); /* Reset DTIMER */ + putreg32(0, LPC17_40_SDCARD_DLEN); /* Reset DLEN */ /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ - regval = getreg32(LPC17_SDCARD_DCTRL); + regval = getreg32(LPC17_40_SDCARD_DCTRL); regval &= ~(SDCARD_DCTRL_DTEN | SDCARD_DCTRL_DTDIR | SDCARD_DCTRL_DTMODE | SDCARD_DCTRL_DMAEN | SDCARD_DCTRL_DBLOCKSIZE_MASK); - putreg32(regval, LPC17_SDCARD_DCTRL); + putreg32(regval, LPC17_40_SDCARD_DCTRL); } /**************************************************************************** - * Name: lpc17_sendfifo + * Name: lpc17_40_sendfifo * * Description: * Send SD card data in interrupt mode @@ -951,7 +951,7 @@ static void lpc17_datadisable(void) * ****************************************************************************/ -static void lpc17_sendfifo(struct lpc17_dev_s *priv) +static void lpc17_40_sendfifo(struct lpc17_40_dev_s *priv) { union { @@ -962,7 +962,7 @@ static void lpc17_sendfifo(struct lpc17_dev_s *priv) /* Loop while there is more data to be sent and the RX FIFO is not full */ while (priv->remaining > 0 && - (getreg32(LPC17_SDCARD_STATUS) & SDCARD_STATUS_TXFIFOF) == 0) + (getreg32(LPC17_40_SDCARD_STATUS) & SDCARD_STATUS_TXFIFOF) == 0) { /* Is there a full word remaining in the user buffer? */ @@ -995,12 +995,12 @@ static void lpc17_sendfifo(struct lpc17_dev_s *priv) /* Put the word in the FIFO */ - putreg32(data.w, LPC17_SDCARD_FIFO); + putreg32(data.w, LPC17_40_SDCARD_FIFO); } } /**************************************************************************** - * Name: lpc17_recvfifo + * Name: lpc17_40_recvfifo * * Description: * Receive SD card data in interrupt mode @@ -1013,7 +1013,7 @@ static void lpc17_sendfifo(struct lpc17_dev_s *priv) * ****************************************************************************/ -static void lpc17_recvfifo(struct lpc17_dev_s *priv) +static void lpc17_40_recvfifo(struct lpc17_40_dev_s *priv) { union { @@ -1026,11 +1026,11 @@ static void lpc17_recvfifo(struct lpc17_dev_s *priv) */ while (priv->remaining > 0 && - (getreg32(LPC17_SDCARD_STATUS) & SDCARD_STATUS_RXDAVL) != 0) + (getreg32(LPC17_40_SDCARD_STATUS) & SDCARD_STATUS_RXDAVL) != 0) { /* Read the next word from the RX FIFO */ - data.w = getreg32(LPC17_SDCARD_FIFO); + data.w = getreg32(LPC17_40_SDCARD_FIFO); if (priv->remaining >= sizeof(uint32_t)) { /* Transfer the whole word to the user buffer */ @@ -1058,7 +1058,7 @@ static void lpc17_recvfifo(struct lpc17_dev_s *priv) } /**************************************************************************** - * Name: lpc17_eventtimeout + * Name: lpc17_40_eventtimeout * * Description: * The watchdog timeout setup when the event wait start has expired without @@ -1076,9 +1076,9 @@ static void lpc17_recvfifo(struct lpc17_dev_s *priv) * ****************************************************************************/ -static void lpc17_eventtimeout(int argc, uint32_t arg) +static void lpc17_40_eventtimeout(int argc, uint32_t arg) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)arg; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)arg; /* There is always race conditions with timer expirations. */ @@ -1090,13 +1090,13 @@ static void lpc17_eventtimeout(int argc, uint32_t arg) { /* Yes.. wake up any waiting threads */ - lpc17_endwait(priv, SDIOWAIT_TIMEOUT); + lpc17_40_endwait(priv, SDIOWAIT_TIMEOUT); mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining); } } /**************************************************************************** - * Name: lpc17_endwait + * Name: lpc17_40_endwait * * Description: * Wake up a waiting thread if the waited-for event has occurred. @@ -1113,7 +1113,7 @@ static void lpc17_eventtimeout(int argc, uint32_t arg) * ****************************************************************************/ -static void lpc17_endwait(struct lpc17_dev_s *priv, sdio_eventset_t wkupevent) +static void lpc17_40_endwait(struct lpc17_40_dev_s *priv, sdio_eventset_t wkupevent) { /* Cancel the watchdog timeout */ @@ -1121,15 +1121,15 @@ static void lpc17_endwait(struct lpc17_dev_s *priv, sdio_eventset_t wkupevent) /* Disable event-related interrupts */ - lpc17_configwaitints(priv, 0, 0, wkupevent); + lpc17_40_configwaitints(priv, 0, 0, wkupevent); /* Wake up the waiting thread */ - lpc17_givesem(priv); + lpc17_40_givesem(priv); } /**************************************************************************** - * Name: lpc17_endtransfer + * Name: lpc17_40_endtransfer * * Description: * Terminate a transfer with the provided status. This function is called @@ -1148,31 +1148,31 @@ static void lpc17_endwait(struct lpc17_dev_s *priv, sdio_eventset_t wkupevent) * ****************************************************************************/ -static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupevent) +static void lpc17_40_endtransfer(struct lpc17_40_dev_s *priv, sdio_eventset_t wkupevent) { /* Disable all transfer related interrupts */ - lpc17_configxfrints(priv, 0); + lpc17_40_configxfrints(priv, 0); /* Clearing pending interrupt status on all transfer related interrupts */ - putreg32(SDCARD_XFRDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_XFRDONE_ICR, LPC17_40_SDCARD_CLEAR); /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA if (priv->dmamode) { /* DMA debug instrumentation */ - lpc17_sample(priv, SAMPLENDX_END_TRANSFER); + lpc17_40_sample(priv, SAMPLENDX_END_TRANSFER); /* Make sure that the DMA is stopped (it will be stopped automatically * on normal transfers, but not necessarily when the transfer terminates * on an error condition). */ - lpc17_dmastop(priv->dma); + lpc17_40_dmastop(priv->dma); } #endif @@ -1186,7 +1186,7 @@ static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupeven { /* Yes.. wake up any waiting threads */ - lpc17_endwait(priv, wkupevent); + lpc17_40_endwait(priv, wkupevent); } } @@ -1195,7 +1195,7 @@ static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupeven ****************************************************************************/ /**************************************************************************** - * Name: lpc17_interrupt + * Name: lpc17_40_interrupt * * Description: * SD card interrupt handler @@ -1208,9 +1208,9 @@ static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupeven * ****************************************************************************/ -static int lpc17_interrupt(int irq, void *context, FAR void *arg) +static int lpc17_40_interrupt(int irq, void *context, FAR void *arg) { - struct lpc17_dev_s *priv = &g_scard_dev; + struct lpc17_40_dev_s *priv = &g_scard_dev; uint32_t enabled; uint32_t pending; @@ -1221,14 +1221,14 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) * bits remaining, then we have work to do here. */ - while ((enabled = getreg32(LPC17_SDCARD_STATUS) & getreg32(LPC17_SDCARD_MASK0)) != 0) + while ((enabled = getreg32(LPC17_40_SDCARD_STATUS) & getreg32(LPC17_40_SDCARD_MASK0)) != 0) { /* Handle in progress, interrupt driven data transfers ****************/ pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA if (!priv->dmamode) #endif { @@ -1240,7 +1240,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) { /* Receive data from the RX FIFO */ - lpc17_recvfifo(priv); + lpc17_40_recvfifo(priv); } /* Otherwise, Is the transmit FIFO half empty or less? If so we must @@ -1252,7 +1252,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) { /* Send data via the TX FIFO */ - lpc17_sendfifo(priv); + lpc17_40_sendfifo(priv); } } @@ -1267,7 +1267,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1277,7 +1277,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) priv->xfrflags |= SDCARD_XFRDONE_FLAG; if (priv->xfrflags == SDCARD_ALLDONE) { - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE); } /* Otherwise, just disable futher transfer interrupts and @@ -1286,7 +1286,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) else { - lpc17_configxfrints(priv, 0); + lpc17_40_configxfrints(priv, 0); } } else @@ -1294,11 +1294,11 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) { /* Receive data from the RX FIFO */ - lpc17_recvfifo(priv); + lpc17_40_recvfifo(priv); /* Then terminate the transfer */ - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE); } } @@ -1309,7 +1309,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Terminate the transfer with an error */ mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle data timeout error */ @@ -1319,7 +1319,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Terminate the transfer with an error */ mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } /* Handle RX FIFO overrun error */ @@ -1329,7 +1329,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Terminate the transfer with an error */ mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle TX FIFO underrun error */ @@ -1339,7 +1339,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Terminate the transfer with an error */ mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle start bit error */ @@ -1349,7 +1349,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) /* Terminate the transfer with an error */ mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } @@ -1368,8 +1368,8 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) { /* Yes.. wake the thread up */ - putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); - lpc17_endwait(priv, SDIOWAIT_RESPONSEDONE); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); + lpc17_40_endwait(priv, SDIOWAIT_RESPONSEDONE); } } @@ -1383,8 +1383,8 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) { /* Yes.. wake the thread up */ - putreg32(SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); - lpc17_endwait(priv, SDIOWAIT_CMDDONE); + putreg32(SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); + lpc17_40_endwait(priv, SDIOWAIT_CMDDONE); } } } @@ -1398,7 +1398,7 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_lock + * Name: lpc17_40_lock * * Description: * Locks the bus. Function calls low-level multiplexed bus routines to @@ -1414,19 +1414,19 @@ static int lpc17_interrupt(int irq, void *context, FAR void *arg) ****************************************************************************/ #ifdef CONFIG_SDIO_MUXBUS -static int lpc17_lock(FAR struct sdio_dev_s *dev, bool lock) +static int lpc17_40_lock(FAR struct sdio_dev_s *dev, bool lock) { /* Single SD card instance so there is only one possibility. The multiplex * bus is part of board support package. */ - lpc17_muxbus_sdio_lock(lock); + lpc17_40_muxbus_sdio_lock(lock); return OK; } #endif /**************************************************************************** - * Name: lpc17_reset + * Name: lpc17_40_reset * * Description: * Reset the SD card controller. Undo all setup and initialization. @@ -1439,9 +1439,9 @@ static int lpc17_lock(FAR struct sdio_dev_s *dev, bool lock) * ****************************************************************************/ -static void lpc17_reset(FAR struct sdio_dev_s *dev) +static void lpc17_40_reset(FAR struct sdio_dev_s *dev) { - FAR struct lpc17_dev_s *priv = (FAR struct lpc17_dev_s *)dev; + FAR struct lpc17_40_dev_s *priv = (FAR struct lpc17_40_dev_s *)dev; irqstate_t flags; uint32_t regval; @@ -1451,22 +1451,22 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev) /* Disable the SD Interface */ - regval = getreg32(LPC17_SDCARD_CLOCK); + regval = getreg32(LPC17_40_SDCARD_CLOCK); regval &= ~SDCARD_CLOCK_CLKEN; - putreg32(regval, LPC17_SDCARD_CLOCK); + putreg32(regval, LPC17_40_SDCARD_CLOCK); - lpc17_setpwrctrl(SDCARD_PWR_CTRL_OFF); + lpc17_40_setpwrctrl(SDCARD_PWR_CTRL_OFF); /* Put SD card registers in their default, reset state */ - lpc17_default(); + lpc17_40_default(); /* Reset data */ priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA priv->xfrflags = 0; /* Used to synchronize SD card and DMA completion events */ #endif @@ -1481,22 +1481,22 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA priv->dmamode = false; /* true: DMA mode transfer */ #endif /* Configure and enable the SD card peripheral */ - lpc17_setclock(LPC17_CLCKCR_INIT | SDCARD_CLOCK_CLKEN); - lpc17_setpwrctrl(SDCARD_PWR_CTRL_ON); + lpc17_40_setclock(LPC17_40_CLCKCR_INIT | SDCARD_CLOCK_CLKEN); + lpc17_40_setpwrctrl(SDCARD_PWR_CTRL_ON); leave_critical_section(flags); mcinfo("CLCKR: %08x POWER: %08x\n", - getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR)); + getreg32(LPC17_40_SDCARD_CLOCK), getreg32(LPC17_40_SDCARD_PWR)); } /**************************************************************************** - * Name: lpc17_capabilities + * Name: lpc17_40_capabilities * * Description: * Get capabilities (and limitations) of the SDIO driver (optional) @@ -1509,14 +1509,14 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static sdio_capset_t lpc17_capabilities(FAR struct sdio_dev_s *dev) +static sdio_capset_t lpc17_40_capabilities(FAR struct sdio_dev_s *dev) { sdio_capset_t caps = 0; -#ifdef CONFIG_LPC17_SDCARD_WIDTH_D1_ONLY +#ifdef CONFIG_LPC17_40_SDCARD_WIDTH_D1_ONLY caps |= SDIO_CAPS_1BIT_ONLY; #endif -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -1524,7 +1524,7 @@ static sdio_capset_t lpc17_capabilities(FAR struct sdio_dev_s *dev) } /**************************************************************************** - * Name: lpc17_status + * Name: lpc17_40_status * * Description: * Get SD card status. @@ -1533,18 +1533,18 @@ static sdio_capset_t lpc17_capabilities(FAR struct sdio_dev_s *dev) * dev - Device-specific state data * * Returned Value: - * Returns a bitset of status values (see lpc17_status_* defines) + * Returns a bitset of status values (see lpc17_40_status_* defines) * ****************************************************************************/ -static sdio_statset_t lpc17_status(FAR struct sdio_dev_s *dev) +static sdio_statset_t lpc17_40_status(FAR struct sdio_dev_s *dev) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; return priv->cdstatus; } /**************************************************************************** - * Name: lpc17_widebus + * Name: lpc17_40_widebus * * Description: * Called after change in Bus width has been selected (via ACMD6). Most @@ -1560,14 +1560,14 @@ static sdio_statset_t lpc17_status(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static void lpc17_widebus(FAR struct sdio_dev_s *dev, bool wide) +static void lpc17_40_widebus(FAR struct sdio_dev_s *dev, bool wide) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; priv->widebus = wide; } /**************************************************************************** - * Name: lpc17_clock + * Name: lpc17_40_clock * * Description: * Enable/disable SD card clocking @@ -1581,7 +1581,7 @@ static void lpc17_widebus(FAR struct sdio_dev_s *dev, bool wide) * ****************************************************************************/ -static void lpc17_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) +static void lpc17_40_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) { uint32_t clkcr; @@ -1591,26 +1591,26 @@ static void lpc17_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) default: case CLOCK_SDIO_DISABLED: - clkcr = LPC17_CLCKCR_INIT; + clkcr = LPC17_40_CLCKCR_INIT; return; /* Enable in initial ID mode clocking (<400KHz) */ case CLOCK_IDMODE: - clkcr = (LPC17_CLCKCR_INIT | SDCARD_CLOCK_CLKEN); + clkcr = (LPC17_40_CLCKCR_INIT | SDCARD_CLOCK_CLKEN); break; /* Enable in MMC normal operation clocking */ case CLOCK_MMC_TRANSFER: clkcr = (SDCARD_CLOCK_MMCXFR | SDCARD_CLOCK_CLKEN); - lpc17_setpwrctrl(SDCARD_PWR_OPENDRAIN); + lpc17_40_setpwrctrl(SDCARD_PWR_OPENDRAIN); break; /* SD normal operation clocking (wide 4-bit mode) */ case CLOCK_SD_TRANSFER_4BIT: -#ifndef CONFIG_LPC17_SDCARD_WIDTH_D1_ONLY +#ifndef CONFIG_LPC17_40_SDCARD_WIDTH_D1_ONLY clkcr = (SDCARD_CLOCK_SDWIDEXFR | SDCARD_CLOCK_CLKEN); break; #endif @@ -1624,11 +1624,11 @@ static void lpc17_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) /* Set the new clock frequency along with the clock enable/disable bit */ - lpc17_setclock(clkcr); + lpc17_40_setclock(clkcr); } /**************************************************************************** - * Name: lpc17_attach + * Name: lpc17_40_attach * * Description: * Attach and prepare interrupts @@ -1641,13 +1641,13 @@ static void lpc17_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) * ****************************************************************************/ -static int lpc17_attach(FAR struct sdio_dev_s *dev) +static int lpc17_40_attach(FAR struct sdio_dev_s *dev) { int ret; /* Attach the SD card interrupt handler */ - ret = irq_attach(LPC17_IRQ_MCI, lpc17_interrupt, NULL); + ret = irq_attach(LPC17_40_IRQ_MCI, lpc17_40_interrupt, NULL); if (ret == OK) { @@ -1655,21 +1655,21 @@ static int lpc17_attach(FAR struct sdio_dev_s *dev) * interrupt flags */ - putreg32(SDCARD_MASK0_RESET, LPC17_SDCARD_MASK0); - putreg32(SDCARD_CLEAR_STATICFLAGS, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_MASK0_RESET, LPC17_40_SDCARD_MASK0); + putreg32(SDCARD_CLEAR_STATICFLAGS, LPC17_40_SDCARD_CLEAR); /* Enable SD card interrupts at the NVIC. They can now be enabled at * the SD card controller as needed. */ - up_enable_irq(LPC17_IRQ_MCI); + up_enable_irq(LPC17_40_IRQ_MCI); } return ret; } /**************************************************************************** - * Name: lpc17_sendcmd + * Name: lpc17_40_sendcmd * * Description: * Send the SD card command @@ -1684,18 +1684,18 @@ static int lpc17_attach(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) +static int lpc17_40_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) { uint32_t regval; uint32_t cmdidx; /* Set the SD card Argument value */ - putreg32(arg, LPC17_SDCARD_ARG); + putreg32(arg, LPC17_40_SDCARD_ARG); /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */ - regval = getreg32(LPC17_SDCARD_CMD); + regval = getreg32(LPC17_40_SDCARD_CMD); regval &= ~(SDCARD_CMD_INDEX_MASK | SDCARD_CMD_WAITRESP_MASK | SDCARD_CMD_WAITINT | SDCARD_CMD_WAITPEND | SDCARD_CMD_CPSMEN); @@ -1732,13 +1732,13 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) /* Write the SD card CMD */ - putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); - putreg32(regval, LPC17_SDCARD_CMD); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); + putreg32(regval, LPC17_40_SDCARD_CMD); return OK; } /**************************************************************************** - * Name: lpc17_recvsetup + * Name: lpc17_40_recvsetup * * Description: * Setup hardware in preparation for data transfer from the card in non-DMA @@ -1758,10 +1758,10 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) * ****************************************************************************/ -static int lpc17_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, +static int lpc17_40_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; uint32_t dblocksize; DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); @@ -1769,33 +1769,33 @@ static int lpc17_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Reset the DPSM configuration */ - lpc17_datadisable(); - lpc17_sampleinit(); - lpc17_sample(priv, SAMPLENDX_BEFORE_SETUP); + lpc17_40_datadisable(); + lpc17_40_sampleinit(); + lpc17_40_sample(priv, SAMPLENDX_BEFORE_SETUP); /* Save the destination buffer information for use by the interrupt handler */ priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA priv->dmamode = false; #endif /* Then set up the SD card data path */ - dblocksize = lpc17_log2(nbytes) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; - lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, + dblocksize = lpc17_40_log2(nbytes) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; + lpc17_40_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, dblocksize | SDCARD_DCTRL_DTDIR); /* And enable interrupts */ - lpc17_configxfrints(priv, SDCARD_RECV_MASK); - lpc17_sample(priv, SAMPLENDX_AFTER_SETUP); + lpc17_40_configxfrints(priv, SDCARD_RECV_MASK); + lpc17_40_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; } /**************************************************************************** - * Name: lpc17_sendsetup + * Name: lpc17_40_sendsetup * * Description: * Setup hardware in preparation for data transfer from the card. This method @@ -1813,10 +1813,10 @@ static int lpc17_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, * ****************************************************************************/ -static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, +static int lpc17_40_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, size_t nbytes) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; uint32_t dblocksize; DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); @@ -1824,32 +1824,32 @@ static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer /* Reset the DPSM configuration */ - lpc17_datadisable(); - lpc17_sampleinit(); - lpc17_sample(priv, SAMPLENDX_BEFORE_SETUP); + lpc17_40_datadisable(); + lpc17_40_sampleinit(); + lpc17_40_sample(priv, SAMPLENDX_BEFORE_SETUP); /* Save the source buffer information for use by the interrupt handler */ priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA priv->dmamode = false; #endif /* Then set up the SD card data path */ - dblocksize = lpc17_log2(nbytes) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; - lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, dblocksize); + dblocksize = lpc17_40_log2(nbytes) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; + lpc17_40_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, dblocksize); /* Enable TX interrupts */ - lpc17_configxfrints(priv, SDCARD_SEND_MASK); - lpc17_sample(priv, SAMPLENDX_AFTER_SETUP); + lpc17_40_configxfrints(priv, SDCARD_SEND_MASK); + lpc17_40_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; } /**************************************************************************** - * Name: lpc17_cancel + * Name: lpc17_40_cancel * * Description: * Cancel the data transfer setup of SDCARD_RECVSETUP, SDCARD_SENDSETUP, @@ -1865,20 +1865,20 @@ static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer * ****************************************************************************/ -static int lpc17_cancel(FAR struct sdio_dev_s *dev) +static int lpc17_40_cancel(FAR struct sdio_dev_s *dev) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; /* Disable all transfer- and event- related interrupts */ - lpc17_configxfrints(priv, 0); - lpc17_configwaitints(priv, 0, 0, 0); + lpc17_40_configxfrints(priv, 0); + lpc17_40_configwaitints(priv, 0, 0, 0); /* Clearing pending interrupt status on all transfer- and event- related * interrupts */ - putreg32(SDCARD_WAITALL_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_WAITALL_ICR, LPC17_40_SDCARD_CLEAR); /* Cancel any watchdog timeout */ @@ -1886,7 +1886,7 @@ static int lpc17_cancel(FAR struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -1894,7 +1894,7 @@ static int lpc17_cancel(FAR struct sdio_dev_s *dev) * on an error condition. */ - lpc17_dmastop(priv->dma); + lpc17_40_dmastop(priv->dma); } #endif @@ -1905,7 +1905,7 @@ static int lpc17_cancel(FAR struct sdio_dev_s *dev) } /**************************************************************************** - * Name: lpc17_waitresponse + * Name: lpc17_40_waitresponse * * Description: * Poll-wait for the response to the last command to be ready. @@ -1919,7 +1919,7 @@ static int lpc17_cancel(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) +static int lpc17_40_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { int32_t timeout; uint32_t events; @@ -1955,23 +1955,23 @@ static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) /* Then wait for the response (or timeout) */ - while ((getreg32(LPC17_SDCARD_STATUS) & events) == 0) + while ((getreg32(LPC17_40_SDCARD_STATUS) & events) == 0) { if (--timeout <= 0) { mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", - cmd, events, getreg32(LPC17_SDCARD_STATUS)); + cmd, events, getreg32(LPC17_40_SDCARD_STATUS)); return -ETIMEDOUT; } } - putreg32(SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); return OK; } /**************************************************************************** - * Name: lpc17_recvRx + * Name: lpc17_40_recvRx * * Description: * Receive response to SD card command. Only the critical payload is @@ -1992,7 +1992,7 @@ static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) * ****************************************************************************/ -static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +static int lpc17_40_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { #ifdef CONFIG_DEBUG_FEATURES uint32_t respcmd; @@ -2044,7 +2044,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t { /* Check if a timeout or CRC error occurred */ - regval = getreg32(LPC17_SDCARD_STATUS); + regval = getreg32(LPC17_40_SDCARD_STATUS); if ((regval & SDCARD_STATUS_CTIMEOUT) != 0) { mcerr("ERROR: Command timeout: %08x\n", regval); @@ -2060,7 +2060,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t { /* Check response received is of desired command */ - respcmd = getreg32(LPC17_SDCARD_RESPCMD); + respcmd = getreg32(LPC17_40_SDCARD_RESPCMD); if ((uint8_t)(respcmd & SDCARD_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); @@ -2072,12 +2072,12 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t /* Clear all pending message completion events and return the R1/R6 response */ - putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); - *rshort = getreg32(LPC17_SDCARD_RESP0); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); + *rshort = getreg32(LPC17_40_SDCARD_RESP0); return ret; } -static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) +static int lpc17_40_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) { uint32_t regval; int ret = OK; @@ -2104,7 +2104,7 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo { /* Check if a timeout or CRC error occurred */ - regval = getreg32(LPC17_SDCARD_STATUS); + regval = getreg32(LPC17_40_SDCARD_STATUS); if (regval & SDCARD_STATUS_CTIMEOUT) { mcerr("ERROR: Timeout STA: %08x\n", regval); @@ -2119,19 +2119,19 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo /* Return the long response */ - putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); if (rlong) { - rlong[0] = getreg32(LPC17_SDCARD_RESP0); - rlong[1] = getreg32(LPC17_SDCARD_RESP1); - rlong[2] = getreg32(LPC17_SDCARD_RESP2); - rlong[3] = getreg32(LPC17_SDCARD_RESP3); + rlong[0] = getreg32(LPC17_40_SDCARD_RESP0); + rlong[1] = getreg32(LPC17_40_SDCARD_RESP1); + rlong[2] = getreg32(LPC17_40_SDCARD_RESP2); + rlong[3] = getreg32(LPC17_40_SDCARD_RESP3); } return ret; } -static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +static int lpc17_40_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { uint32_t regval; int ret = OK; @@ -2161,7 +2161,7 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r * a good response) */ - regval = getreg32(LPC17_SDCARD_STATUS); + regval = getreg32(LPC17_40_SDCARD_STATUS); if (regval & SDCARD_STATUS_CTIMEOUT) { mcerr("ERROR: Timeout STA: %08x\n", regval); @@ -2169,29 +2169,29 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r } } - putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); if (rshort) { - *rshort = getreg32(LPC17_SDCARD_RESP0); + *rshort = getreg32(LPC17_40_SDCARD_RESP0); } return ret; } /* MMC responses not supported */ -static int lpc17_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) +static int lpc17_40_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { - putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_40_SDCARD_CLEAR); return -ENOSYS; } /**************************************************************************** - * Name: lpc17_waitenable + * Name: lpc17_40_waitenable * * Description: * Enable/disable of a set of SD card wait events. This is part of the * the SDCARD_WAITEVENT sequence. The set of to-be-waited-for events is - * configured before calling lpc17_eventwait. This is done in this way + * configured before calling lpc17_40_eventwait. This is done in this way * to help the driver to eliminate race conditions between the command * setup and the subsequent events. * @@ -2209,17 +2209,17 @@ static int lpc17_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t * ****************************************************************************/ -static void lpc17_waitenable(FAR struct sdio_dev_s *dev, +static void lpc17_40_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; uint32_t waitmask; DEBUGASSERT(priv != NULL); /* Disable event-related interrupts */ - lpc17_configwaitints(priv, 0, 0, 0); + lpc17_40_configwaitints(priv, 0, 0, 0); /* Select the interrupt mask that will give us the appropriate wakeup * interrupts. @@ -2243,17 +2243,17 @@ static void lpc17_waitenable(FAR struct sdio_dev_s *dev, /* Enable event-related interrupts */ - putreg32(SDCARD_WAITALL_ICR, LPC17_SDCARD_CLEAR); - lpc17_configwaitints(priv, waitmask, eventset, 0); + putreg32(SDCARD_WAITALL_ICR, LPC17_40_SDCARD_CLEAR); + lpc17_40_configwaitints(priv, waitmask, eventset, 0); } /**************************************************************************** - * Name: lpc17_eventwait + * Name: lpc17_40_eventwait * * Description: * Wait for one of the enabled events to occur (or a timeout). Note that - * all events enabled by SDCARD_WAITEVENTS are disabled when lpc17_eventwait - * returns. SDCARD_WAITEVENTS must be called again before lpc17_eventwait + * all events enabled by SDCARD_WAITEVENTS are disabled when lpc17_40_eventwait + * returns. SDCARD_WAITEVENTS must be called again before lpc17_40_eventwait * can be used again. * * Input Parameters: @@ -2268,10 +2268,10 @@ static void lpc17_waitenable(FAR struct sdio_dev_s *dev, * ****************************************************************************/ -static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, +static sdio_eventset_t lpc17_40_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; sdio_eventset_t wkupevent = 0; irqstate_t flags; int ret; @@ -2305,7 +2305,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, /* Start the watchdog timer */ delay = MSEC2TICK(timeout); - ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc17_eventtimeout, + ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc17_40_eventtimeout, 1, (uint32_t)priv); if (ret < 0) { @@ -2314,7 +2314,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, } /* Loop until the event (or the timeout occurs). Race conditions are avoided - * by calling lpc17_waitenable prior to triggering the logic that will cause + * by calling lpc17_40_waitenable prior to triggering the logic that will cause * the wait to terminate. Under certain race conditions, the waited-for * may have already occurred before this function was called! */ @@ -2326,7 +2326,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, * there will be no wait. */ - lpc17_takesem(priv); + lpc17_40_takesem(priv); wkupevent = priv->wkupevent; /* Check if the event has occurred. When the event has occurred, then @@ -2343,24 +2343,24 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, /* Disable event-related interrupts */ - lpc17_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_LPC17_SDCARD_DMA + lpc17_40_configwaitints(priv, 0, 0, 0); +#ifdef CONFIG_LPC17_40_SDCARD_DMA priv->xfrflags = 0; #endif errout: leave_critical_section(flags); - lpc17_dumpsamples(priv); + lpc17_40_dumpsamples(priv); return wkupevent; } /**************************************************************************** - * Name: lpc17_callbackenable + * Name: lpc17_40_callbackenable * * Description: * Enable/disable of a set of SD card callback events. This is part of the * the SD card callback sequence. The set of events is configured to enabled - * callbacks to the function provided in lpc17_registercallback. + * callbacks to the function provided in lpc17_40_registercallback. * * Events are automatically disabled once the callback is performed and no * further callback events will occur until they are again enabled by @@ -2376,20 +2376,20 @@ errout: * ****************************************************************************/ -static void lpc17_callbackenable(FAR struct sdio_dev_s *dev, +static void lpc17_40_callbackenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; - lpc17_callback(priv); + lpc17_40_callback(priv); } /**************************************************************************** - * Name: lpc17_registercallback + * Name: lpc17_40_registercallback * * Description: * Register a callback that that will be invoked on any media status @@ -2410,10 +2410,10 @@ static void lpc17_callbackenable(FAR struct sdio_dev_s *dev, * ****************************************************************************/ -static int lpc17_registercallback(FAR struct sdio_dev_s *dev, +static int lpc17_40_registercallback(FAR struct sdio_dev_s *dev, worker_t callback, void *arg) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; /* Disable callbacks and register this callback and is argument */ @@ -2427,7 +2427,7 @@ static int lpc17_registercallback(FAR struct sdio_dev_s *dev, } /**************************************************************************** - * Name: lpc17_dmarecvsetup + * Name: lpc17_40_dmarecvsetup * * Description: * Setup to perform a read DMA. If the processor supports a data cache, @@ -2445,11 +2445,11 @@ static int lpc17_registercallback(FAR struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_LPC17_SDCARD_DMA -static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, +#ifdef CONFIG_LPC17_40_SDCARD_DMA +static int lpc17_40_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t buflen) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; uint32_t dblocksize; uint32_t regval; int ret = -EINVAL; @@ -2459,14 +2459,14 @@ static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Reset the DPSM configuration */ - lpc17_datadisable(); + lpc17_40_datadisable(); /* Wide bus operation is required for DMA */ if (priv->widebus) { - lpc17_sampleinit(); - lpc17_sample(priv, SAMPLENDX_BEFORE_SETUP); + lpc17_40_sampleinit(); + lpc17_40_sample(priv, SAMPLENDX_BEFORE_SETUP); /* Save the destination buffer information for use by the interrupt handler */ @@ -2476,28 +2476,28 @@ static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Then set up the SD card data path */ - dblocksize = lpc17_log2(buflen) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; - lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, buflen, + dblocksize = lpc17_40_log2(buflen) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; + lpc17_40_dataconfig(SDCARD_DTIMER_DATATIMEOUT, buflen, dblocksize | SDCARD_DCTRL_DTDIR); /* Configure the RX DMA */ - lpc17_configxfrints(priv, SDCARD_DMARECV_MASK); + lpc17_40_configxfrints(priv, SDCARD_DMARECV_MASK); - regval = getreg32(LPC17_SDCARD_DCTRL); + regval = getreg32(LPC17_40_SDCARD_DCTRL); regval |= SDCARD_DCTRL_DMAEN; - putreg32(regval, LPC17_SDCARD_DCTRL); + putreg32(regval, LPC17_40_SDCARD_DCTRL); - ret = lpc17_dmasetup(priv->dma, SDCARD_RXDMA32_CONTROL, - SDCARD_RXDMA32_CONFIG, LPC17_SDCARD_FIFO, + ret = lpc17_40_dmasetup(priv->dma, SDCARD_RXDMA32_CONTROL, + SDCARD_RXDMA32_CONFIG, LPC17_40_SDCARD_FIFO, (uint32_t)buffer, (buflen + 3) >> 2); if (ret == OK) { /* Start the DMA */ - lpc17_sample(priv, SAMPLENDX_BEFORE_ENABLE); - lpc17_dmastart(priv->dma, lpc17_dmacallback, priv); - lpc17_sample(priv, SAMPLENDX_AFTER_SETUP); + lpc17_40_sample(priv, SAMPLENDX_BEFORE_ENABLE); + lpc17_40_dmastart(priv->dma, lpc17_40_dmacallback, priv); + lpc17_40_sample(priv, SAMPLENDX_AFTER_SETUP); } } @@ -2506,7 +2506,7 @@ static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, #endif /**************************************************************************** - * Name: lpc17_dmasendsetup + * Name: lpc17_40_dmasendsetup * * Description: * Setup to perform a write DMA. If the processor supports a data cache, @@ -2524,11 +2524,11 @@ static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, * ****************************************************************************/ -#ifdef CONFIG_LPC17_SDCARD_DMA -static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, +#ifdef CONFIG_LPC17_40_SDCARD_DMA +static int lpc17_40_dmasendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, size_t buflen) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; uint32_t dblocksize; uint32_t regval; int ret = -EINVAL; @@ -2538,14 +2538,14 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, /* Reset the DPSM configuration */ - lpc17_datadisable(); + lpc17_40_datadisable(); /* Wide bus operation is required for DMA */ if (priv->widebus) { - lpc17_sampleinit(); - lpc17_sample(priv, SAMPLENDX_BEFORE_SETUP); + lpc17_40_sampleinit(); + lpc17_40_sample(priv, SAMPLENDX_BEFORE_SETUP); /* Save the source buffer information for use by the interrupt handler */ @@ -2555,30 +2555,30 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, /* Then set up the SD card data path */ - dblocksize = lpc17_log2(buflen) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; - lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, buflen, dblocksize); + dblocksize = lpc17_40_log2(buflen) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; + lpc17_40_dataconfig(SDCARD_DTIMER_DATATIMEOUT, buflen, dblocksize); /* Configure the TX DMA */ - ret = lpc17_dmasetup(priv->dma, SDCARD_TXDMA32_CONTROL, + ret = lpc17_40_dmasetup(priv->dma, SDCARD_TXDMA32_CONTROL, SDCARD_TXDMA32_CONFIG, (uint32_t)buffer, - LPC17_SDCARD_FIFO, (buflen + 3) >> 2); + LPC17_40_SDCARD_FIFO, (buflen + 3) >> 2); if (ret == OK) { - lpc17_sample(priv, SAMPLENDX_BEFORE_ENABLE); + lpc17_40_sample(priv, SAMPLENDX_BEFORE_ENABLE); - regval = getreg32(LPC17_SDCARD_DCTRL); + regval = getreg32(LPC17_40_SDCARD_DCTRL); regval |= SDCARD_DCTRL_DMAEN; - putreg32(regval, LPC17_SDCARD_DCTRL); + putreg32(regval, LPC17_40_SDCARD_DCTRL); /* Start the DMA */ - lpc17_dmastart(priv->dma, lpc17_dmacallback, priv); - lpc17_sample(priv, SAMPLENDX_AFTER_SETUP); + lpc17_40_dmastart(priv->dma, lpc17_40_dmacallback, priv); + lpc17_40_sample(priv, SAMPLENDX_AFTER_SETUP); /* Enable TX interrupts */ - lpc17_configxfrints(priv, SDCARD_DMASEND_MASK); + lpc17_40_configxfrints(priv, SDCARD_DMASEND_MASK); } } @@ -2590,7 +2590,7 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, * Initialization/uninitialization/reset ****************************************************************************/ /**************************************************************************** - * Name: lpc17_callback + * Name: lpc17_40_callback * * Description: * Perform callback. @@ -2602,9 +2602,9 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, * ****************************************************************************/ -static void lpc17_callback(void *arg) +static void lpc17_40_callback(void *arg) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)arg; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)arg; /* Is a callback registered? */ @@ -2668,24 +2668,24 @@ static void lpc17_callback(void *arg) } /**************************************************************************** - * Name: lpc17_default + * Name: lpc17_40_default * * Description: * Restore SD card registers to their default, reset values * ****************************************************************************/ -static void lpc17_default(void) +static void lpc17_40_default(void) { - putreg32(SDCARD_PWR_RESET, LPC17_SDCARD_PWR); - putreg32(SDCARD_CLOCK_RESET, LPC17_SDCARD_CLOCK); - putreg32(SDCARD_ARG_RESET, LPC17_SDCARD_ARG); - putreg32(SDCARD_CMD_RESET, LPC17_SDCARD_CMD); - putreg32(SDCARD_DTIMER_RESET, LPC17_SDCARD_DTIMER); - putreg32(SDCARD_DLEN_RESET, LPC17_SDCARD_DLEN); - putreg32(SDCARD_DCTRL_RESET, LPC17_SDCARD_DCTRL); - putreg32(SDCARD_CLEAR_RESET, LPC17_SDCARD_CLEAR); - putreg32(SDCARD_MASK0_RESET, LPC17_SDCARD_MASK0); + putreg32(SDCARD_PWR_RESET, LPC17_40_SDCARD_PWR); + putreg32(SDCARD_CLOCK_RESET, LPC17_40_SDCARD_CLOCK); + putreg32(SDCARD_ARG_RESET, LPC17_40_SDCARD_ARG); + putreg32(SDCARD_CMD_RESET, LPC17_40_SDCARD_CMD); + putreg32(SDCARD_DTIMER_RESET, LPC17_40_SDCARD_DTIMER); + putreg32(SDCARD_DLEN_RESET, LPC17_40_SDCARD_DLEN); + putreg32(SDCARD_DCTRL_RESET, LPC17_40_SDCARD_DCTRL); + putreg32(SDCARD_CLEAR_RESET, LPC17_40_SDCARD_CLEAR); + putreg32(SDCARD_MASK0_RESET, LPC17_40_SDCARD_MASK0); } /**************************************************************************** @@ -2712,13 +2712,13 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) /* There is only one slot */ - struct lpc17_dev_s *priv = &g_scard_dev; + struct lpc17_40_dev_s *priv = &g_scard_dev; /* Enable power on SD Interface */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCSDC; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Initialize the SD card slot structure */ /* Initialize semaphores */ @@ -2736,14 +2736,14 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); -#ifdef CONFIG_LPC17_SDCARD_DMA +#ifdef CONFIG_LPC17_40_SDCARD_DMA /* Configure the SDCARD DMA request */ - lpc17_dmaconfigure(DMA_REQ_SDCARD, DMA_DMASEL_SDCARD); + lpc17_40_dmaconfigure(DMA_REQ_SDCARD, DMA_DMASEL_SDCARD); /* Allocate a DMA channel for SDCARD DMA */ - priv->dma = lpc17_dmachannel(); + priv->dma = lpc17_40_dmachannel(); DEBUGASSERT(priv->dma); #endif @@ -2754,21 +2754,21 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) */ #ifndef CONFIG_SDIO_MUXBUS - lpc17_configgpio(GPIO_SD_DAT0); -#ifndef CONFIG_LPC17_SDCARD_WIDTH_D1_ONLY - lpc17_configgpio(GPIO_SD_DAT1); - lpc17_configgpio(GPIO_SD_DAT2); - lpc17_configgpio(GPIO_SD_DAT3); + lpc17_40_configgpio(GPIO_SD_DAT0); +#ifndef CONFIG_LPC17_40_SDCARD_WIDTH_D1_ONLY + lpc17_40_configgpio(GPIO_SD_DAT1); + lpc17_40_configgpio(GPIO_SD_DAT2); + lpc17_40_configgpio(GPIO_SD_DAT3); #endif - lpc17_configgpio(GPIO_SD_CLK); - lpc17_configgpio(GPIO_SD_CMD); + lpc17_40_configgpio(GPIO_SD_CLK); + lpc17_40_configgpio(GPIO_SD_CMD); #endif /* Reset the card and assure that it is in the initial, unconfigured * state. */ - lpc17_reset(&priv->dev); + lpc17_40_reset(&priv->dev); return &g_scard_dev.dev; } @@ -2794,7 +2794,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; sdio_statset_t cdstatus; irqstate_t flags; @@ -2816,7 +2816,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) if (cdstatus != priv->cdstatus) { - lpc17_callback(priv); + lpc17_40_callback(priv); } leave_critical_section(flags); @@ -2840,7 +2840,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; + struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)dev; irqstate_t flags; /* Update card status */ @@ -2858,4 +2858,4 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_LPC17_SDCARD */ +#endif /* CONFIG_LPC17_40_SDCARD */ diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.h similarity index 94% rename from arch/arm/src/lpc17xx/lpc17_sdcard.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.h index 1057bcb60db..65bca084e44 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_sdcard.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SDCARD_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SDCARD_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SDCARD_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SDCARD_H /************************************************************************************ * Included Files @@ -45,7 +45,7 @@ #include #include "chip.h" -#include "hardware/lpc17_sdcard.h" +#include "hardware/lpc17_40_sdcard.h" /************************************************************************************ * Public Functions @@ -124,4 +124,4 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SDCARD_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SDCARD_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c similarity index 84% rename from arch/arm/src/lpc17xx/lpc17_serial.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c index cdd4ae29a9a..7b3c920013b 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_serial.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c * * Copyright (C) 2010-2013, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -62,9 +62,9 @@ #include "up_internal.h" #include "chip.h" -#include "hardware/lpc17_uart.h" -#include "lpc17_gpio.h" -#include "lpc17_serial.h" +#include "hardware/lpc17_40_uart.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_serial.h" /**************************************************************************** * Pre-processor definitions @@ -139,34 +139,34 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_LPC17_UART0 +#ifdef CONFIG_LPC17_40_UART0 static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; #endif -#ifdef CONFIG_LPC17_UART1 +#ifdef CONFIG_LPC17_40_UART1 static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #endif -#ifdef CONFIG_LPC17_UART2 +#ifdef CONFIG_LPC17_40_UART2 static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; #endif -#ifdef CONFIG_LPC17_UART3 +#ifdef CONFIG_LPC17_40_UART3 static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; #endif -/* This describes the state of the LPC17xx uart0 port. */ +/* This describes the state of the LPC17xx/LPC40xx uart0 port. */ -#ifdef CONFIG_LPC17_UART0 +#ifdef CONFIG_LPC17_40_UART0 static struct up_dev_s g_uart0priv = { - .uartbase = LPC17_UART0_BASE, + .uartbase = LPC17_40_UART0_BASE, .baud = CONFIG_UART0_BAUD, - .irq = LPC17_IRQ_UART0, + .irq = LPC17_40_IRQ_UART0, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stopbits2 = CONFIG_UART0_2STOP, @@ -189,14 +189,14 @@ static uart_dev_t g_uart0port = }; #endif -/* This describes the state of the LPC17xx uart1 port. */ +/* This describes the state of the LPC17xx/LPC40xx uart1 port. */ -#ifdef CONFIG_LPC17_UART1 +#ifdef CONFIG_LPC17_40_UART1 static struct up_dev_s g_uart1priv = { - .uartbase = LPC17_UART1_BASE, + .uartbase = LPC17_40_UART1_BASE, .baud = CONFIG_UART1_BAUD, - .irq = LPC17_IRQ_UART1, + .irq = LPC17_40_IRQ_UART1, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, @@ -219,14 +219,14 @@ static uart_dev_t g_uart1port = }; #endif -/* This describes the state of the LPC17xx uart1 port. */ +/* This describes the state of the LPC17xx/LPC40xx uart1 port. */ -#ifdef CONFIG_LPC17_UART2 +#ifdef CONFIG_LPC17_40_UART2 static struct up_dev_s g_uart2priv = { - .uartbase = LPC17_UART2_BASE, + .uartbase = LPC17_40_UART2_BASE, .baud = CONFIG_UART2_BAUD, - .irq = LPC17_IRQ_UART2, + .irq = LPC17_40_IRQ_UART2, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, @@ -249,14 +249,14 @@ static uart_dev_t g_uart2port = }; #endif -/* This describes the state of the LPC17xx uart1 port. */ +/* This describes the state of the LPC17xx/LPC40xx uart1 port. */ -#ifdef CONFIG_LPC17_UART3 +#ifdef CONFIG_LPC17_40_UART3 static struct up_dev_s g_uart3priv = { - .uartbase = LPC17_UART3_BASE, + .uartbase = LPC17_40_UART3_BASE, .baud = CONFIG_UART3_BAUD, - .irq = LPC17_IRQ_UART3, + .irq = LPC17_40_IRQ_UART3, .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, .stopbits2 = CONFIG_UART3_2STOP, @@ -285,17 +285,17 @@ static uart_dev_t g_uart3port = # if defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart0port /* UART0=console */ # define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ -# ifdef CONFIG_LPC17_UART1 +# ifdef CONFIG_LPC17_40_UART1 # define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */ -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS3_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2;UART3=ttyS3 */ # else # undef TTYS3_DEV /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS;No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART3=ttys2;No ttyS3 */ # else # undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ @@ -303,16 +303,16 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1;No ttyS3 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ # else # undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ # endif # undef TTYS3_DEV /* No ttyS3 */ # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS1_DEV g_uart3port /* UART0=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ # else # undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ @@ -324,17 +324,17 @@ static uart_dev_t g_uart3port = # elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1port /* UART1=console */ # define TTYS0_DEV g_uart1port /* UART1=ttyS0 */ -# ifdef CONFIG_LPC17_UART0 +# ifdef CONFIG_LPC17_40_UART0 # define TTYS1_DEV g_uart0port /* UART1=ttyS0;UART0=ttyS1 */ -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS2_DEV g_uart2port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS3_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2;UART3=ttyS3 */ # else # undef TTYS3_DEV /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS;No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */ # else # undef TTYS2_DEV /* UART1=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ @@ -342,16 +342,16 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS1_DEV g_uart2port /* UART1=ttyS0;UART2=ttyS1 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ # else # undef TTYS2_DEV /* UART1=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ # endif # undef TTYS3_DEV /* No ttyS3 */ # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS1_DEV g_uart3port /* UART1=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ # else # undef TTYS1_DEV /* UART1=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ @@ -363,17 +363,17 @@ static uart_dev_t g_uart3port = # elif defined(CONFIG_UART2_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart2port /* UART2=console */ # define TTYS0_DEV g_uart2port /* UART2=ttyS0 */ -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS1_DEV g_uart0port /* UART2=ttyS0;UART0=ttyS1 */ -# ifdef CONFIG_LPC17_UART1 +# ifdef CONFIG_LPC17_40_UART1 # define TTYS2_DEV g_uart1port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS3_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2;UART3=ttyS3 */ # else # undef TTYS3_DEV /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */ # else # undef TTYS2_DEV /* UART2=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ @@ -381,16 +381,16 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART1 +# ifdef CONFIG_LPC17_40_UART1 # define TTYS1_DEV g_uart1port /* UART2=ttyS0;UART1=ttyS1 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART1=ttyS1;UART3=ttyS2 */ # else # undef TTYS2_DEV /* UART2=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ # endif # undef TTYS3_DEV /* No ttyS3 */ # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS1_DEV g_uart3port /* UART2=ttyS0;UART3=ttyS1;No ttyS3 */ # else # undef TTYS1_DEV /* UART2=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ @@ -402,17 +402,17 @@ static uart_dev_t g_uart3port = # elif defined(CONFIG_UART3_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart3port /* UART3=console */ # define TTYS0_DEV g_uart3port /* UART3=ttyS0 */ -# ifdef CONFIG_LPC17_UART0 +# ifdef CONFIG_LPC17_40_UART0 # define TTYS1_DEV g_uart0port /* UART3=ttyS0;UART0=ttyS1 */ -# ifdef CONFIG_LPC17_UART1 +# ifdef CONFIG_LPC17_40_UART1 # define TTYS2_DEV g_uart1port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2 */ -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS3_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2;UART2=ttyS3 */ # else # undef TTYS3_DEV /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART2=ttys2;No ttyS3 */ # else # undef TTYS2_DEV /* UART3=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ @@ -420,16 +420,16 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART1 +# ifdef CONFIG_LPC17_40_UART1 # define TTYS1_DEV g_uart1port /* UART3=ttyS0;UART1=ttyS1 */ -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART1=ttyS1;UART2=ttyS2;No ttyS3 */ # else # undef TTYS2_DEV /* UART3=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ # endif # undef TTYS3_DEV /* No ttyS3 */ # else -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS1_DEV g_uart2port /* UART3=ttyS0;UART2=ttyS1;No ttyS3;No ttyS3 */ # undef TTYS3_DEV /* UART3=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ # else @@ -442,17 +442,17 @@ static uart_dev_t g_uart3port = # endif #else /* No console */ # define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ -# ifdef CONFIG_LPC17_UART1 +# ifdef CONFIG_LPC17_40_UART1 # define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */ -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS3_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2;UART3=ttyS3 */ # else # undef TTYS3_DEV /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS;No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART3=ttys2;No ttyS3 */ # else # undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ @@ -460,16 +460,16 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # else -# ifdef CONFIG_LPC17_UART2 +# ifdef CONFIG_LPC17_40_UART2 # define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1;No ttyS3 */ -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ # else # undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ # endif # undef TTYS3_DEV /* No ttyS3 */ # else -# ifdef CONFIG_LPC17_UART3 +# ifdef CONFIG_LPC17_40_UART3 # define TTYS1_DEV g_uart3port /* UART0=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ # else # undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ @@ -514,7 +514,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier) } priv->ier &= ~UART_IER_ALLIE; - up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); + up_serialout(priv, LPC17_40_UART_IER_OFFSET, priv->ier); } /**************************************************************************** @@ -524,7 +524,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier) static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier) { priv->ier |= ier & UART_IER_ALLIE; - up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); + up_serialout(priv, LPC17_40_UART_IER_OFFSET, priv->ier); } /**************************************************************************** @@ -533,7 +533,7 @@ static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier) static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { - uint32_t lcr = up_serialin(priv, LPC17_UART_LCR_OFFSET); + uint32_t lcr = up_serialin(priv, LPC17_40_UART_LCR_OFFSET); if (enable) { @@ -544,11 +544,11 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) lcr &= ~UART_LCR_BRK; } - up_serialout(priv, LPC17_UART_LCR_OFFSET, lcr); + up_serialout(priv, LPC17_40_UART_LCR_OFFSET, lcr); } /************************************************************************************ - * Name: lpc17_uartcclkdiv + * Name: lpc17_40_uartcclkdiv * * Description: * Select a CCLK divider to produce the UART PCLK. The stratey is to select the @@ -567,7 +567,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) * * PCLK = CCLK / divisor * - * For the LPC178x, the PCLK is determined by the global divisor setting in + * For the LPC178x/40xx, the PCLK is determined by the global divisor setting in * the PLKSEL register (and, in that case, this function is not needed). * * NOTE: This is an inline function. If a typical optimization level is used and @@ -577,7 +577,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) ************************************************************************************/ #ifdef LPC176x -static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) +static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud) { /* Ignoring the fractional divider, the BAUD is given by: * @@ -589,7 +589,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * * PCLK = CCLK / divisor * - * And for the LPC178x, the PCLK is determined by the global divisor setting in + * And for the LPC178x/40xx, the PCLK is determined by the global divisor setting in * the PLKSEL register (and, in that case, this function is not needed). */ @@ -609,7 +609,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 16 / MinDL */ - if (baud < (LPC17_CCLK / 16 / UART_MINDL)) + if (baud < (LPC17_40_CCLK / 16 / UART_MINDL)) { return SYSCON_PCLKSEL_CCLK; } @@ -625,7 +625,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 8 / MinDL */ - else if (baud < (LPC17_CCLK / 8 / UART_MINDL)) + else if (baud < (LPC17_40_CCLK / 8 / UART_MINDL)) { return SYSCON_PCLKSEL_CCLK2; } @@ -641,7 +641,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 4 / MinDL */ - else if (baud < (LPC17_CCLK / 4 / UART_MINDL)) + else if (baud < (LPC17_40_CCLK / 4 / UART_MINDL)) { return SYSCON_PCLKSEL_CCLK4; } @@ -657,7 +657,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 2 / MinDL */ - else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL)) */ + else /* if (baud < (LPC17_40_CCLK / 2 / UART_MINDL)) */ { return SYSCON_PCLKSEL_CCLK8; } @@ -665,7 +665,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) #endif /* LPC176x */ /************************************************************************************ - * Name: lpc17_uart0config, uart1config, uart2config, and uart3config + * Name: lpc17_40_uart0config, uart1config, uart2config, and uart3config * * Description: * Configure the UART. UART0/1/2/3 peripherals are configured using the following @@ -682,8 +682,8 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * ************************************************************************************/ -#ifdef CONFIG_LPC17_UART0 -static inline void lpc17_uart0config(void) +#ifdef CONFIG_LPC17_40_UART0 +static inline void lpc17_40_uart0config(void) { uint32_t regval; irqstate_t flags; @@ -691,29 +691,29 @@ static inline void lpc17_uart0config(void) /* Step 1: Enable power on UART0 */ flags = enter_critical_section(); - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCUART0; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Step 2: Enable clocking on UART */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_UART0_MASK; regval |= ((uint32_t)g_uart0priv.cclkdiv << SYSCON_PCLKSEL0_UART0_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); #endif /* Step 3: Configure I/O pins */ - lpc17_configgpio(GPIO_UART0_TXD); - lpc17_configgpio(GPIO_UART0_RXD); + lpc17_40_configgpio(GPIO_UART0_TXD); + lpc17_40_configgpio(GPIO_UART0_RXD); leave_critical_section(flags); }; #endif -#ifdef CONFIG_LPC17_UART1 -static inline void lpc17_uart1config(void) +#ifdef CONFIG_LPC17_40_UART1 +static inline void lpc17_40_uart1config(void) { uint32_t regval; irqstate_t flags; @@ -721,39 +721,39 @@ static inline void lpc17_uart1config(void) /* Step 1: Enable power on UART1 */ flags = enter_critical_section(); - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCUART1; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Step 2: Enable clocking on UART */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_UART1_MASK; regval |= ((uint32_t)g_uart1priv.cclkdiv << SYSCON_PCLKSEL0_UART1_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); #endif /* Step 3: Configure I/O pins */ - lpc17_configgpio(GPIO_UART1_TXD); - lpc17_configgpio(GPIO_UART1_RXD); + lpc17_40_configgpio(GPIO_UART1_TXD); + lpc17_40_configgpio(GPIO_UART1_RXD); #if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) - lpc17_configgpio(GPIO_UART1_CTS); - lpc17_configgpio(GPIO_UART1_RTS); - lpc17_configgpio(GPIO_UART1_DCD); - lpc17_configgpio(GPIO_UART1_DSR); - lpc17_configgpio(GPIO_UART1_DTR); -#ifdef CONFIG_LPC17_UART1_RINGINDICATOR - lpc17_configgpio(GPIO_UART1_RI); + lpc17_40_configgpio(GPIO_UART1_CTS); + lpc17_40_configgpio(GPIO_UART1_RTS); + lpc17_40_configgpio(GPIO_UART1_DCD); + lpc17_40_configgpio(GPIO_UART1_DSR); + lpc17_40_configgpio(GPIO_UART1_DTR); +#ifdef CONFIG_LPC17_40_UART1_RINGINDICATOR + lpc17_40_configgpio(GPIO_UART1_RI); #endif #endif leave_critical_section(flags); }; #endif -#ifdef CONFIG_LPC17_UART2 -static inline void lpc17_uart2config(void) +#ifdef CONFIG_LPC17_40_UART2 +static inline void lpc17_40_uart2config(void) { uint32_t regval; irqstate_t flags; @@ -761,29 +761,29 @@ static inline void lpc17_uart2config(void) /* Step 1: Enable power on UART2 */ flags = enter_critical_section(); - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCUART2; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Step 2: Enable clocking on UART */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~SYSCON_PCLKSEL1_UART2_MASK; regval |= ((uint32_t)g_uart2priv.cclkdiv << SYSCON_PCLKSEL1_UART2_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); #endif /* Step 3: Configure I/O pins */ - lpc17_configgpio(GPIO_UART2_TXD); - lpc17_configgpio(GPIO_UART2_RXD); + lpc17_40_configgpio(GPIO_UART2_TXD); + lpc17_40_configgpio(GPIO_UART2_RXD); leave_critical_section(flags); }; #endif -#ifdef CONFIG_LPC17_UART3 -static inline void lpc17_uart3config(void) +#ifdef CONFIG_LPC17_40_UART3 +static inline void lpc17_40_uart3config(void) { uint32_t regval; irqstate_t flags; @@ -791,29 +791,29 @@ static inline void lpc17_uart3config(void) /* Step 1: Enable power on UART3 */ flags = enter_critical_section(); - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCUART3; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Step 2: Enable clocking on UART */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~SYSCON_PCLKSEL1_UART3_MASK; regval |= ((uint32_t)g_uart3priv.cclkdiv << SYSCON_PCLKSEL1_UART3_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); #endif /* Step 3: Configure I/O pins */ - lpc17_configgpio(GPIO_UART3_TXD); - lpc17_configgpio(GPIO_UART3_RXD); + lpc17_40_configgpio(GPIO_UART3_TXD); + lpc17_40_configgpio(GPIO_UART3_RXD); leave_critical_section(flags); }; #endif /************************************************************************************ - * Name: lpc17_uartdl + * Name: lpc17_40_uartdl * * Description: * Select a divider to produce the BAUD from the UART PCLK. @@ -828,34 +828,34 @@ static inline void lpc17_uart3config(void) ************************************************************************************/ #ifdef LPC176x -static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode) +static inline uint32_t lpc17_40_uartdl(uint32_t baud, uint8_t divcode) { uint32_t num; switch (divcode) { case SYSCON_PCLKSEL_CCLK4: /* PCLK_peripheral = CCLK/4 */ - num = (LPC17_CCLK / 4); + num = (LPC17_40_CCLK / 4); break; case SYSCON_PCLKSEL_CCLK: /* PCLK_peripheral = CCLK */ - num = LPC17_CCLK; + num = LPC17_40_CCLK; break; case SYSCON_PCLKSEL_CCLK2: /* PCLK_peripheral = CCLK/2 */ - num = (LPC17_CCLK / 2); + num = (LPC17_40_CCLK / 2); break; case SYSCON_PCLKSEL_CCLK8: /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ default: - num = (LPC17_CCLK / 8); + num = (LPC17_40_CCLK / 8); break; } return num / (baud << 4); } #else -static inline uint32_t lpc17_uartdl(uint32_t baud) +static inline uint32_t lpc17_40_uartdl(uint32_t baud) { return (uint32_t)BOARD_PCLK_FREQUENCY / (baud << 4); } @@ -883,15 +883,15 @@ static int up_setup(struct uart_dev_s *dev) /* Clear fifos */ - up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST)); + up_serialout(priv, LPC17_40_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST)); /* Set trigger */ - up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8)); + up_serialout(priv, LPC17_40_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8)); /* Set up the IER */ - priv->ier = up_serialin(priv, LPC17_UART_IER_OFFSET); + priv->ier = up_serialin(priv, LPC17_40_UART_IER_OFFSET); /* Set up the LCR */ @@ -924,44 +924,44 @@ static int up_setup(struct uart_dev_s *dev) * ignored by baudrate calculation => has to be disabled */ - up_serialout(priv, LPC17_UART_FDR_OFFSET, + up_serialout(priv, LPC17_40_UART_FDR_OFFSET, (1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT)); /* Enter DLAB=1 */ - up_serialout(priv, LPC17_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + up_serialout(priv, LPC17_40_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); /* Set the BAUD divisor */ #ifdef LPC176x - dl = lpc17_uartdl(priv->baud, priv->cclkdiv); + dl = lpc17_40_uartdl(priv->baud, priv->cclkdiv); #else - dl = lpc17_uartdl(priv->baud); + dl = lpc17_40_uartdl(priv->baud); #endif - up_serialout(priv, LPC17_UART_DLM_OFFSET, dl >> 8); - up_serialout(priv, LPC17_UART_DLL_OFFSET, dl & 0xff); + up_serialout(priv, LPC17_40_UART_DLM_OFFSET, dl >> 8); + up_serialout(priv, LPC17_40_UART_DLL_OFFSET, dl & 0xff); /* Clear DLAB */ - up_serialout(priv, LPC17_UART_LCR_OFFSET, lcr); + up_serialout(priv, LPC17_40_UART_LCR_OFFSET, lcr); /* Configure the FIFOs */ - up_serialout(priv, LPC17_UART_FCR_OFFSET, + up_serialout(priv, LPC17_40_UART_FCR_OFFSET, (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | UART_FCR_FIFOEN)); /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ #if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) - if (priv->uartbase == LPC17_UART1_BASE) + if (priv->uartbase == LPC17_40_UART1_BASE) { #if defined(CONFIG_UART1_IFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL) - up_serialout(priv, LPC17_UART_MCR_OFFSET, (UART_MCR_RTSEN | UART_MCR_CTSEN)); + up_serialout(priv, LPC17_40_UART_MCR_OFFSET, (UART_MCR_RTSEN | UART_MCR_CTSEN)); #elif defined(CONFIG_UART1_IFLOWCONTROL) - up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_RTSEN); + up_serialout(priv, LPC17_40_UART_MCR_OFFSET, UART_MCR_RTSEN); #else - up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_CTSEN); + up_serialout(priv, LPC17_40_UART_MCR_OFFSET, UART_MCR_CTSEN); #endif } #endif @@ -1068,7 +1068,7 @@ static int up_interrupt(int irq, void *context, void *arg) * termination conditions */ - status = up_serialin(priv, LPC17_UART_IIR_OFFSET); + status = up_serialin(priv, LPC17_40_UART_IIR_OFFSET); /* The UART_IIR_INTSTATUS bit should be zero if there are pending * interrupts @@ -1110,7 +1110,7 @@ static int up_interrupt(int irq, void *context, void *arg) { /* Read the modem status register (MSR) to clear */ - status = up_serialin(priv, LPC17_UART_MSR_OFFSET); + status = up_serialin(priv, LPC17_40_UART_MSR_OFFSET); _info("MSR: %02x\n", status); break; } @@ -1121,7 +1121,7 @@ static int up_interrupt(int irq, void *context, void *arg) { /* Read the line status register (LSR) to clear */ - status = up_serialin(priv, LPC17_UART_LSR_OFFSET); + status = up_serialin(priv, LPC17_40_UART_LSR_OFFSET); _info("LSR: %02x\n", status); break; } @@ -1235,27 +1235,27 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) */ #if 0 /* ifdef LPC176x */ - priv->cclkdiv = lpc17_uartcclkdiv(priv->baud); + priv->cclkdiv = lpc17_40_uartcclkdiv(priv->baud); #endif /* DLAB open latch */ /* REVISIT: Shouldn't we just call up_setup() to do all of the following? */ - lcr = getreg32(priv->uartbase + LPC17_UART_LCR_OFFSET); - up_serialout(priv, LPC17_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + lcr = getreg32(priv->uartbase + LPC17_40_UART_LCR_OFFSET); + up_serialout(priv, LPC17_40_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); /* Set the BAUD divisor */ #ifdef LPC176x - dl = lpc17_uartdl(priv->baud, priv->cclkdiv); + dl = lpc17_40_uartdl(priv->baud, priv->cclkdiv); #else - dl = lpc17_uartdl(priv->baud); + dl = lpc17_40_uartdl(priv->baud); #endif - up_serialout(priv, LPC17_UART_DLM_OFFSET, dl >> 8); - up_serialout(priv, LPC17_UART_DLL_OFFSET, dl & 0xff); + up_serialout(priv, LPC17_40_UART_DLM_OFFSET, dl >> 8); + up_serialout(priv, LPC17_40_UART_DLL_OFFSET, dl & 0xff); /* Clear DLAB */ - up_serialout(priv, LPC17_UART_LCR_OFFSET, lcr); + up_serialout(priv, LPC17_40_UART_LCR_OFFSET, lcr); } break; #endif @@ -1283,8 +1283,8 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; - *status = up_serialin(priv, LPC17_UART_LSR_OFFSET); - rbr = up_serialin(priv, LPC17_UART_RBR_OFFSET); + *status = up_serialin(priv, LPC17_40_UART_LSR_OFFSET); + rbr = up_serialin(priv, LPC17_40_UART_RBR_OFFSET); return rbr; } @@ -1310,7 +1310,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) priv->ier &= ~UART_IER_RBRIE; } - up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); + up_serialout(priv, LPC17_40_UART_IER_OFFSET, priv->ier); } /**************************************************************************** @@ -1324,7 +1324,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); + return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); } /**************************************************************************** @@ -1338,7 +1338,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_serialout(priv, LPC17_UART_THR_OFFSET, (uint32_t)ch); + up_serialout(priv, LPC17_40_UART_THR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -1359,7 +1359,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS priv->ier |= UART_IER_THREIE; - up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); + up_serialout(priv, LPC17_40_UART_IER_OFFSET, priv->ier); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -1371,7 +1371,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) else { priv->ier &= ~UART_IER_THREIE; - up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); + up_serialout(priv, LPC17_40_UART_IER_OFFSET, priv->ier); } leave_critical_section(flags); @@ -1388,7 +1388,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); + return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); } /**************************************************************************** @@ -1402,7 +1402,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); + return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); } /**************************************************************************** @@ -1426,43 +1426,43 @@ void up_earlyserialinit(void) { /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */ -#ifdef CONFIG_LPC17_UART0 +#ifdef CONFIG_LPC17_40_UART0 #ifdef LPC176x - g_uart0priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART0_BAUD); + g_uart0priv.cclkdiv = lpc17_40_uartcclkdiv(CONFIG_UART0_BAUD); #endif #ifndef CONFIG_UART0_SERIAL_CONSOLE - lpc17_uart0config(); + lpc17_40_uart0config(); #endif up_disableuartint(&g_uart0priv, NULL); #endif -#ifdef CONFIG_LPC17_UART1 +#ifdef CONFIG_LPC17_40_UART1 #ifdef LPC176x - g_uart1priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART1_BAUD); + g_uart1priv.cclkdiv = lpc17_40_uartcclkdiv(CONFIG_UART1_BAUD); #endif #ifndef CONFIG_UART1_SERIAL_CONSOLE - lpc17_uart1config(); + lpc17_40_uart1config(); #else #endif up_disableuartint(&g_uart1priv, NULL); #endif -#ifdef CONFIG_LPC17_UART2 +#ifdef CONFIG_LPC17_40_UART2 #ifdef LPC176x - g_uart2priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART2_BAUD); + g_uart2priv.cclkdiv = lpc17_40_uartcclkdiv(CONFIG_UART2_BAUD); #endif #ifndef CONFIG_UART2_SERIAL_CONSOLE - lpc17_uart2config(); + lpc17_40_uart2config(); #endif up_disableuartint(&g_uart2priv, NULL); #endif -#ifdef CONFIG_LPC17_UART3 +#ifdef CONFIG_LPC17_40_UART3 #ifdef LPC176x - g_uart3priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART3_BAUD); + g_uart3priv.cclkdiv = lpc17_40_uartcclkdiv(CONFIG_UART3_BAUD); #endif #ifndef CONFIG_UART3_SERIAL_CONSOLE - lpc17_uart3config(); + lpc17_40_uart3config(); #endif up_disableuartint(&g_uart3priv, NULL); #endif diff --git a/arch/arm/src/lpc17xx/lpc17_serial.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_serial.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h index 9e0205182bb..624deaa7b45 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_serial.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SERIAL_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SERIAL_H /************************************************************************************ * Included Files @@ -43,10 +43,10 @@ #include #include -#include "hardware/lpc17_uart.h" -#include "hardware/lpc17_syscon.h" +#include "hardware/lpc17_40_uart.h" +#include "hardware/lpc17_40_syscon.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" /************************************************************************************ * Pre-processor Definitions @@ -57,8 +57,8 @@ /* Are any UARTs enabled? */ #undef HAVE_UART -#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \ - defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3) +#if defined(CONFIG_LPC17_40_UART0) || defined(CONFIG_LPC17_40_UART1) || \ + defined(CONFIG_LPC17_40_UART2) || defined(CONFIG_LPC17_40_UART3) # define HAVE_UART 1 #endif @@ -66,22 +66,22 @@ * any UARTn, n=0,1,2,3 */ -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_40_UART0) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1) +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_40_UART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2) +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_40_UART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3) +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_40_UART3) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -102,7 +102,7 @@ # undef CONFIG_UART2_OFLOWCONTROL # undef CONFIG_UART3_IFLOWCONTROL # undef CONFIG_UART3_OFLOWCONTROL -#ifndef CONFIG_LPC17_UART1 +#ifndef CONFIG_LPC17_40_UART1 # undef CONFIG_UART1_IFLOWCONTROL # undef CONFIG_UART1_OFLOWCONTROL #endif @@ -130,4 +130,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SERIAL_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c similarity index 88% rename from arch/arm/src/lpc17xx/lpc17_spi.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c index c75a57fa80e..d56f89154ee 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_spi.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c * * Copyright (C) 2010, 2012-2013, 2016-2017 Gregory Nutt. All rights * reserved. @@ -56,11 +56,11 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_spi.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_spi.h" -#ifdef CONFIG_LPC17_SPI +#ifdef CONFIG_LPC17_40_SPI /**************************************************************************** * Pre-processor Definitions @@ -86,7 +86,7 @@ */ #define SPI_PCLKSET_DIV SYSCON_PCLKSEL_CCLK -#define SPI_CLOCK LPC17_CCLK +#define SPI_CLOCK LPC17_40_CCLK /**************************************************************************** * Private Types @@ -94,7 +94,7 @@ /* This structure descibes the state of the SSP driver */ -struct lpc17_spidev_s +struct lpc17_40_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ sem_t exclsem; /* Held while chip is selected for mutual exclusion */ @@ -125,28 +125,28 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_ static const struct spi_ops_s g_spiops = { .lock = spi_lock, - .select = lpc17_spiselect, + .select = lpc17_40_spiselect, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = 0, /* Not supported */ #endif - .status = lpc17_spistatus, + .status = lpc17_40_spistatus, #ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc17_spicmddata, + .cmddata = lpc17_40_spicmddata, #endif .send = spi_send, .sndblock = spi_sndblock, .recvblock = spi_recvblock, #ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc17_spiregister, /* Provided externally */ + .registercallback = lpc17_40_spiregister, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct lpc17_spidev_s g_spidev = +static struct lpc17_40_spidev_s g_spidev = { .spidev = { &g_spiops }, }; @@ -182,7 +182,7 @@ static struct lpc17_spidev_s g_spidev = static int spi_lock(FAR struct spi_dev_s *dev, bool lock) { - FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev; + FAR struct lpc17_40_spidev_s *priv = (FAR struct lpc17_40_spidev_s *)dev; int ret; if (lock) @@ -227,7 +227,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) { - FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev; + FAR struct lpc17_40_spidev_s *priv = (FAR struct lpc17_40_spidev_s *)dev; uint32_t divisor; uint32_t actual; @@ -263,7 +263,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) /* Save the new divisor value */ - putreg32(divisor, LPC17_SPI_CCR); + putreg32(divisor, LPC17_40_SPI_CCR); /* Calculate the new actual */ @@ -295,7 +295,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { - FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev; + FAR struct lpc17_40_spidev_s *priv = (FAR struct lpc17_40_spidev_s *)dev; uint32_t regval; /* Has the mode changed? */ @@ -304,7 +304,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { /* Yes... Set CR appropriately */ - regval = getreg32(LPC17_SPI_CR); + regval = getreg32(LPC17_40_SPI_CR); regval &= ~(SPI_CR_CPOL | SPI_CR_CPHA); switch (mode) @@ -329,7 +329,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) return; } - putreg32(regval, LPC17_SPI_CR); + putreg32(regval, LPC17_40_SPI_CR); /* Save the mode so that subsequent re-configuratins will be faster */ @@ -354,7 +354,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) { - FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev; + FAR struct lpc17_40_spidev_s *priv = (FAR struct lpc17_40_spidev_s *)dev; uint32_t regval; /* Has the number of bits changed? */ @@ -365,11 +365,11 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) { /* Yes... Set CR appropriately */ - regval = getreg32(LPC17_SPI_CR); + regval = getreg32(LPC17_40_SPI_CR); regval &= ~SPI_CR_BITS_MASK; regval |= (nbits << SPI_CR_BITS_SHIFT) & SPI_CR_BITS_MASK; regval |= SPI_CR_BITENABLE; - regval = getreg32(LPC17_SPI_CR); + regval = getreg32(LPC17_40_SPI_CR); /* Save the selection so the subsequence re-configurations will be faster */ @@ -397,19 +397,19 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) { /* Write the data to transmitted to the SPI Data Register */ - putreg32((uint32_t)wd, LPC17_SPI_DR); + putreg32((uint32_t)wd, LPC17_40_SPI_DR); /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The * SPIF bit will be set after the last sampling clock edge of the SPI * data transfer. */ - while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC17_40_SPI_SR) & SPI_SR_SPIF) == 0); /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC17_SPI_SR); - return (uint16_t)getreg32(LPC17_SPI_DR); + (void)getreg32(LPC17_40_SPI_SR); + return (uint16_t)getreg32(LPC17_40_SPI_DR); } /**************************************************************************** @@ -442,18 +442,18 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size /* Write the data to transmitted to the SPI Data Register */ data = *ptr++; - putreg32((uint32_t)data, LPC17_SPI_DR); + putreg32((uint32_t)data, LPC17_40_SPI_DR); /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The * SPIF bit will be set after the last sampling clock edge of the SPI * data transfer. */ - while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC17_40_SPI_SR) & SPI_SR_SPIF) == 0); /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC17_SPI_SR); + (void)getreg32(LPC17_40_SPI_SR); nwords--; } } @@ -488,22 +488,22 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw * read data. */ - putreg32(0xff, LPC17_SPI_DR); + putreg32(0xff, LPC17_40_SPI_DR); /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The * SPIF bit will be set after the last sampling clock edge of the SPI * data transfer. */ - while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC17_40_SPI_SR) & SPI_SR_SPIF) == 0); /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC17_SPI_SR); + (void)getreg32(LPC17_40_SPI_SR); /* Read the received data from the SPI Data Register */ - *ptr++ = (uint8_t)getreg32(LPC17_SPI_DR); + *ptr++ = (uint8_t)getreg32(LPC17_40_SPI_DR); nwords--; } } @@ -513,7 +513,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw ****************************************************************************/ /**************************************************************************** - * Name: lpc17_spibus_initialize + * Name: lpc17_40_spibus_initialize * * Description: * Initialize the selected SPI port. @@ -526,9 +526,9 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw * ****************************************************************************/ -FAR struct spi_dev_s *lpc17_spibus_initialize(int port) +FAR struct spi_dev_s *lpc17_40_spibus_initialize(int port) { - FAR struct lpc17_spidev_s *priv = &g_spidev; + FAR struct lpc17_40_spidev_s *priv = &g_spidev; irqstate_t flags; uint32_t regval; @@ -542,28 +542,28 @@ FAR struct spi_dev_s *lpc17_spibus_initialize(int port) */ flags = enter_critical_section(); - lpc17_configgpio(GPIO_SPI_SCK); - lpc17_configgpio(GPIO_SPI_MISO); - lpc17_configgpio(GPIO_SPI_MOSI); + lpc17_40_configgpio(GPIO_SPI_SCK); + lpc17_40_configgpio(GPIO_SPI_MISO); + lpc17_40_configgpio(GPIO_SPI_MOSI); /* Configure clocking */ - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_SPI_MASK; regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); /* Enable peripheral clocking to SPI and SPI1 */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCSPI; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); leave_critical_section(flags); /* Configure 8-bit SPI mode and master mode */ putreg32(SPI_CR_BITS_8BITS | SPI_CR_BITENABLE | SPI_CR_MSTR, - LPC17_SPI_CR); + LPC17_40_SPI_CR); /* Set the initial SPI configuration */ @@ -581,4 +581,4 @@ FAR struct spi_dev_s *lpc17_spibus_initialize(int port) return &priv->spidev; } -#endif /* CONFIG_LPC17_SPI */ +#endif /* CONFIG_LPC17_40_SPI */ diff --git a/arch/arm/src/lpc17xx/lpc17_spi.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.h similarity index 81% rename from arch/arm/src/lpc17xx/lpc17_spi.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_spi.h index c807b88a53f..37ad9cd98fd 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_spi.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_spi.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SPI_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SPI_H /************************************************************************************ * Included Files @@ -44,7 +44,7 @@ #include -#include "hardware/lpc17_spi.h" +#include "hardware/lpc17_40_spi.h" /************************************************************************************ * Pre-processor Definitions @@ -58,7 +58,7 @@ * Public Data ************************************************************************************/ -#ifdef CONFIG_LPC17_SPI +#ifdef CONFIG_LPC17_40_SPI #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -73,7 +73,7 @@ extern "C" struct spi_dev_s; /* Forward reference */ /************************************************************************************ - * Name: lpc17_spibus_initialize + * Name: lpc17_40_spibus_initialize * * Description: * Initialize the selected SPI port. @@ -86,38 +86,38 @@ struct spi_dev_s; /* Forward reference */ * ************************************************************************************/ -FAR struct spi_dev_s *lpc17_spibus_initialize(int port); +FAR struct spi_dev_s *lpc17_40_spibus_initialize(int port); /************************************************************************************ - * Name: lpc17_spiselect, lpc17_status, and lpc17_spicmddata + * Name: lpc17_40_spiselect, lpc17_40_status, and lpc17_40_spicmddata * * Description: * These external functions must be provided by board-specific logic. They are * implementations of the select, status, and cmddata methods of the SPI interface * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including lpc17_spibus_initialize()) are provided by common LPC17xx logic. To use + * including lpc17_40_spibus_initialize()) are provided by common LPC17xx/LPC40xx logic. To use * this common SPI logic on your board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI chip select pins. - * 2. Provide lpc17_spiselect() and lpc17_spistatus() functions in your board- + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI chip select pins. + * 2. Provide lpc17_40_spiselect() and lpc17_40_spistatus() functions in your board- * specific logic. These functions will perform chip selection and status * operations using GPIOs in the way your board is configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * lpc17_spicmddata() functions in your board-specific logic. This function + * lpc17_40_spicmddata() functions in your board-specific logic. This function * will perform cmd/data selection operations using GPIOs in the way your * board is configured. - * 3. Add a call to lpc17_spibus_initialize() in your low level application + * 3. Add a call to lpc17_40_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_spibus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_spibus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), * for example, will bind the SPI driver to the SPI MMC/SD driver). * ************************************************************************************/ -void lpc17_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); +void lpc17_40_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +uint8_t lpc17_40_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA -int lpc17_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int lpc17_40_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** @@ -139,7 +139,7 @@ int lpc17_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); void spi_flush(FAR struct spi_dev_s *dev); /**************************************************************************** - * Name: lpc17_spiregister + * Name: lpc17_40_spiregister * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -159,7 +159,7 @@ void spi_flush(FAR struct spi_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -int lpc17_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, +int lpc17_40_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, FAR void *arg); #endif @@ -168,5 +168,5 @@ int lpc17_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_LPC17_SPI */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */ +#endif /* CONFIG_LPC17_40_SPI */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SPI_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c similarity index 77% rename from arch/arm/src/lpc17xx/lpc17_ssp.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c index 477572c8695..f91ca568ccc 100644 --- a/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_ssp.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c * * Copyright (C) 2010-2013, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -55,12 +55,12 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) || \ - defined(CONFIG_LPC17_SSP2) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) /**************************************************************************** * Pre-processor Definitions @@ -86,15 +86,15 @@ * use the CCLK undivided to get the SSP_CLOCK. */ -# if LPC17_CCLK > 100000000 +# if LPC17_40_CCLK > 100000000 # error "CCLK <= 100,000,000 assumed" # endif # define SSP_PCLKSET_DIV SYSCON_PCLKSEL_CCLK -# define SSP_CLOCK LPC17_CCLK +# define SSP_CLOCK LPC17_40_CCLK -#elif defined(LPC178x) -/* All peripherals are clocked by the same peripheral clock in the LPC178x +#elif defined(LPC178x_40xx) +/* All peripherals are clocked by the same peripheral clock in the LPC178x/40xx * family. */ @@ -108,11 +108,11 @@ /* This structure descibes the state of the SSP driver */ -struct lpc17_sspdev_s +struct lpc17_40_sspdev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t sspbase; /* SPIn base address */ -#ifdef CONFIG_LPC17_SSP_INTERRUPTS +#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS uint8_t sspirq; /* SPI IRQ number */ #endif sem_t exclsem; /* Held while chip is selected for mutual exclusion */ @@ -128,8 +128,8 @@ struct lpc17_sspdev_s /* Helpers */ -static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset); -static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset, +static inline uint32_t ssp_getreg(FAR struct lpc17_40_sspdev_s *priv, uint8_t offset); +static inline void ssp_putreg(FAR struct lpc17_40_sspdev_s *priv, uint8_t offset, uint32_t value); /* SPI methods */ @@ -144,118 +144,118 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_ /* Initialization */ -#ifdef CONFIG_LPC17_SSP0 -static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void); +#ifdef CONFIG_LPC17_40_SSP0 +static inline FAR struct lpc17_40_sspdev_s *lpc17_40_ssp0initialize(void); #endif -#ifdef CONFIG_LPC17_SSP1 -static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void); +#ifdef CONFIG_LPC17_40_SSP1 +static inline FAR struct lpc17_40_sspdev_s *lpc17_40_ssp1initialize(void); #endif -#ifdef CONFIG_LPC17_SSP2 -static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void); +#ifdef CONFIG_LPC17_40_SSP2 +static inline FAR struct lpc17_40_sspdev_s *lpc17_40_ssp2initialize(void); #endif /**************************************************************************** * Private Data ****************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 static const struct spi_ops_s g_spi0ops = { .lock = ssp_lock, - .select = lpc17_ssp0select, /* Provided externally */ + .select = lpc17_40_ssp0select, /* Provided externally */ .setfrequency = ssp_setfrequency, .setmode = ssp_setmode, .setbits = ssp_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = 0, /* Not supported */ #endif - .status = lpc17_ssp0status, /* Provided externally */ + .status = lpc17_40_ssp0status, /* Provided externally */ #ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc17_ssp0cmddata, /* Provided externally */ + .cmddata = lpc17_40_ssp0cmddata, /* Provided externally */ #endif .send = ssp_send, .sndblock = ssp_sndblock, .recvblock = ssp_recvblock, #ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc17_ssp0register, /* Provided externally */ + .registercallback = lpc17_40_ssp0register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct lpc17_sspdev_s g_ssp0dev = +static struct lpc17_40_sspdev_s g_ssp0dev = { .spidev = { &g_spi0ops }, - .sspbase = LPC17_SSP0_BASE, -#ifdef CONFIG_LPC17_SSP_INTERRUPTS - .sspirq = LPC17_IRQ_SSP0, + .sspbase = LPC17_40_SSP0_BASE, +#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS + .sspirq = LPC17_40_IRQ_SSP0, #endif }; -#endif /* CONFIG_LPC17_SSP0 */ +#endif /* CONFIG_LPC17_40_SSP0 */ -#ifdef CONFIG_LPC17_SSP1 +#ifdef CONFIG_LPC17_40_SSP1 static const struct spi_ops_s g_spi1ops = { .lock = ssp_lock, - .select = lpc17_ssp1select, /* Provided externally */ + .select = lpc17_40_ssp1select, /* Provided externally */ .setfrequency = ssp_setfrequency, .setmode = ssp_setmode, .setbits = ssp_setbits, - .status = lpc17_ssp1status, /* Provided externally */ + .status = lpc17_40_ssp1status, /* Provided externally */ #ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc17_ssp1cmddata, /* Provided externally */ + .cmddata = lpc17_40_ssp1cmddata, /* Provided externally */ #endif .send = ssp_send, .sndblock = ssp_sndblock, .recvblock = ssp_recvblock, #ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc17_ssp1register, /* Provided externally */ + .registercallback = lpc17_40_ssp1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct lpc17_sspdev_s g_ssp1dev = +static struct lpc17_40_sspdev_s g_ssp1dev = { .spidev = { &g_spi1ops }, - .sspbase = LPC17_SSP1_BASE, -#ifdef CONFIG_LPC17_SSP_INTERRUPTS - .sspirq = LPC17_IRQ_SSP1, + .sspbase = LPC17_40_SSP1_BASE, +#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS + .sspirq = LPC17_40_IRQ_SSP1, #endif }; -#endif /* CONFIG_LPC17_SSP1 */ +#endif /* CONFIG_LPC17_40_SSP1 */ -#ifdef CONFIG_LPC17_SSP2 +#ifdef CONFIG_LPC17_40_SSP2 static const struct spi_ops_s g_spi2ops = { .lock = ssp_lock, - .select = lpc17_ssp2select, /* Provided externally */ + .select = lpc17_40_ssp2select, /* Provided externally */ .setfrequency = ssp_setfrequency, .setmode = ssp_setmode, .setbits = ssp_setbits, - .status = lpc17_ssp2status, /* Provided externally */ + .status = lpc17_40_ssp2status, /* Provided externally */ #ifdef CONFIG_SPI_CMDDATA - .cmddata = lpc17_ssp2cmddata, /* Provided externally */ + .cmddata = lpc17_40_ssp2cmddata, /* Provided externally */ #endif .send = ssp_send, .sndblock = ssp_sndblock, .recvblock = ssp_recvblock, #ifdef CONFIG_SPI_CALLBACK - .registercallback = lpc17_ssp2register, /* Provided externally */ + .registercallback = lpc17_40_ssp2register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct lpc17_sspdev_s g_ssp2dev = +static struct lpc17_40_sspdev_s g_ssp2dev = { .spidev = { &g_spi2ops }, - .sspbase = LPC17_SSP2_BASE, -#ifdef CONFIG_LPC17_SSP_INTERRUPTS - .sspirq = LPC17_IRQ_SSP2, + .sspbase = LPC17_40_SSP2_BASE, +#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS + .sspirq = LPC17_40_IRQ_SSP2, #endif }; -#endif /* CONFIG_LPC17_SSP2 */ +#endif /* CONFIG_LPC17_40_SSP2 */ /**************************************************************************** * Public Data @@ -280,7 +280,7 @@ static struct lpc17_sspdev_s g_ssp2dev = * ****************************************************************************/ -static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset) +static inline uint32_t ssp_getreg(FAR struct lpc17_40_sspdev_s *priv, uint8_t offset) { return getreg32(priv->sspbase + (uint32_t)offset); } @@ -301,7 +301,7 @@ static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offse * ****************************************************************************/ -static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset, uint32_t value) +static inline void ssp_putreg(FAR struct lpc17_40_sspdev_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->sspbase + (uint32_t)offset); } @@ -329,7 +329,7 @@ static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset, u static int ssp_lock(FAR struct spi_dev_s *dev, bool lock) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; int ret; if (lock) @@ -374,7 +374,7 @@ static int ssp_lock(FAR struct spi_dev_s *dev, bool lock) static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; uint32_t cpsdvsr; uint32_t scr; uint32_t regval; @@ -397,7 +397,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * * Let's try for a solution with the smallest value of SCR. NOTES: * (1) In the calculations below, the value of the variable 'scr' is - * (SCR+1) in the above equation. (2) On slower LPC17xx parts, SCR + * (SCR+1) in the above equation. (2) On slower LPC17xx/LPC40xx parts, SCR * will probably always be zero. */ @@ -440,12 +440,12 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) /* Save the new CPSDVSR and SCR values */ - ssp_putreg(priv, LPC17_SSP_CPSR_OFFSET, cpsdvsr); + ssp_putreg(priv, LPC17_40_SSP_CPSR_OFFSET, cpsdvsr); - regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET); + regval = ssp_getreg(priv, LPC17_40_SSP_CR0_OFFSET); regval &= ~SSP_CR0_SCR_MASK; regval |= ((scr - 1) << SSP_CR0_SCR_SHIFT); - ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, regval); + ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, regval); /* Calculate the new actual */ @@ -477,7 +477,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; uint32_t regval; /* Has the mode changed? */ @@ -486,7 +486,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { /* Yes... Set CR0 appropriately */ - regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET); + regval = ssp_getreg(priv, LPC17_40_SSP_CR0_OFFSET); regval &= ~(SSP_CR0_CPOL | SSP_CR0_CPHA); switch (mode) @@ -512,7 +512,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) return; } - ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, regval); + ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, regval); /* Save the mode so that subsequent re-configurations will be faster */ @@ -537,7 +537,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; uint32_t regval; /* Has the number of bits changed? */ @@ -548,10 +548,10 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits) { /* Yes... Set CR1 appropriately */ - regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET); + regval = ssp_getreg(priv, LPC17_40_SSP_CR0_OFFSET); regval &= ~SSP_CR0_DSS_MASK; regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT); - ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, regval); + ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, regval); /* Save the selection so the subsequence re-configurations will be faster */ @@ -577,24 +577,24 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits) static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; register uint32_t regval; /* Wait while the TX FIFO is full */ - while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF)); + while (!(ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_TNF)); /* Write the byte to the TX FIFO */ - ssp_putreg(priv, LPC17_SSP_DR_OFFSET, (uint32_t)wd); + ssp_putreg(priv, LPC17_40_SSP_DR_OFFSET, (uint32_t)wd); /* Wait for the RX FIFO not empty */ - while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE)); + while (!(ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE)); /* Get the value from the RX FIFO and return it */ - regval = ssp_getreg(priv, LPC17_SSP_DR_OFFSET); + regval = ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET); spiinfo("%04x->%04x\n", wd, regval); return (uint16_t)regval; } @@ -620,7 +620,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd) static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; union { FAR const uint8_t *p8; @@ -638,7 +638,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size { /* While the TX FIFO is not full and there are bytes left to send */ - while ((ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords) + while ((ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords) { /* Fetch the data to send */ @@ -653,7 +653,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size /* Send the data */ - ssp_putreg(priv, LPC17_SSP_DR_OFFSET, data); + ssp_putreg(priv, LPC17_40_SSP_DR_OFFSET, data); nwords--; } } @@ -665,12 +665,12 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size { /* Is there anything in the RX fifo? */ - sr = ssp_getreg(priv, LPC17_SSP_SR_OFFSET); + sr = ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET); if ((sr & SSP_SR_RNE) != 0) { /* Yes.. Read and discard */ - (void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET); + (void)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET); } /* There is a race condition where TFE may go true just before @@ -682,7 +682,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size else if ((sr & SSP_SR_TFE) != 0) { up_udelay(100); - sr = ssp_getreg(priv, LPC17_SSP_SR_OFFSET); + sr = ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET); } } while ((sr & SSP_SR_RNE) != 0 || (sr & SSP_SR_TFE) == 0); @@ -709,7 +709,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; union { FAR uint8_t *p8; @@ -732,10 +732,10 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw */ spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords); - while ((ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF) && - (rxpending < LPC17_SSP_FIFOSZ) && nwords) + while ((ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_TNF) && + (rxpending < LPC17_40_SSP_FIFOSZ) && nwords) { - ssp_putreg(priv, LPC17_SSP_DR_OFFSET, 0xffff); + ssp_putreg(priv, LPC17_40_SSP_DR_OFFSET, 0xffff); nwords--; rxpending++; } @@ -743,9 +743,9 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */ spiinfo("RX: rxpending: %d\n", rxpending); - while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE) + while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE) { - data = (uint8_t)ssp_getreg(priv, LPC17_SSP_DR_OFFSET); + data = (uint8_t)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET); if (priv->nbits > 8) { *u.p16++ = (uint16_t)data; @@ -760,7 +760,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw } /**************************************************************************** - * Name: lpc17_ssp0initialize + * Name: lpc17_40_ssp0initialize * * Description: * Initialize the SSP0 @@ -773,8 +773,8 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw * ****************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void) +#ifdef CONFIG_LPC17_40_SSP0 +static inline FAR struct lpc17_40_sspdev_s *lpc17_40_ssp0initialize(void) { irqstate_t flags; uint32_t regval; @@ -789,24 +789,24 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void) */ flags = enter_critical_section(); - lpc17_configgpio(GPIO_SSP0_SCK); - lpc17_configgpio(GPIO_SSP0_MISO); - lpc17_configgpio(GPIO_SSP0_MOSI); + lpc17_40_configgpio(GPIO_SSP0_SCK); + lpc17_40_configgpio(GPIO_SSP0_MISO); + lpc17_40_configgpio(GPIO_SSP0_MOSI); /* Configure clocking */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~SYSCON_PCLKSEL1_SSP0_MASK; regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); #endif /* Enable peripheral clocking to SSP0 */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCSSP0; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); leave_critical_section(flags); return &g_ssp0dev; @@ -814,7 +814,7 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void) #endif /**************************************************************************** - * Name: lpc17_ssp1initialize + * Name: lpc17_40_ssp1initialize * * Description: * Initialize the SSP1 @@ -827,8 +827,8 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void) * ****************************************************************************/ -#ifdef CONFIG_LPC17_SSP1 -static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void) +#ifdef CONFIG_LPC17_40_SSP1 +static inline FAR struct lpc17_40_sspdev_s *lpc17_40_ssp1initialize(void) { irqstate_t flags; uint32_t regval; @@ -843,24 +843,24 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void) */ flags = enter_critical_section(); - lpc17_configgpio(GPIO_SSP1_SCK); - lpc17_configgpio(GPIO_SSP1_MISO); - lpc17_configgpio(GPIO_SSP1_MOSI); + lpc17_40_configgpio(GPIO_SSP1_SCK); + lpc17_40_configgpio(GPIO_SSP1_MISO); + lpc17_40_configgpio(GPIO_SSP1_MOSI); /* Configure clocking */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_SSP1_MASK; regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); #endif /* Enable peripheral clocking to SSP0 and SSP1 */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCSSP1; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); leave_critical_section(flags); return &g_ssp1dev; @@ -868,7 +868,7 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void) #endif /**************************************************************************** - * Name: lpc17_ssp2initialize + * Name: lpc17_40_ssp2initialize * * Description: * Initialize the SSP2 @@ -881,8 +881,8 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void) * ****************************************************************************/ -#ifdef CONFIG_LPC17_SSP2 -static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void) +#ifdef CONFIG_LPC17_40_SSP2 +static inline FAR struct lpc17_40_sspdev_s *lpc17_40_ssp2initialize(void) { irqstate_t flags; uint32_t regval; @@ -896,24 +896,24 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void) */ flags = enter_critical_section(); - lpc17_configgpio(GPIO_SSP2_SCK); - lpc17_configgpio(GPIO_SSP2_MISO); - lpc17_configgpio(GPIO_SSP2_MOSI); + lpc17_40_configgpio(GPIO_SSP2_SCK); + lpc17_40_configgpio(GPIO_SSP2_MISO); + lpc17_40_configgpio(GPIO_SSP2_MOSI); /* Configure clocking */ #ifdef LPC176x - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_SSP2_MASK; regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP2_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); #endif /* Enable peripheral clocking to SSP0 and SSP1 */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCSSP2; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); leave_critical_section(flags); return &g_ssp2dev; @@ -925,7 +925,7 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_sspbus_initialize + * Name: lpc17_40_sspbus_initialize * * Description: * Initialize the selected SSP port. @@ -938,9 +938,9 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void) * ****************************************************************************/ -FAR struct spi_dev_s *lpc17_sspbus_initialize(int port) +FAR struct spi_dev_s *lpc17_40_sspbus_initialize(int port) { - FAR struct lpc17_sspdev_s *priv; + FAR struct lpc17_40_sspdev_s *priv; uint32_t regval; int i; @@ -948,19 +948,19 @@ FAR struct spi_dev_s *lpc17_sspbus_initialize(int port) switch (port) { -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 case 0: - priv = lpc17_ssp0initialize(); + priv = lpc17_40_ssp0initialize(); break; #endif -#ifdef CONFIG_LPC17_SSP1 +#ifdef CONFIG_LPC17_40_SSP1 case 1: - priv = lpc17_ssp1initialize(); + priv = lpc17_40_ssp1initialize(); break; #endif -#ifdef CONFIG_LPC17_SSP2 +#ifdef CONFIG_LPC17_40_SSP2 case 2: - priv = lpc17_ssp2initialize(); + priv = lpc17_40_ssp2initialize(); break; #endif default: @@ -969,12 +969,12 @@ FAR struct spi_dev_s *lpc17_sspbus_initialize(int port) /* Configure 8-bit SPI mode */ - ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT | SSP_CR0_FRF_SPI); + ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT | SSP_CR0_FRF_SPI); /* Disable the SSP and all interrupts (we'll poll for all data) */ - ssp_putreg(priv, LPC17_SSP_CR1_OFFSET, 0); - ssp_putreg(priv, LPC17_SSP_IMSC_OFFSET, 0); + ssp_putreg(priv, LPC17_40_SSP_CR1_OFFSET, 0); + ssp_putreg(priv, LPC17_40_SSP_IMSC_OFFSET, 0); /* Set the initial SSP configuration */ @@ -992,11 +992,11 @@ FAR struct spi_dev_s *lpc17_sspbus_initialize(int port) /* Enable the SPI */ - regval = ssp_getreg(priv, LPC17_SSP_CR1_OFFSET); - ssp_putreg(priv, LPC17_SSP_CR1_OFFSET, regval | SSP_CR1_SSE); - for (i = 0; i < LPC17_SSP_FIFOSZ; i++) + regval = ssp_getreg(priv, LPC17_40_SSP_CR1_OFFSET); + ssp_putreg(priv, LPC17_40_SSP_CR1_OFFSET, regval | SSP_CR1_SSE); + for (i = 0; i < LPC17_40_SSP_FIFOSZ; i++) { - (void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET); + (void)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET); } return &priv->spidev; @@ -1019,28 +1019,28 @@ FAR struct spi_dev_s *lpc17_sspbus_initialize(int port) void ssp_flush(FAR struct spi_dev_s *dev) { - FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev; + FAR struct lpc17_40_sspdev_s *priv = (FAR struct lpc17_40_sspdev_s *)dev; /* Wait for the TX FIFO not full indication */ - while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF)); - ssp_putreg(priv, LPC17_SSP_DR_OFFSET, 0xff); + while (!(ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_TNF)); + ssp_putreg(priv, LPC17_40_SSP_DR_OFFSET, 0xff); /* Wait until TX FIFO and TX shift buffer are empty */ - while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_BSY); + while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_BSY); /* Wait until RX FIFO is not empty */ - while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE)); + while (!(ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE)); /* Then read and discard bytes until the RX FIFO is empty */ do { - (void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET); + (void)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET); } - while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE); + while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE); } -#endif /* CONFIG_LPC17_SSP0/1 */ +#endif /* CONFIG_LPC17_40_SSP0/1 */ diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.h similarity index 75% rename from arch/arm/src/lpc17xx/lpc17_ssp.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.h index d08e1b8d179..4f4bb4c4179 100644 --- a/arch/arm/src/lpc17xx/lpc17_ssp.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_ssp.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.h * * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SSP_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SSP_H /************************************************************************************ * Included Files @@ -44,9 +44,9 @@ #include -#include "hardware/lpc17_ssp.h" +#include "hardware/lpc17_40_ssp.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) /************************************************************************************ * Pre-processor Definitions @@ -71,7 +71,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: lpc17_sspbus_initialize + * Name: lpc17_40_sspbus_initialize * * Description: * Initialize the selected SSP port. @@ -84,47 +84,47 @@ extern "C" * ************************************************************************************/ -FAR struct spi_dev_s *lpc17_sspbus_initialize(int port); +FAR struct spi_dev_s *lpc17_40_sspbus_initialize(int port); /************************************************************************************ - * Name: lpc17_ssp0/ssp1select, lpc17_ssp0/ssp1status, and lpc17_ssp0/ssp1cmddata + * Name: lpc17_40_ssp0/ssp1select, lpc17_40_ssp0/ssp1status, and lpc17_40_ssp0/ssp1cmddata * * Description: * These external functions must be provided by board-specific logic. They are * implementations of the select, status, and cmddata methods of the SPI interface * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including lpc17_sspbus_initialize()) are provided by common LPC17xx logic. To use + * including lpc17_40_sspbus_initialize()) are provided by common LPC17xx/LPC40xx logic. To use * this common SPI logic on your board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SSP chip select pins. - * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * 1. Provide logic in lpc17_40_boardinitialize() to configure SSP chip select pins. + * 2. Provide lpc17_40_ssp0/ssp1select() and lpc17_40_ssp0/ssp1status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * lpc17_ssp0/ssp1cmddata() functions in your board-specific logic. These + * lpc17_40_ssp0/ssp1cmddata() functions in your board-specific logic. These * functions will perform cmd/data selection operations using GPIOs in the way * your board is configured. - * 3. Add a call to lpc17_sspbus_initialize() in your low level application + * 3. Add a call to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SSP driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), * for example, will bind the SSP driver to the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid); +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA -int lpc17_ssp0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int lpc17_40_ssp0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #endif -#ifdef CONFIG_LPC17_SSP1 -void lpc17_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid); +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA -int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int lpc17_40_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #endif @@ -144,12 +144,12 @@ int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); * ****************************************************************************/ -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) void ssp_flush(FAR struct spi_dev_s *dev); #endif /**************************************************************************** - * Name: lpc17_ssp0/1register + * Name: lpc17_40_ssp0/1register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -169,13 +169,13 @@ void ssp_flush(FAR struct spi_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_LPC17_SSP0 -int lpc17_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, +#ifdef CONFIG_LPC17_40_SSP0 +int lpc17_40_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, FAR void *arg); #endif -#ifdef CONFIG_LPC17_SSP1 -int lpc17_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, +#ifdef CONFIG_LPC17_40_SSP1 +int lpc17_40_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, FAR void *arg); #endif #endif @@ -185,5 +185,5 @@ int lpc17_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H */ +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SSP_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_start.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c similarity index 95% rename from arch/arm/src/lpc17xx/lpc17_start.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_start.c index 441a0a38e83..a985dd2c128 100644 --- a/arch/arm/src/lpc17xx/lpc17_start.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_start.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_start.c * * Copyright (C) 2010, 2012-2013, 2015, 2018 Gregory Nutt. All rights * reserved. @@ -52,10 +52,10 @@ #include "up_internal.h" #include "nvic.h" -#include "lpc17_clockconfig.h" -#include "lpc17_lowputc.h" -#include "lpc17_userspace.h" -#include "lpc17_start.h" +#include "lpc17_40_clockconfig.h" +#include "lpc17_40_lowputc.h" +#include "lpc17_40_userspace.h" +#include "lpc17_40_start.h" /**************************************************************************** * Pre-processor Definitions @@ -106,7 +106,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #endif /**************************************************************************** - * Name: lpc17_fpuconfig + * Name: lpc17_40_fpuconfig * * Description: * Configure the FPU. Relative bit settings: @@ -131,7 +131,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU #ifndef CONFIG_ARMV7M_LAZYFPU -static inline void lpc17_fpuconfig(void) +static inline void lpc17_40_fpuconfig(void) { uint32_t regval; @@ -161,7 +161,7 @@ static inline void lpc17_fpuconfig(void) #else -static inline void lpc17_fpuconfig(void) +static inline void lpc17_40_fpuconfig(void) { uint32_t regval; @@ -192,7 +192,7 @@ static inline void lpc17_fpuconfig(void) #endif #else -# define lpc17_fpuconfig() +# define lpc17_40_fpuconfig() #endif /**************************************************************************** @@ -230,9 +230,9 @@ void __start(void) /* Configure the uart so that we can get debug output as soon as possible */ - lpc17_clockconfig(); - lpc17_fpuconfig(); - lpc17_lowsetup(); + lpc17_40_clockconfig(); + lpc17_40_fpuconfig(); + lpc17_40_lowsetup(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -273,13 +273,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - lpc17_userspace(); + lpc17_40_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - lpc17_boardinitialize(); + lpc17_40_boardinitialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/lpc17xx/lpc17_start.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h similarity index 90% rename from arch/arm/src/lpc17xx/lpc17_start.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_start.h index 79d6fbac397..3bcbf3a1c8d 100644 --- a/arch/arm/src/lpc17xx/lpc17_start.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_start.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_start.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_START_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_START_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_START_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_START_H /************************************************************************************ * Included Files @@ -63,16 +63,16 @@ extern const uintptr_t g_idle_topstack; ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry * point is called early in the initialization -- after clocking and memory have * been configured but before caches have been enabled and before any devices have * been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void); +void lpc17_40_boardinitialize(void); -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_START_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_START_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_timer.c similarity index 80% rename from arch/arm/src/lpc17xx/lpc17_timer.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_timer.c index ea780238f77..4db14dd9f18 100644 --- a/arch/arm/src/lpc17xx/lpc17_timer.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_timer.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_timer.c * * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,17 +54,17 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_timer.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_timer.h" #include "hardware/lpc176x_pinconfig.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lpc176x_gpio.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the TIMER upper half driver. */ -#if defined(CONFIG_LPC17_TMR0) +#if defined(CONFIG_LPC17_40_TMR0) /**************************************************************************** * Pre-processor Definitions @@ -94,7 +94,7 @@ ****************************************************************************/ /* This structure represents the state of one PWM timer */ -struct lpc17_timer_s +struct lpc17_40_timer_s { FAR const struct pwm_ops_s *ops; /* PWM operations */ uint8_t timid; /* Timer ID {0,...,7} */ @@ -111,18 +111,18 @@ struct lpc17_timer_s ****************************************************************************/ /* Register access */ -static uint32_t timer_getreg(struct lpc17_timer_s *priv, int offset); -static void timer_putreg(struct lpc17_timer_s *priv, int offset, uint32_t value); +static uint32_t timer_getreg(struct lpc17_40_timer_s *priv, int offset); +static void timer_putreg(struct lpc17_40_timer_s *priv, int offset, uint32_t value); #ifdef CONFIG_DEBUG_PWM_INFO -static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg); +static void timer_dumpregs(struct lpc17_40_timer_s *priv, FAR const char *msg); #else # define timer_dumpregs(priv,msg) #endif /* Timer management */ -static int timer_timer(FAR struct lpc17_timer_s *priv, +static int timer_timer(FAR struct lpc17_40_timer_s *priv, FAR const struct pwm_info_s *info); /* PWM driver methods */ @@ -151,14 +151,14 @@ static const struct pwm_ops_s g_pwmops = .ioctl = timer_ioctl, }; -#ifdef CONFIG_LPC17_TMR0 -static struct lpc17_timer_s g_pwm1dev = +#ifdef CONFIG_LPC17_40_TMR0 +static struct lpc17_40_timer_s g_pwm1dev = { .ops = &g_pwmops, .timid = 1, - .channel = CONFIG_LPC17_MAT0_PIN, + .channel = CONFIG_LPC17_40_MAT0_PIN, .timtype = TIMTYPE_TIM1, - .base = LPC17_TMR1_BASE, + .base = LPC17_40_TMR1_BASE, .pincfg = GPIO_MAT0p1_2, .pclk = (0x1 << 12), }; @@ -183,7 +183,7 @@ static struct lpc17_timer_s g_pwm1dev = * ****************************************************************************/ -static uint32_t timer_getreg(struct lpc17_timer_s *priv, int offset) +static uint32_t timer_getreg(struct lpc17_40_timer_s *priv, int offset) { return getreg32(priv->base + offset); } @@ -203,7 +203,7 @@ static uint32_t timer_getreg(struct lpc17_timer_s *priv, int offset) * ****************************************************************************/ -static void timer_putreg(struct lpc17_timer_s *priv, int offset, +static void timer_putreg(struct lpc17_40_timer_s *priv, int offset, uint32_t value) { putreg32(value, priv->base + offset); @@ -224,29 +224,29 @@ static void timer_putreg(struct lpc17_timer_s *priv, int offset, ****************************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg) +static void timer_dumpregs(struct lpc17_40_timer_s *priv, FAR const char *msg) { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - timer_getreg(priv, LPC17_PWM_MR0_OFFSET), - timer_getreg(priv, LPC17_PWM_MR1_OFFSET), - timer_getreg(priv, LPC17_PWM_MR2_OFFSET), - timer_getreg(priv, LPC17_PWM_MR3_OFFSET)); -#if defined(CONFIG_LPC17_TMR0) + timer_getreg(priv, LPC17_40_PWM_MR0_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR1_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); +#if defined(CONFIG_LPC17_40_TMR0) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - timer_getreg(priv, LPC17_PWM_MR0_OFFSET), - timer_getreg(priv, LPC17_PWM_MR1_OFFSET), - timer_getreg(priv, LPC17_PWM_MR2_OFFSET), - timer_getreg(priv, LPC17_PWM_MR3_OFFSET)); + timer_getreg(priv, LPC17_40_PWM_MR0_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR1_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - timer_getreg(priv, LPC17_PWM_MR2_OFFSET), - timer_getreg(priv, LPC17_PWM_MR3_OFFSET)); + timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET), + timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET)); } } #endif @@ -266,7 +266,7 @@ static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg) * ****************************************************************************/ -static int timer_timer(FAR struct lpc17_timer_s *priv, +static int timer_timer(FAR struct lpc17_40_timer_s *priv, FAR const struct pwm_info_s *info) { irqstate_t flags; @@ -274,11 +274,11 @@ static int timer_timer(FAR struct lpc17_timer_s *priv, flags = enter_critical_section(); - putreg32(info->frequency, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ - putreg32(info->frequency, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ + putreg32(info->frequency, LPC17_40_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ + putreg32(info->frequency, LPC17_40_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ - putreg32(1, LPC17_TMR0_TCR); /* Start timer0 */ - putreg32(1, LPC17_TMR1_TCR); /* Start timer1 */ + putreg32(1, LPC17_40_TMR0_TCR); /* Start timer0 */ + putreg32(1, LPC17_40_TMR1_TCR); /* Start timer1 */ leave_critical_section(flags); timer_dumpregs(priv, "After starting"); @@ -300,7 +300,7 @@ static int timer_timer(FAR struct lpc17_timer_s *priv, * ****************************************************************************/ -static int timer_interrupt(struct lpc17_timer_s *priv) +static int timer_interrupt(struct lpc17_40_timer_s *priv) { uint16_t regval; @@ -363,7 +363,7 @@ static int timer_tim1interrupt(int irq, void *context) static int timer_setup(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; + FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev; irqstate_t flags; uint32_t regval; @@ -371,58 +371,58 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) /* Power on the timer peripherals */ - regval = getreg32(LPC17_SYSCON_PCONP); + regval = getreg32(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCTIM0; regval |= SYSCON_PCONP_PCTIM1; regval |= SYSCON_PCONP_PCTIM2; regval |= SYSCON_PCONP_PCTIM3; - putreg32(regval, LPC17_SYSCON_PCONP); + putreg32(regval, LPC17_40_SYSCON_PCONP); /* Select clock for the timer peripheral */ - regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL0); regval &= ~(0x3 << 2); regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ regval &= ~(0x3 << 4); regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ - putreg32(regval, LPC17_SYSCON_PCLKSEL0); - regval = getreg32(LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_40_SYSCON_PCLKSEL1); regval &= ~(0x3 << 12); regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ regval &= ~(0x3 << 14); regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ - putreg32(regval, LPC17_SYSCON_PCLKSEL1); + putreg32(regval, LPC17_40_SYSCON_PCLKSEL1); priv->pclk = (0x1 << 12) | (0x1 << 4); - putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ + putreg32(1000, LPC17_40_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ - putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */ - putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */ + putreg32(1, LPC17_40_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_40_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_40_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32((2 << 3), LPC17_40_TMR0_MCR); /* Reset on match register MR1 */ /* Output bit toggle on external match event External match on MR1, Toggle * external bit */ - putreg32(((1 << 1) | (3 << 6)), LPC17_TMR0_EMR); - putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */ + putreg32(((1 << 1) | (3 << 6)), LPC17_40_TMR0_EMR); + putreg32((1 << 0), LPC17_40_TMR0_TCR); /* Start timer0 */ /* Configure the output pins GPIO3.26 */ - lpc17_configgpio(GPIO_MAT0p1_2); + lpc17_40_configgpio(GPIO_MAT0p1_2); - putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ + putreg32(500, LPC17_40_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ - putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */ - putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ -// putreg32(((1 << 0 )| (3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ - putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ + putreg32(1, LPC17_40_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_40_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_40_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32((2 << 0), LPC17_40_TMR1_MCR); /* Reset on match register MR0 */ +// putreg32(((1 << 0 )| (3 << 4)), LPC17_40_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ + putreg32((1 << 0), LPC17_40_TMR1_TCR); /* Start timer1 */ /* configure the output pins GPIO3.26 */ -// lpc17_configgpio(GPIO_MAT0p1_2); +// lpc17_40_configgpio(GPIO_MAT0p1_2); leave_critical_section(flags); pwm_dumpgpio(priv->pincfg, "TIMER setup"); @@ -447,7 +447,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; + FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev; uint32_t pincfg; pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); @@ -475,7 +475,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev) static int timer_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) { - FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; + FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev; return timer_timer(priv, info); } @@ -500,7 +500,7 @@ static int timer_start(FAR struct pwm_lowerhalf_s *dev, static int timer_stop(FAR struct pwm_lowerhalf_s *dev) { - FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; + FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev; uint32_t resetbit; uint32_t regaddr; uint32_t regval; @@ -520,7 +520,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_LPC17_TMR0 +#ifdef CONFIG_LPC17_40_TMR0 case 1: break; #endif @@ -556,7 +556,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO - FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; + FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev; /* There are no platform-specific ioctl commands */ @@ -570,7 +570,7 @@ static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long a ****************************************************************************/ /**************************************************************************** - * Name: lpc17_timerinitialize + * Name: lpc17_40_timerinitialize * * Description: * Initialize one timer for use with the upper_level TIMER driver. @@ -586,15 +586,15 @@ static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long a * ****************************************************************************/ -FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer) +FAR struct pwm_lowerhalf_s *lpc17_40_timerinitialize(int timer) { - FAR struct lpc17_timer_s *lower; + FAR struct lpc17_40_timer_s *lower; pwminfo("TIM%d\n", timer); switch (timer) { -#ifdef CONFIG_LPC17_TMR0 +#ifdef CONFIG_LPC17_40_TMR0 case 0: lower = &g_pwm1dev; @@ -611,4 +611,4 @@ FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer) return (FAR struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_LPC17_TIMn_TIMER, n = 1,...,14 */ +#endif /* CONFIG_LPC17_40_TIMn_TIMER, n = 1,...,14 */ diff --git a/arch/arm/src/lpc11xx/lpc11_timer.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_timer.h similarity index 91% rename from arch/arm/src/lpc11xx/lpc11_timer.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_timer.h index 02f58a50ca7..9c5144cdc9d 100644 --- a/arch/arm/src/lpc11xx/lpc11_timer.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_timer.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc11_timer.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_timer.h * * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_TIMER_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_TIMER_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_TIMER_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_TIMER_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc11_timer.h" +#include "hardware/lpc17_40_timer.h" /************************************************************************************ * Pre-processor Definitions @@ -59,4 +59,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_TIMER_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_TIMER_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_timerisr.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c similarity index 93% rename from arch/arm/src/lpc17xx/lpc17_timerisr.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c index 9b2ed6d04e7..9b1d9c34cd6 100644 --- a/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_timerisr.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c * * Copyright (C) 2010, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -68,7 +68,7 @@ * timer to use CCLK as its source. */ -#define SYSTICK_RELOAD ((LPC17_CCLK / CLK_TCK) - 1) +#define SYSTICK_RELOAD ((LPC17_40_CCLK / CLK_TCK) - 1) /* The size of the reload field is 24 bits. Verify that the reload value * will fit in the reload register. @@ -83,7 +83,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: lpc17_timerisr + * Function: lpc17_40_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -91,7 +91,7 @@ * ****************************************************************************/ -static int lpc17_timerisr(int irq, uint32_t *regs, void *arg) +static int lpc17_40_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -123,7 +123,7 @@ void arm_timer_initialize(void) regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); putreg32(regval, NVIC_SYSH12_15_PRIORITY); - /* Make sure that the SYSTICK clock source is set to use the LPC17xx CCLK */ + /* Make sure that the SYSTICK clock source is set to use the LPC17xx/LPC40xx CCLK */ regval = getreg32(NVIC_SYSTICK_CTRL); regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -135,7 +135,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(LPC17_IRQ_SYSTICK, (xcpt_t)lpc17_timerisr, NULL); + (void)irq_attach(LPC17_40_IRQ_SYSTICK, (xcpt_t)lpc17_40_timerisr, NULL); /* Enable SysTick interrupts */ @@ -144,5 +144,5 @@ void arm_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(LPC17_IRQ_SYSTICK); + up_enable_irq(LPC17_40_IRQ_SYSTICK); } diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c similarity index 62% rename from arch/arm/src/lpc17xx/lpc17_usbdev.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c index 6bb27bc06c4..9bd22b4ca6e 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_usbdev.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c * * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -60,10 +60,10 @@ #include "up_internal.h" #include "chip.h" -#include "hardware/lpc17_usb.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_gpdma.h" +#include "hardware/lpc17_40_usb.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_gpdma.h" /**************************************************************************** * Pre-processor Definitions @@ -71,8 +71,8 @@ /* Configuration ***************************************************************/ -#ifndef CONFIG_LPC17_USBDEV_EP0_MAXSIZE -# define CONFIG_LPC17_USBDEV_EP0_MAXSIZE 64 +#ifndef CONFIG_LPC17_40_USBDEV_EP0_MAXSIZE +# define CONFIG_LPC17_40_USBDEV_EP0_MAXSIZE 64 #endif #ifndef CONFIG_USBDEV_MAXPOWER @@ -82,7 +82,7 @@ #define USB_SLOW_INT USBDEV_INT_EPSLOW #define USB_DEVSTATUS_INT USBDEV_INT_DEVSTAT -#ifdef CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT +#ifdef CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT # define USB_FAST_INT USBDEV_INT_EPFAST #else # define USB_FAST_INT 0 @@ -93,7 +93,7 @@ * asynchronously. */ -#ifdef CONFIG_LPC17_USBDEV_FRAME_INTERRUPT +#ifdef CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT # define USB_FRAME_INT USBDEV_INT_FRAME #else # define USB_FRAME_INT 0 @@ -106,21 +106,21 @@ #endif #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_LPC17_USBDEV_REGDEBUG +# undef CONFIG_LPC17_40_USBDEV_REGDEBUG #endif /* CLKCTRL enable bits */ -#define LPC17_CLKCTRL_ENABLES (USBDEV_CLK_DEVCLK|USBDEV_CLK_AHBCLK) +#define LPC17_40_CLKCTRL_ENABLES (USBDEV_CLK_DEVCLK|USBDEV_CLK_AHBCLK) /* Dump GPIO registers */ -#if defined(CONFIG_LPC17_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) +#if defined(CONFIG_LPC17_40_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) # define usbdev_dumpgpio() \ do { \ - lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \ - lpc17_dumpgpio(GPIO_USB_VBUS, "LED P1:18; VBUS P1:30"); \ - lpc17_dumpgpio(GPIO_USB_CONNECT, "CONNECT P2:9"); \ + lpc17_40_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \ + lpc17_40_dumpgpio(GPIO_USB_VBUS, "LED P1:18; VBUS P1:30"); \ + lpc17_40_dumpgpio(GPIO_USB_CONNECT, "CONNECT P2:9"); \ } while (0); #else # define usbdev_dumpgpio() @@ -128,12 +128,12 @@ /* Number of DMA descriptors */ -#ifdef CONFIG_LPC17_USBDEV_DMA +#ifdef CONFIG_LPC17_40_USBDEV_DMA # error DMA SUPPORT NOT YET FULLY IMPLEMENTED -# ifndef CONFIG_LPC17_USBDEV_NDMADESCRIPTORS -# define CONFIG_LPC17_USBDEV_NDMADESCRIPTORS 8 -# elif CONFIG_LPC17_USBDEV_NDMADESCRIPTORS > 30 -# define CONFIG_LPC17_USBDEV_NDMADESCRIPTORS 30 +# ifndef CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS +# define CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS 8 +# elif CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS > 30 +# define CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS 30 # endif #endif @@ -141,73 +141,73 @@ /* Trace error codes */ -#define LPC17_TRACEERR_ALLOCFAIL 0x0001 -#define LPC17_TRACEERR_BADCLEARFEATURE 0x0002 -#define LPC17_TRACEERR_BADDEVGETSTATUS 0x0003 -#define LPC17_TRACEERR_BADEPNO 0x0004 -#define LPC17_TRACEERR_BADEPGETSTATUS 0x0005 -#define LPC17_TRACEERR_BADEPTYPE 0x0006 -#define LPC17_TRACEERR_BADGETCONFIG 0x0007 -#define LPC17_TRACEERR_BADGETSETDESC 0x0008 -#define LPC17_TRACEERR_BADGETSTATUS 0x0009 -#define LPC17_TRACEERR_BADSETADDRESS 0x000a -#define LPC17_TRACEERR_BADSETCONFIG 0x000b -#define LPC17_TRACEERR_BADSETFEATURE 0x000c -#define LPC17_TRACEERR_BINDFAILED 0x000d -#define LPC17_TRACEERR_DISPATCHSTALL 0x000e -#define LPC17_TRACEERR_DMABUSY 0x000f -#define LPC17_TRACEERR_DRIVER 0x0010 -#define LPC17_TRACEERR_DRIVERREGISTERED 0x0011 -#define LPC17_TRACEERR_EP0INSTALLED 0x0012 -#define LPC17_TRACEERR_EP0OUTSTALLED 0x0013 -#define LPC17_TRACEERR_EP0SETUPSTALLED 0x0014 -#define LPC17_TRACEERR_EPINNULLPACKET 0x0015 -#define LPC17_TRACEERR_EPOUTNULLPACKET 0x0016 -#define LPC17_TRACEERR_EPREAD 0x0017 -#define LPC17_TRACEERR_INVALIDCMD 0x0018 -#define LPC17_TRACEERR_INVALIDCTRLREQ 0x0019 -#define LPC17_TRACEERR_INVALIDPARMS 0x001a -#define LPC17_TRACEERR_IRQREGISTRATION 0x001b -#define LPC17_TRACEERR_NODMADESC 0x001c -#define LPC17_TRACEERR_NOEP 0x001d -#define LPC17_TRACEERR_NOTCONFIGURED 0x001e -#define LPC17_TRACEERR_REQABORTED 0x001f +#define LPC17_40_TRACEERR_ALLOCFAIL 0x0001 +#define LPC17_40_TRACEERR_BADCLEARFEATURE 0x0002 +#define LPC17_40_TRACEERR_BADDEVGETSTATUS 0x0003 +#define LPC17_40_TRACEERR_BADEPNO 0x0004 +#define LPC17_40_TRACEERR_BADEPGETSTATUS 0x0005 +#define LPC17_40_TRACEERR_BADEPTYPE 0x0006 +#define LPC17_40_TRACEERR_BADGETCONFIG 0x0007 +#define LPC17_40_TRACEERR_BADGETSETDESC 0x0008 +#define LPC17_40_TRACEERR_BADGETSTATUS 0x0009 +#define LPC17_40_TRACEERR_BADSETADDRESS 0x000a +#define LPC17_40_TRACEERR_BADSETCONFIG 0x000b +#define LPC17_40_TRACEERR_BADSETFEATURE 0x000c +#define LPC17_40_TRACEERR_BINDFAILED 0x000d +#define LPC17_40_TRACEERR_DISPATCHSTALL 0x000e +#define LPC17_40_TRACEERR_DMABUSY 0x000f +#define LPC17_40_TRACEERR_DRIVER 0x0010 +#define LPC17_40_TRACEERR_DRIVERREGISTERED 0x0011 +#define LPC17_40_TRACEERR_EP0INSTALLED 0x0012 +#define LPC17_40_TRACEERR_EP0OUTSTALLED 0x0013 +#define LPC17_40_TRACEERR_EP0SETUPSTALLED 0x0014 +#define LPC17_40_TRACEERR_EPINNULLPACKET 0x0015 +#define LPC17_40_TRACEERR_EPOUTNULLPACKET 0x0016 +#define LPC17_40_TRACEERR_EPREAD 0x0017 +#define LPC17_40_TRACEERR_INVALIDCMD 0x0018 +#define LPC17_40_TRACEERR_INVALIDCTRLREQ 0x0019 +#define LPC17_40_TRACEERR_INVALIDPARMS 0x001a +#define LPC17_40_TRACEERR_IRQREGISTRATION 0x001b +#define LPC17_40_TRACEERR_NODMADESC 0x001c +#define LPC17_40_TRACEERR_NOEP 0x001d +#define LPC17_40_TRACEERR_NOTCONFIGURED 0x001e +#define LPC17_40_TRACEERR_REQABORTED 0x001f /* Trace interrupt codes */ -#define LPC17_TRACEINTID_USB 0x0001 -#define LPC17_TRACEINTID_CLEARFEATURE 0x0002 -#define LPC17_TRACEINTID_CONNECTCHG 0x0003 -#define LPC17_TRACEINTID_CONNECTED 0x0004 -#define LPC17_TRACEINTID_DEVGETSTATUS 0x0005 -#define LPC17_TRACEINTID_DEVRESET 0x0006 -#define LPC17_TRACEINTID_DEVSTAT 0x0007 -#define LPC17_TRACEINTID_DISCONNECTED 0x0008 -#define LPC17_TRACEINTID_DISPATCH 0x0009 -#define LPC17_TRACEINTID_EP0IN 0x000a -#define LPC17_TRACEINTID_EP0OUT 0x000b -#define LPC17_TRACEINTID_EP0SETUP 0x000c -#define LPC17_TRACEINTID_EPDMA 0x000d -#define LPC17_TRACEINTID_EPFAST 0x000e -#define LPC17_TRACEINTID_EPGETSTATUS 0x000f -#define LPC17_TRACEINTID_EPIN 0x0010 -#define LPC17_TRACEINTID_EPINQEMPTY 0x0011 -#define LPC17_TRACEINTID_EP0INSETADDRESS 0x0012 -#define LPC17_TRACEINTID_EPOUT 0x0013 -#define LPC17_TRACEINTID_EPOUTQEMPTY 0x0014 -#define LPC17_TRACEINTID_EP0SETUPSETADDRESS 0x0015 -#define LPC17_TRACEINTID_ERRINT 0x0016 -#define LPC17_TRACEINTID_EPSLOW 0x0017 -#define LPC17_TRACEINTID_FRAME 0x0018 -#define LPC17_TRACEINTID_GETCONFIG 0x0019 -#define LPC17_TRACEINTID_GETSETDESC 0x001a -#define LPC17_TRACEINTID_GETSETIF 0x001b -#define LPC17_TRACEINTID_GETSTATUS 0x001c -#define LPC17_TRACEINTID_IFGETSTATUS 0x001d -#define LPC17_TRACEINTID_SETCONFIG 0x001e -#define LPC17_TRACEINTID_SETFEATURE 0x001f -#define LPC17_TRACEINTID_SUSPENDCHG 0x0020 -#define LPC17_TRACEINTID_SYNCHFRAME 0x0021 +#define LPC17_40_TRACEINTID_USB 0x0001 +#define LPC17_40_TRACEINTID_CLEARFEATURE 0x0002 +#define LPC17_40_TRACEINTID_CONNECTCHG 0x0003 +#define LPC17_40_TRACEINTID_CONNECTED 0x0004 +#define LPC17_40_TRACEINTID_DEVGETSTATUS 0x0005 +#define LPC17_40_TRACEINTID_DEVRESET 0x0006 +#define LPC17_40_TRACEINTID_DEVSTAT 0x0007 +#define LPC17_40_TRACEINTID_DISCONNECTED 0x0008 +#define LPC17_40_TRACEINTID_DISPATCH 0x0009 +#define LPC17_40_TRACEINTID_EP0IN 0x000a +#define LPC17_40_TRACEINTID_EP0OUT 0x000b +#define LPC17_40_TRACEINTID_EP0SETUP 0x000c +#define LPC17_40_TRACEINTID_EPDMA 0x000d +#define LPC17_40_TRACEINTID_EPFAST 0x000e +#define LPC17_40_TRACEINTID_EPGETSTATUS 0x000f +#define LPC17_40_TRACEINTID_EPIN 0x0010 +#define LPC17_40_TRACEINTID_EPINQEMPTY 0x0011 +#define LPC17_40_TRACEINTID_EP0INSETADDRESS 0x0012 +#define LPC17_40_TRACEINTID_EPOUT 0x0013 +#define LPC17_40_TRACEINTID_EPOUTQEMPTY 0x0014 +#define LPC17_40_TRACEINTID_EP0SETUPSETADDRESS 0x0015 +#define LPC17_40_TRACEINTID_ERRINT 0x0016 +#define LPC17_40_TRACEINTID_EPSLOW 0x0017 +#define LPC17_40_TRACEINTID_FRAME 0x0018 +#define LPC17_40_TRACEINTID_GETCONFIG 0x0019 +#define LPC17_40_TRACEINTID_GETSETDESC 0x001a +#define LPC17_40_TRACEINTID_GETSETIF 0x001b +#define LPC17_40_TRACEINTID_GETSTATUS 0x001c +#define LPC17_40_TRACEINTID_IFGETSTATUS 0x001d +#define LPC17_40_TRACEINTID_SETCONFIG 0x001e +#define LPC17_40_TRACEINTID_SETFEATURE 0x001f +#define LPC17_40_TRACEINTID_SUSPENDCHG 0x0020 +#define LPC17_40_TRACEINTID_SYNCHFRAME 0x0021 /* Hardware interface **********************************************************/ @@ -219,61 +219,61 @@ #define DEVSTATUS_SUSPCHG(s) (((s)&CMD_STATUS_SUSPCHG)!=0) #define DEVSTATUS_RESET(s) (((s)&CMD_STATUS_RESET)!=0) -/* If this bit is set in the lpc17_epread response, it means that the +/* If this bit is set in the lpc17_40_epread response, it means that the * recevied packet was overwritten by a later setup packet (ep0 only). */ -#define LPC17_READOVERRUN_BIT (0x80000000) -#define LPC17_READOVERRUN(s) (((s) & LPC17_READOVERRUN_BIT) != 0) +#define LPC17_40_READOVERRUN_BIT (0x80000000) +#define LPC17_40_READOVERRUN(s) (((s) & LPC17_40_READOVERRUN_BIT) != 0) /* Endpoints ******************************************************************/ /* Number of endpoints */ -#define LPC17_NLOGENDPOINTS (16) /* ep0-15 */ -#define LPC17_NPHYSENDPOINTS (32) /* x2 for IN and OUT */ +#define LPC17_40_NLOGENDPOINTS (16) /* ep0-15 */ +#define LPC17_40_NPHYSENDPOINTS (32) /* x2 for IN and OUT */ /* Odd physical endpoint numbers are IN; even are out */ -#define LPC17_EPPHYIN(epphy) (((epphy)&1)!=0) -#define LPC17_EPPHYOUT(epphy) (((epphy)&1)==0) +#define LPC17_40_EPPHYIN(epphy) (((epphy)&1)!=0) +#define LPC17_40_EPPHYOUT(epphy) (((epphy)&1)==0) -#define LPC17_EPPHYIN2LOG(epphy) (((uint8_t)(epphy)>>1)|USB_DIR_IN) -#define LPC17_EPPHYOUT2LOG(epphy) (((uint8_t)(epphy)>>1)|USB_DIR_OUT) +#define LPC17_40_EPPHYIN2LOG(epphy) (((uint8_t)(epphy)>>1)|USB_DIR_IN) +#define LPC17_40_EPPHYOUT2LOG(epphy) (((uint8_t)(epphy)>>1)|USB_DIR_OUT) /* Each endpoint has somewhat different characteristics */ -#define LPC17_EPALLSET (0xffffffff) /* All endpoints */ -#define LPC17_EPOUTSET (0x55555555) /* Even phy endpoint numbers are OUT EPs */ -#define LPC17_EPINSET (0xaaaaaaaa) /* Odd endpoint numbers are IN EPs */ -#define LPC17_EPCTRLSET (0x00000003) /* EP0 IN/OUT are control endpoints */ -#define LPC17_EPINTRSET (0x0c30c30c) /* Interrupt endpoints */ -#define LPC17_EPBULKSET (0xf0c30c30) /* Bulk endpoints */ -#define LPC17_EPISOCSET (0x030c30c0) /* Isochronous endpoints */ -#define LPC17_EPDBLBUFFER (0xf3cf3cf0) /* Double buffered endpoints */ +#define LPC17_40_EPALLSET (0xffffffff) /* All endpoints */ +#define LPC17_40_EPOUTSET (0x55555555) /* Even phy endpoint numbers are OUT EPs */ +#define LPC17_40_EPINSET (0xaaaaaaaa) /* Odd endpoint numbers are IN EPs */ +#define LPC17_40_EPCTRLSET (0x00000003) /* EP0 IN/OUT are control endpoints */ +#define LPC17_40_EPINTRSET (0x0c30c30c) /* Interrupt endpoints */ +#define LPC17_40_EPBULKSET (0xf0c30c30) /* Bulk endpoints */ +#define LPC17_40_EPISOCSET (0x030c30c0) /* Isochronous endpoints */ +#define LPC17_40_EPDBLBUFFER (0xf3cf3cf0) /* Double buffered endpoints */ -#define LPC17_EP0MAXPACKET (64) /* EP0 max packet size (1-64) */ -#define LPC17_BULKMAXPACKET (64) /* Bulk endpoint max packet (8/16/32/64) */ -#define LPC17_INTRMAXPACKET (64) /* Interrupt endpoint max packet (1 to 64) */ -#define LPC17_ISOCMAXPACKET (512) /* Acutally 1..1023 */ +#define LPC17_40_EP0MAXPACKET (64) /* EP0 max packet size (1-64) */ +#define LPC17_40_BULKMAXPACKET (64) /* Bulk endpoint max packet (8/16/32/64) */ +#define LPC17_40_INTRMAXPACKET (64) /* Interrupt endpoint max packet (1 to 64) */ +#define LPC17_40_ISOCMAXPACKET (512) /* Acutally 1..1023 */ /* EP0 status. EP0 transfers occur in a number of different contexts. A * simple state machine is required to handle the various transfer complete * interrupt responses. The following values are the various states: */ /*** INTERRUPT CAUSE ***/ -#define LPC17_EP0REQUEST (0) /* Normal request handling */ -#define LPC17_EP0STATUSIN (1) /* Status sent */ -#define LPC17_EP0STATUSOUT (2) /* Status received */ -#define LPC17_EP0SHORTWRITE (3) /* Short data sent with no request */ -#define LPC17_EP0SHORTWRSENT (4) /* Short data write complete */ -#define LPC17_EP0SETADDRESS (5) /* Set address received */ -#define LPC17_EP0WRITEREQUEST (6) /* EP0 write request sent */ +#define LPC17_40_EP0REQUEST (0) /* Normal request handling */ +#define LPC17_40_EP0STATUSIN (1) /* Status sent */ +#define LPC17_40_EP0STATUSOUT (2) /* Status received */ +#define LPC17_40_EP0SHORTWRITE (3) /* Short data sent with no request */ +#define LPC17_40_EP0SHORTWRSENT (4) /* Short data write complete */ +#define LPC17_40_EP0SETADDRESS (5) /* Set address received */ +#define LPC17_40_EP0WRITEREQUEST (6) /* EP0 write request sent */ /* Request queue operations ****************************************************/ -#define lpc17_rqempty(ep) ((ep)->head == NULL) -#define lpc17_rqpeek(ep) ((ep)->head) +#define lpc17_40_rqempty(ep) ((ep)->head == NULL) +#define lpc17_40_rqpeek(ep) ((ep)->head) /**************************************************************************** * Private Types @@ -281,28 +281,28 @@ /* A container for a request so that the request make be retained in a list */ -struct lpc17_req_s +struct lpc17_40_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct lpc17_req_s *flink; /* Supports a singly linked list */ + struct lpc17_40_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct lpc17_ep_s +struct lpc17_40_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct lpc17_ep_s. + * to struct lpc17_40_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ - /* LPC17xx-specific fields */ + /* LPC17xx/LPC40xx-specific fields */ - struct lpc17_usbdev_s *dev; /* Reference to private driver data */ - struct lpc17_req_s *head; /* Request list for this endpoint */ - struct lpc17_req_s *tail; + struct lpc17_40_usbdev_s *dev; /* Reference to private driver data */ + struct lpc17_40_req_s *head; /* Request list for this endpoint */ + struct lpc17_40_req_s *tail; uint8_t epphy; /* Physical EP address */ uint8_t stalled:1; /* 1: Endpoint is stalled */ uint8_t halted:1; /* 1: Endpoint feature halted */ @@ -312,8 +312,8 @@ struct lpc17_ep_s /* This represents a DMA descriptor */ -#ifdef CONFIG_LPC17_USBDEV_DMA -struct lpc17_dmadesc_s +#ifdef CONFIG_LPC17_40_USBDEV_DMA +struct lpc17_40_dmadesc_s { uint32_t nextdesc; /* Address of the next DMA descriptor in RAM */ uint32_t config; /* Misc. bit encoded configuration information */ @@ -327,11 +327,11 @@ struct lpc17_dmadesc_s /* This structure retains the state of the USB device controller */ -struct lpc17_usbdev_s +struct lpc17_40_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s - * to structlpc17_usbdev_s. + * to structlpc17_40_usbdev_s. */ struct usbdev_s usbdev; @@ -340,7 +340,7 @@ struct lpc17_usbdev_s struct usbdevclass_driver_s *driver; - /* LPC17xx-specific fields */ + /* LPC17xx/LPC40xx-specific fields */ uint8_t devstatus; /* Last response to device status command */ uint8_t ep0state; /* State of certain EP0 operations */ @@ -352,19 +352,19 @@ struct lpc17_usbdev_s uint8_t rxpending:2; /* 2: RX pending */ uint32_t softprio; /* Bitset of high priority interrupts */ uint32_t epavail; /* Bitset of available endpoints */ -#ifdef CONFIG_LPC17_USBDEV_FRAME_INTERRUPT +#ifdef CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT uint32_t sof; /* Last start-of-frame */ #endif /* Allocated DMA descriptor */ -#ifdef CONFIG_LPC17_USBDEV_DMA - struct lpc17_dmadesc_s *dmadesc; +#ifdef CONFIG_LPC17_40_USBDEV_DMA + struct lpc17_40_dmadesc_s *dmadesc; #endif /* The endpoint list */ - struct lpc17_ep_s eplist[LPC17_NPHYSENDPOINTS]; + struct lpc17_40_ep_s eplist[LPC17_40_NPHYSENDPOINTS]; }; /**************************************************************************** @@ -373,92 +373,92 @@ struct lpc17_usbdev_s /* Register operations ********************************************************/ -#ifdef CONFIG_LPC17_USBDEV_REGDEBUG -static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t lpc17_getreg(uint32_t addr); -static void lpc17_putreg(uint32_t val, uint32_t addr); +#ifdef CONFIG_LPC17_40_USBDEV_REGDEBUG +static void lpc17_40_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t lpc17_40_getreg(uint32_t addr); +static void lpc17_40_putreg(uint32_t val, uint32_t addr); #else -# define lpc17_getreg(addr) getreg32(addr) -# define lpc17_putreg(val,addr) putreg32(val,addr) +# define lpc17_40_getreg(addr) getreg32(addr) +# define lpc17_40_putreg(val,addr) putreg32(val,addr) #endif /* Command operations **********************************************************/ -static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data); +static uint32_t lpc17_40_usbcmd(uint16_t cmd, uint8_t data); /* Request queue operations ****************************************************/ -static FAR struct lpc17_req_s *lpc17_rqdequeue(FAR struct lpc17_ep_s *privep); -static void lpc17_rqenqueue(FAR struct lpc17_ep_s *privep, - FAR struct lpc17_req_s *req); +static FAR struct lpc17_40_req_s *lpc17_40_rqdequeue(FAR struct lpc17_40_ep_s *privep); +static void lpc17_40_rqenqueue(FAR struct lpc17_40_ep_s *privep, + FAR struct lpc17_40_req_s *req); /* Low level data transfers and request operations *****************************/ -static void lpc17_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes); -static int lpc17_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes); -static inline void lpc17_abortrequest(struct lpc17_ep_s *privep, - struct lpc17_req_s *privreq, int16_t result); -static void lpc17_reqcomplete(struct lpc17_ep_s *privep, int16_t result); -static int lpc17_wrrequest(struct lpc17_ep_s *privep); -static int lpc17_rdrequest(struct lpc17_ep_s *privep); -static void lpc17_cancelrequests(struct lpc17_ep_s *privep); +static void lpc17_40_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes); +static int lpc17_40_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes); +static inline void lpc17_40_abortrequest(struct lpc17_40_ep_s *privep, + struct lpc17_40_req_s *privreq, int16_t result); +static void lpc17_40_reqcomplete(struct lpc17_40_ep_s *privep, int16_t result); +static int lpc17_40_wrrequest(struct lpc17_40_ep_s *privep); +static int lpc17_40_rdrequest(struct lpc17_40_ep_s *privep); +static void lpc17_40_cancelrequests(struct lpc17_40_ep_s *privep); /* Interrupt handling **********************************************************/ -static struct lpc17_ep_s *lpc17_epfindbyaddr(struct lpc17_usbdev_s *priv, +static struct lpc17_40_ep_s *lpc17_40_epfindbyaddr(struct lpc17_40_usbdev_s *priv, uint16_t eplog); -static void lpc17_eprealize(struct lpc17_ep_s *privep, bool prio, +static void lpc17_40_eprealize(struct lpc17_40_ep_s *privep, bool prio, uint32_t packetsize); -static uint8_t lpc17_epclrinterrupt(uint8_t epphy); -static inline void lpc17_ep0configure(struct lpc17_usbdev_s *priv); -#ifdef CONFIG_LPC17_USBDEV_DMA -static inline void lpc17_dmareset(uint32_t enable); +static uint8_t lpc17_40_epclrinterrupt(uint8_t epphy); +static inline void lpc17_40_ep0configure(struct lpc17_40_usbdev_s *priv); +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static inline void lpc17_40_dmareset(uint32_t enable); #endif -static void lpc17_usbreset(struct lpc17_usbdev_s *priv); -static void lpc17_dispatchrequest(struct lpc17_usbdev_s *priv, +static void lpc17_40_usbreset(struct lpc17_40_usbdev_s *priv); +static void lpc17_40_dispatchrequest(struct lpc17_40_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl); -static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv); -static inline void lpc17_ep0dataoutinterrupt(struct lpc17_usbdev_s *priv); -static inline void lpc17_ep0dataininterrupt(struct lpc17_usbdev_s *priv); -static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg); +static inline void lpc17_40_ep0setup(struct lpc17_40_usbdev_s *priv); +static inline void lpc17_40_ep0dataoutinterrupt(struct lpc17_40_usbdev_s *priv); +static inline void lpc17_40_ep0dataininterrupt(struct lpc17_40_usbdev_s *priv); +static int lpc17_40_usbinterrupt(int irq, FAR void *context, FAR void *arg); -#ifdef CONFIG_LPC17_USBDEV_DMA -static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static int lpc17_40_dmasetup(struct lpc17_40_usbdev_s *priv, uint8_t epphy, uint32_t epmaxsize, uint32_t nbytes, uint32_t *isocpacket, bool isochronous); -static void lpc17_dmarestart(uint8_t epphy, uint32_t descndx); -static void lpc17_dmadisable(uint8_t epphy); -#endif /* CONFIG_LPC17_USBDEV_DMA */ +static void lpc17_40_dmarestart(uint8_t epphy, uint32_t descndx); +static void lpc17_40_dmadisable(uint8_t epphy); +#endif /* CONFIG_LPC17_40_USBDEV_DMA */ /* Endpoint operations *********************************************************/ -static int lpc17_epconfigure(FAR struct usbdev_ep_s *ep, +static int lpc17_40_epconfigure(FAR struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static int lpc17_epdisable(FAR struct usbdev_ep_s *ep); -static FAR struct usbdev_req_s *lpc17_epallocreq(FAR struct usbdev_ep_s *ep); -static void lpc17_epfreereq(FAR struct usbdev_ep_s *ep, +static int lpc17_40_epdisable(FAR struct usbdev_ep_s *ep); +static FAR struct usbdev_req_s *lpc17_40_epallocreq(FAR struct usbdev_ep_s *ep); +static void lpc17_40_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *); #ifdef CONFIG_USBDEV_DMA -static FAR void *lpc17_epallocbuffer(FAR struct usbdev_ep_s *ep, +static FAR void *lpc17_40_epallocbuffer(FAR struct usbdev_ep_s *ep, uint16_t nbytes); -static void lpc17_epfreebuffer(FAR struct usbdev_ep_s *ep, void *buf); +static void lpc17_40_epfreebuffer(FAR struct usbdev_ep_s *ep, void *buf); #endif -static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, +static int lpc17_40_epsubmit(FAR struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int lpc17_epcancel(FAR struct usbdev_ep_s *ep, +static int lpc17_40_epcancel(FAR struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int lpc17_epstall(FAR struct usbdev_ep_s *ep, bool resume); +static int lpc17_40_epstall(FAR struct usbdev_ep_s *ep, bool resume); /* USB device controller operations ********************************************/ -static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, +static FAR struct usbdev_ep_s *lpc17_40_allocep(FAR struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void lpc17_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep); -static int lpc17_getframe(struct usbdev_s *dev); -static int lpc17_wakeup(struct usbdev_s *dev); -static int lpc17_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int lpc17_pullup(struct usbdev_s *dev, bool enable); +static void lpc17_40_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep); +static int lpc17_40_getframe(struct usbdev_s *dev); +static int lpc17_40_wakeup(struct usbdev_s *dev); +static int lpc17_40_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int lpc17_40_pullup(struct usbdev_s *dev, bool enable); /**************************************************************************** * Private Data @@ -468,31 +468,31 @@ static int lpc17_pullup(struct usbdev_s *dev, bool enable); * be simply retained in a single global instance. */ -static struct lpc17_usbdev_s g_usbdev; +static struct lpc17_40_usbdev_s g_usbdev; static const struct usbdev_epops_s g_epops = { - .configure = lpc17_epconfigure, - .disable = lpc17_epdisable, - .allocreq = lpc17_epallocreq, - .freereq = lpc17_epfreereq, + .configure = lpc17_40_epconfigure, + .disable = lpc17_40_epdisable, + .allocreq = lpc17_40_epallocreq, + .freereq = lpc17_40_epfreereq, #ifdef CONFIG_USBDEV_DMA - .allocbuffer = lpc17_epallocbuffer, - .freebuffer = lpc17_epfreebuffer, + .allocbuffer = lpc17_40_epallocbuffer, + .freebuffer = lpc17_40_epfreebuffer, #endif - .submit = lpc17_epsubmit, - .cancel = lpc17_epcancel, - .stall = lpc17_epstall, + .submit = lpc17_40_epsubmit, + .cancel = lpc17_40_epcancel, + .stall = lpc17_40_epstall, }; static const struct usbdev_ops_s g_devops = { - .allocep = lpc17_allocep, - .freeep = lpc17_freeep, - .getframe = lpc17_getframe, - .wakeup = lpc17_wakeup, - .selfpowered = lpc17_selfpowered, - .pullup = lpc17_pullup, + .allocep = lpc17_40_allocep, + .freeep = lpc17_40_freeep, + .getframe = lpc17_40_getframe, + .wakeup = lpc17_40_wakeup, + .selfpowered = lpc17_40_selfpowered, + .pullup = lpc17_40_pullup, }; /* USB Device Communication Area *********************************************** @@ -510,9 +510,9 @@ static const struct usbdev_ops_s g_devops = * 8Kb memory region). */ -#ifdef CONFIG_LPC17_USBDEV_DMA -static uint32_t g_udca[LPC17_NPHYSENDPOINTS] __attribute__ ((aligned (128))); -static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS]; +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static uint32_t g_udca[LPC17_40_NPHYSENDPOINTS] __attribute__ ((aligned (128))); +static struct lpc17_40_dmadesc_s g_usbddesc[CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS]; #endif /**************************************************************************** @@ -524,30 +524,30 @@ static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS]; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_printreg + * Name: lpc17_40_printreg * * Description: - * Print the contents of an LPC17xx register operation + * Print the contents of an LPC17xx/LPC40xx register operation * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_REGDEBUG -static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_LPC17_40_USBDEV_REGDEBUG +static void lpc17_40_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif /**************************************************************************** - * Name: lpc17_checkreg + * Name: lpc17_40_checkreg * * Description: - * Get the contents of an LPC17xx register + * Get the contents of an LPC17xx/LPC40xx register * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_REGDEBUG -static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_LPC17_40_USBDEV_REGDEBUG +static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -578,7 +578,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* Yes.. Just one */ - lpc17_printreg(prevaddr, preval, prevwrite); + lpc17_40_printreg(prevaddr, preval, prevwrite); } else { @@ -597,21 +597,21 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) /* Show the new regisgter access */ - lpc17_printreg(addr, val, iswrite); + lpc17_40_printreg(addr, val, iswrite); } } #endif /**************************************************************************** - * Name: lpc17_getreg + * Name: lpc17_40_getreg * * Description: - * Get the contents of an LPC17xx register + * Get the contents of an LPC17xx/LPC40xx register * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_REGDEBUG -static uint32_t lpc17_getreg(uint32_t addr) +#ifdef CONFIG_LPC17_40_USBDEV_REGDEBUG +static uint32_t lpc17_40_getreg(uint32_t addr) { /* Read the value from the register */ @@ -619,25 +619,25 @@ static uint32_t lpc17_getreg(uint32_t addr) /* Check if we need to print this value */ - lpc17_checkreg(addr, val, false); + lpc17_40_checkreg(addr, val, false); return val; } #endif /**************************************************************************** - * Name: lpc17_putreg + * Name: lpc17_40_putreg * * Description: - * Set the contents of an LPC17xx register to a value + * Set the contents of an LPC17xx/LPC40xx register to a value * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_REGDEBUG -static void lpc17_putreg(uint32_t val, uint32_t addr) +#ifdef CONFIG_LPC17_40_USBDEV_REGDEBUG +static void lpc17_40_putreg(uint32_t val, uint32_t addr) { /* Check if we need to print this value */ - lpc17_checkreg(addr, val, true); + lpc17_40_checkreg(addr, val, true); /* Write the value */ @@ -646,14 +646,14 @@ static void lpc17_putreg(uint32_t val, uint32_t addr) #endif /**************************************************************************** - * Name: lpc17_usbcmd + * Name: lpc17_40_usbcmd * * Description: * Transmit commands to the USB engine * ****************************************************************************/ -static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) +static uint32_t lpc17_40_usbcmd(uint16_t cmd, uint8_t data) { irqstate_t flags; uint32_t cmd32; @@ -663,7 +663,7 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) /* Disable interrupt and clear CDFULL and CCEMPTY interrupt status */ flags = enter_critical_section(); - lpc17_putreg(USBDEV_INT_CDFULL | USBDEV_INT_CCEMPTY, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(USBDEV_INT_CDFULL | USBDEV_INT_CCEMPTY, LPC17_40_USBDEV_INTCLR); /* Shift the command in position and mask out extra bits */ @@ -671,15 +671,15 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) /* Load command + WR in command code register */ - lpc17_putreg(cmd32 | CMD_USBDEV_CMDWR, LPC17_USBDEV_CMDCODE); + lpc17_40_putreg(cmd32 | CMD_USBDEV_CMDWR, LPC17_40_USBDEV_CMDCODE); /* Wait until the command register is empty (CCEMPTY != 0, command is accepted) */ - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CCEMPTY) == 0); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CCEMPTY) == 0); /* Clear command register empty (CCEMPTY) interrupt */ - lpc17_putreg(USBDEV_INT_CCEMPTY, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(USBDEV_INT_CCEMPTY, LPC17_40_USBDEV_INTCLR); /* Determine next phase of the command */ @@ -695,8 +695,8 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) /* Send data + WR and wait for CCEMPTY */ data32 = (uint32_t)data << CMD_USBDEV_WDATASHIFT; - lpc17_putreg(data32 | CMD_USBDEV_DATAWR, LPC17_USBDEV_CMDCODE); - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CCEMPTY) == 0); + lpc17_40_putreg(data32 | CMD_USBDEV_DATAWR, LPC17_40_USBDEV_CMDCODE); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CCEMPTY) == 0); } break; @@ -707,22 +707,22 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) { /* Send command code + RD and wait for CDFULL */ - lpc17_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_USBDEV_CMDCODE); - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); + lpc17_40_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_40_USBDEV_CMDCODE); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); /* Clear CDFULL and read LS data */ - lpc17_putreg(USBDEV_INT_CDFULL, LPC17_USBDEV_INTCLR); - tmp = lpc17_getreg(LPC17_USBDEV_CMDDATA); + lpc17_40_putreg(USBDEV_INT_CDFULL, LPC17_40_USBDEV_INTCLR); + tmp = lpc17_40_getreg(LPC17_40_USBDEV_CMDDATA); /* Send command code + RD and wait for CDFULL */ - lpc17_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_USBDEV_CMDCODE); - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); + lpc17_40_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_40_USBDEV_CMDCODE); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); /* Read MS data */ - tmp |= lpc17_getreg(LPC17_USBDEV_CMDDATA) << 8; + tmp |= lpc17_40_getreg(LPC17_40_USBDEV_CMDDATA) << 8; } break; @@ -735,12 +735,12 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) { /* Send command code + RD and wait for CDFULL */ - lpc17_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_USBDEV_CMDCODE); - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); + lpc17_40_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_40_USBDEV_CMDCODE); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); /* Read data */ - tmp = lpc17_getreg(LPC17_USBDEV_CMDDATA); + tmp = lpc17_40_getreg(LPC17_40_USBDEV_CMDDATA); } break; @@ -757,12 +757,12 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) { /* Send command code + RD and wait for CDFULL */ - lpc17_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_USBDEV_CMDCODE); - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); + lpc17_40_putreg(cmd32 | CMD_USBDEV_DATARD, LPC17_40_USBDEV_CMDCODE); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); /* Read data */ - tmp = lpc17_getreg(LPC17_USBDEV_CMDDATA); + tmp = lpc17_40_getreg(LPC17_40_USBDEV_CMDDATA); } break; @@ -771,13 +771,13 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) /* Send data + RD and wait for CCEMPTY */ data32 = (uint32_t)data << CMD_USBDEV_WDATASHIFT; - lpc17_putreg(data32 | CMD_USBDEV_DATAWR, LPC17_USBDEV_CMDCODE); - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CCEMPTY) == 0); + lpc17_40_putreg(data32 | CMD_USBDEV_DATAWR, LPC17_40_USBDEV_CMDCODE); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CCEMPTY) == 0); } break; default: - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDCMD), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDCMD), 0); break; } break; @@ -790,16 +790,16 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) } /**************************************************************************** - * Name: lpc17_rqdequeue + * Name: lpc17_40_rqdequeue * * Description: * Remove a request from an endpoint request queue * ****************************************************************************/ -static FAR struct lpc17_req_s *lpc17_rqdequeue(FAR struct lpc17_ep_s *privep) +static FAR struct lpc17_40_req_s *lpc17_40_rqdequeue(FAR struct lpc17_40_ep_s *privep) { - FAR struct lpc17_req_s *ret = privep->head; + FAR struct lpc17_40_req_s *ret = privep->head; if (ret) { @@ -816,15 +816,15 @@ static FAR struct lpc17_req_s *lpc17_rqdequeue(FAR struct lpc17_ep_s *privep) } /**************************************************************************** - * Name: lpc17_rqenqueue + * Name: lpc17_40_rqenqueue * * Description: * Add a request from an endpoint request queue * ****************************************************************************/ -static void lpc17_rqenqueue(FAR struct lpc17_ep_s *privep, - FAR struct lpc17_req_s *req) +static void lpc17_40_rqenqueue(FAR struct lpc17_40_ep_s *privep, + FAR struct lpc17_40_req_s *req) { req->flink = NULL; if (!privep->head) @@ -840,14 +840,14 @@ static void lpc17_rqenqueue(FAR struct lpc17_ep_s *privep, } /**************************************************************************** - * Name: lpc17_epwrite + * Name: lpc17_40_epwrite * * Description: * Endpoint write (IN) * ****************************************************************************/ -static void lpc17_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes) +static void lpc17_40_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes) { uint32_t value; bool aligned = (((uint32_t)data & 3) == 0); @@ -856,12 +856,12 @@ static void lpc17_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes) * the logical endpoint number (0-15) */ - lpc17_putreg(((epphy << 1) & USBDEV_CTRL_LOGEP_MASK) | USBDEV_CTRL_WREN, - LPC17_USBDEV_CTRL); + lpc17_40_putreg(((epphy << 1) & USBDEV_CTRL_LOGEP_MASK) | USBDEV_CTRL_WREN, + LPC17_40_USBDEV_CTRL); /* Set the transmit packet length (nbytes must be less than 2048) */ - lpc17_putreg(nbytes, LPC17_USBDEV_TXPLEN); + lpc17_40_putreg(nbytes, LPC17_40_USBDEV_TXPLEN); /* Transfer the packet data */ @@ -881,34 +881,34 @@ static void lpc17_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes) ((uint32_t)data[2] << 16) | ((uint32_t)data[3] << 24); } - lpc17_putreg(value, LPC17_USBDEV_TXDATA); + lpc17_40_putreg(value, LPC17_40_USBDEV_TXDATA); data += 4; } else { /* Zero length packet */ - lpc17_putreg(0, LPC17_USBDEV_TXDATA); + lpc17_40_putreg(0, LPC17_40_USBDEV_TXDATA); } } - while ((lpc17_getreg(LPC17_USBDEV_CTRL) & USBDEV_CTRL_WREN) != 0); + while ((lpc17_40_getreg(LPC17_40_USBDEV_CTRL) & USBDEV_CTRL_WREN) != 0); /* Done */ - lpc17_putreg(0, LPC17_USBDEV_CTRL); - (void)lpc17_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); - (void)lpc17_usbcmd(CMD_USBDEV_EPVALIDATEBUFFER, 0); + lpc17_40_putreg(0, LPC17_40_USBDEV_CTRL); + (void)lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); + (void)lpc17_40_usbcmd(CMD_USBDEV_EPVALIDATEBUFFER, 0); } /**************************************************************************** - * Name: lpc17_epread + * Name: lpc17_40_epread * * Description: * Endpoint read (OUT) * ****************************************************************************/ -static int lpc17_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) +static int lpc17_40_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) { uint32_t pktlen; uint32_t result; @@ -936,22 +936,22 @@ static int lpc17_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) * the logical endpoint number (0-15). */ - lpc17_putreg(((epphy << 1) & USBDEV_CTRL_LOGEP_MASK) | USBDEV_CTRL_RDEN, - LPC17_USBDEV_CTRL); + lpc17_40_putreg(((epphy << 1) & USBDEV_CTRL_LOGEP_MASK) | USBDEV_CTRL_RDEN, + LPC17_40_USBDEV_CTRL); /* Wait for packet buffer ready for reading */ - while ((lpc17_getreg(LPC17_USBDEV_RXPLEN) & USBDEV_RXPLEN_PKTRDY) == 0); + while ((lpc17_40_getreg(LPC17_40_USBDEV_RXPLEN) & USBDEV_RXPLEN_PKTRDY) == 0); /* Get the number of bytes of data to be read */ - pktlen = lpc17_getreg(LPC17_USBDEV_RXPLEN) & USBDEV_RXPLEN_MASK; + pktlen = lpc17_40_getreg(LPC17_40_USBDEV_RXPLEN) & USBDEV_RXPLEN_MASK; /* Read data from input buffer while read data is valid (DV) */ - while ((lpc17_getreg(LPC17_USBDEV_RXPLEN) & USBDEV_RXPLEN_DV) != 0) + while ((lpc17_40_getreg(LPC17_40_USBDEV_RXPLEN) & USBDEV_RXPLEN_DV) != 0) { - value = lpc17_getreg(LPC17_USBDEV_RXDATA); + value = lpc17_40_getreg(LPC17_40_USBDEV_RXDATA); if (aligned == 1) { *(uint32_t *)data = value; @@ -968,37 +968,37 @@ static int lpc17_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) /* Done */ - lpc17_putreg(0, LPC17_USBDEV_CTRL); - (void)lpc17_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); - result = lpc17_usbcmd(CMD_USBDEV_EPCLRBUFFER, 0); + lpc17_40_putreg(0, LPC17_40_USBDEV_CTRL); + (void)lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); + result = lpc17_40_usbcmd(CMD_USBDEV_EPCLRBUFFER, 0); /* The packet overrun bit in the clear buffer response is applicable only * on EP0 transfers. If set it means that the recevied packet was overwritten * by a later setup packet. */ - if (epphy == LPC17_EP0_OUT && (result & CMD_USBDEV_CLRBUFFER_PO) != 0) + if (epphy == LPC17_40_EP0_OUT && (result & CMD_USBDEV_CLRBUFFER_PO) != 0) { /* Pass this information in bit 31 */ - pktlen |= LPC17_READOVERRUN_BIT; + pktlen |= LPC17_40_READOVERRUN_BIT; } return pktlen; } /**************************************************************************** - * Name: lpc17_abortrequest + * Name: lpc17_40_abortrequest * * Description: * Discard a request * ****************************************************************************/ -static inline void lpc17_abortrequest(struct lpc17_ep_s *privep, - struct lpc17_req_s *privreq, +static inline void lpc17_40_abortrequest(struct lpc17_40_ep_s *privep, + struct lpc17_40_req_s *privreq, int16_t result) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_REQABORTED), (uint16_t)privep->epphy); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_REQABORTED), (uint16_t)privep->epphy); /* Save the result in the request structure */ @@ -1010,23 +1010,23 @@ static inline void lpc17_abortrequest(struct lpc17_ep_s *privep, } /**************************************************************************** - * Name: lpc17_reqcomplete + * Name: lpc17_40_reqcomplete * * Description: * Handle termination of the request at the head of the endpoint request queue. * ****************************************************************************/ -static void lpc17_reqcomplete(struct lpc17_ep_s *privep, int16_t result) +static void lpc17_40_reqcomplete(struct lpc17_40_ep_s *privep, int16_t result) { - struct lpc17_req_s *privreq; + struct lpc17_40_req_s *privreq; int stalled = privep->stalled; irqstate_t flags; /* Remove the completed request at the head of the endpoint request list */ flags = enter_critical_section(); - privreq = lpc17_rqdequeue(privep); + privreq = lpc17_40_rqdequeue(privep); leave_critical_section(flags); if (privreq) @@ -1035,7 +1035,7 @@ static void lpc17_reqcomplete(struct lpc17_ep_s *privep, int16_t result) * in the callback. */ - if (privep->epphy == LPC17_EP0_IN) + if (privep->epphy == LPC17_40_EP0_IN) { privep->stalled = privep->dev->stalled; } @@ -1056,26 +1056,26 @@ static void lpc17_reqcomplete(struct lpc17_ep_s *privep, int16_t result) } /**************************************************************************** - * Name: lpc17_wrrequest + * Name: lpc17_40_wrrequest * * Description: * Send from the next queued write request * ****************************************************************************/ -static int lpc17_wrrequest(struct lpc17_ep_s *privep) +static int lpc17_40_wrrequest(struct lpc17_40_ep_s *privep) { - struct lpc17_req_s *privreq; + struct lpc17_40_req_s *privreq; uint8_t *buf; int nbytes; int bytesleft; /* Check the request from the head of the endpoint request queue */ - privreq = lpc17_rqpeek(privep); + privreq = lpc17_40_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPINQEMPTY), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPINQEMPTY), 0); return OK; } @@ -1087,18 +1087,18 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep) if (privreq->req.len == 0) { - if (privep->epphy == LPC17_EP0_IN) + if (privep->epphy == LPC17_40_EP0_IN) { - lpc17_epwrite(LPC17_EP0_IN, NULL, 0); + lpc17_40_epwrite(LPC17_40_EP0_IN, NULL, 0); } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_EPINNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_EPINNULLPACKET), 0); } /* In any event, the request is complete */ - lpc17_reqcomplete(privep, OK); + lpc17_40_reqcomplete(privep, OK); return OK; } @@ -1145,7 +1145,7 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep) /* Send the largest number of bytes that we can in this packet */ buf = privreq->req.buf + privreq->req.xfrd; - lpc17_epwrite(privep->epphy, buf, nbytes); + lpc17_40_epwrite(privep->epphy, buf, nbytes); /* Update for the next time through the loop */ @@ -1160,32 +1160,32 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep) { usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); privep->txnullpkt = 0; - lpc17_reqcomplete(privep, OK); + lpc17_40_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: lpc17_rdrequest + * Name: lpc17_40_rdrequest * * Description: * Receive to the next queued read request * ****************************************************************************/ -static int lpc17_rdrequest(struct lpc17_ep_s *privep) +static int lpc17_40_rdrequest(struct lpc17_40_ep_s *privep) { - struct lpc17_req_s *privreq; + struct lpc17_40_req_s *privreq; uint8_t *buf; int nbytesread; /* Check the request from the head of the endpoint request queue */ - privreq = lpc17_rqpeek(privep); + privreq = lpc17_40_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPOUTQEMPTY), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPOUTQEMPTY), 0); return OK; } @@ -1196,8 +1196,8 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep) if (privreq->req.len == 0) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_EPOUTNULLPACKET), 0); - lpc17_reqcomplete(privep, OK); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_EPOUTNULLPACKET), 0); + lpc17_40_reqcomplete(privep, OK); return OK; } @@ -1206,10 +1206,10 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep) /* Receive the next packet */ buf = privreq->req.buf + privreq->req.xfrd; - nbytesread = lpc17_epread(privep->epphy, buf, privep->ep.maxpacket); + nbytesread = lpc17_40_epread(privep->epphy, buf, privep->ep.maxpacket); if (nbytesread < 0) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_EPREAD), nbytesread); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_EPREAD), nbytesread); return ERROR; } @@ -1221,32 +1221,32 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep) if (privreq->req.xfrd >= privreq->req.len || nbytesread < privep->ep.maxpacket) { usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - lpc17_reqcomplete(privep, OK); + lpc17_40_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: lpc17_cancelrequests + * Name: lpc17_40_cancelrequests * * Description: * Cancel all pending requests for an endpoint * ****************************************************************************/ -static void lpc17_cancelrequests(struct lpc17_ep_s *privep) +static void lpc17_40_cancelrequests(struct lpc17_40_ep_s *privep) { - while (!lpc17_rqempty(privep)) + while (!lpc17_40_rqempty(privep)) { usbtrace(TRACE_COMPLETE(privep->epphy), - (lpc17_rqpeek(privep))->req.xfrd); - lpc17_reqcomplete(privep, -ESHUTDOWN); + (lpc17_40_rqpeek(privep))->req.xfrd); + lpc17_40_reqcomplete(privep, -ESHUTDOWN); } } /**************************************************************************** - * Name: lpc17_epfindbyaddr + * Name: lpc17_40_epfindbyaddr * * Description: * Find the physical endpoint structure corresponding to a logic endpoint @@ -1254,10 +1254,10 @@ static void lpc17_cancelrequests(struct lpc17_ep_s *privep) * ****************************************************************************/ -static struct lpc17_ep_s *lpc17_epfindbyaddr(struct lpc17_usbdev_s *priv, +static struct lpc17_40_ep_s *lpc17_40_epfindbyaddr(struct lpc17_40_usbdev_s *priv, uint16_t eplog) { - struct lpc17_ep_s *privep; + struct lpc17_40_ep_s *privep; int i; /* Endpoint zero is a special case */ @@ -1269,7 +1269,7 @@ static struct lpc17_ep_s *lpc17_epfindbyaddr(struct lpc17_usbdev_s *priv, /* Handle the remaining */ - for (i = 1; i < LPC17_NPHYSENDPOINTS; i++) + for (i = 1; i < LPC17_40_NPHYSENDPOINTS; i++) { privep = &priv->eplist[i]; @@ -1289,16 +1289,16 @@ static struct lpc17_ep_s *lpc17_epfindbyaddr(struct lpc17_usbdev_s *priv, } /**************************************************************************** - * Name: lpc17_eprealize + * Name: lpc17_40_eprealize * * Description: * Enable or disable an endpoint * ****************************************************************************/ -static void lpc17_eprealize(struct lpc17_ep_s *privep, bool prio, uint32_t packetsize) +static void lpc17_40_eprealize(struct lpc17_40_ep_s *privep, bool prio, uint32_t packetsize) { - struct lpc17_usbdev_s *priv = privep->dev; + struct lpc17_40_usbdev_s *priv = privep->dev; uint32_t mask; uint32_t regval; @@ -1316,157 +1316,157 @@ static void lpc17_eprealize(struct lpc17_ep_s *privep, bool prio, uint32_t packe /* Clear realize interrupt bit */ - lpc17_putreg(USBDEV_INT_EPRLZED, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(USBDEV_INT_EPRLZED, LPC17_40_USBDEV_INTCLR); /* Realize the endpoint */ - regval = lpc17_getreg(LPC17_USBDEV_REEP); + regval = lpc17_40_getreg(LPC17_40_USBDEV_REEP); regval |= (1 << privep->epphy); - lpc17_putreg(regval, LPC17_USBDEV_REEP); + lpc17_40_putreg(regval, LPC17_40_USBDEV_REEP); /* Set endpoint maximum packet size */ - lpc17_putreg(privep->epphy, LPC17_USBDEV_EPIND); - lpc17_putreg(packetsize, LPC17_USBDEV_MAXPSIZE); + lpc17_40_putreg(privep->epphy, LPC17_40_USBDEV_EPIND); + lpc17_40_putreg(packetsize, LPC17_40_USBDEV_MAXPSIZE); /* Wait for Realize complete */ - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_EPRLZED) == 0); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_EPRLZED) == 0); /* Clear realize interrupt bit */ - lpc17_putreg(USBDEV_INT_EPRLZED, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(USBDEV_INT_EPRLZED, LPC17_40_USBDEV_INTCLR); } /**************************************************************************** - * Name: lpc17_epclrinterrupt + * Name: lpc17_40_epclrinterrupt * * Description: * Clear the EP interrupt flag and return the current EP status * ****************************************************************************/ -static uint8_t lpc17_epclrinterrupt(uint8_t epphy) +static uint8_t lpc17_40_epclrinterrupt(uint8_t epphy) { /* Clear the endpoint interrupt */ - lpc17_putreg(1 << epphy, LPC17_USBDEV_EPINTCLR); + lpc17_40_putreg(1 << epphy, LPC17_40_USBDEV_EPINTCLR); /* Wait for data in the command data register */ - while ((lpc17_getreg(LPC17_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); + while ((lpc17_40_getreg(LPC17_40_USBDEV_INTST) & USBDEV_INT_CDFULL) == 0); /* Return the value of the command data register */ - return lpc17_getreg(LPC17_USBDEV_CMDDATA); + return lpc17_40_getreg(LPC17_40_USBDEV_CMDDATA); } /**************************************************************************** - * Name: lpc17_ep0configure + * Name: lpc17_40_ep0configure * * Description: * Configure endpoint 0 * ****************************************************************************/ -static inline void lpc17_ep0configure(struct lpc17_usbdev_s *priv) +static inline void lpc17_40_ep0configure(struct lpc17_40_usbdev_s *priv) { uint32_t inten; /* EndPoint 0 initialization */ - lpc17_eprealize(&priv->eplist[LPC17_CTRLEP_OUT], 0, CONFIG_LPC17_USBDEV_EP0_MAXSIZE); - lpc17_eprealize(&priv->eplist[LPC17_CTRLEP_IN], 1, CONFIG_LPC17_USBDEV_EP0_MAXSIZE); + lpc17_40_eprealize(&priv->eplist[LPC17_40_CTRLEP_OUT], 0, CONFIG_LPC17_40_USBDEV_EP0_MAXSIZE); + lpc17_40_eprealize(&priv->eplist[LPC17_40_CTRLEP_IN], 1, CONFIG_LPC17_40_USBDEV_EP0_MAXSIZE); /* Enable EP0 interrupts (not DMA) */ - inten = lpc17_getreg(LPC17_USBDEV_EPINTEN); + inten = lpc17_40_getreg(LPC17_40_USBDEV_EPINTEN); inten |= 3; /* EP0 Rx and Tx */ - lpc17_putreg(inten, LPC17_USBDEV_EPINTEN); + lpc17_40_putreg(inten, LPC17_40_USBDEV_EPINTEN); } /**************************************************************************** - * Name: lpc17_dmareset + * Name: lpc17_40_dmareset * * Description: Reset USB DMA * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_DMA -static inline void lpc17_dmareset(uint32_t enable) +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static inline void lpc17_40_dmareset(uint32_t enable) { int i; /* Disable All DMA interrupts */ - lpc17_putreg(0, LPC17_USBDEV_DMAINTEN); + lpc17_40_putreg(0, LPC17_40_USBDEV_DMAINTEN); /* DMA Disable */ - lpc17_putreg(0xffffffff, LPC17_USBDEV_EPDMADIS); + lpc17_40_putreg(0xffffffff, LPC17_40_USBDEV_EPDMADIS); /* DMA Request clear */ - putreq32(0xffffffff, LPC17_USBDEV_DMARCLR); + putreq32(0xffffffff, LPC17_40_USBDEV_DMARCLR); /* End of Transfer Interrupt Clear */ - putreq32(0xffffffff, LPC17_USBDEV_EOTINTCLR); + putreq32(0xffffffff, LPC17_40_USBDEV_EOTINTCLR); /* New DD Request Interrupt Clear */ - putreq32(0xffffffff, LPC17_USBDEV_NDDRINTCLR); + putreq32(0xffffffff, LPC17_40_USBDEV_NDDRINTCLR); /* System Error Interrupt Clear */ - putreq32(0xffffffff, LPC17_USBDEV_SYSERRINTCLR); + putreq32(0xffffffff, LPC17_40_USBDEV_SYSERRINTCLR); /* Nullify all pointers in the UDCA */ - for (i = 0; i < LPC17_NPHYSENDPOINTS; ++i) + for (i = 0; i < LPC17_40_NPHYSENDPOINTS; ++i) { g_udca[i] = NULL; } /* Set USB UDCA Head register */ - lpc17_putreg((uint32_t)g_udca, LPC17_USBDEV_UDCAH); + lpc17_40_putreg((uint32_t)g_udca, LPC17_40_USBDEV_UDCAH); /* Invalidate all DMA descriptors */ - for (i = 0; i < CONFIG_LPC17_USBDEV_NDMADESCRIPTORS; ++i) + for (i = 0; i < CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS; ++i) { - memset(&g_usbddesc[i], 0, sizeof(struct lpc17_dmadesc_s)); + memset(&g_usbddesc[i], 0, sizeof(struct lpc17_40_dmadesc_s)); } /* Enable DMA interrupts */ - lpc17_putreg(enable, LPC17_USBDEV_DMAINTEN); + lpc17_40_putreg(enable, LPC17_40_USBDEV_DMAINTEN); } #endif /**************************************************************************** - * Name: lpc17_usbreset + * Name: lpc17_40_usbreset * * Description: * Reset Usb engine * ****************************************************************************/ -static void lpc17_usbreset(struct lpc17_usbdev_s *priv) +static void lpc17_40_usbreset(struct lpc17_40_usbdev_s *priv) { /* Disable all endpoint interrupts */ - lpc17_putreg(0, LPC17_USBDEV_EPINTEN); + lpc17_40_putreg(0, LPC17_40_USBDEV_EPINTEN); /* Frame is Hp interrupt */ - lpc17_putreg(USBDEV_INT_FRAME, LPC17_USBDEV_INTPRI); + lpc17_40_putreg(USBDEV_INT_FRAME, LPC17_40_USBDEV_INTPRI); /* Clear all pending interrupts */ - lpc17_putreg(0xffffffff, LPC17_USBDEV_EPINTCLR); - lpc17_putreg(0xffffffff, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(0xffffffff, LPC17_40_USBDEV_EPINTCLR); + lpc17_40_putreg(0xffffffff, LPC17_40_USBDEV_INTCLR); /* Periperhal address is needed */ @@ -1474,26 +1474,26 @@ static void lpc17_usbreset(struct lpc17_usbdev_s *priv) /* Endpoints not yet configured */ - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 0); /* EndPoint 0 initialization */ - lpc17_ep0configure(priv); + lpc17_40_ep0configure(priv); -#ifdef CONFIG_LPC17_USBDEV_DMA +#ifdef CONFIG_LPC17_40_USBDEV_DMA /* Enable End_of_Transfer_Interrupt and System_Error_Interrupt USB DMA * interrupts */ - lpc17_dmareset(CONFIG_LPC17_USBDEV_DMAINT_MASK); + lpc17_40_dmareset(CONFIG_LPC17_40_USBDEV_DMAINT_MASK); #endif /* Enable Device interrupts */ - lpc17_putreg(USB_SLOW_INT | USB_DEVSTATUS_INT | USB_FAST_INT | + lpc17_40_putreg(USB_SLOW_INT | USB_DEVSTATUS_INT | USB_FAST_INT | USB_FRAME_INT | USB_ERROR_INT, - LPC17_USBDEV_INTEN); + LPC17_40_USBDEV_INTEN); /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. @@ -1506,7 +1506,7 @@ static void lpc17_usbreset(struct lpc17_usbdev_s *priv) } /**************************************************************************** - * Name: lpc17_dispatchrequest + * Name: lpc17_40_dispatchrequest * * Description: * Provide unhandled setup actions to the class driver. This is logically part @@ -1514,12 +1514,12 @@ static void lpc17_usbreset(struct lpc17_usbdev_s *priv) * ****************************************************************************/ -static void lpc17_dispatchrequest(struct lpc17_usbdev_s *priv, +static void lpc17_40_dispatchrequest(struct lpc17_40_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl) { int ret; - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_DISPATCH), 0); if (priv && priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -1529,14 +1529,14 @@ static void lpc17_dispatchrequest(struct lpc17_usbdev_s *priv, { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_DISPATCHSTALL), 0); priv->stalled = 1; } } } /**************************************************************************** - * Name: lpc17_ep0setup + * Name: lpc17_40_ep0setup * * Description: * USB Ctrl EP Setup Event. This is logically part of the USB interrupt @@ -1544,11 +1544,11 @@ static void lpc17_dispatchrequest(struct lpc17_usbdev_s *priv, * ****************************************************************************/ -static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) +static inline void lpc17_40_ep0setup(struct lpc17_40_usbdev_s *priv) { - struct lpc17_ep_s *ep0 = &priv->eplist[LPC17_EP0_OUT]; - struct lpc17_ep_s *privep; - struct lpc17_req_s *privreq = lpc17_rqpeek(ep0); + struct lpc17_40_ep_s *ep0 = &priv->eplist[LPC17_40_EP0_OUT]; + struct lpc17_40_ep_s *privep; + struct lpc17_40_req_s *privreq = lpc17_40_rqpeek(ep0); struct usb_ctrlreq_s ctrl; uint16_t value; uint16_t index; @@ -1561,12 +1561,12 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) if (priv->usbdev.speed == USB_SPEED_UNKNOWN) { priv->usbdev.speed = USB_SPEED_FULL; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 1); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 1); } /* Terminate any pending requests */ - while (!lpc17_rqempty(ep0)) + while (!lpc17_40_rqempty(ep0)) { int16_t result = OK; if (privreq->req.xfrd != privreq->req.len) @@ -1575,7 +1575,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) } usbtrace(TRACE_COMPLETE(ep0->epphy), privreq->req.xfrd); - lpc17_reqcomplete(ep0, result); + lpc17_40_reqcomplete(ep0, result); } /* Assume NOT stalled */ @@ -1585,7 +1585,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) /* Read EP0 data */ - ret = lpc17_epread(LPC17_EP0_OUT, (uint8_t *)&ctrl, USB_SIZEOF_CTRLREQ); + ret = lpc17_40_epread(LPC17_40_EP0_OUT, (uint8_t *)&ctrl, USB_SIZEOF_CTRLREQ); if (ret <= 0) { return; @@ -1604,7 +1604,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) if ((ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - lpc17_dispatchrequest(priv, &ctrl); + lpc17_40_dispatchrequest(priv, &ctrl); return; } @@ -1622,7 +1622,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_GETSTATUS), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_GETSTATUS), 0); if (!priv->paddrset || len != 2 || (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0) { @@ -1634,16 +1634,16 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) { case USB_REQ_RECIPIENT_ENDPOINT: { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPGETSTATUS), 0); - privep = lpc17_epfindbyaddr(priv, index); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPGETSTATUS), 0); + privep = lpc17_40_epfindbyaddr(priv, index); if (!privep) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADEPGETSTATUS), 0); priv->stalled = 1; } else { - if ((lpc17_usbcmd(CMD_USBDEV_EPSELECT | privep->epphy, 0) & + if ((lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | privep->epphy, 0) & CMD_EPSELECT_ST) != 0) { response[0] = 1; /* Stalled */ @@ -1653,8 +1653,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) response[0] = 0; /* Not stalled */ } response[1] = 0; - lpc17_epwrite(LPC17_EP0_IN, response, 2); - priv->ep0state = LPC17_EP0SHORTWRITE; + lpc17_40_epwrite(LPC17_40_EP0_IN, response, 2); + priv->ep0state = LPC17_40_EP0SHORTWRITE; } } break; @@ -1663,19 +1663,19 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) { if (index == 0) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup=YES; selfpowered=? */ response[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | (1 << USB_FEATURE_REMOTEWAKEUP); response[1] = 0; - lpc17_epwrite(LPC17_EP0_IN, response, 2); - priv->ep0state = LPC17_EP0SHORTWRITE; + lpc17_40_epwrite(LPC17_40_EP0_IN, response, 2); + priv->ep0state = LPC17_40_EP0SHORTWRITE; } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADDEVGETSTATUS), 0); priv->stalled = 1; } } @@ -1683,17 +1683,17 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_IFGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_IFGETSTATUS), 0); response[0] = 0; response[1] = 0; - lpc17_epwrite(LPC17_EP0_IN, response, 2); - priv->ep0state = LPC17_EP0SHORTWRITE; + lpc17_40_epwrite(LPC17_40_EP0_IN, response, 2); + priv->ep0state = LPC17_40_EP0SHORTWRITE; } break; default: { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADGETSTATUS), 0); priv->stalled = 1; } break; @@ -1710,22 +1710,22 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_CLEARFEATURE), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_CLEARFEATURE), 0); if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) { - lpc17_dispatchrequest(priv, &ctrl); + lpc17_40_dispatchrequest(priv, &ctrl); } else if (priv->paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT && len == 0 && - (privep = lpc17_epfindbyaddr(priv, index)) != NULL) + (privep = lpc17_40_epfindbyaddr(priv, index)) != NULL) { privep->halted = 0; - (void)lpc17_epstall(&privep->ep, true); - lpc17_epwrite(LPC17_EP0_IN, NULL, 0); - priv->ep0state = LPC17_EP0STATUSIN; + (void)lpc17_40_epstall(&privep->ep, true); + lpc17_40_epwrite(LPC17_40_EP0_IN, NULL, 0); + priv->ep0state = LPC17_40_EP0STATUSIN; } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADCLEARFEATURE), 0); priv->stalled = 1; } } @@ -1739,7 +1739,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_SETFEATURE), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_SETFEATURE), 0); if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value == USB_FEATURE_TESTMODE) { @@ -1747,18 +1747,18 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) } else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) { - lpc17_dispatchrequest(priv, &ctrl); + lpc17_40_dispatchrequest(priv, &ctrl); } else if (priv->paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT && len == 0 && - (privep = lpc17_epfindbyaddr(priv, index)) != NULL) + (privep = lpc17_40_epfindbyaddr(priv, index)) != NULL) { privep->halted = 1; - lpc17_epwrite(LPC17_EP0_IN, NULL, 0); - priv->ep0state = LPC17_EP0STATUSIN; + lpc17_40_epwrite(LPC17_40_EP0_IN, NULL, 0); + priv->ep0state = LPC17_40_EP0STATUSIN; } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADSETFEATURE), 0); priv->stalled = 1; } } @@ -1772,7 +1772,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EP0SETUPSETADDRESS), value); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EP0SETUPSETADDRESS), value); if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index == 0 && len == 0 && value < 128) { @@ -1787,18 +1787,18 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * address at the end of the status phase. */ - lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | priv->paddr); + lpc17_40_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | priv->paddr); /* Send a NULL packet. The status phase completes when the null packet has * been sent successfully. */ - lpc17_epwrite(LPC17_EP0_IN, NULL, 0); - priv->ep0state = LPC17_EP0SETADDRESS; + lpc17_40_epwrite(LPC17_40_EP0_IN, NULL, 0); + priv->ep0state = LPC17_40_EP0SETADDRESS; } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADSETADDRESS), 0); priv->stalled = 1; } } @@ -1817,14 +1817,14 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: descriptor len; data = descriptor */ { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_GETSETDESC), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_GETSETDESC), 0); if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { - lpc17_dispatchrequest(priv, &ctrl); + lpc17_40_dispatchrequest(priv, &ctrl); } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADGETSETDESC), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADGETSETDESC), 0); priv->stalled = 1; } } @@ -1837,15 +1837,15 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 1; data = configuration value */ { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_GETCONFIG), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_GETCONFIG), 0); if (priv->paddrset && (ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && value == 0 && index == 0 && len == 1) { - lpc17_dispatchrequest(priv, &ctrl); + lpc17_40_dispatchrequest(priv, &ctrl); } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADGETCONFIG), 0); priv->stalled = 1; } } @@ -1858,15 +1858,15 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 0; data = none */ { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_SETCONFIG), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_SETCONFIG), 0); if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index == 0 && len == 0) { - lpc17_dispatchrequest(priv, &ctrl); + lpc17_40_dispatchrequest(priv, &ctrl); } else { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADSETCONFIG), 0); priv->stalled = 1; } } @@ -1885,8 +1885,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 0; data = none */ { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_GETSETIF), 0); - lpc17_dispatchrequest(priv, &ctrl); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_GETSETIF), 0); + lpc17_40_dispatchrequest(priv, &ctrl); } break; @@ -1897,13 +1897,13 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * len: 2; data = frame number */ { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDCTRLREQ), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDCTRLREQ), 0); priv->stalled = 1; } break; @@ -1911,14 +1911,14 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_EP0SETUPSTALLED), priv->ep0state); - lpc17_epstall(&priv->eplist[LPC17_EP0_IN].ep, false); - lpc17_epstall(&priv->eplist[LPC17_EP0_OUT].ep, false); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + lpc17_40_epstall(&priv->eplist[LPC17_40_EP0_IN].ep, false); + lpc17_40_epstall(&priv->eplist[LPC17_40_EP0_OUT].ep, false); } } /**************************************************************************** - * Name: lpc17_ep0dataoutinterrupt + * Name: lpc17_40_ep0dataoutinterrupt * * Description: * USB Ctrl EP Data OUT Event. This is logically part of the USB interrupt @@ -1927,7 +1927,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) * ****************************************************************************/ -static inline void lpc17_ep0dataoutinterrupt(struct lpc17_usbdev_s *priv) +static inline void lpc17_40_ep0dataoutinterrupt(struct lpc17_40_usbdev_s *priv) { uint32_t pktlen; @@ -1935,33 +1935,33 @@ static inline void lpc17_ep0dataoutinterrupt(struct lpc17_usbdev_s *priv) switch (priv->ep0state) { - case LPC17_EP0SHORTWRITE: + case LPC17_40_EP0SHORTWRITE: { - priv->ep0state = LPC17_EP0STATUSOUT; - pktlen = lpc17_epread(LPC17_EP0_OUT, NULL, CONFIG_LPC17_USBDEV_EP0_MAXSIZE); - if (LPC17_READOVERRUN(pktlen)) + priv->ep0state = LPC17_40_EP0STATUSOUT; + pktlen = lpc17_40_epread(LPC17_40_EP0_OUT, NULL, CONFIG_LPC17_40_USBDEV_EP0_MAXSIZE); + if (LPC17_40_READOVERRUN(pktlen)) { - lpc17_ep0setup(priv); + lpc17_40_ep0setup(priv); } } break; - case LPC17_EP0SHORTWRSENT: + case LPC17_40_EP0SHORTWRSENT: { - priv->ep0state = LPC17_EP0REQUEST; - pktlen = lpc17_epread(LPC17_EP0_OUT, NULL, CONFIG_LPC17_USBDEV_EP0_MAXSIZE); - if (LPC17_READOVERRUN(pktlen)) + priv->ep0state = LPC17_40_EP0REQUEST; + pktlen = lpc17_40_epread(LPC17_40_EP0_OUT, NULL, CONFIG_LPC17_40_USBDEV_EP0_MAXSIZE); + if (LPC17_40_READOVERRUN(pktlen)) { - lpc17_ep0setup(priv); + lpc17_40_ep0setup(priv); } } break; - case LPC17_EP0REQUEST: + case LPC17_40_EP0REQUEST: { /* Process the next request action (if any) */ - lpc17_rdrequest(&priv->eplist[LPC17_EP0_OUT]); + lpc17_40_rdrequest(&priv->eplist[LPC17_40_EP0_OUT]); } break; @@ -1972,14 +1972,14 @@ static inline void lpc17_ep0dataoutinterrupt(struct lpc17_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_EP0OUTSTALLED), priv->ep0state); - lpc17_epstall(&priv->eplist[LPC17_EP0_IN].ep, false); - lpc17_epstall(&priv->eplist[LPC17_EP0_OUT].ep, false); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_EP0OUTSTALLED), priv->ep0state); + lpc17_40_epstall(&priv->eplist[LPC17_40_EP0_IN].ep, false); + lpc17_40_epstall(&priv->eplist[LPC17_40_EP0_OUT].ep, false); } } /**************************************************************************** - * Name: lpc17_ep0dataininterrupt + * Name: lpc17_40_ep0dataininterrupt * * Description: * USB Ctrl EP Data IN Event. This is logically part of the USB interrupt @@ -1989,44 +1989,44 @@ static inline void lpc17_ep0dataoutinterrupt(struct lpc17_usbdev_s *priv) * ****************************************************************************/ -static inline void lpc17_ep0dataininterrupt(struct lpc17_usbdev_s *priv) +static inline void lpc17_40_ep0dataininterrupt(struct lpc17_40_usbdev_s *priv) { - struct lpc17_ep_s *ep0; + struct lpc17_40_ep_s *ep0; switch (priv->ep0state) { - case LPC17_EP0STATUSOUT: - case LPC17_EP0STATUSIN: - priv->ep0state = LPC17_EP0REQUEST; + case LPC17_40_EP0STATUSOUT: + case LPC17_40_EP0STATUSIN: + priv->ep0state = LPC17_40_EP0REQUEST; break; - case LPC17_EP0SHORTWRITE: - priv->ep0state = LPC17_EP0SHORTWRSENT; + case LPC17_40_EP0SHORTWRITE: + priv->ep0state = LPC17_40_EP0SHORTWRSENT; break; - case LPC17_EP0SETADDRESS: + case LPC17_40_EP0SETADDRESS: { /* If the address was set to a non-zero value, then thiscompletes the * default phase, and begins the address phase (still not fully configured) */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EP0INSETADDRESS), (uint16_t)priv->paddr); - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EP0INSETADDRESS), (uint16_t)priv->paddr); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 0); if (priv->paddr) { priv->paddrset = 1; - priv->ep0state = LPC17_EP0REQUEST; + priv->ep0state = LPC17_40_EP0REQUEST; } } break; - case LPC17_EP0REQUEST: + case LPC17_40_EP0REQUEST: { /* Process the next request action (if any) */ - ep0 = &priv->eplist[LPC17_EP0_IN]; + ep0 = &priv->eplist[LPC17_40_EP0_IN]; ep0->txbusy = 0; - lpc17_wrrequest(ep0); + lpc17_40_wrrequest(ep0); } break; @@ -2037,28 +2037,28 @@ static inline void lpc17_ep0dataininterrupt(struct lpc17_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_EP0INSTALLED), priv->ep0state); - lpc17_epstall(&priv->eplist[LPC17_EP0_IN].ep, false); - lpc17_epstall(&priv->eplist[LPC17_EP0_OUT].ep, false); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_EP0INSTALLED), priv->ep0state); + lpc17_40_epstall(&priv->eplist[LPC17_40_EP0_IN].ep, false); + lpc17_40_epstall(&priv->eplist[LPC17_40_EP0_OUT].ep, false); } } /**************************************************************************** - * Name: lpc17_usbinterrupt + * Name: lpc17_40_usbinterrupt * * Description: * USB interrupt handler * ****************************************************************************/ -static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) +static int lpc17_40_usbinterrupt(int irq, FAR void *context, FAR void *arg) { - struct lpc17_usbdev_s *priv = &g_usbdev; - struct lpc17_ep_s *privep ; + struct lpc17_40_usbdev_s *priv = &g_usbdev; + struct lpc17_40_ep_s *privep ; uint32_t devintstatus; /* Sampled state of the device interrupt status register */ uint32_t epintstatus; /* Sampled state of the endpoint interrupt status register */ -#ifdef CONFIG_LPC17_USBDEV_DMA +#ifdef CONFIG_LPC17_40_USBDEV_DMA uint32_t usbintstatus; /* Sampled state is SYSCON USB interrupt status */ uint32_t dmaintstatus; /* Sampled state of dma interrupt status register */ #endif @@ -2069,25 +2069,25 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* Read the device interrupt status register */ - devintstatus = lpc17_getreg(LPC17_USBDEV_INTST); - usbtrace(TRACE_INTENTRY(LPC17_TRACEINTID_USB), (uint16_t)devintstatus); + devintstatus = lpc17_40_getreg(LPC17_40_USBDEV_INTST); + usbtrace(TRACE_INTENTRY(LPC17_40_TRACEINTID_USB), (uint16_t)devintstatus); -#ifdef CONFIG_LPC17_USBDEV_DMA +#ifdef CONFIG_LPC17_40_USBDEV_DMA /* Check for low priority and high priority (non-DMA) interrupts */ - usbintstatus = lpc17_getreg(LPC17_SYSCON_USBINTST); + usbintstatus = lpc17_40_getreg(LPC17_40_SYSCON_USBINTST); if ((usbintstatus & (SYSCON_USBINTST_REQLP | SYSCON_USBINTST_REQHP)) != 0) { #endif -#ifdef CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT +#ifdef CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT /* Fast EP interrupt */ if ((devintstatus & USBDEV_INT_EPFAST) != 0) { /* Clear Fast EP interrupt */ - lpc17_putreg(USBDEV_INT_EPFAST, LPC17_USBDEV_INTCLR); - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPFAST), 0); + lpc17_40_putreg(USBDEV_INT_EPFAST, LPC17_40_USBDEV_INTCLR); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPFAST), 0); /* Do what? */ } @@ -2103,28 +2103,28 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* Clear the error interrupt */ - lpc17_putreg(USBDEV_INT_ERRINT, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(USBDEV_INT_ERRINT, LPC17_40_USBDEV_INTCLR); /* And show what error occurred */ - errcode = (uint8_t)lpc17_usbcmd(CMD_USBDEV_READERRORSTATUS, 0) & CMD_READERRORSTATUS_ALLERRS; - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_ERRINT), (uint16_t)errcode); + errcode = (uint8_t)lpc17_40_usbcmd(CMD_USBDEV_READERRORSTATUS, 0) & CMD_READERRORSTATUS_ALLERRS; + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_ERRINT), (uint16_t)errcode); } #endif -#ifdef CONFIG_LPC17_USBDEV_FRAME_INTERRUPT +#ifdef CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT /* Frame interrupt */ if ((devintstatus & USBDEV_INT_FRAME) != 0) { /* Clear the frame interrupt */ - lpc17_putreg(USBDEV_INT_FRAME, LPC17_USBDEV_INTCLR); - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_FRAME), 0); + lpc17_40_putreg(USBDEV_INT_FRAME, LPC17_40_USBDEV_INTCLR); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_FRAME), 0); /* Then read the start of frame value */ - priv->sof = (uint16_t)lpc17_usbcmd(CMD_USBDEV_READFRAMENO, 0); + priv->sof = (uint16_t)lpc17_40_usbcmd(CMD_USBDEV_READFRAMENO, 0); } #endif @@ -2134,18 +2134,18 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* Clear Device status interrupt */ - lpc17_putreg(USBDEV_INT_DEVSTAT, LPC17_USBDEV_INTCLR); + lpc17_40_putreg(USBDEV_INT_DEVSTAT, LPC17_40_USBDEV_INTCLR); /* Get device status */ - g_usbdev.devstatus = (uint8_t)lpc17_usbcmd(CMD_USBDEV_GETSTATUS, 0); - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DEVSTAT), (uint16_t)g_usbdev.devstatus); + g_usbdev.devstatus = (uint8_t)lpc17_40_usbcmd(CMD_USBDEV_GETSTATUS, 0); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_DEVSTAT), (uint16_t)g_usbdev.devstatus); /* Device connection status */ if (DEVSTATUS_CONNCHG(g_usbdev.devstatus)) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_CONNECTCHG), + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_CONNECTCHG), (uint16_t)g_usbdev.devstatus); if (DEVSTATUS_CONNECT(g_usbdev.devstatus)) { @@ -2155,10 +2155,10 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* We have a transition from unattached to attached */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_CONNECTED), + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_CONNECTED), (uint16_t)g_usbdev.devstatus); priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 0); priv->attached = 1; } } @@ -2167,10 +2167,10 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) else if (priv->attached) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DISCONNECTED), + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_DISCONNECTED), (uint16_t)g_usbdev.devstatus); priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 0); priv->attached = 0; priv->paddrset = 0; } @@ -2180,7 +2180,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) if (DEVSTATUS_SUSPCHG(g_usbdev.devstatus)) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_SUSPENDCHG), + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_SUSPENDCHG), (uint16_t)g_usbdev.devstatus); /* Inform the Class driver of the change */ @@ -2204,9 +2204,9 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) if (DEVSTATUS_RESET(g_usbdev.devstatus)) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DEVRESET), + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_DEVRESET), (uint16_t)g_usbdev.devstatus); - lpc17_usbreset(priv); + lpc17_40_usbreset(priv); } } @@ -2216,14 +2216,14 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* Clear Slow EP interrupt */ - lpc17_putreg(USBDEV_INT_EPSLOW, LPC17_USBDEV_INTCLR); - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPSLOW), 0); + lpc17_40_putreg(USBDEV_INT_EPSLOW, LPC17_40_USBDEV_INTCLR); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPSLOW), 0); do { /* Read the endpoint interrupt status register */ - epintstatus = lpc17_getreg(LPC17_USBDEV_EPINTST); + epintstatus = lpc17_40_getreg(LPC17_40_USBDEV_EPINTST); /* Loop twice: Process software high priority interrupts * on the first pass and low priority interrupts on the @@ -2247,16 +2247,16 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* Clear the endpoint interrupt */ - uint32_t result = lpc17_epclrinterrupt(LPC17_CTRLEP_OUT); + uint32_t result = lpc17_40_epclrinterrupt(LPC17_40_CTRLEP_OUT); if (result & CMD_EPSELECT_STP) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EP0SETUP), (uint16_t)result); - lpc17_ep0setup(priv); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EP0SETUP), (uint16_t)result); + lpc17_40_ep0setup(priv); } else { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EP0OUT), priv->ep0state); - lpc17_ep0dataoutinterrupt(priv); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EP0OUT), priv->ep0state); + lpc17_40_ep0dataoutinterrupt(priv); } break; } @@ -2267,9 +2267,9 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* Clear the endpoint interrupt */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EP0IN), priv->ep0state); - (void)lpc17_epclrinterrupt(LPC17_CTRLEP_IN); - lpc17_ep0dataininterrupt(priv); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EP0IN), priv->ep0state); + (void)lpc17_40_epclrinterrupt(LPC17_40_CTRLEP_IN); + lpc17_40_ep0dataininterrupt(priv); } pending >>= 2; @@ -2283,7 +2283,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* Yes.. clear the endpoint interrupt */ - (void)lpc17_epclrinterrupt(epphy); + (void)lpc17_40_epclrinterrupt(epphy); /* Get the endpoint sructure corresponding to the physical * endpoint number. @@ -2299,29 +2299,29 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* IN: device-to-host */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPOUT), (uint16_t)epphy); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPOUT), (uint16_t)epphy); if (priv->usbdev.speed == USB_SPEED_UNKNOWN) { priv->usbdev.speed = USB_SPEED_FULL; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 1); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 1); } /* Write host data from the current write request (if any) */ privep->txbusy = 0; - lpc17_wrrequest(privep); + lpc17_40_wrrequest(privep); } else { /* OUT: host-to-device */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPIN), (uint16_t)epphy); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPIN), (uint16_t)epphy); /* Read host data into the current read request */ - if (!lpc17_rqempty(privep)) + if (!lpc17_40_rqempty(privep)) { - lpc17_rdrequest(privep); + lpc17_40_rdrequest(privep); } else { @@ -2336,7 +2336,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) } while (epintstatus); } -#ifdef CONFIG_LPC17_USBDEV_DMA +#ifdef CONFIG_LPC17_40_USBDEV_DMA } /* Check for DMA interrupts */ @@ -2350,26 +2350,26 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* Collect the DMA interrupt sources */ dmaintstatus = 0; - tmp = lpc17_getreg(LPC17_USBDEV_EOTINTST); - if (lpc17_getreg(LPC17_USBDEV_DMAINTEN) & 1) + tmp = lpc17_40_getreg(LPC17_40_USBDEV_EOTINTST); + if (lpc17_40_getreg(LPC17_40_USBDEV_DMAINTEN) & 1) { dmaintstatus |= tmp; } - lpc17_putreg(tmp, LPC17_USBDEV_EOTINTCLR); + lpc17_40_putreg(tmp, LPC17_40_USBDEV_EOTINTCLR); - tmp = lpc17_getreg(LPC17_USBDEV_NDDRINTST); - if (lpc17_getreg(LPC17_USBDEV_DMAINTEN) & 2) + tmp = lpc17_40_getreg(LPC17_40_USBDEV_NDDRINTST); + if (lpc17_40_getreg(LPC17_40_USBDEV_DMAINTEN) & 2) { dmaintstatus |= tmp; } - lpc17_putreg(tmp, LPC17_USBDEV_NDDRINTCLR); + lpc17_40_putreg(tmp, LPC17_40_USBDEV_NDDRINTCLR); - tmp = lpc17_getreg(LPC17_USBDEV_SYSERRINTST); - if (lpc17_getreg(LPC17_USBDEV_DMAINTEN) & 4) + tmp = lpc17_40_getreg(LPC17_40_USBDEV_SYSERRINTST); + if (lpc17_40_getreg(LPC17_40_USBDEV_DMAINTEN) & 4) { dmaintstatus |= tmp; } - lpc17_putreg(tmp, LPC17_USBDEV_SYSERRINTCLR); + lpc17_40_putreg(tmp, LPC17_40_USBDEV_SYSERRINTCLR); /* Loop twice: Process software high priority interrupts on the * first pass and low priority interrupts on the second. @@ -2390,37 +2390,37 @@ static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { if ((pending & 1) != 0) { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPDMA), (uint16_t)epphy); + usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EPDMA), (uint16_t)epphy); #warning DO WHAT? } } } } #endif - usbtrace(TRACE_INTEXIT(LPC17_TRACEINTID_USB), 0); + usbtrace(TRACE_INTEXIT(LPC17_40_TRACEINTID_USB), 0); return OK; } /**************************************************************************** - * Name: lpc17_dmasetup + * Name: lpc17_40_dmasetup * * Description: * Setup for DMA Transfer * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_DMA -static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static int lpc17_40_dmasetup(struct lpc17_40_usbdev_s *priv, uint8_t epphy, uint32_t epmaxsize, uint32_t nbytes, uint32_t *isocpacket, bool isochronous); { - struct lpc17_dmadesc_s *dmadesc = priv; + struct lpc17_40_dmadesc_s *dmadesc = priv; uint32_t regval; #ifdef CONFIG_DEBUG_USB if (!priv || epphy < 2) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -2431,7 +2431,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, if (!dmadesc) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_NODMADESC), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_NODMADESC), 0); return -EBUSY; } @@ -2439,7 +2439,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, if ((dmadesc->status & USB_DMADESC_STATUS_MASK) == USB_DMADESC_BEINGSERVICED) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_DMABUSY), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_DMABUSY), 0); return -EBUSY; /* Shouldn't happen */ } @@ -2466,14 +2466,14 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, /* Enable DMA transfer for this endpoint */ - putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN); + putreq32(1 << epphy, LPC17_40_USBDEV_EPDMAEN); /* Check state of IN/OUT Ep buffer */ - regval = lpc17_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); + regval = lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); - if ((LPC17_EPPHYIN(epphy) && (regval & 0x60) == 0) || - (LPC17_EPPHYOUT(epphy) && (regval & 0x60) == 0x60)) + if ((LPC17_40_EPPHYIN(epphy) && (regval & 0x60) == 0) || + (LPC17_40_EPPHYOUT(epphy) && (regval & 0x60) == 0x60)) { /* DMA should be "being serviced" */ @@ -2481,24 +2481,24 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, { /* Re-trigger the DMA Transfer */ - putreq32(1 << epphy, LPC17_USBDEV_DMARCLR); - putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN); + putreq32(1 << epphy, LPC17_40_USBDEV_DMARCLR); + putreq32(1 << epphy, LPC17_40_USBDEV_EPDMAEN); } } return OK; } -#endif /* CONFIG_LPC17_USBDEV_DMA */ +#endif /* CONFIG_LPC17_40_USBDEV_DMA */ /**************************************************************************** - * Name: lpc17_dmarestart + * Name: lpc17_40_dmarestart * * Description: * Restart DMA Transfer * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_DMA -static void lpc17_dmarestart(uint8_t epphy, uint32_t descndx) +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static void lpc17_40_dmarestart(uint8_t epphy, uint32_t descndx) { uint32_t regval; @@ -2508,43 +2508,43 @@ static void lpc17_dmarestart(uint8_t epphy, uint32_t descndx) /* Enable DMA transfer on the endpoint */ - lpc17_putreg(1 << epph, LPC17_USBDEV_EPDMAEN); + lpc17_40_putreg(1 << epph, LPC17_40_USBDEV_EPDMAEN); /* Check the state of IN/OUT EP buffer */ - uint32_t regval = lpc17_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); - if ((LPC17_EPPHYIN(epphy) && (regval & 0x60) == 0) || - (LPC17_EPPHYIN(epphy) && (regval & 0x60) == 0x60)) + uint32_t regval = lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0); + if ((LPC17_40_EPPHYIN(epphy) && (regval & 0x60) == 0) || + (LPC17_40_EPPHYIN(epphy) && (regval & 0x60) == 0x60)) { /* Re-trigger the DMA Transfer */ - putreq32(1 << epphy, LPC17_USBDEV_DMARCLR); - putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN); + putreq32(1 << epphy, LPC17_40_USBDEV_DMARCLR); + putreq32(1 << epphy, LPC17_40_USBDEV_EPDMAEN); } } -#endif /* CONFIG_LPC17_USBDEV_DMA */ +#endif /* CONFIG_LPC17_40_USBDEV_DMA */ /**************************************************************************** - * Name: lpc17_dmadisable + * Name: lpc17_40_dmadisable * * Description: * Disable DMA transfer for the EP * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBDEV_DMA -static void lpc17_dmadisable(uint8_t epphy) +#ifdef CONFIG_LPC17_40_USBDEV_DMA +static void lpc17_40_dmadisable(uint8_t epphy) { EPDMADIS = 1 << epphy; } -#endif /* CONFIG_LPC17_USBDEV_DMA */ +#endif /* CONFIG_LPC17_40_USBDEV_DMA */ /**************************************************************************** * Endpoint operations ****************************************************************************/ /**************************************************************************** - * Name: lpc17_epconfigure + * Name: lpc17_40_epconfigure * * Description: * Configure endpoint, making it usable @@ -2558,11 +2558,11 @@ static void lpc17_dmadisable(uint8_t epphy) * ****************************************************************************/ -static int lpc17_epconfigure(FAR struct usbdev_ep_s *ep, +static int lpc17_40_epconfigure(FAR struct usbdev_ep_s *ep, FAR const struct usb_epdesc_s *desc, bool last) { - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; uint32_t inten; usbtrace(TRACE_EPCONFIGURE, privep->epphy); @@ -2570,23 +2570,23 @@ static int lpc17_epconfigure(FAR struct usbdev_ep_s *ep, /* Realize the endpoint */ - lpc17_eprealize(privep, 1, GETUINT16(desc->mxpacketsize)); + lpc17_40_eprealize(privep, 1, GETUINT16(desc->mxpacketsize)); /* Enable and reset EP -- twice */ - lpc17_usbcmd(CMD_USBDEV_EPSETSTATUS | privep->epphy, 0); - lpc17_usbcmd(CMD_USBDEV_EPSETSTATUS | privep->epphy, 0); + lpc17_40_usbcmd(CMD_USBDEV_EPSETSTATUS | privep->epphy, 0); + lpc17_40_usbcmd(CMD_USBDEV_EPSETSTATUS | privep->epphy, 0); -#ifdef CONFIG_LPC17_USBDEV_DMA +#ifdef CONFIG_LPC17_40_USBDEV_DMA /* Enable DMA Ep interrupt (WO) */ - lpc17_putreg(1 << privep->epphy, LPC17_USBDEV_EPDMAEN); + lpc17_40_putreg(1 << privep->epphy, LPC17_40_USBDEV_EPDMAEN); #else /* Enable Ep interrupt (R/W) */ - inten = lpc17_getreg(LPC17_USBDEV_EPINTEN); + inten = lpc17_40_getreg(LPC17_40_USBDEV_EPINTEN); inten |= (1 << privep->epphy); - lpc17_putreg(inten, LPC17_USBDEV_EPINTEN); + lpc17_40_putreg(inten, LPC17_40_USBDEV_EPINTEN); #endif /* If all of the endpoints have been configured, then tell the USB controller @@ -2595,23 +2595,23 @@ static int lpc17_epconfigure(FAR struct usbdev_ep_s *ep, if (last) { - lpc17_usbcmd(CMD_USBDEV_CONFIG, 1); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 1); } return OK; } /**************************************************************************** - * Name: lpc17_epdisable + * Name: lpc17_40_epdisable * * Description: * The endpoint will no longer be used * ****************************************************************************/ -static int lpc17_epdisable(FAR struct usbdev_ep_s *ep) +static int lpc17_40_epdisable(FAR struct usbdev_ep_s *ep) { - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; irqstate_t flags; uint32_t mask = (1 << privep->epphy); uint32_t regval; @@ -2619,7 +2619,7 @@ static int lpc17_epdisable(FAR struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -2629,84 +2629,84 @@ static int lpc17_epdisable(FAR struct usbdev_ep_s *ep) /* Cancel any ongoing activity */ flags = enter_critical_section(); - lpc17_cancelrequests(privep); + lpc17_40_cancelrequests(privep); /* Disable endpoint and interrupt */ - regval = lpc17_getreg(LPC17_USBDEV_REEP); + regval = lpc17_40_getreg(LPC17_40_USBDEV_REEP); regval &= ~mask; - lpc17_putreg(regval, LPC17_USBDEV_REEP); + lpc17_40_putreg(regval, LPC17_40_USBDEV_REEP); - lpc17_putreg(mask, LPC17_USBDEV_EPDMADIS); + lpc17_40_putreg(mask, LPC17_40_USBDEV_EPDMADIS); - regval = lpc17_getreg(LPC17_USBDEV_EPINTEN); + regval = lpc17_40_getreg(LPC17_40_USBDEV_EPINTEN); regval &= ~mask; - lpc17_putreg(regval, LPC17_USBDEV_EPINTEN); + lpc17_40_putreg(regval, LPC17_40_USBDEV_EPINTEN); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: lpc17_epallocreq + * Name: lpc17_40_epallocreq * * Description: * Allocate an I/O request * ****************************************************************************/ -static FAR struct usbdev_req_s *lpc17_epallocreq(FAR struct usbdev_ep_s *ep) +static FAR struct usbdev_req_s *lpc17_40_epallocreq(FAR struct usbdev_ep_s *ep) { - FAR struct lpc17_req_s *privreq; + FAR struct lpc17_40_req_s *privreq; #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif - usbtrace(TRACE_EPALLOCREQ, ((FAR struct lpc17_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCREQ, ((FAR struct lpc17_40_ep_s *)ep)->epphy); - privreq = (FAR struct lpc17_req_s *)kmm_malloc(sizeof(struct lpc17_req_s)); + privreq = (FAR struct lpc17_40_req_s *)kmm_malloc(sizeof(struct lpc17_40_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct lpc17_req_s)); + memset(privreq, 0, sizeof(struct lpc17_40_req_s)); return &privreq->req; } /**************************************************************************** - * Name: lpc17_epfreereq + * Name: lpc17_40_epfreereq * * Description: * Free an I/O request * ****************************************************************************/ -static void lpc17_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static void lpc17_40_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) { - FAR struct lpc17_req_s *privreq = (FAR struct lpc17_req_s *)req; + FAR struct lpc17_40_req_s *privreq = (FAR struct lpc17_40_req_s *)req; #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return; } #endif - usbtrace(TRACE_EPFREEREQ, ((FAR struct lpc17_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEREQ, ((FAR struct lpc17_40_ep_s *)ep)->epphy); kmm_free(privreq); } /**************************************************************************** - * Name: lpc17_epallocbuffer + * Name: lpc17_40_epallocbuffer * * Description: * Allocate an I/O buffer @@ -2714,11 +2714,11 @@ static void lpc17_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static FAR void *lpc17_epallocbuffer(FAR struct usbdev_ep_s *ep, uint16_t nbytes) +static FAR void *lpc17_40_epallocbuffer(FAR struct usbdev_ep_s *ep, uint16_t nbytes) { -#if defined(CONFIG_LPC17_USBDEV_DMA) +#if defined(CONFIG_LPC17_40_USBDEV_DMA) - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; int descndx; usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); @@ -2747,7 +2747,7 @@ static FAR void *lpc17_epallocbuffer(FAR struct usbdev_ep_s *ep, uint16_t nbytes #endif /**************************************************************************** - * Name: lpc17_epfreebuffer + * Name: lpc17_40_epfreebuffer * * Description: * Free an I/O buffer @@ -2755,11 +2755,11 @@ static FAR void *lpc17_epallocbuffer(FAR struct usbdev_ep_s *ep, uint16_t nbytes ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void lpc17_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) +static void lpc17_40_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) { -#if defined(CONFIG_LPC17_USBDEV_DMA) +#if defined(CONFIG_LPC17_40_USBDEV_DMA) - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; usbtrace(TRACE_EPFREEBUFFER, privep->epphy); @@ -2786,25 +2786,25 @@ static void lpc17_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) #endif /**************************************************************************** - * Name: lpc17_epsubmit + * Name: lpc17_40_epsubmit * * Description: * Submit an I/O request to the endpoint * ****************************************************************************/ -static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int lpc17_40_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) { - FAR struct lpc17_req_s *privreq = (FAR struct lpc17_req_s *)req; - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; - FAR struct lpc17_usbdev_s *priv; + FAR struct lpc17_40_req_s *privreq = (FAR struct lpc17_40_req_s *)req; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; + FAR struct lpc17_40_usbdev_s *priv; irqstate_t flags; int ret = OK; #ifdef CONFIG_DEBUG_USB if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -2816,7 +2816,7 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r if (!priv->driver || priv->usbdev.speed == USB_SPEED_UNKNOWN) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); return -ESHUTDOWN; } @@ -2830,24 +2830,24 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r if (privep->stalled) { - lpc17_abortrequest(privep, privreq, -EBUSY); + lpc17_40_abortrequest(privep, privreq, -EBUSY); ret = -EBUSY; } /* Handle IN (device-to-host) requests */ - else if (LPC17_EPPHYIN(privep->epphy)) + else if (LPC17_40_EPPHYIN(privep->epphy)) { /* Add the new request to the request queue for the IN endpoint */ - lpc17_rqenqueue(privep, privreq); + lpc17_40_rqenqueue(privep, privreq); usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); /* If the IN endpoint FIFO is available, then transfer the data now */ if (privep->txbusy == 0) { - ret = lpc17_wrrequest(privep); + ret = lpc17_40_wrrequest(privep); } } @@ -2858,14 +2858,14 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r /* Add the new request to the request queue for the OUT endpoint */ privep->txnullpkt = 0; - lpc17_rqenqueue(privep, privreq); + lpc17_40_rqenqueue(privep, privreq); usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); /* This there a incoming data pending the availability of a request? */ if (priv->rxpending > 0) { - ret = lpc17_rdrequest(privep); + ret = lpc17_40_rdrequest(privep); priv->rxpending--; } } @@ -2875,22 +2875,22 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r } /**************************************************************************** - * Name: lpc17_epcancel + * Name: lpc17_40_epcancel * * Description: * Cancel an I/O request previously sent to an endpoint * ****************************************************************************/ -static int lpc17_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int lpc17_40_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) { - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -2898,35 +2898,35 @@ static int lpc17_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r usbtrace(TRACE_EPCANCEL, privep->epphy); flags = enter_critical_section(); - lpc17_cancelrequests(privep); + lpc17_40_cancelrequests(privep); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: lpc17_epstall + * Name: lpc17_40_epstall * * Description: * Stall or resume and endpoint * ****************************************************************************/ -static int lpc17_epstall(FAR struct usbdev_ep_s *ep, bool resume) +static int lpc17_40_epstall(FAR struct usbdev_ep_s *ep, bool resume) { - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; irqstate_t flags; /* STALL or RESUME the endpoint */ flags = enter_critical_section(); usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, privep->epphy); - lpc17_usbcmd(CMD_USBDEV_EPSETSTATUS | privep->epphy, (resume ? 0 : CMD_SETSTAUS_ST)); + lpc17_40_usbcmd(CMD_USBDEV_EPSETSTATUS | privep->epphy, (resume ? 0 : CMD_SETSTAUS_ST)); /* If the endpoint of was resumed, then restart any queue write requests */ if (resume) { - (void)lpc17_wrrequest(privep); + (void)lpc17_40_wrrequest(privep); } leave_critical_section(flags); return OK; @@ -2937,7 +2937,7 @@ static int lpc17_epstall(FAR struct usbdev_ep_s *ep, bool resume) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_allocep + * Name: lpc17_40_allocep * * Description: * Allocate an endpoint matching the parameters. @@ -2952,11 +2952,11 @@ static int lpc17_epstall(FAR struct usbdev_ep_s *ep, bool resume) * ****************************************************************************/ -static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, uint8_t eplog, +static FAR struct usbdev_ep_s *lpc17_40_allocep(FAR struct usbdev_s *dev, uint8_t eplog, bool in, uint8_t eptype) { - FAR struct lpc17_usbdev_s *priv = (FAR struct lpc17_usbdev_s *)dev; - uint32_t epset = LPC17_EPALLSET & ~LPC17_EPCTRLSET; + FAR struct lpc17_40_usbdev_s *priv = (FAR struct lpc17_40_usbdev_s *)dev; + uint32_t epset = LPC17_40_EPALLSET & ~LPC17_40_EPCTRLSET; irqstate_t flags; int epndx = 0; @@ -2977,9 +2977,9 @@ static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, uint8_t e * by the hardware. */ - if (eplog >= LPC17_NLOGENDPOINTS) + if (eplog >= LPC17_40_NLOGENDPOINTS) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADEPNO), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADEPNO), (uint16_t)eplog); return NULL; } @@ -2995,11 +2995,11 @@ static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, uint8_t e if (in) { - epset &= LPC17_EPINSET; + epset &= LPC17_40_EPINSET; } else { - epset &= LPC17_EPOUTSET; + epset &= LPC17_40_EPOUTSET; } /* Get the subset matching the requested type */ @@ -3007,24 +3007,24 @@ static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, uint8_t e switch (eptype) { case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ - epset &= LPC17_EPINTRSET; + epset &= LPC17_40_EPINTRSET; break; case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ - epset &= LPC17_EPBULKSET; + epset &= LPC17_40_EPBULKSET; break; case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ - epset &= LPC17_EPISOCSET; + epset &= LPC17_40_EPISOCSET; break; case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint -- not a valid choice */ default: - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BADEPTYPE), (uint16_t)eptype); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BADEPTYPE), (uint16_t)eptype); return NULL; } - /* Is the resulting endpoint supported by the LPC17xx? */ + /* Is the resulting endpoint supported by the LPC17xx/LPC40xx? */ if (epset) { @@ -3036,7 +3036,7 @@ static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, uint8_t e { /* Select the lowest bit in the set of matching, available endpoints */ - for (epndx = 2; epndx < LPC17_NPHYSENDPOINTS; epndx++) + for (epndx = 2; epndx < LPC17_40_NPHYSENDPOINTS; epndx++) { uint32_t bit = 1 << epndx; if ((epset & bit) != 0) @@ -3056,22 +3056,22 @@ static FAR struct usbdev_ep_s *lpc17_allocep(FAR struct usbdev_s *dev, uint8_t e leave_critical_section(flags); } - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_NOEP), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_NOEP), (uint16_t)eplog); return NULL; } /**************************************************************************** - * Name: lpc17_freeep + * Name: lpc17_40_freeep * * Description: * Free the previously allocated endpoint * ****************************************************************************/ -static void lpc17_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) +static void lpc17_40_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) { - FAR struct lpc17_usbdev_s *priv = (FAR struct lpc17_usbdev_s *)dev; - FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep; + FAR struct lpc17_40_usbdev_s *priv = (FAR struct lpc17_40_usbdev_s *)dev; + FAR struct lpc17_40_ep_s *privep = (FAR struct lpc17_40_ep_s *)ep; irqstate_t flags; usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); @@ -3087,17 +3087,17 @@ static void lpc17_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) } /**************************************************************************** - * Name: lpc17_getframe + * Name: lpc17_40_getframe * * Description: * Returns the current frame number * ****************************************************************************/ -static int lpc17_getframe(struct usbdev_s *dev) +static int lpc17_40_getframe(struct usbdev_s *dev) { -#ifdef CONFIG_LPC17_USBDEV_FRAME_INTERRUPT - FAR struct lpc17_usbdev_s *priv = (FAR struct lpc17_usbdev_s *)dev; +#ifdef CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT + FAR struct lpc17_40_usbdev_s *priv = (FAR struct lpc17_40_usbdev_s *)dev; /* Return last valid value of SOF read by the interrupt handler */ @@ -3107,19 +3107,19 @@ static int lpc17_getframe(struct usbdev_s *dev) /* Return the last frame number detected by the hardware */ usbtrace(TRACE_DEVGETFRAME, 0); - return (int)lpc17_usbcmd(CMD_USBDEV_READFRAMENO, 0); + return (int)lpc17_40_usbcmd(CMD_USBDEV_READFRAMENO, 0); #endif } /**************************************************************************** - * Name: lpc17_wakeup + * Name: lpc17_40_wakeup * * Description: * Tries to wake up the host connected to this device * ****************************************************************************/ -static int lpc17_wakeup(struct usbdev_s *dev) +static int lpc17_40_wakeup(struct usbdev_s *dev) { uint8_t arg = CMD_STATUS_SUSPEND; irqstate_t flags; @@ -3132,29 +3132,29 @@ static int lpc17_wakeup(struct usbdev_s *dev) arg |= CMD_STATUS_CONNECT; } - lpc17_usbcmd(CMD_USBDEV_SETSTATUS, arg); + lpc17_40_usbcmd(CMD_USBDEV_SETSTATUS, arg); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: lpc17_selfpowered + * Name: lpc17_40_selfpowered * * Description: * Sets/clears the device selfpowered feature * ****************************************************************************/ -static int lpc17_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int lpc17_40_selfpowered(struct usbdev_s *dev, bool selfpowered) { - FAR struct lpc17_usbdev_s *priv = (FAR struct lpc17_usbdev_s *)dev; + FAR struct lpc17_40_usbdev_s *priv = (FAR struct lpc17_40_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -3164,22 +3164,22 @@ static int lpc17_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: lpc17_pullup + * Name: lpc17_40_pullup * * Description: * Software-controlled connect to/disconnect from USB host * ****************************************************************************/ -static int lpc17_pullup(struct usbdev_s *dev, bool enable) +static int lpc17_40_pullup(struct usbdev_s *dev, bool enable) { usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); /* The CMD_STATUS_CONNECT bit in the CMD_USBDEV_SETSTATUS command - * controls the LPC17xx SoftConnect_N output pin that is used for SoftConnect. + * controls the LPC17xx/LPC40xx SoftConnect_N output pin that is used for SoftConnect. */ - lpc17_usbcmd(CMD_USBDEV_SETSTATUS, (enable ? CMD_STATUS_CONNECT : 0)); + lpc17_40_usbcmd(CMD_USBDEV_SETSTATUS, (enable ? CMD_STATUS_CONNECT : 0)); return OK; } @@ -3201,7 +3201,7 @@ static int lpc17_pullup(struct usbdev_s *dev, bool enable) void up_usbinitialize(void) { - struct lpc17_usbdev_s *priv = &g_usbdev; + struct lpc17_40_usbdev_s *priv = &g_usbdev; uint32_t regval; irqstate_t flags; int i; @@ -3211,56 +3211,56 @@ void up_usbinitialize(void) /* Step 1: Enable power by setting PCUSB in the PCONP register */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_SYSCON_PCONP); + regval = lpc17_40_getreg(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCUSB; - lpc17_putreg(regval, LPC17_SYSCON_PCONP); + lpc17_40_putreg(regval, LPC17_40_SYSCON_PCONP); /* Step 2: Enable clocking on USB (USB PLL clocking was initialized in - * in very low-level clock setup logic (see lpc17_clockconfig.c)). We + * in very low-level clock setup logic (see lpc17_40_clockconfig.c)). We * do still need to set up USBCLKCTRL to enable device and AHB clocking. */ - lpc17_putreg(LPC17_CLKCTRL_ENABLES, LPC17_USBDEV_CLKCTRL); + lpc17_40_putreg(LPC17_40_CLKCTRL_ENABLES, LPC17_40_USBDEV_CLKCTRL); /* Then wait for the clocks to be reported as "ON" */ do { - regval = lpc17_getreg(LPC17_USBDEV_CLKST); + regval = lpc17_40_getreg(LPC17_40_USBDEV_CLKST); } - while ((regval & LPC17_CLKCTRL_ENABLES) != LPC17_CLKCTRL_ENABLES); + while ((regval & LPC17_40_CLKCTRL_ENABLES) != LPC17_40_CLKCTRL_ENABLES); /* Step 3: Configure I/O pins */ usbdev_dumpgpio(); -#ifndef CONFIG_LPC17_USBDEV_NOVBUS - lpc17_configgpio(GPIO_USB_VBUS); /* VBUS status input */ +#ifndef CONFIG_LPC17_40_USBDEV_NOVBUS + lpc17_40_configgpio(GPIO_USB_VBUS); /* VBUS status input */ #endif - lpc17_configgpio(GPIO_USB_CONNECT); /* SoftConnect control signal */ -#ifndef CONFIG_LPC17_USBDEV_NOLED - lpc17_configgpio(GPIO_USB_UPLED); /* GoodLink LED control signal */ + lpc17_40_configgpio(GPIO_USB_CONNECT); /* SoftConnect control signal */ +#ifndef CONFIG_LPC17_40_USBDEV_NOLED + lpc17_40_configgpio(GPIO_USB_UPLED); /* GoodLink LED control signal */ #endif - lpc17_configgpio(GPIO_USB_DP); /* Positive differential data */ - lpc17_configgpio(GPIO_USB_DM); /* Negative differential data */ + lpc17_40_configgpio(GPIO_USB_DP); /* Positive differential data */ + lpc17_40_configgpio(GPIO_USB_DM); /* Negative differential data */ usbdev_dumpgpio(); /* Disable USB interrupts */ - regval = lpc17_getreg(LPC17_SYSCON_USBINTST); + regval = lpc17_40_getreg(LPC17_40_SYSCON_USBINTST); regval &= ~SYSCON_USBINTST_ENINTS; - lpc17_putreg(regval, LPC17_SYSCON_USBINTST); + lpc17_40_putreg(regval, LPC17_40_SYSCON_USBINTST); leave_critical_section(flags); /* Initialize the device state structure */ - memset(priv, 0, sizeof(struct lpc17_usbdev_s)); + memset(priv, 0, sizeof(struct lpc17_40_usbdev_s)); priv->usbdev.ops = &g_devops; - priv->usbdev.ep0 = &priv->eplist[LPC17_EP0_IN].ep; - priv->epavail = LPC17_EPALLSET; + priv->usbdev.ep0 = &priv->eplist[LPC17_40_EP0_IN].ep; + priv->epavail = LPC17_40_EPALLSET; /* Initialize the endpoint list */ - for (i = 0; i < LPC17_NPHYSENDPOINTS; i++) + for (i = 0; i < LPC17_40_NPHYSENDPOINTS; i++) { uint32_t bit = 1 << i; @@ -3277,55 +3277,55 @@ void up_usbinitialize(void) */ priv->eplist[i].epphy = i; - if (LPC17_EPPHYIN(i)) + if (LPC17_40_EPPHYIN(i)) { - priv->eplist[i].ep.eplog = LPC17_EPPHYIN2LOG(i); + priv->eplist[i].ep.eplog = LPC17_40_EPPHYIN2LOG(i); } else { - priv->eplist[i].ep.eplog = LPC17_EPPHYOUT2LOG(i); + priv->eplist[i].ep.eplog = LPC17_40_EPPHYOUT2LOG(i); } /* The maximum packet size may depend on the type of endpoint */ - if ((LPC17_EPCTRLSET & bit) != 0) + if ((LPC17_40_EPCTRLSET & bit) != 0) { - priv->eplist[i].ep.maxpacket = LPC17_EP0MAXPACKET; + priv->eplist[i].ep.maxpacket = LPC17_40_EP0MAXPACKET; } - else if ((LPC17_EPINTRSET & bit) != 0) + else if ((LPC17_40_EPINTRSET & bit) != 0) { - priv->eplist[i].ep.maxpacket = LPC17_INTRMAXPACKET; + priv->eplist[i].ep.maxpacket = LPC17_40_INTRMAXPACKET; } - else if ((LPC17_EPBULKSET & bit) != 0) + else if ((LPC17_40_EPBULKSET & bit) != 0) { - priv->eplist[i].ep.maxpacket = LPC17_BULKMAXPACKET; + priv->eplist[i].ep.maxpacket = LPC17_40_BULKMAXPACKET; } - else /* if ((LPC17_EPISOCSET & bit) != 0) */ + else /* if ((LPC17_40_EPISOCSET & bit) != 0) */ { - priv->eplist[i].ep.maxpacket = LPC17_ISOCMAXPACKET; + priv->eplist[i].ep.maxpacket = LPC17_40_ISOCMAXPACKET; } } /* Make sure all USB interrupts are disabled and cleared */ - lpc17_putreg(0, LPC17_USBDEV_INTEN); - lpc17_putreg(0xffffffff, LPC17_USBDEV_INTCLR); - lpc17_putreg(0, LPC17_USBDEV_INTPRI); + lpc17_40_putreg(0, LPC17_40_USBDEV_INTEN); + lpc17_40_putreg(0xffffffff, LPC17_40_USBDEV_INTCLR); + lpc17_40_putreg(0, LPC17_40_USBDEV_INTPRI); - lpc17_putreg(0, LPC17_USBDEV_EPINTEN); - lpc17_putreg(0xffffffff, LPC17_USBDEV_EPINTCLR); - lpc17_putreg(0, LPC17_USBDEV_EPINTPRI); + lpc17_40_putreg(0, LPC17_40_USBDEV_EPINTEN); + lpc17_40_putreg(0xffffffff, LPC17_40_USBDEV_EPINTCLR); + lpc17_40_putreg(0, LPC17_40_USBDEV_EPINTPRI); /* Interrupt only on ACKs */ - lpc17_usbcmd(CMD_USBDEV_SETMODE, 0); + lpc17_40_usbcmd(CMD_USBDEV_SETMODE, 0); /* Attach USB controller interrupt handler */ - if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt, NULL) != 0) + if (irq_attach(LPC17_40_IRQ_USB, lpc17_40_usbinterrupt, NULL) != 0) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_IRQREGISTRATION), - (uint16_t)LPC17_IRQ_USB); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_IRQREGISTRATION), + (uint16_t)LPC17_40_IRQ_USB); goto errout; } @@ -3335,27 +3335,27 @@ void up_usbinitialize(void) */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_SYSCON_USBINTST); + regval = lpc17_40_getreg(LPC17_40_SYSCON_USBINTST); regval |= SYSCON_USBINTST_ENINTS; - lpc17_putreg(regval, LPC17_SYSCON_USBINTST); + lpc17_40_putreg(regval, LPC17_40_SYSCON_USBINTST); leave_critical_section(flags); /* Disconnect device */ - lpc17_pullup(&priv->usbdev, false); + lpc17_40_pullup(&priv->usbdev, false); /* Enable EP0 for OUT (host-to-device) */ - lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | 0); - lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | 0); + lpc17_40_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | 0); + lpc17_40_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | 0); /* Reset/Re-initialize the USB hardware */ - lpc17_usbreset(priv); + lpc17_40_usbreset(priv); /* Init Device state structure */ - priv->devstatus = lpc17_usbcmd(CMD_USBDEV_GETSTATUS, 0); + priv->devstatus = lpc17_40_usbcmd(CMD_USBDEV_GETSTATUS, 0); return; errout: @@ -3368,7 +3368,7 @@ errout: void up_usbuninitialize(void) { - struct lpc17_usbdev_s *priv = &g_usbdev; + struct lpc17_40_usbdev_s *priv = &g_usbdev; uint32_t regval; irqstate_t flags; @@ -3376,27 +3376,27 @@ void up_usbuninitialize(void) if (priv->driver) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } /* Disconnect device */ flags = enter_critical_section(); - lpc17_pullup(&priv->usbdev, false); + lpc17_40_pullup(&priv->usbdev, false); priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + lpc17_40_usbcmd(CMD_USBDEV_CONFIG, 0); /* Disable and detach IRQs */ - up_disable_irq(LPC17_IRQ_USB); - irq_detach(LPC17_IRQ_USB); + up_disable_irq(LPC17_40_IRQ_USB); + irq_detach(LPC17_40_IRQ_USB); /* Turn off USB power and clocking */ - regval = lpc17_getreg(LPC17_SYSCON_PCONP); + regval = lpc17_40_getreg(LPC17_40_SYSCON_PCONP); regval &= ~SYSCON_PCONP_PCUSB; - lpc17_putreg(regval, LPC17_SYSCON_PCONP); + lpc17_40_putreg(regval, LPC17_40_SYSCON_PCONP); leave_critical_section(flags); } @@ -3419,13 +3419,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (g_usbdev.driver) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -3439,14 +3439,14 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &g_usbdev.usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_BINDFAILED), (uint16_t)-ret); g_usbdev.driver = NULL; } else { /* Enable USB controller interrupts */ - up_enable_irq(LPC17_IRQ_USB); + up_enable_irq(LPC17_40_IRQ_USB); } return ret; } @@ -3468,7 +3468,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_USB if (driver != g_usbdev.driver) { - usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(LPC17_40_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3479,7 +3479,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupts */ - up_disable_irq(LPC17_IRQ_USB); + up_disable_irq(LPC17_40_IRQ_USB); /* Unhook the driver */ diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c similarity index 74% rename from arch/arm/src/lpc17xx/lpc17_usbhost.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c index e8954bbc68e..b2350d63078 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_usbhost.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c * * Copyright (C) 2010-2012, 2014-2017 Gregory Nutt. All rights reserved. * Authors: Rafael Noronha @@ -66,10 +66,10 @@ #include "up_internal.h" #include "chip.h" -#include "hardware/lpc17_usb.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_gpio.h" -#include "lpc17_ohciram.h" +#include "hardware/lpc17_40_usb.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ohciram.h" /**************************************************************************** * Pre-processor Definitions @@ -82,16 +82,16 @@ * end-user I/O buffers reside in AHB SRAM. */ -#if LPC17_IOBUFFERS < 1 +#if LPC17_40_IOBUFFERS < 1 # warning "No IO buffers allocated" #endif -#ifndef CONFIG_LPC17_USBHOST_NPREALLOC -# define CONFIG_LPC17_USBHOST_NPREALLOC 8 +#ifndef CONFIG_LPC17_40_USBHOST_NPREALLOC +# define CONFIG_LPC17_40_USBHOST_NPREALLOC 8 #endif #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_LPC17_USBHOST_REGDEBUG +# undef CONFIG_LPC17_40_USBHOST_REGDEBUG #endif /* OHCI Setup ******************************************************************/ @@ -105,26 +105,26 @@ /* CLKCTRL enable bits */ -#define LPC17_CLKCTRL_ENABLES (USBOTG_CLK_HOSTCLK|USBOTG_CLK_PORTSELCLK|USBOTG_CLK_AHBCLK) +#define LPC17_40_CLKCTRL_ENABLES (USBOTG_CLK_HOSTCLK|USBOTG_CLK_PORTSELCLK|USBOTG_CLK_AHBCLK) /* Interrupt enable bits */ #ifdef CONFIG_DEBUG_USB -# define LPC17_DEBUG_INTS (OHCI_INT_SO|OHCI_INT_RD|OHCI_INT_UE|OHCI_INT_OC) +# define LPC17_40_DEBUG_INTS (OHCI_INT_SO|OHCI_INT_RD|OHCI_INT_UE|OHCI_INT_OC) #else -# define LPC17_DEBUG_INTS 0 +# define LPC17_40_DEBUG_INTS 0 #endif -#define LPC17_NORMAL_INTS (OHCI_INT_WDH|OHCI_INT_RHSC) -#define LPC17_ALL_INTS (LPC17_NORMAL_INTS|LPC17_DEBUG_INTS) +#define LPC17_40_NORMAL_INTS (OHCI_INT_WDH|OHCI_INT_RHSC) +#define LPC17_40_ALL_INTS (LPC17_40_NORMAL_INTS|LPC17_40_DEBUG_INTS) /* Dump GPIO registers */ -#ifdef CONFIG_LPC17_USBHOST_REGDEBUG +#ifdef CONFIG_LPC17_40_USBHOST_REGDEBUG # define usbhost_dumpgpio() \ do { \ - lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \ - lpc17_dumpgpio(GPIO_USB_UPLED, "LED P1:18; PPWR P1:19 PWRD P1:22 PVRCR P1:27"); \ + lpc17_40_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \ + lpc17_40_dumpgpio(GPIO_USB_UPLED, "LED P1:18; PPWR P1:19 PWRD P1:22 PVRCR P1:27"); \ } while (0); #else # define usbhost_dumpgpio() @@ -134,9 +134,9 @@ /* Helper definitions */ -#define HCCA ((struct ohci_hcca_s *)LPC17_HCCA_BASE) -#define TDTAIL ((struct lpc17_gtd_s *)LPC17_TDTAIL_ADDR) -#define EDCTRL ((struct lpc17_ed_s *)LPC17_EDCTRL_ADDR) +#define HCCA ((struct ohci_hcca_s *)LPC17_40_HCCA_BASE) +#define TDTAIL ((struct lpc17_40_gtd_s *)LPC17_40_TDTAIL_ADDR) +#define EDCTRL ((struct lpc17_40_ed_s *)LPC17_40_EDCTRL_ADDR) /* Periodic intervals 2, 4, 8, 16,and 32 supported */ @@ -155,11 +155,11 @@ /* This structure retains the state of the USB host controller */ -struct lpc17_usbhost_s +struct lpc17_40_usbhost_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbhost_s - * to structlpc17_usbhost_s. + * to structlpc17_40_usbhost_s. */ struct usbhost_driver_s drvr; @@ -191,7 +191,7 @@ struct lpc17_usbhost_s /* This structure describes one asynchronous transfer */ -struct lpc17_xfrinfo_s +struct lpc17_40_xfrinfo_s { volatile bool wdhwait; /* Thread is waiting for WDH interrupt */ volatile uint8_t tdstatus; /* TD control status bits from last Writeback Done Head event */ @@ -200,7 +200,7 @@ struct lpc17_xfrinfo_s uint16_t xfrd; /* Number of bytes transferred */ #ifdef CONFIG_USBHOST_ASYNCH -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Remember the allocated DMA buffer address so that it can be freed when * the transfer completes. */ @@ -219,11 +219,11 @@ struct lpc17_xfrinfo_s /* The OCHI expects the size of an endpoint descriptor to be 16 bytes. * However, the size allocated for an endpoint descriptor is 32 bytes in - * lpc17_ohciram.h. This extra 16-bytes is used by the OHCI host driver in + * lpc17_40_ohciram.h. This extra 16-bytes is used by the OHCI host driver in * order to maintain additional endpoint-specific data. */ -struct lpc17_ed_s +struct lpc17_40_ed_s { /* Hardware specific fields */ @@ -237,16 +237,16 @@ struct lpc17_ed_s /* Unused bytes may follow, depending on the size of sem_t */ /* Pointer to structure that manages asynchronous transfers on this pipe */ - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_xfrinfo_s *xfrinfo; }; /* The OCHI expects the size of an transfer descriptor to be 16 bytes. * However, the size allocated for an endpoint descriptor is 32 bytes in - * lpc17_ohciram.h. This extra 16-bytes is used by the OHCI host driver in + * lpc17_40_ohciram.h. This extra 16-bytes is used by the OHCI host driver in * order to maintain additional endpoint-specific data. */ -struct lpc17_gtd_s +struct lpc17_40_gtd_s { /* Hardware specific fields */ @@ -254,15 +254,15 @@ struct lpc17_gtd_s /* Software specific fields */ - struct lpc17_ed_s *ed; /* Pointer to parent ED */ + struct lpc17_40_ed_s *ed; /* Pointer to parent ED */ uint8_t pad[12]; }; /* The following is used to manage lists of free EDs, TDs, and TD buffers */ -struct lpc17_list_s +struct lpc17_40_list_s { - struct lpc17_list_s *flink; /* Link to next buffer in the list */ + struct lpc17_40_list_s *flink; /* Link to next buffer in the list */ /* Variable length buffer data follows */ }; @@ -272,143 +272,143 @@ struct lpc17_list_s /* Register operations ********************************************************/ -#ifdef CONFIG_LPC17_USBHOST_REGDEBUG -static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t lpc17_getreg(uint32_t addr); -static void lpc17_putreg(uint32_t val, uint32_t addr); +#ifdef CONFIG_LPC17_40_USBHOST_REGDEBUG +static void lpc17_40_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t lpc17_40_getreg(uint32_t addr); +static void lpc17_40_putreg(uint32_t val, uint32_t addr); #else -# define lpc17_getreg(addr) getreg32(addr) -# define lpc17_putreg(val,addr) putreg32(val,addr) +# define lpc17_40_getreg(addr) getreg32(addr) +# define lpc17_40_putreg(val,addr) putreg32(val,addr) #endif /* Semaphores ******************************************************************/ -static void lpc17_takesem(sem_t *sem); -#define lpc17_givesem(s) nxsem_post(s); +static void lpc17_40_takesem(sem_t *sem); +#define lpc17_40_givesem(s) nxsem_post(s); /* Byte stream access helper functions *****************************************/ -static inline uint16_t lpc17_getle16(const uint8_t *val); +static inline uint16_t lpc17_40_getle16(const uint8_t *val); #if 0 /* Not used */ -static void lpc17_putle16(uint8_t *dest, uint16_t val); +static void lpc17_40_putle16(uint8_t *dest, uint16_t val); #endif /* OHCI memory pool helper functions *******************************************/ -static inline void lpc17_edfree(struct lpc17_ed_s *ed); -static struct lpc17_gtd_s *lpc17_tdalloc(void); -static void lpc17_tdfree(struct lpc17_gtd_s *buffer); -static uint8_t *lpc17_tballoc(void); -static void lpc17_tbfree(uint8_t *buffer); -#if LPC17_IOBUFFERS > 0 -static uint8_t *lpc17_allocio(void); -static void lpc17_freeio(uint8_t *buffer); +static inline void lpc17_40_edfree(struct lpc17_40_ed_s *ed); +static struct lpc17_40_gtd_s *lpc17_40_tdalloc(void); +static void lpc17_40_tdfree(struct lpc17_40_gtd_s *buffer); +static uint8_t *lpc17_40_tballoc(void); +static void lpc17_40_tbfree(uint8_t *buffer); +#if LPC17_40_IOBUFFERS > 0 +static uint8_t *lpc17_40_allocio(void); +static void lpc17_40_freeio(uint8_t *buffer); #endif -static struct lpc17_xfrinfo_s *lpc17_alloc_xfrinfo(void); -static void lpc17_free_xfrinfo(struct lpc17_xfrinfo_s *xfrinfo); +static struct lpc17_40_xfrinfo_s *lpc17_40_alloc_xfrinfo(void); +static void lpc17_40_free_xfrinfo(struct lpc17_40_xfrinfo_s *xfrinfo); /* ED list helper functions ****************************************************/ -static inline int lpc17_addctrled(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); -static inline int lpc17_remctrled(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); +static inline int lpc17_40_addctrled(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); +static inline int lpc17_40_remctrled(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); -static inline int lpc17_addbulked(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); -static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); +static inline int lpc17_40_addbulked(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); +static inline int lpc17_40_rembulked(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); #if !defined(CONFIG_USBHOST_INT_DISABLE) || !defined(CONFIG_USBHOST_ISOC_DISABLE) -static unsigned int lpc17_getinterval(uint8_t interval); -static void lpc17_setinttab(uint32_t value, unsigned int interval, unsigned int offset); +static unsigned int lpc17_40_getinterval(uint8_t interval); +static void lpc17_40_setinttab(uint32_t value, unsigned int interval, unsigned int offset); #endif -static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, +static inline int lpc17_40_addinted(struct lpc17_40_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, - struct lpc17_ed_s *ed); -static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); + struct lpc17_40_ed_s *ed); +static inline int lpc17_40_reminted(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); -static inline int lpc17_addisoced(struct lpc17_usbhost_s *priv, +static inline int lpc17_40_addisoced(struct lpc17_40_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, - struct lpc17_ed_s *ed); -static inline int lpc17_remisoced(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); + struct lpc17_40_ed_s *ed); +static inline int lpc17_40_remisoced(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); /* Descriptor helper functions *************************************************/ -static int lpc17_enqueuetd(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint32_t dirpid, +static int lpc17_40_enqueuetd(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint32_t dirpid, uint32_t toggle, volatile uint8_t *buffer, size_t buflen); -static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, +static int lpc17_40_ctrltd(struct lpc17_40_usbhost_s *priv, struct lpc17_40_ed_s *ed, uint32_t dirpid, uint8_t *buffer, size_t buflen); /* Interrupt handling **********************************************************/ -static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg); +static int lpc17_40_usbinterrupt(int irq, void *context, FAR void *arg); /* USB host controller operations **********************************************/ -static int lpc17_wait(struct usbhost_connection_s *conn, +static int lpc17_40_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport); -static int lpc17_rh_enumerate(struct usbhost_connection_s *conn, +static int lpc17_40_rh_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int lpc17_enumerate(struct usbhost_connection_s *conn, +static int lpc17_40_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int lpc17_ep0configure(struct usbhost_driver_s *drvr, +static int lpc17_40_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize); -static int lpc17_epalloc(struct usbhost_driver_s *drvr, +static int lpc17_40_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int lpc17_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -static int lpc17_alloc(struct usbhost_driver_s *drvr, +static int lpc17_40_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int lpc17_40_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen); -static int lpc17_free(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int lpc17_ioalloc(struct usbhost_driver_s *drvr, +static int lpc17_40_free(struct usbhost_driver_s *drvr, uint8_t *buffer); +static int lpc17_40_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen); -static int lpc17_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, +static int lpc17_40_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer); +static int lpc17_40_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer); -static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, +static int lpc17_40_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer); -static int lpc17_transfer_common(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint8_t *buffer, +static int lpc17_40_transfer_common(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint8_t *buffer, size_t buflen); -#if LPC17_IOBUFFERS > 0 -static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint8_t *userbuffer, +#if LPC17_40_IOBUFFERS > 0 +static int lpc17_40_dma_alloc(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint8_t *userbuffer, size_t buflen, uint8_t **alloc); -static void lpc17_dma_free(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint8_t *userbuffer, +static void lpc17_40_dma_free(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint8_t *userbuffer, size_t buflen, uint8_t *alloc); #endif -static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static ssize_t lpc17_40_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed); -static int lpc17_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static void lpc17_40_asynch_completion(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed); +static int lpc17_40_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, FAR uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, FAR void *arg); #endif -static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int lpc17_40_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); #ifdef CONFIG_USBHOST_HUB -static int lpc17_connect(FAR struct usbhost_driver_s *drvr, +static int lpc17_40_connect(FAR struct usbhost_driver_s *drvr, FAR struct usbhost_hubport_s *hport, bool connected); #endif -static void lpc17_disconnect(struct usbhost_driver_s *drvr, +static void lpc17_40_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport); /* Initialization **************************************************************/ -static inline void lpc17_ep0init(struct lpc17_usbhost_s *priv); +static inline void lpc17_40_ep0init(struct lpc17_40_usbhost_s *priv); /**************************************************************************** * Private Data @@ -419,29 +419,29 @@ static inline void lpc17_ep0init(struct lpc17_usbhost_s *priv); * instance. */ -static struct lpc17_usbhost_s g_usbhost; +static struct lpc17_40_usbhost_s g_usbhost; /* This is the connection/enumeration interface */ static struct usbhost_connection_s g_usbconn = { - .wait = lpc17_wait, - .enumerate = lpc17_enumerate, + .wait = lpc17_40_wait, + .enumerate = lpc17_40_enumerate, }; /* This is a free list of EDs and TD buffers */ -static struct lpc17_list_s *g_edfree; /* List of unused EDs */ -static struct lpc17_list_s *g_tdfree; /* List of unused TDs */ -static struct lpc17_list_s *g_tbfree; /* List of unused transfer buffers */ -#if LPC17_IOBUFFERS > 0 -static struct lpc17_list_s *g_iofree; /* List of unused I/O buffers */ +static struct lpc17_40_list_s *g_edfree; /* List of unused EDs */ +static struct lpc17_40_list_s *g_tdfree; /* List of unused TDs */ +static struct lpc17_40_list_s *g_tbfree; /* List of unused transfer buffers */ +#if LPC17_40_IOBUFFERS > 0 +static struct lpc17_40_list_s *g_iofree; /* List of unused I/O buffers */ #endif /* Pool and freelist of transfer structures */ -static struct lpc17_list_s *g_xfrfree; -static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC]; +static struct lpc17_40_list_s *g_xfrfree; +static struct lpc17_40_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_40_USBHOST_NPREALLOC]; /**************************************************************************** * Public Data @@ -452,30 +452,30 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC]; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_printreg + * Name: lpc17_40_printreg * * Description: - * Print the contents of an LPC17xx register operation + * Print the contents of an LPC17xx/LPC40xx register operation * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBHOST_REGDEBUG -static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_LPC17_40_USBHOST_REGDEBUG +static void lpc17_40_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif /**************************************************************************** - * Name: lpc17_checkreg + * Name: lpc17_40_checkreg * * Description: - * Get the contents of an LPC17xx register + * Get the contents of an LPC17xx/LPC40xx register * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBHOST_REGDEBUG -static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_LPC17_40_USBHOST_REGDEBUG +static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -506,7 +506,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* Yes.. Just one */ - lpc17_printreg(prevaddr, preval, prevwrite); + lpc17_40_printreg(prevaddr, preval, prevwrite); } else { @@ -525,21 +525,21 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) /* Show the new regisgter access */ - lpc17_printreg(addr, val, iswrite); + lpc17_40_printreg(addr, val, iswrite); } } #endif /**************************************************************************** - * Name: lpc17_getreg + * Name: lpc17_40_getreg * * Description: - * Get the contents of an LPC17xx register + * Get the contents of an LPC17xx/LPC40xx register * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBHOST_REGDEBUG -static uint32_t lpc17_getreg(uint32_t addr) +#ifdef CONFIG_LPC17_40_USBHOST_REGDEBUG +static uint32_t lpc17_40_getreg(uint32_t addr) { /* Read the value from the register */ @@ -547,25 +547,25 @@ static uint32_t lpc17_getreg(uint32_t addr) /* Check if we need to print this value */ - lpc17_checkreg(addr, val, false); + lpc17_40_checkreg(addr, val, false); return val; } #endif /**************************************************************************** - * Name: lpc17_putreg + * Name: lpc17_40_putreg * * Description: - * Set the contents of an LPC17xx register to a value + * Set the contents of an LPC17xx/LPC40xx register to a value * ****************************************************************************/ -#ifdef CONFIG_LPC17_USBHOST_REGDEBUG -static void lpc17_putreg(uint32_t val, uint32_t addr) +#ifdef CONFIG_LPC17_40_USBHOST_REGDEBUG +static void lpc17_40_putreg(uint32_t val, uint32_t addr) { /* Check if we need to print this value */ - lpc17_checkreg(addr, val, true); + lpc17_40_checkreg(addr, val, true); /* Write the value */ @@ -574,7 +574,7 @@ static void lpc17_putreg(uint32_t val, uint32_t addr) #endif /**************************************************************************** - * Name: lpc17_takesem + * Name: lpc17_40_takesem * * Description: * This is just a wrapper to handle the annoying behavior of semaphore @@ -582,7 +582,7 @@ static void lpc17_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static void lpc17_takesem(sem_t *sem) +static void lpc17_40_takesem(sem_t *sem) { int ret; @@ -602,20 +602,20 @@ static void lpc17_takesem(sem_t *sem) } /**************************************************************************** - * Name: lpc17_getle16 + * Name: lpc17_40_getle16 * * Description: * Get a (possibly unaligned) 16-bit little endian value. * ****************************************************************************/ -static inline uint16_t lpc17_getle16(const uint8_t *val) +static inline uint16_t lpc17_40_getle16(const uint8_t *val) { return (uint16_t)val[1] << 8 | (uint16_t)val[0]; } /**************************************************************************** - * Name: lpc17_putle16 + * Name: lpc17_40_putle16 * * Description: * Put a (possibly unaligned) 16-bit little endian value. @@ -623,7 +623,7 @@ static inline uint16_t lpc17_getle16(const uint8_t *val) ****************************************************************************/ #if 0 /* Not used */ -static void lpc17_putle16(uint8_t *dest, uint16_t val) +static void lpc17_40_putle16(uint8_t *dest, uint16_t val) { dest[0] = val & 0xff; /* Little endian means LS byte first in byte stream */ dest[1] = val >> 8; @@ -631,16 +631,16 @@ static void lpc17_putle16(uint8_t *dest, uint16_t val) #endif /**************************************************************************** - * Name: lpc17_edfree + * Name: lpc17_40_edfree * * Description: * Return an endpoint descriptor to the free list * ****************************************************************************/ -static inline void lpc17_edfree(struct lpc17_ed_s *ed) +static inline void lpc17_40_edfree(struct lpc17_40_ed_s *ed) { - struct lpc17_list_s *entry = (struct lpc17_list_s *)ed; + struct lpc17_40_list_s *entry = (struct lpc17_40_list_s *)ed; /* Put the ED back into the free list */ @@ -649,7 +649,7 @@ static inline void lpc17_edfree(struct lpc17_ed_s *ed) } /**************************************************************************** - * Name: lpc17_tdalloc + * Name: lpc17_40_tdalloc * * Description: * Allocate an transfer descriptor from the free list @@ -662,20 +662,20 @@ static inline void lpc17_edfree(struct lpc17_ed_s *ed) * ****************************************************************************/ -static struct lpc17_gtd_s *lpc17_tdalloc(void) +static struct lpc17_40_gtd_s *lpc17_40_tdalloc(void) { - struct lpc17_gtd_s *ret; + struct lpc17_40_gtd_s *ret; irqstate_t flags; - /* Disable interrupts momentarily so that lpc17_tdfree is not called from the + /* Disable interrupts momentarily so that lpc17_40_tdfree is not called from the * interrupt handler. */ flags = enter_critical_section(); - ret = (struct lpc17_gtd_s *)g_tdfree; + ret = (struct lpc17_40_gtd_s *)g_tdfree; if (ret) { - g_tdfree = ((struct lpc17_list_s *)ret)->flink; + g_tdfree = ((struct lpc17_40_list_s *)ret)->flink; } leave_critical_section(flags); @@ -683,7 +683,7 @@ static struct lpc17_gtd_s *lpc17_tdalloc(void) } /**************************************************************************** - * Name: lpc17_tdfree + * Name: lpc17_40_tdfree * * Description: * Return an transfer descriptor to the free list @@ -694,9 +694,9 @@ static struct lpc17_gtd_s *lpc17_tdalloc(void) * ****************************************************************************/ -static void lpc17_tdfree(struct lpc17_gtd_s *td) +static void lpc17_40_tdfree(struct lpc17_40_gtd_s *td) { - struct lpc17_list_s *tdfree = (struct lpc17_list_s *)td; + struct lpc17_40_list_s *tdfree = (struct lpc17_40_list_s *)td; /* This should not happen but just to be safe, don't free the common, pre- * allocated tail TD. @@ -710,7 +710,7 @@ static void lpc17_tdfree(struct lpc17_gtd_s *td) } /**************************************************************************** - * Name: lpc17_tballoc + * Name: lpc17_40_tballoc * * Description: * Allocate an request/descriptor transfer buffer from the free list @@ -721,27 +721,27 @@ static void lpc17_tdfree(struct lpc17_gtd_s *td) * ****************************************************************************/ -static uint8_t *lpc17_tballoc(void) +static uint8_t *lpc17_40_tballoc(void) { uint8_t *ret = (uint8_t *)g_tbfree; if (ret) { - g_tbfree = ((struct lpc17_list_s *)ret)->flink; + g_tbfree = ((struct lpc17_40_list_s *)ret)->flink; } return ret; } /**************************************************************************** - * Name: lpc17_tbfree + * Name: lpc17_40_tbfree * * Description: * Return an request/descriptor transfer buffer to the free list * ****************************************************************************/ -static void lpc17_tbfree(uint8_t *buffer) +static void lpc17_40_tbfree(uint8_t *buffer) { - struct lpc17_list_s *tbfree = (struct lpc17_list_s *)buffer; + struct lpc17_40_list_s *tbfree = (struct lpc17_40_list_s *)buffer; if (tbfree) { @@ -751,7 +751,7 @@ static void lpc17_tbfree(uint8_t *buffer) } /**************************************************************************** - * Name: lpc17_allocio + * Name: lpc17_40_allocio * * Description: * Allocate an IO buffer from the free list @@ -762,19 +762,19 @@ static void lpc17_tbfree(uint8_t *buffer) * ****************************************************************************/ -#if LPC17_IOBUFFERS > 0 -static uint8_t *lpc17_allocio(void) +#if LPC17_40_IOBUFFERS > 0 +static uint8_t *lpc17_40_allocio(void) { uint8_t *ret; irqstate_t flags; - /* lpc17_freeio() may be called from the interrupt level */ + /* lpc17_40_freeio() may be called from the interrupt level */ flags = enter_critical_section(); ret = (uint8_t *)g_iofree; if (ret) { - g_iofree = ((struct lpc17_list_s *)ret)->flink; + g_iofree = ((struct lpc17_40_list_s *)ret)->flink; } leave_critical_section(flags); @@ -783,23 +783,23 @@ static uint8_t *lpc17_allocio(void) #endif /**************************************************************************** - * Name: lpc17_freeio + * Name: lpc17_40_freeio * * Description: * Return an TD buffer to the free list * ****************************************************************************/ -#if LPC17_IOBUFFERS > 0 -static void lpc17_freeio(uint8_t *buffer) +#if LPC17_40_IOBUFFERS > 0 +static void lpc17_40_freeio(uint8_t *buffer) { - struct lpc17_list_s *iofree; + struct lpc17_40_list_s *iofree; irqstate_t flags; /* Could be called from the interrupt level */ flags = enter_critical_section(); - iofree = (struct lpc17_list_s *)buffer; + iofree = (struct lpc17_40_list_s *)buffer; iofree->flink = g_iofree; g_iofree = iofree; leave_critical_section(flags); @@ -807,7 +807,7 @@ static void lpc17_freeio(uint8_t *buffer) #endif /**************************************************************************** - * Name: lpc17_alloc_xfrinfo + * Name: lpc17_40_alloc_xfrinfo * * Description: * Allocate an asynchronous data structure from the free list @@ -818,18 +818,18 @@ static void lpc17_freeio(uint8_t *buffer) * ****************************************************************************/ -static struct lpc17_xfrinfo_s *lpc17_alloc_xfrinfo(void) +static struct lpc17_40_xfrinfo_s *lpc17_40_alloc_xfrinfo(void) { - struct lpc17_xfrinfo_s *ret; + struct lpc17_40_xfrinfo_s *ret; irqstate_t flags; - /* lpc17_free_xfrinfo() may be called from the interrupt level */ + /* lpc17_40_free_xfrinfo() may be called from the interrupt level */ flags = enter_critical_section(); - ret = (struct lpc17_xfrinfo_s *)g_xfrfree; + ret = (struct lpc17_40_xfrinfo_s *)g_xfrfree; if (ret) { - g_xfrfree = ((struct lpc17_list_s *)ret)->flink; + g_xfrfree = ((struct lpc17_40_list_s *)ret)->flink; } leave_critical_section(flags); @@ -837,37 +837,37 @@ static struct lpc17_xfrinfo_s *lpc17_alloc_xfrinfo(void) } /**************************************************************************** - * Name: lpc17_freeio + * Name: lpc17_40_freeio * * Description: * Return an TD buffer to the free list * ****************************************************************************/ -static void lpc17_free_xfrinfo(struct lpc17_xfrinfo_s *xfrinfo) +static void lpc17_40_free_xfrinfo(struct lpc17_40_xfrinfo_s *xfrinfo) { - struct lpc17_list_s *node; + struct lpc17_40_list_s *node; irqstate_t flags; /* Could be called from the interrupt level */ flags = enter_critical_section(); - node = (struct lpc17_list_s *)xfrinfo; + node = (struct lpc17_40_list_s *)xfrinfo; node->flink = g_xfrfree; g_xfrfree = node; leave_critical_section(flags); } /**************************************************************************** - * Name: lpc17_addctrled + * Name: lpc17_40_addctrled * * Description: * Helper function to add an ED to the control list. * ****************************************************************************/ -static inline int lpc17_addctrled(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static inline int lpc17_40_addctrled(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { irqstate_t flags; uint32_t regval; @@ -875,57 +875,57 @@ static inline int lpc17_addctrled(struct lpc17_usbhost_s *priv, /* Disable control list processing while we modify the list */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_CLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Add the new bulk ED to the head of the bulk list */ - ed->hw.nexted = lpc17_getreg(LPC17_USBHOST_CTRLHEADED); - lpc17_putreg((uint32_t)ed, LPC17_USBHOST_CTRLHEADED); + ed->hw.nexted = lpc17_40_getreg(LPC17_40_USBHOST_CTRLHEADED); + lpc17_40_putreg((uint32_t)ed, LPC17_40_USBHOST_CTRLHEADED); /* Re-enable control list processing. */ - lpc17_putreg(0, LPC17_USBHOST_CTRLED); + lpc17_40_putreg(0, LPC17_40_USBHOST_CTRLED); - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval |= OHCI_CTRL_CLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: lpc17_remctrled + * Name: lpc17_40_remctrled * * Description: * Helper function remove an ED from the control list. * ****************************************************************************/ -static inline int lpc17_remctrled(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static inline int lpc17_40_remctrled(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { - struct lpc17_ed_s *curr; - struct lpc17_ed_s *prev; - struct lpc17_ed_s *head; + struct lpc17_40_ed_s *curr; + struct lpc17_40_ed_s *prev; + struct lpc17_40_ed_s *head; irqstate_t flags; uint32_t regval; /* Disable control list processing while we modify the list */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_CLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Find the ED in the control list. */ - head = (struct lpc17_ed_s *)lpc17_getreg(LPC17_USBHOST_CTRLHEADED); + head = (struct lpc17_40_ed_s *)lpc17_40_getreg(LPC17_40_USBHOST_CTRLHEADED); for (prev = NULL, curr = head; curr && curr != ed; - prev = curr, curr = (struct lpc17_ed_s *)curr->hw.nexted); + prev = curr, curr = (struct lpc17_40_ed_s *)curr->hw.nexted); /* It would be a bug if we do not find the ED in the control list. */ @@ -941,8 +941,8 @@ static inline int lpc17_remctrled(struct lpc17_usbhost_s *priv, { /* Yes... set the head of the control list to skip over this ED */ - head = (struct lpc17_ed_s *)ed->hw.nexted; - lpc17_putreg((uint32_t)head, LPC17_USBHOST_CTRLHEADED); + head = (struct lpc17_40_ed_s *)ed->hw.nexted; + lpc17_40_putreg((uint32_t)head, LPC17_40_USBHOST_CTRLHEADED); } else { @@ -964,14 +964,14 @@ static inline int lpc17_remctrled(struct lpc17_usbhost_s *priv, * after removing the ED node. */ - lpc17_putreg(0, LPC17_USBHOST_CTRLED); - if (lpc17_getreg(LPC17_USBHOST_CTRLHEADED) != 0) + lpc17_40_putreg(0, LPC17_40_USBHOST_CTRLED); + if (lpc17_40_getreg(LPC17_40_USBHOST_CTRLHEADED) != 0) { /* If the control list is now empty, then disable it */ - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_CLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); } leave_critical_section(flags); @@ -979,15 +979,15 @@ static inline int lpc17_remctrled(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_addbulked + * Name: lpc17_40_addbulked * * Description: * Helper function to add an ED to the bulk list. * ****************************************************************************/ -static inline int lpc17_addbulked(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static inline int lpc17_40_addbulked(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { #ifndef CONFIG_USBHOST_BULK_DISABLE irqstate_t flags; @@ -996,22 +996,22 @@ static inline int lpc17_addbulked(struct lpc17_usbhost_s *priv, /* Disable bulk list processing while we modify the list */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_BLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Add the new bulk ED to the head of the bulk list */ - ed->hw.nexted = lpc17_getreg(LPC17_USBHOST_BULKHEADED); - lpc17_putreg((uint32_t)ed, LPC17_USBHOST_BULKHEADED); + ed->hw.nexted = lpc17_40_getreg(LPC17_40_USBHOST_BULKHEADED); + lpc17_40_putreg((uint32_t)ed, LPC17_40_USBHOST_BULKHEADED); /* Re-enable bulk list processing. */ - lpc17_putreg(0, LPC17_USBHOST_BULKED); + lpc17_40_putreg(0, LPC17_40_USBHOST_BULKED); - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval |= OHCI_CTRL_BLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); leave_critical_section(flags); return OK; @@ -1021,36 +1021,36 @@ static inline int lpc17_addbulked(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_rembulked + * Name: lpc17_40_rembulked * * Description: * Helper function remove an ED from the bulk list. * ****************************************************************************/ -static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static inline int lpc17_40_rembulked(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { #ifndef CONFIG_USBHOST_BULK_DISABLE - struct lpc17_ed_s *curr; - struct lpc17_ed_s *prev; - struct lpc17_ed_s *head; + struct lpc17_40_ed_s *curr; + struct lpc17_40_ed_s *prev; + struct lpc17_40_ed_s *head; irqstate_t flags; uint32_t regval; /* Disable bulk list processing while we modify the list */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_BLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Find the ED in the bulk list. */ - head = (struct lpc17_ed_s *)lpc17_getreg(LPC17_USBHOST_BULKHEADED); + head = (struct lpc17_40_ed_s *)lpc17_40_getreg(LPC17_40_USBHOST_BULKHEADED); for (prev = NULL, curr = head; curr && curr != ed; - prev = curr, curr = (struct lpc17_ed_s *)curr->hw.nexted); + prev = curr, curr = (struct lpc17_40_ed_s *)curr->hw.nexted); /* It would be a bug if we do not find the ED in the bulk list. */ @@ -1066,8 +1066,8 @@ static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, { /* Yes... set the head of the bulk list to skip over this ED */ - head = (struct lpc17_ed_s *)ed->hw.nexted; - lpc17_putreg((uint32_t)head, LPC17_USBHOST_BULKHEADED); + head = (struct lpc17_40_ed_s *)ed->hw.nexted; + lpc17_40_putreg((uint32_t)head, LPC17_40_USBHOST_BULKHEADED); } else { @@ -1083,14 +1083,14 @@ static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, * after removing the ED node. */ - lpc17_putreg(0, LPC17_USBHOST_BULKED); - if (lpc17_getreg(LPC17_USBHOST_BULKHEADED) != 0) + lpc17_40_putreg(0, LPC17_40_USBHOST_BULKED); + if (lpc17_40_getreg(LPC17_40_USBHOST_BULKHEADED) != 0) { /* If the bulk list is now empty, then disable it */ - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval |= OHCI_CTRL_BLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); } leave_critical_section(flags); @@ -1101,7 +1101,7 @@ static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_getinterval + * Name: lpc17_40_getinterval * * Description: * Convert the endpoint polling interval into a HCCA table increment @@ -1109,7 +1109,7 @@ static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, ****************************************************************************/ #if !defined(CONFIG_USBHOST_INT_DISABLE) || !defined(CONFIG_USBHOST_ISOC_DISABLE) -static unsigned int lpc17_getinterval(uint8_t interval) +static unsigned int lpc17_40_getinterval(uint8_t interval) { /* The bInterval field of the endpoint descriptor contains the polling interval * for interrupt and isochronous endpoints. For other types of endpoint, this @@ -1140,7 +1140,7 @@ static unsigned int lpc17_getinterval(uint8_t interval) #endif /**************************************************************************** - * Name: lpc17_setinttab + * Name: lpc17_40_setinttab * * Description: * Set the interrupt table to the selected value using the provided interval @@ -1149,7 +1149,7 @@ static unsigned int lpc17_getinterval(uint8_t interval) ****************************************************************************/ #if !defined(CONFIG_USBHOST_INT_DISABLE) || !defined(CONFIG_USBHOST_ISOC_DISABLE) -static void lpc17_setinttab(uint32_t value, unsigned int interval, unsigned int offset) +static void lpc17_40_setinttab(uint32_t value, unsigned int interval, unsigned int offset) { unsigned int i; for (i = offset; i < HCCA_INTTBL_WSIZE; i += interval) @@ -1160,7 +1160,7 @@ static void lpc17_setinttab(uint32_t value, unsigned int interval, unsigned int #endif /**************************************************************************** - * Name: lpc17_addinted + * Name: lpc17_40_addinted * * Description: * Helper function to add an ED to the HCCA interrupt table. @@ -1179,9 +1179,9 @@ static void lpc17_setinttab(uint32_t value, unsigned int interval, unsigned int * ****************************************************************************/ -static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, +static inline int lpc17_40_addinted(struct lpc17_40_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, - struct lpc17_ed_s *ed) + struct lpc17_40_ed_s *ed) { #ifndef CONFIG_USBHOST_INT_DISABLE unsigned int interval; @@ -1193,15 +1193,15 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, * at the next SOF... need to check. */ - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_PLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Get the quantized interval value associated with this ED and save it * in the ED. */ - interval = lpc17_getinterval(epdesc->interval); + interval = lpc17_40_getinterval(epdesc->interval); ed->interval = interval; uinfo("interval: %d->%d\n", epdesc->interval, interval); @@ -1246,7 +1246,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, /* Clear all current entries in the interrupt table for this direction */ - lpc17_setinttab(0, 2, offset); + lpc17_40_setinttab(0, 2, offset); /* Add the new ED before the old head of the periodic ED list and set the * new ED as the head ED in all of the appropriate entries of the HCCA @@ -1254,14 +1254,14 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, */ ed->hw.nexted = head; - lpc17_setinttab((uint32_t)ed, interval, offset); + lpc17_40_setinttab((uint32_t)ed, interval, offset); uinfo("head: %08x next: %08x\n", ed, head); /* Re-enabled periodic list processing */ - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval |= OHCI_CTRL_PLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); return OK; #else return -ENOSYS; @@ -1269,7 +1269,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_reminted + * Name: lpc17_40_reminted * * Description: * Helper function to remove an ED from the HCCA interrupt table. @@ -1288,13 +1288,13 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, * ****************************************************************************/ -static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static inline int lpc17_40_reminted(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { #ifndef CONFIG_USBHOST_INT_DISABLE - struct lpc17_ed_s *head; - struct lpc17_ed_s *curr; - struct lpc17_ed_s *prev; + struct lpc17_40_ed_s *head; + struct lpc17_40_ed_s *curr; + struct lpc17_40_ed_s *prev; unsigned int interval; unsigned int offset; uint32_t regval; @@ -1303,9 +1303,9 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, * at the next SOF... need to check. */ - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_PLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Get the offset associated with the ED direction. IN EDs get the even * entries, OUT EDs get the odd entries. @@ -1324,7 +1324,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, * entry is always guaranteed to contain the common ED list head. */ - head = (struct lpc17_ed_s *)HCCA->inttbl[offset]; + head = (struct lpc17_40_ed_s *)HCCA->inttbl[offset]; uinfo("ed: %08x head: %08x next: %08x offset: %d\n", ed, head, head ? head->hw.nexted : 0, offset); @@ -1332,7 +1332,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, for (curr = head, prev = NULL; curr && curr != ed; - prev = curr, curr = (struct lpc17_ed_s *)curr->hw.nexted); + prev = curr, curr = (struct lpc17_40_ed_s *)curr->hw.nexted); /* Hmmm.. It would be a bug if we do not find the ED in the bulk list. */ @@ -1341,7 +1341,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, { /* Clear all current entries in the interrupt table for this direction */ - lpc17_setinttab(0, 2, offset); + lpc17_40_setinttab(0, 2, offset); /* Remove the ED from the list.. Is this ED the first on in the list? */ @@ -1349,7 +1349,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, { /* Yes... set the head of the bulk list to skip over this ED */ - head = (struct lpc17_ed_s *)ed->hw.nexted; + head = (struct lpc17_40_ed_s *)ed->hw.nexted; } else { @@ -1366,7 +1366,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, /* Calculate the new minimum interval for this list */ interval = MAX_PERINTERVAL; - for (curr = head; curr; curr = (struct lpc17_ed_s *)curr->hw.nexted) + for (curr = head; curr; curr = (struct lpc17_40_ed_s *)curr->hw.nexted) { if (curr->interval < interval) { @@ -1391,16 +1391,16 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, * table (head might be NULL). */ - lpc17_setinttab((uint32_t)head, interval, offset); + lpc17_40_setinttab((uint32_t)head, interval, offset); } /* Re-enabled periodic list processing */ if (head != NULL) { - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval |= OHCI_CTRL_PLE; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); } return OK; @@ -1410,16 +1410,16 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_addisoced + * Name: lpc17_40_addisoced * * Description: * Helper functions to add an ED to the periodic table. * ****************************************************************************/ -static inline int lpc17_addisoced(struct lpc17_usbhost_s *priv, +static inline int lpc17_40_addisoced(struct lpc17_40_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, - struct lpc17_ed_s *ed) + struct lpc17_40_ed_s *ed) { #ifndef CONFIG_USBHOST_ISOC_DISABLE # warning "Isochronous endpoints not yet supported" @@ -1428,15 +1428,15 @@ static inline int lpc17_addisoced(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_remisoced + * Name: lpc17_40_remisoced * * Description: * Helper functions to remove an ED from the periodic table. * ****************************************************************************/ -static inline int lpc17_remisoced(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static inline int lpc17_40_remisoced(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { #ifndef CONFIG_USBHOST_ISOC_DISABLE # warning "Isochronous endpoints not yet supported" @@ -1445,7 +1445,7 @@ static inline int lpc17_remisoced(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_enqueuetd + * Name: lpc17_40_enqueuetd * * Description: * Enqueue a transfer descriptor. Notice that this function only supports @@ -1453,16 +1453,16 @@ static inline int lpc17_remisoced(struct lpc17_usbhost_s *priv, * ****************************************************************************/ -static int lpc17_enqueuetd(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint32_t dirpid, +static int lpc17_40_enqueuetd(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint32_t dirpid, uint32_t toggle, volatile uint8_t *buffer, size_t buflen) { - struct lpc17_gtd_s *td; + struct lpc17_40_gtd_s *td; int ret = -ENOMEM; /* Allocate a TD from the free list */ - td = lpc17_tdalloc(); + td = lpc17_40_tdalloc(); if (td != NULL) { /* Initialize the allocated TD and link it before the common tail TD. */ @@ -1492,7 +1492,7 @@ static int lpc17_enqueuetd(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_wdhwait + * Name: lpc17_40_wdhwait * * Description: * Set the request for the Writeback Done Head event well BEFORE enabling the @@ -1502,9 +1502,9 @@ static int lpc17_enqueuetd(struct lpc17_usbhost_s *priv, * ****************************************************************************/ -static int lpc17_wdhwait(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) +static int lpc17_40_wdhwait(struct lpc17_40_usbhost_s *priv, struct lpc17_40_ed_s *ed) { - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_xfrinfo_s *xfrinfo; irqstate_t flags = enter_critical_section(); int ret = -ENODEV; @@ -1528,7 +1528,7 @@ static int lpc17_wdhwait(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) } /**************************************************************************** - * Name: lpc17_ctrltd + * Name: lpc17_40_ctrltd * * Description: * Process a IN or OUT request on the control endpoint. This function @@ -1541,10 +1541,10 @@ static int lpc17_wdhwait(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) * ****************************************************************************/ -static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, +static int lpc17_40_ctrltd(struct lpc17_40_usbhost_s *priv, struct lpc17_40_ed_s *ed, uint32_t dirpid, uint8_t *buffer, size_t buflen) { - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_xfrinfo_s *xfrinfo; uint32_t toggle; uint32_t regval; int ret; @@ -1555,16 +1555,16 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, DEBUGASSERT(ed->xfrinfo == NULL); - xfrinfo = lpc17_alloc_xfrinfo(); + xfrinfo = lpc17_40_alloc_xfrinfo(); if (xfrinfo == NULL) { - uerr("ERROR: lpc17_alloc_xfrinfo failed\n"); + uerr("ERROR: lpc17_40_alloc_xfrinfo failed\n"); return -ENOMEM; } /* Initialize the transfer structure */ - memset(xfrinfo, 0, sizeof(struct lpc17_xfrinfo_s)); + memset(xfrinfo, 0, sizeof(struct lpc17_40_xfrinfo_s)); xfrinfo->buffer = buffer; xfrinfo->buflen = buflen; @@ -1574,7 +1574,7 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, * transfer. */ - ret = lpc17_wdhwait(priv, ed); + ret = lpc17_40_wdhwait(priv, ed); if (ret < 0) { uerr("ERROR: Device disconnected\n"); @@ -1595,20 +1595,20 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, /* Then enqueue the transfer */ xfrinfo->tdstatus = TD_CC_NOERROR; - ret = lpc17_enqueuetd(priv, ed, dirpid, toggle, buffer, buflen); + ret = lpc17_40_enqueuetd(priv, ed, dirpid, toggle, buffer, buflen); if (ret == OK) { /* Set ControlListFilled. This bit is used to indicate whether there are * TDs on the Control list. */ - regval = lpc17_getreg(LPC17_USBHOST_CMDST); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CMDST); regval |= OHCI_CMDST_CLF; - lpc17_putreg(regval, LPC17_USBHOST_CMDST); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CMDST); /* Wait for the Writeback Done Head interrupt */ - lpc17_takesem(&ed->wdhsem); + lpc17_40_takesem(&ed->wdhsem); /* Check the TD completion status bits */ @@ -1626,24 +1626,24 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, /* Make sure that there is no outstanding request on this endpoint */ errout_with_xfrinfo: - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; return ret; } /**************************************************************************** - * Name: lpc17_usbinterrupt + * Name: lpc17_40_usbinterrupt * * Description: * USB interrupt handler * ****************************************************************************/ -static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) +static int lpc17_40_usbinterrupt(int irq, void *context, FAR void *arg) { - struct lpc17_usbhost_s *priv = &g_usbhost; - struct lpc17_ed_s *ed; - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_usbhost_s *priv = &g_usbhost; + struct lpc17_40_ed_s *ed; + struct lpc17_40_xfrinfo_s *xfrinfo; uintptr_t tmp; uint32_t intst; uint32_t pending; @@ -1651,8 +1651,8 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) /* Read Interrupt Status and mask out interrupts that are not enabled. */ - intst = lpc17_getreg(LPC17_USBHOST_INTST); - regval = lpc17_getreg(LPC17_USBHOST_INTEN); + intst = lpc17_40_getreg(LPC17_40_USBHOST_INTST); + regval = lpc17_40_getreg(LPC17_40_USBHOST_INTEN); uinfo("INST: %08x INTEN: %08x\n", intst, regval); pending = intst & regval; @@ -1662,12 +1662,12 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) if ((pending & OHCI_INT_RHSC) != 0) { - uint32_t rhportst1 = lpc17_getreg(LPC17_USBHOST_RHPORTST1); + uint32_t rhportst1 = lpc17_40_getreg(LPC17_40_USBHOST_RHPORTST1); uinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1); if ((rhportst1 & OHCI_RHPORTST_CSC) != 0) { - uint32_t rhstatus = lpc17_getreg(LPC17_USBHOST_RHSTATUS); + uint32_t rhstatus = lpc17_40_getreg(LPC17_40_USBHOST_RHSTATUS); uinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus); /* If DRWE is set, Connect Status Change indicates a remote wake-up event */ @@ -1699,7 +1699,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) if (priv->pscwait) { - lpc17_givesem(&priv->pscsem); + lpc17_40_givesem(&priv->pscsem); priv->pscwait = false; } } @@ -1755,7 +1755,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) if (priv->pscwait) { - lpc17_givesem(&priv->pscsem); + lpc17_40_givesem(&priv->pscsem); priv->pscwait = false; } } @@ -1767,7 +1767,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) /* Clear the status change interrupt */ - lpc17_putreg(OHCI_RHPORTST_CSC, LPC17_USBHOST_RHPORTST1); + lpc17_40_putreg(OHCI_RHPORTST_CSC, LPC17_40_USBHOST_RHPORTST1); } /* Check for port reset status change */ @@ -1776,7 +1776,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) { /* Release the RH port from reset */ - lpc17_putreg(OHCI_RHPORTST_PRSC, LPC17_USBHOST_RHPORTST1); + lpc17_40_putreg(OHCI_RHPORTST_PRSC, LPC17_40_USBHOST_RHPORTST1); } } @@ -1784,8 +1784,8 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) if ((pending & OHCI_INT_WDH) != 0) { - struct lpc17_gtd_s *td; - struct lpc17_gtd_s *next; + struct lpc17_40_gtd_s *td; + struct lpc17_40_gtd_s *next; /* The host controller just wrote the list of finished TDs into the HCCA * done head. This may include multiple packets that were transferred @@ -1797,7 +1797,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) * cleared in the interrupt status register. */ - td = (struct lpc17_gtd_s *)(HCCA->donehead & HCCA_DONEHEAD_MASK); + td = (struct lpc17_40_gtd_s *)(HCCA->donehead & HCCA_DONEHEAD_MASK); HCCA->donehead = 0; next = NULL; @@ -1811,8 +1811,8 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) * this work-around. */ - if ((uintptr_t)td < LPC17_TDFREE_BASE || - (uintptr_t)td >= (LPC17_TDFREE_BASE + LPC17_TD_SIZE*CONFIG_LP17_USBHOST_NTDS)) + if ((uintptr_t)td < LPC17_40_TDFREE_BASE || + (uintptr_t)td >= (LPC17_40_TDFREE_BASE + LPC17_40_TD_SIZE*CONFIG_LP17_USBHOST_NTDS)) { break; } @@ -1843,7 +1843,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) uerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n", ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus, - lpc17_getreg(LPC17_USBHOST_RHPORTST1)); + lpc17_40_getreg(LPC17_40_USBHOST_RHPORTST1)); } #endif @@ -1876,14 +1876,14 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) /* Return the TD to the free list */ - next = (struct lpc17_gtd_s *)td->hw.nexttd; - lpc17_tdfree(td); + next = (struct lpc17_40_gtd_s *)td->hw.nexttd; + lpc17_40_tdfree(td); if (xfrinfo->wdhwait) { /* Wake up the thread waiting for the WDH event */ - lpc17_givesem(&ed->wdhsem); + lpc17_40_givesem(&ed->wdhsem); xfrinfo->wdhwait = false; } @@ -1895,7 +1895,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) else if (xfrinfo->callback) { DEBUGASSERT(xfrinfo->wdhwait == false); - lpc17_asynch_completion(priv, ed); + lpc17_40_asynch_completion(priv, ed); } #endif } @@ -1903,7 +1903,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) } #ifdef CONFIG_DEBUG_USB - if ((pending & LPC17_DEBUG_INTS) != 0) + if ((pending & LPC17_40_DEBUG_INTS) != 0) { uerr("ERROR: Unhandled interrupts INTST:%08x\n", intst); } @@ -1911,7 +1911,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) /* Clear interrupt status register */ - lpc17_putreg(intst, LPC17_USBHOST_INTST); + lpc17_40_putreg(intst, LPC17_40_USBHOST_INTST); } return OK; @@ -1922,7 +1922,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_wait + * Name: lpc17_40_wait * * Description: * Wait for a device to be connected or disconnected to/from a hub port. @@ -1946,10 +1946,10 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) * ****************************************************************************/ -static int lpc17_wait(struct usbhost_connection_s *conn, +static int lpc17_40_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)&g_usbhost; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)&g_usbhost; struct usbhost_hubport_s *connport; irqstate_t flags; @@ -2006,12 +2006,12 @@ static int lpc17_wait(struct usbhost_connection_s *conn, /* Wait for the next connection event */ priv->pscwait = true; - lpc17_takesem(&priv->pscsem); + lpc17_40_takesem(&priv->pscsem); } } /**************************************************************************** - * Name: lpc17_enumerate + * Name: lpc17_40_enumerate * * Description: * Enumerate the connected device. As part of this enumeration process, @@ -2038,10 +2038,10 @@ static int lpc17_wait(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int lpc17_rh_enumerate(struct usbhost_connection_s *conn, +static int lpc17_40_rh_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)&g_usbhost; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)&g_usbhost; DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); /* Are we connected to a device? The caller should have called the wait() @@ -2062,20 +2062,20 @@ static int lpc17_rh_enumerate(struct usbhost_connection_s *conn, /* Put RH port 1 in reset (the LPC176x supports only a single downstream port) */ - lpc17_putreg(OHCI_RHPORTST_PRS, LPC17_USBHOST_RHPORTST1); + lpc17_40_putreg(OHCI_RHPORTST_PRS, LPC17_40_USBHOST_RHPORTST1); /* Wait for the port reset to complete */ - while ((lpc17_getreg(LPC17_USBHOST_RHPORTST1) & OHCI_RHPORTST_PRS) != 0); + while ((lpc17_40_getreg(LPC17_40_USBHOST_RHPORTST1) & OHCI_RHPORTST_PRS) != 0); /* Release RH port 1 from reset and wait a bit */ - lpc17_putreg(OHCI_RHPORTST_PRSC, LPC17_USBHOST_RHPORTST1); + lpc17_40_putreg(OHCI_RHPORTST_PRSC, LPC17_40_USBHOST_RHPORTST1); (void)nxsig_usleep(200*1000); return OK; } -static int lpc17_enumerate(FAR struct usbhost_connection_s *conn, +static int lpc17_40_enumerate(FAR struct usbhost_connection_s *conn, FAR struct usbhost_hubport_s *hport) { int ret; @@ -2091,7 +2091,7 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn, if (ROOTHUB(hport)) #endif { - ret = lpc17_rh_enumerate(conn, hport); + ret = lpc17_40_rh_enumerate(conn, hport); if (ret < 0) { return ret; @@ -2111,7 +2111,7 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn, } /************************************************************************************ - * Name: lpc17_ep0configure + * Name: lpc17_40_ep0configure * * Description: * Configure endpoint 0. This method is normally used internally by the @@ -2137,19 +2137,19 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn, * ************************************************************************************/ -static int lpc17_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, +static int lpc17_40_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; - struct lpc17_ed_s *ed; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; + struct lpc17_40_ed_s *ed; uint32_t hwctrl; DEBUGASSERT(drvr != NULL && ep0 != NULL && funcaddr < 128 && maxpacketsize < 2048); - ed = (struct lpc17_ed_s *)ep0; + ed = (struct lpc17_40_ed_s *)ep0; /* We must have exclusive access to EP0 and the control list */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); /* Set the EP0 ED control word */ @@ -2164,14 +2164,14 @@ static int lpc17_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, ed->hw.ctrl = hwctrl; - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); uinfo("EP0 CTRL:%08x\n", ed->hw.ctrl); return OK; } /************************************************************************************ - * Name: lpc17_epalloc + * Name: lpc17_40_epalloc * * Description: * Allocate and configure one endpoint. @@ -2192,12 +2192,12 @@ static int lpc17_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, * ************************************************************************************/ -static int lpc17_epalloc(struct usbhost_driver_s *drvr, +static int lpc17_40_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; struct usbhost_hubport_s *hport; - struct lpc17_ed_s *ed; + struct lpc17_40_ed_s *ed; int ret = -ENOMEM; /* Sanity check. NOTE that this method should only be called if a device is @@ -2210,20 +2210,20 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, * and the interrupt table. */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); /* Take the next ED from the beginning of the free list */ - ed = (struct lpc17_ed_s *)g_edfree; + ed = (struct lpc17_40_ed_s *)g_edfree; if (ed) { /* Remove the ED from the freelist */ - g_edfree = ((struct lpc17_list_s *)ed)->flink; + g_edfree = ((struct lpc17_40_list_s *)ed)->flink; /* Configure the endpoint descriptor. */ - memset((void *)ed, 0, sizeof(struct lpc17_ed_s)); + memset((void *)ed, 0, sizeof(struct lpc17_40_ed_s)); hport = epdesc->hport; ed->hw.ctrl = (uint32_t)(hport->funcaddr) << ED_CONTROL_FA_SHIFT | @@ -2286,19 +2286,19 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, switch (ed->xfrtype) { case USB_EP_ATTR_XFER_CONTROL: - ret = lpc17_addctrled(priv, ed); + ret = lpc17_40_addctrled(priv, ed); break; case USB_EP_ATTR_XFER_BULK: - ret = lpc17_addbulked(priv, ed); + ret = lpc17_40_addbulked(priv, ed); break; case USB_EP_ATTR_XFER_INT: - ret = lpc17_addinted(priv, epdesc, ed); + ret = lpc17_40_addinted(priv, epdesc, ed); break; case USB_EP_ATTR_XFER_ISOC: - ret = lpc17_addisoced(priv, epdesc, ed); + ret = lpc17_40_addisoced(priv, epdesc, ed); break; default: @@ -2314,7 +2314,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, uerr("ERROR: Failed to queue ED for transfer type: %d\n", ed->xfrtype); nxsem_destroy(&ed->wdhsem); - lpc17_edfree(ed); + lpc17_40_edfree(ed); } else { @@ -2324,12 +2324,12 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, } } - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return ret; } /************************************************************************************ - * Name: lpc17_epfree + * Name: lpc17_40_epfree * * Description: * Free and endpoint previously allocated by DRVR_EPALLOC. @@ -2348,40 +2348,40 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, * ************************************************************************************/ -static int lpc17_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int lpc17_40_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; - struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; + struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep; int ret; /* There should not be any pending, real TDs linked to this ED */ - DEBUGASSERT(ed && (ed->hw.headp & ED_HEADP_ADDR_MASK) == LPC17_TDTAIL_ADDR); + DEBUGASSERT(ed && (ed->hw.headp & ED_HEADP_ADDR_MASK) == LPC17_40_TDTAIL_ADDR); /* We must have exclusive access to the ED pool, the bulk list, the periodic list * and the interrupt table. */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); /* Remove the ED to the correct list depending on the trasfer type */ switch (ed->xfrtype) { case USB_EP_ATTR_XFER_CONTROL: - ret = lpc17_remctrled(priv, ed); + ret = lpc17_40_remctrled(priv, ed); break; case USB_EP_ATTR_XFER_BULK: - ret = lpc17_rembulked(priv, ed); + ret = lpc17_40_rembulked(priv, ed); break; case USB_EP_ATTR_XFER_INT: - ret = lpc17_reminted(priv, ed); + ret = lpc17_40_reminted(priv, ed); break; case USB_EP_ATTR_XFER_ISOC: - ret = lpc17_remisoced(priv, ed); + ret = lpc17_40_remisoced(priv, ed); break; default: @@ -2395,13 +2395,13 @@ static int lpc17_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) /* Put the ED back into the free list */ - lpc17_edfree(ed); - lpc17_givesem(&priv->exclsem); + lpc17_40_edfree(ed); + lpc17_40_givesem(&priv->exclsem); return ret; } /**************************************************************************** - * Name: lpc17_alloc + * Name: lpc17_40_alloc * * Description: * Some hardware supports special memory in which request and descriptor data can @@ -2432,30 +2432,30 @@ static int lpc17_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) * ****************************************************************************/ -static int lpc17_alloc(struct usbhost_driver_s *drvr, +static int lpc17_40_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; DEBUGASSERT(priv && buffer && maxlen); int ret = -ENOMEM; /* We must have exclusive access to the transfer buffer pool */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); - *buffer = lpc17_tballoc(); + *buffer = lpc17_40_tballoc(); if (*buffer) { - *maxlen = CONFIG_LPC17_USBHOST_TDBUFSIZE; + *maxlen = CONFIG_LPC17_40_USBHOST_TDBUFSIZE; ret = OK; } - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return ret; } /**************************************************************************** - * Name: lpc17_free + * Name: lpc17_40_free * * Description: * Some hardware supports special memory in which request and descriptor data can @@ -2477,21 +2477,21 @@ static int lpc17_alloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int lpc17_free(struct usbhost_driver_s *drvr, uint8_t *buffer) +static int lpc17_40_free(struct usbhost_driver_s *drvr, uint8_t *buffer) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; DEBUGASSERT(buffer); /* We must have exclusive access to the transfer buffer pool */ - lpc17_takesem(&priv->exclsem); - lpc17_tbfree(buffer); - lpc17_givesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); + lpc17_40_tbfree(buffer); + lpc17_40_givesem(&priv->exclsem); return OK; } /************************************************************************************ - * Name: lpc17_ioalloc + * Name: lpc17_40_ioalloc * * Description: * Some hardware supports special memory in which larger IO buffers can @@ -2517,15 +2517,15 @@ static int lpc17_free(struct usbhost_driver_s *drvr, uint8_t *buffer) * ************************************************************************************/ -static int lpc17_ioalloc(struct usbhost_driver_s *drvr, +static int lpc17_40_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen) { DEBUGASSERT(drvr && buffer); -#if LPC17_IOBUFFERS > 0 - if (buflen <= CONFIG_LPC17_USBHOST_IOBUFSIZE) +#if LPC17_40_IOBUFFERS > 0 + if (buflen <= CONFIG_LPC17_40_USBHOST_IOBUFSIZE) { - uint8_t *alloc = lpc17_allocio(); + uint8_t *alloc = lpc17_40_allocio(); if (alloc) { *buffer = alloc; @@ -2540,7 +2540,7 @@ static int lpc17_ioalloc(struct usbhost_driver_s *drvr, } /************************************************************************************ - * Name: lpc17_iofree + * Name: lpc17_40_iofree * * Description: * Some hardware supports special memory in which IO data can be accessed more @@ -2562,12 +2562,12 @@ static int lpc17_ioalloc(struct usbhost_driver_s *drvr, * ************************************************************************************/ -static int lpc17_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) +static int lpc17_40_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) { DEBUGASSERT(drvr && buffer); -#if LPC17_IOBUFFERS > 0 - lpc17_freeio(buffer); +#if LPC17_40_IOBUFFERS > 0 + lpc17_40_freeio(buffer); return OK; #else return -ENOSYS; @@ -2575,7 +2575,7 @@ static int lpc17_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) } /**************************************************************************** - * Name: lpc17_ctrlin and lpc17_ctrlout + * Name: lpc17_40_ctrlin and lpc17_40_ctrlout * * Description: * Description: @@ -2610,12 +2610,12 @@ static int lpc17_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) * ****************************************************************************/ -static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, +static int lpc17_40_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; - struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep0; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; + struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep0; uint16_t len; int ret; @@ -2627,33 +2627,33 @@ static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, /* We must have exclusive access to EP0 and the control list */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); - len = lpc17_getle16(req->len); - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); + len = lpc17_40_getle16(req->len); + ret = lpc17_40_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); if (ret == OK) { if (len) { - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_IN, buffer, len); + ret = lpc17_40_ctrltd(priv, ed, GTD_STATUS_DP_IN, buffer, len); } if (ret == OK) { - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_OUT, NULL, 0); + ret = lpc17_40_ctrltd(priv, ed, GTD_STATUS_DP_OUT, NULL, 0); } } - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return ret; } -static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, +static int lpc17_40_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; - struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep0; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; + struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep0; uint16_t len; int ret; @@ -2665,29 +2665,29 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, /* We must have exclusive access to EP0 and the control list */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); - len = lpc17_getle16(req->len); - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); + len = lpc17_40_getle16(req->len); + ret = lpc17_40_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); if (ret == OK) { if (len) { - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_OUT, (uint8_t *)buffer, len); + ret = lpc17_40_ctrltd(priv, ed, GTD_STATUS_DP_OUT, (uint8_t *)buffer, len); } if (ret == OK) { - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_IN, NULL, 0); + ret = lpc17_40_ctrltd(priv, ed, GTD_STATUS_DP_IN, NULL, 0); } } - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return ret; } /**************************************************************************** - * Name: lpc17_transfer_common + * Name: lpc17_40_transfer_common * * Description: * Initiate a request to handle a transfer descriptor. This method will @@ -2712,11 +2712,11 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, * ****************************************************************************/ -static int lpc17_transfer_common(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint8_t *buffer, +static int lpc17_40_transfer_common(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint8_t *buffer, size_t buflen) { - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_xfrinfo_s *xfrinfo; uint32_t dirpid; uint32_t regval; bool in; @@ -2746,7 +2746,7 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv, /* Then enqueue the transfer */ xfrinfo->tdstatus = TD_CC_NOERROR; - ret = lpc17_enqueuetd(priv, ed, dirpid, GTD_STATUS_T_TOGGLE, buffer, buflen); + ret = lpc17_40_enqueuetd(priv, ed, dirpid, GTD_STATUS_T_TOGGLE, buffer, buflen); if (ret == OK) { /* BulkListFilled. This bit is used to indicate whether there are any @@ -2755,9 +2755,9 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv, if (ed->xfrtype == USB_EP_ATTR_XFER_BULK) { - regval = lpc17_getreg(LPC17_USBHOST_CMDST); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CMDST); regval |= OHCI_CMDST_BLF; - lpc17_putreg(regval, LPC17_USBHOST_CMDST); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CMDST); } } @@ -2765,7 +2765,7 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_dma_alloc + * Name: lpc17_40_dma_alloc * * Description: * Allocate DMA memory to perform a transfer, copying user data as necessary @@ -2789,28 +2789,28 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv, * ****************************************************************************/ -#if LPC17_IOBUFFERS > 0 -static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint8_t *userbuffer, +#if LPC17_40_IOBUFFERS > 0 +static int lpc17_40_dma_alloc(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint8_t *userbuffer, size_t buflen, uint8_t **alloc) { uint8_t *newbuffer; - if ((uintptr_t)userbuffer < LPC17_SRAM_BANK0 || - (uintptr_t)userbuffer >= (LPC17_SRAM_BANK0 + LPC17_BANK0_SIZE + LPC17_BANK1_SIZE)) + if ((uintptr_t)userbuffer < LPC17_40_SRAM_BANK0 || + (uintptr_t)userbuffer >= (LPC17_40_SRAM_BANK0 + LPC17_40_BANK0_SIZE + LPC17_40_BANK1_SIZE)) { /* Will the transfer fit in an IO buffer? */ - if (buflen > CONFIG_LPC17_USBHOST_IOBUFSIZE) + if (buflen > CONFIG_LPC17_40_USBHOST_IOBUFSIZE) { uinfo("buflen (%d) > IO buffer size (%d)\n", - buflen, CONFIG_LPC17_USBHOST_IOBUFSIZE); + buflen, CONFIG_LPC17_40_USBHOST_IOBUFSIZE); return -ENOMEM; } /* Allocate an IO buffer in AHB SRAM */ - newbuffer = lpc17_allocio(); + newbuffer = lpc17_40_allocio(); if (!newbuffer) { uinfo("IO buffer allocation failed\n"); @@ -2837,7 +2837,7 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv, } /**************************************************************************** - * Name: lpc17_dma_free + * Name: lpc17_40_dma_free * * Description: * Free allocated DMA memory. @@ -2861,8 +2861,8 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv, * ****************************************************************************/ -static void lpc17_dma_free(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed, uint8_t *userbuffer, +static void lpc17_40_dma_free(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed, uint8_t *userbuffer, size_t buflen, uint8_t *newbuffer) { irqstate_t flags; @@ -2885,7 +2885,7 @@ static void lpc17_dma_free(struct lpc17_usbhost_s *priv, /* Then free the temporary I/O buffer */ - lpc17_freeio(newbuffer); + lpc17_40_freeio(newbuffer); } leave_critical_section(flags); @@ -2893,7 +2893,7 @@ static void lpc17_dma_free(struct lpc17_usbhost_s *priv, #endif /**************************************************************************** - * Name: lpc17_transfer + * Name: lpc17_40_transfer * * Description: * Process a request to handle a transfer descriptor. This method will @@ -2930,13 +2930,13 @@ static void lpc17_dma_free(struct lpc17_usbhost_s *priv, * ****************************************************************************/ -static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static ssize_t lpc17_40_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; - struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep; - struct lpc17_xfrinfo_s *xfrinfo; -#if LPC17_IOBUFFERS > 0 + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; + struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep; + struct lpc17_40_xfrinfo_s *xfrinfo; +#if LPC17_40_IOBUFFERS > 0 uint8_t *alloc = NULL; uint8_t *userbuffer = NULL; #endif @@ -2949,7 +2949,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * pool, the bulk and interrupt lists, and the HCCA interrupt table. */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); /* Allocate a structure to retain the information needed when the transfer * completes. @@ -2957,29 +2957,29 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, DEBUGASSERT(ed->xfrinfo == NULL); - xfrinfo = lpc17_alloc_xfrinfo(); + xfrinfo = lpc17_40_alloc_xfrinfo(); if (xfrinfo == NULL) { - uerr("ERROR: lpc17_alloc_xfrinfo failed\n"); + uerr("ERROR: lpc17_40_alloc_xfrinfo failed\n"); nbytes = -ENOMEM; goto errout_with_sem; } /* Initialize the transfer structure */ - memset(xfrinfo, 0, sizeof(struct lpc17_xfrinfo_s)); + memset(xfrinfo, 0, sizeof(struct lpc17_40_xfrinfo_s)); xfrinfo->buffer = buffer; xfrinfo->buflen = buflen; ed->xfrinfo = xfrinfo; -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Allocate an IO buffer if the user buffer does not lie in AHB SRAM */ - ret = lpc17_dma_alloc(priv, ed, buffer, buflen, &alloc); + ret = lpc17_40_dma_alloc(priv, ed, buffer, buflen, &alloc); if (ret < 0) { - uerr("ERROR: lpc17_dma_alloc failed: %d\n", ret); + uerr("ERROR: lpc17_40_dma_alloc failed: %d\n", ret); nbytes = (ssize_t)ret; goto errout_with_xfrinfo; } @@ -2997,7 +2997,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * transfer. */ - ret = lpc17_wdhwait(priv, ed); + ret = lpc17_40_wdhwait(priv, ed); if (ret < 0) { uerr("ERROR: Device disconnected\n"); @@ -3007,17 +3007,17 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, /* Set up the transfer */ - ret = lpc17_transfer_common(priv, ed, buffer, buflen); + ret = lpc17_40_transfer_common(priv, ed, buffer, buflen); if (ret < 0) { - uerr("ERROR: lpc17_transfer_common failed: %d\n", ret); + uerr("ERROR: lpc17_40_transfer_common failed: %d\n", ret); nbytes = (ssize_t)ret; goto errout_with_wdhwait; } /* Wait for the Writeback Done Head interrupt */ - lpc17_takesem(&ed->wdhsem); + lpc17_40_takesem(&ed->wdhsem); /* Check the TD completion status bits */ @@ -3058,25 +3058,25 @@ errout_with_wdhwait: xfrinfo->wdhwait = false; errout_with_buffers: -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Free any temporary IO buffers */ - lpc17_dma_free(priv, ed, userbuffer, buflen, alloc); + lpc17_40_dma_free(priv, ed, userbuffer, buflen, alloc); #endif errout_with_xfrinfo: /* Make sure that there is no outstanding request on this endpoint */ - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; errout_with_sem: - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return nbytes; } /**************************************************************************** - * Name: lpc17_asynch_completion + * Name: lpc17_40_asynch_completion * * Description: * This function is called at the interrupt level when an asynchronous @@ -3096,10 +3096,10 @@ errout_with_sem: ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv, - struct lpc17_ed_s *ed) +static void lpc17_40_asynch_completion(struct lpc17_40_usbhost_s *priv, + struct lpc17_40_ed_s *ed) { - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_xfrinfo_s *xfrinfo; usbhost_asynch_t callback; void *arg; ssize_t nbytes; @@ -3142,10 +3142,10 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv, } } -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Free any temporary IO buffers */ - lpc17_dma_free(priv, ed, xfrinfo->buffer, xfrinfo->buflen, xfrinfo->alloc); + lpc17_40_dma_free(priv, ed, xfrinfo->buffer, xfrinfo->buflen, xfrinfo->alloc); #endif /* Extract the callback information before freeing the buffer */ @@ -3155,7 +3155,7 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv, /* Make sure that there is no outstanding request on this endpoint */ - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; /* Then perform the callback */ @@ -3165,7 +3165,7 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv, #endif /**************************************************************************** - * Name: lpc17_asynch + * Name: lpc17_40_asynch * * Description: * Process a request to handle a transfer descriptor. This method will @@ -3200,13 +3200,13 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int lpc17_40_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; - struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep; - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; + struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep; + struct lpc17_40_xfrinfo_s *xfrinfo; int ret; DEBUGASSERT(priv && ed && ed->xfrinfo == NULL && buffer && buflen > 0 && callback); @@ -3215,7 +3215,7 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * pool, the bulk and interrupt lists, and the HCCA interrupt table. */ - lpc17_takesem(&priv->exclsem); + lpc17_40_takesem(&priv->exclsem); /* Allocate a structure to retain the information needed when the asynchronous * transfer completes. @@ -3223,17 +3223,17 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, DEBUGASSERT(ed->xfrinfo == NULL); - xfrinfo = lpc17_alloc_xfrinfo(); + xfrinfo = lpc17_40_alloc_xfrinfo(); if (xfrinfo == NULL) { - uerr("ERROR: lpc17_alloc_xfrinfo failed\n"); + uerr("ERROR: lpc17_40_alloc_xfrinfo failed\n"); ret = -ENOMEM; goto errout_with_sem; } /* Initialize the transfer structure */ - memset(xfrinfo, 0, sizeof(struct lpc17_xfrinfo_s)); + memset(xfrinfo, 0, sizeof(struct lpc17_40_xfrinfo_s)); xfrinfo->buffer = buffer; xfrinfo->buflen = buflen; xfrinfo->callback = callback; @@ -3241,13 +3241,13 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, ed->xfrinfo = xfrinfo; -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Allocate an IO buffer if the user buffer does not lie in AHB SRAM */ - ret = lpc17_dma_alloc(priv, ed, buffer, buflen, &xfrinfo->alloc); + ret = lpc17_40_dma_alloc(priv, ed, buffer, buflen, &xfrinfo->alloc); if (ret < 0) { - uerr("ERROR: lpc17_dma_alloc failed: %d\n", ret); + uerr("ERROR: lpc17_40_dma_alloc failed: %d\n", ret); goto errout_with_sem; } @@ -3261,10 +3261,10 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, /* Set up the transfer */ - ret = lpc17_transfer_common(priv, ed, buffer, buflen); + ret = lpc17_40_transfer_common(priv, ed, buffer, buflen); if (ret < 0) { - uerr("ERROR: lpc17_transfer_common failed: %d\n", ret); + uerr("ERROR: lpc17_40_transfer_common failed: %d\n", ret); goto errout_with_asynch; } @@ -3272,29 +3272,29 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * completes. */ - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return OK; errout_with_asynch: -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Free any temporary IO buffers */ - lpc17_dma_free(priv, ed, buffer, buflen, xfrinfo->alloc); + lpc17_40_dma_free(priv, ed, buffer, buflen, xfrinfo->alloc); #endif /* Free the transfer structure */ - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; errout_with_sem: - lpc17_givesem(&priv->exclsem); + lpc17_40_givesem(&priv->exclsem); return ret; } #endif /* CONFIG_USBHOST_ASYNCH */ /************************************************************************************ - * Name: lpc17_cancel + * Name: lpc17_40_cancel * * Description: * Cancel a pending transfer on an endpoint. Cancelled synchronous or @@ -3312,15 +3312,15 @@ errout_with_sem: * ************************************************************************************/ -static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int lpc17_40_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { #ifdef CONFIG_USBHOST_ASYNCH - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; #endif - struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep; - struct lpc17_gtd_s *td; - struct lpc17_gtd_s *next; - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep; + struct lpc17_40_gtd_s *td; + struct lpc17_40_gtd_s *next; + struct lpc17_40_xfrinfo_s *xfrinfo; uint32_t ctrl; irqstate_t flags; @@ -3354,26 +3354,26 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { /* Disable bulk list processing while we modify the list */ - ctrl = lpc17_getreg(LPC17_USBHOST_CTRL); - lpc17_putreg(ctrl & ~OHCI_CTRL_BLE, LPC17_USBHOST_CTRL); + ctrl = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); + lpc17_40_putreg(ctrl & ~OHCI_CTRL_BLE, LPC17_40_USBHOST_CTRL); /* Remove the TDs attached to the ED, keeping the ED in the list */ - td = (struct lpc17_gtd_s *)(ed->hw.headp & ED_HEADP_ADDR_MASK); - ed->hw.headp = LPC17_TDTAIL_ADDR; + td = (struct lpc17_40_gtd_s *)(ed->hw.headp & ED_HEADP_ADDR_MASK); + ed->hw.headp = LPC17_40_TDTAIL_ADDR; ed->xfrinfo = NULL; /* Re-enable bulk list processing, if it was enabled before */ - lpc17_putreg(0, LPC17_USBHOST_BULKED); - lpc17_putreg(ctrl, LPC17_USBHOST_CTRL); + lpc17_40_putreg(0, LPC17_40_USBHOST_BULKED); + lpc17_40_putreg(ctrl, LPC17_40_USBHOST_CTRL); } else { /* Remove the TDs attached to the ED, keeping the Ed in the list */ - td = (struct lpc17_gtd_s *)(ed->hw.headp & ED_HEADP_ADDR_MASK); - ed->hw.headp = LPC17_TDTAIL_ADDR; + td = (struct lpc17_40_gtd_s *)(ed->hw.headp & ED_HEADP_ADDR_MASK); + ed->hw.headp = LPC17_40_TDTAIL_ADDR; ed->xfrinfo = NULL; } @@ -3381,10 +3381,10 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) * some race conditions with the hardware, this might be none. */ - while (td != (struct lpc17_gtd_s *)LPC17_TDTAIL_ADDR) + while (td != (struct lpc17_40_gtd_s *)LPC17_40_TDTAIL_ADDR) { - next = (struct lpc17_gtd_s *)td->hw.nexttd; - lpc17_tdfree(td); + next = (struct lpc17_40_gtd_s *)td->hw.nexttd; + lpc17_40_tdfree(td); td = next; } @@ -3404,12 +3404,12 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) /* Wake up the waiting thread */ - lpc17_givesem(&ed->wdhsem); + lpc17_40_givesem(&ed->wdhsem); xfrinfo->wdhwait = false; /* And free the transfer structure */ - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; } #ifdef CONFIG_USBHOST_ASYNCH @@ -3417,7 +3417,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { /* Otherwise, perform the callback and free the transfer structure */ - lpc17_asynch_completion(priv, ed); + lpc17_40_asynch_completion(priv, ed); } #endif } @@ -3425,7 +3425,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { /* Just free the transfer structure */ - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; } } @@ -3437,7 +3437,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /************************************************************************************ - * Name: lpc17_connect + * Name: lpc17_40_connect * * Description: * New connections may be detected by an attached hub. This method is the @@ -3458,11 +3458,11 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) ************************************************************************************/ #ifdef CONFIG_USBHOST_HUB -static int lpc17_connect(FAR struct usbhost_driver_s *drvr, +static int lpc17_40_connect(FAR struct usbhost_driver_s *drvr, FAR struct usbhost_hubport_s *hport, bool connected) { - struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; + struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr; DEBUGASSERT(priv != NULL && hport != NULL); irqstate_t flags; @@ -3478,7 +3478,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr, if (priv->pscwait) { priv->pscwait = false; - lpc17_givesem(&priv->pscsem); + lpc17_40_givesem(&priv->pscsem); } leave_critical_section(flags); @@ -3487,7 +3487,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr, #endif /**************************************************************************** - * Name: lpc17_disconnect + * Name: lpc17_40_disconnect * * Description: * Called by the class when an error occurs and driver has been disconnected. @@ -3511,7 +3511,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void lpc17_disconnect(struct usbhost_driver_s *drvr, +static void lpc17_40_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport) { DEBUGASSERT(hport != NULL); @@ -3522,7 +3522,7 @@ static void lpc17_disconnect(struct usbhost_driver_s *drvr, * Initialization ****************************************************************************/ /**************************************************************************** - * Name: lpc17_ep0init + * Name: lpc17_40_ep0init * * Description: * Initialize ED for EP0, add it to the control ED list, and enable control @@ -3536,27 +3536,27 @@ static void lpc17_disconnect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static inline void lpc17_ep0init(struct lpc17_usbhost_s *priv) +static inline void lpc17_40_ep0init(struct lpc17_40_usbhost_s *priv) { /* Initialize the common tail TD. */ - memset(TDTAIL, 0, sizeof(struct lpc17_gtd_s)); + memset(TDTAIL, 0, sizeof(struct lpc17_40_gtd_s)); TDTAIL->ed = EDCTRL; /* Link the common tail TD to the ED's TD list */ - memset(EDCTRL, 0, sizeof(struct lpc17_ed_s)); + memset(EDCTRL, 0, sizeof(struct lpc17_40_ed_s)); EDCTRL->hw.headp = (uint32_t)TDTAIL; EDCTRL->hw.tailp = (uint32_t)TDTAIL; EDCTRL->xfrtype = USB_EP_ATTR_XFER_CONTROL; /* Set the head of the control list to the NULL (for now). */ - lpc17_putreg(0, LPC17_USBHOST_CTRLHEADED); + lpc17_40_putreg(0, LPC17_40_USBHOST_CTRLHEADED); /* Then add EP0 to the empty Control List */ - lpc17_addctrled(priv, EDCTRL); + lpc17_40_addctrled(priv, EDCTRL); } /**************************************************************************** @@ -3564,7 +3564,7 @@ static inline void lpc17_ep0init(struct lpc17_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_usbhost_initialize + * Name: lpc17_40_usbhost_initialize * * Description: * Initialize USB host device controller hardware. @@ -3588,47 +3588,47 @@ static inline void lpc17_ep0init(struct lpc17_usbhost_s *priv) * ****************************************************************************/ -struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) +struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller) { - struct lpc17_usbhost_s *priv = &g_usbhost; + struct lpc17_40_usbhost_s *priv = &g_usbhost; struct usbhost_driver_s *drvr; struct usbhost_hubport_s *hport; - struct lpc17_xfrinfo_s *xfrinfo; + struct lpc17_40_xfrinfo_s *xfrinfo; uint32_t regval; uint8_t *buffer; irqstate_t flags; int i; /* Sanity checks. NOTE: If certain OS features are enabled, it may be - * necessary to increase the size of LPC17_ED/TD_SIZE in lpc17_ohciram.h + * necessary to increase the size of LPC17_40_ED/TD_SIZE in lpc17_40_ohciram.h */ DEBUGASSERT(controller == 0); - DEBUGASSERT(sizeof(struct lpc17_ed_s) <= LPC17_ED_SIZE); - DEBUGASSERT(sizeof(struct lpc17_gtd_s) <= LPC17_TD_SIZE); + DEBUGASSERT(sizeof(struct lpc17_40_ed_s) <= LPC17_40_ED_SIZE); + DEBUGASSERT(sizeof(struct lpc17_40_gtd_s) <= LPC17_40_TD_SIZE); /* Initialize the state data structure */ /* Initialize the device operations */ drvr = &priv->drvr; - drvr->ep0configure = lpc17_ep0configure; - drvr->epalloc = lpc17_epalloc; - drvr->epfree = lpc17_epfree; - drvr->alloc = lpc17_alloc; - drvr->free = lpc17_free; - drvr->ioalloc = lpc17_ioalloc; - drvr->iofree = lpc17_iofree; - drvr->ctrlin = lpc17_ctrlin; - drvr->ctrlout = lpc17_ctrlout; - drvr->transfer = lpc17_transfer; + drvr->ep0configure = lpc17_40_ep0configure; + drvr->epalloc = lpc17_40_epalloc; + drvr->epfree = lpc17_40_epfree; + drvr->alloc = lpc17_40_alloc; + drvr->free = lpc17_40_free; + drvr->ioalloc = lpc17_40_ioalloc; + drvr->iofree = lpc17_40_iofree; + drvr->ctrlin = lpc17_40_ctrlin; + drvr->ctrlout = lpc17_40_ctrlout; + drvr->transfer = lpc17_40_transfer; #ifdef CONFIG_USBHOST_ASYNCH - drvr->asynch = lpc17_asynch; + drvr->asynch = lpc17_40_asynch; #endif - drvr->cancel = lpc17_cancel; + drvr->cancel = lpc17_40_cancel; #ifdef CONFIG_USBHOST_HUB - drvr->connect = lpc17_connect; + drvr->connect = lpc17_40_connect; #endif - drvr->disconnect = lpc17_disconnect; + drvr->disconnect = lpc17_40_disconnect; /* Initialize the public port representation */ @@ -3666,27 +3666,27 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_SYSCON_PCONP); + regval = lpc17_40_getreg(LPC17_40_SYSCON_PCONP); regval |= SYSCON_PCONP_PCUSB; - lpc17_putreg(regval, LPC17_SYSCON_PCONP); + lpc17_40_putreg(regval, LPC17_40_SYSCON_PCONP); leave_critical_section(flags); /* Enable clocking on USB (USB PLL clocking was initialized in very low- - * evel clock setup logic (see lpc17_clockconfig.c)). We do still need + * evel clock setup logic (see lpc17_40_clockconfig.c)). We do still need * to set up USBOTG CLKCTRL to enable clocking. * * NOTE: The PORTSEL clock needs to be enabled only when accessing OTGSTCTRL */ - lpc17_putreg(LPC17_CLKCTRL_ENABLES, LPC17_USBOTG_CLKCTRL); + lpc17_40_putreg(LPC17_40_CLKCTRL_ENABLES, LPC17_40_USBOTG_CLKCTRL); /* Then wait for the clocks to be reported as "ON" */ do { - regval = lpc17_getreg(LPC17_USBOTG_CLKST); + regval = lpc17_40_getreg(LPC17_40_USBOTG_CLKST); } - while ((regval & LPC17_CLKCTRL_ENABLES) != LPC17_CLKCTRL_ENABLES); + while ((regval & LPC17_40_CLKCTRL_ENABLES) != LPC17_40_CLKCTRL_ENABLES); /* Set the OTG status and control register. Bits 0:1 apparently mean: * @@ -3699,21 +3699,21 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) * NOTE: The PORTSEL clock needs to be enabled when accessing OTGSTCTRL */ - lpc17_putreg(1, LPC17_USBOTG_STCTRL); + lpc17_40_putreg(1, LPC17_40_USBOTG_STCTRL); /* Now we can turn off the PORTSEL clock */ - lpc17_putreg((LPC17_CLKCTRL_ENABLES & ~USBOTG_CLK_PORTSELCLK), LPC17_USBOTG_CLKCTRL); + lpc17_40_putreg((LPC17_40_CLKCTRL_ENABLES & ~USBOTG_CLK_PORTSELCLK), LPC17_40_USBOTG_CLKCTRL); /* Configure I/O pins */ usbhost_dumpgpio(); - lpc17_configgpio(GPIO_USB_DP); /* Positive differential data */ - lpc17_configgpio(GPIO_USB_DM); /* Negative differential data */ - lpc17_configgpio(GPIO_USB_UPLED); /* GoodLink LED control signal */ - lpc17_configgpio(GPIO_USB_PPWR); /* Port Power enable signal for USB port */ - lpc17_configgpio(GPIO_USB_PWRD); /* Power Status for USB port (host power switch) */ - lpc17_configgpio(GPIO_USB_OVRCR); /* USB port Over-Current status */ + lpc17_40_configgpio(GPIO_USB_DP); /* Positive differential data */ + lpc17_40_configgpio(GPIO_USB_DM); /* Negative differential data */ + lpc17_40_configgpio(GPIO_USB_UPLED); /* GoodLink LED control signal */ + lpc17_40_configgpio(GPIO_USB_PPWR); /* Port Power enable signal for USB port */ + lpc17_40_configgpio(GPIO_USB_PWRD); /* Power Status for USB port (host power switch) */ + lpc17_40_configgpio(GPIO_USB_OVRCR); /* USB port Over-Current status */ usbhost_dumpgpio(); uinfo("Initializing Host Stack\n"); @@ -3722,20 +3722,20 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) #if 0 /* Useful if you have doubts about the layout */ uinfo("AHB SRAM:\n"); - uinfo(" HCCA: %08x %d\n", LPC17_HCCA_BASE, LPC17_HCCA_SIZE); - uinfo(" TDTAIL: %08x %d\n", LPC17_TDTAIL_ADDR, LPC17_TD_SIZE); - uinfo(" EDCTRL: %08x %d\n", LPC17_EDCTRL_ADDR, LPC17_ED_SIZE); - uinfo(" EDFREE: %08x %d\n", LPC17_EDFREE_BASE, LPC17_ED_SIZE); - uinfo(" TDFREE: %08x %d\n", LPC17_TDFREE_BASE, LPC17_EDFREE_SIZE); - uinfo(" TBFREE: %08x %d\n", LPC17_TBFREE_BASE, LPC17_TBFREE_SIZE); - uinfo(" IOFREE: %08x %d\n", LPC17_IOFREE_BASE, LPC17_IOBUFFERS * CONFIG_LPC17_USBHOST_IOBUFSIZE); + uinfo(" HCCA: %08x %d\n", LPC17_40_HCCA_BASE, LPC17_40_HCCA_SIZE); + uinfo(" TDTAIL: %08x %d\n", LPC17_40_TDTAIL_ADDR, LPC17_40_TD_SIZE); + uinfo(" EDCTRL: %08x %d\n", LPC17_40_EDCTRL_ADDR, LPC17_40_ED_SIZE); + uinfo(" EDFREE: %08x %d\n", LPC17_40_EDFREE_BASE, LPC17_40_ED_SIZE); + uinfo(" TDFREE: %08x %d\n", LPC17_40_TDFREE_BASE, LPC17_40_EDFREE_SIZE); + uinfo(" TBFREE: %08x %d\n", LPC17_40_TBFREE_BASE, LPC17_40_TBFREE_SIZE); + uinfo(" IOFREE: %08x %d\n", LPC17_40_IOFREE_BASE, LPC17_40_IOBUFFERS * CONFIG_LPC17_40_USBHOST_IOBUFSIZE); #endif /* Initialize all the TDs, EDs and HCCA to 0 */ memset((void *)HCCA, 0, sizeof(struct ohci_hcca_s)); memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s)); - memset((void *)EDCTRL, 0, sizeof(struct lpc17_ed_s)); + memset((void *)EDCTRL, 0, sizeof(struct lpc17_40_ed_s)); /* The EDCTRL wdhsem semaphore is used for signaling and, hence, should * not have priority inheritance enabled. @@ -3746,111 +3746,111 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) /* Initialize user-configurable EDs */ - buffer = (uint8_t *)LPC17_EDFREE_BASE; + buffer = (uint8_t *)LPC17_40_EDFREE_BASE; for (i = 0; i < CONFIG_LP17_USBHOST_NEDS; i++) { /* Put the ED in a free list */ - lpc17_edfree((struct lpc17_ed_s *)buffer); - buffer += LPC17_ED_SIZE; + lpc17_40_edfree((struct lpc17_40_ed_s *)buffer); + buffer += LPC17_40_ED_SIZE; } /* Initialize user-configurable TDs */ - buffer = (uint8_t *)LPC17_TDFREE_BASE; + buffer = (uint8_t *)LPC17_40_TDFREE_BASE; for (i = 0; i < CONFIG_LP17_USBHOST_NTDS; i++) { /* Put the TD in a free list */ - lpc17_tdfree((struct lpc17_gtd_s *)buffer); - buffer += LPC17_TD_SIZE; + lpc17_40_tdfree((struct lpc17_40_gtd_s *)buffer); + buffer += LPC17_40_TD_SIZE; } /* Initialize user-configurable request/descriptor transfer buffers */ - buffer = (uint8_t *)LPC17_TBFREE_BASE; - for (i = 0; i < CONFIG_LPC17_USBHOST_TDBUFFERS; i++) + buffer = (uint8_t *)LPC17_40_TBFREE_BASE; + for (i = 0; i < CONFIG_LPC17_40_USBHOST_TDBUFFERS; i++) { /* Put the TD buffer in a free list */ - lpc17_tbfree(buffer); - buffer += CONFIG_LPC17_USBHOST_TDBUFSIZE; + lpc17_40_tbfree(buffer); + buffer += CONFIG_LPC17_40_USBHOST_TDBUFSIZE; } -#if LPC17_IOBUFFERS > 0 +#if LPC17_40_IOBUFFERS > 0 /* Initialize user-configurable IO buffers */ - buffer = (uint8_t *)LPC17_IOFREE_BASE; - for (i = 0; i < LPC17_IOBUFFERS; i++) + buffer = (uint8_t *)LPC17_40_IOFREE_BASE; + for (i = 0; i < LPC17_40_IOBUFFERS; i++) { /* Put the IO buffer in a free list */ - lpc17_freeio(buffer); - buffer += CONFIG_LPC17_USBHOST_IOBUFSIZE; + lpc17_40_freeio(buffer); + buffer += CONFIG_LPC17_40_USBHOST_IOBUFSIZE; } #endif /* Initialize transfer structures */ for (i = 0, xfrinfo = g_xfrbuffers; - i < CONFIG_LPC17_USBHOST_NPREALLOC; + i < CONFIG_LPC17_40_USBHOST_NPREALLOC; i++, xfrinfo++) { /* Put the transfer structure in a free list */ - lpc17_free_xfrinfo(xfrinfo); + lpc17_40_free_xfrinfo(xfrinfo); } /* Wait 50MS then perform hardware reset */ up_mdelay(50); - lpc17_putreg(0, LPC17_USBHOST_CTRL); /* Hardware reset */ - lpc17_putreg(0, LPC17_USBHOST_CTRLHEADED); /* Initialize control list head to Zero */ - lpc17_putreg(0, LPC17_USBHOST_BULKHEADED); /* Initialize bulk list head to Zero */ + lpc17_40_putreg(0, LPC17_40_USBHOST_CTRL); /* Hardware reset */ + lpc17_40_putreg(0, LPC17_40_USBHOST_CTRLHEADED); /* Initialize control list head to Zero */ + lpc17_40_putreg(0, LPC17_40_USBHOST_BULKHEADED); /* Initialize bulk list head to Zero */ /* Software reset */ - lpc17_putreg(OHCI_CMDST_HCR, LPC17_USBHOST_CMDST); + lpc17_40_putreg(OHCI_CMDST_HCR, LPC17_40_USBHOST_CMDST); /* Write Fm interval (FI), largest data packet counter (FSMPS), and * periodic start. */ - lpc17_putreg(DEFAULT_FMINTERVAL, LPC17_USBHOST_FMINT); - lpc17_putreg(DEFAULT_PERSTART, LPC17_USBHOST_PERSTART); + lpc17_40_putreg(DEFAULT_FMINTERVAL, LPC17_40_USBHOST_FMINT); + lpc17_40_putreg(DEFAULT_PERSTART, LPC17_40_USBHOST_PERSTART); /* Put HC in operational state */ - regval = lpc17_getreg(LPC17_USBHOST_CTRL); + regval = lpc17_40_getreg(LPC17_40_USBHOST_CTRL); regval &= ~OHCI_CTRL_HCFS_MASK; regval |= OHCI_CTRL_HCFS_OPER; - lpc17_putreg(regval, LPC17_USBHOST_CTRL); + lpc17_40_putreg(regval, LPC17_40_USBHOST_CTRL); /* Set global power in HcRhStatus */ - lpc17_putreg(OHCI_RHSTATUS_SGP, LPC17_USBHOST_RHSTATUS); + lpc17_40_putreg(OHCI_RHSTATUS_SGP, LPC17_40_USBHOST_RHSTATUS); /* Set HCCA base address */ - lpc17_putreg((uint32_t)HCCA, LPC17_USBHOST_HCCA); + lpc17_40_putreg((uint32_t)HCCA, LPC17_40_USBHOST_HCCA); /* Set up the root hub port EP0 */ - lpc17_ep0init(priv); + lpc17_40_ep0init(priv); /* Clear pending interrupts */ - regval = lpc17_getreg(LPC17_USBHOST_INTST); - lpc17_putreg(regval, LPC17_USBHOST_INTST); + regval = lpc17_40_getreg(LPC17_40_USBHOST_INTST); + lpc17_40_putreg(regval, LPC17_40_USBHOST_INTST); /* Enable OHCI interrupts */ - lpc17_putreg((LPC17_ALL_INTS | OHCI_INT_MIE), LPC17_USBHOST_INTEN); + lpc17_40_putreg((LPC17_40_ALL_INTS | OHCI_INT_MIE), LPC17_40_USBHOST_INTEN); /* Attach USB host controller interrupt handler */ - if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt, NULL) != 0) + if (irq_attach(LPC17_40_IRQ_USB, lpc17_40_usbinterrupt, NULL) != 0) { uerr("ERROR: Failed to attach IRQ\n"); return NULL; @@ -3861,9 +3861,9 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) */ flags = enter_critical_section(); - regval = lpc17_getreg(LPC17_SYSCON_USBINTST); + regval = lpc17_40_getreg(LPC17_40_SYSCON_USBINTST); regval |= SYSCON_USBINTST_ENINTS; - lpc17_putreg(regval, LPC17_SYSCON_USBINTST); + lpc17_40_putreg(regval, LPC17_40_SYSCON_USBINTST); leave_critical_section(flags); /* If there is a USB device in the slot at power up, then we will not @@ -3871,12 +3871,12 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) * connected. We need to set the initial connected state accordingly. */ - regval = lpc17_getreg(LPC17_USBHOST_RHPORTST1); + regval = lpc17_40_getreg(LPC17_40_USBHOST_RHPORTST1); priv->connected = ((regval & OHCI_RHPORTST_CCS) != 0); /* Enable interrupts at the interrupt controller */ - up_enable_irq(LPC17_IRQ_USB); /* enable USB interrupt */ + up_enable_irq(LPC17_40_IRQ_USB); /* enable USB interrupt */ uinfo("USB host Initialized, Device connected:%s\n", priv->connected ? "YES" : "NO"); diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.h similarity index 92% rename from arch/arm/src/lpc17xx/lpc17_usbhost.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.h index 5efec074f96..355337950e8 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_usbhost.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USBHOST_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_USBHOST_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_USBHOST_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_USBHOST_H /************************************************************************************ * Included Files @@ -70,7 +70,7 @@ extern "C" #endif /**************************************************************************** - * Name: lpc17_usbhost_initialize + * Name: lpc17_40_usbhost_initialize * * Description: * Initialize USB host device controller hardware. @@ -96,7 +96,7 @@ extern "C" #ifdef CONFIG_USBHOST struct usbhost_connection_s; -FAR struct usbhost_connection_s *lpc17_usbhost_initialize(int controller); +FAR struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller); #endif #undef EXTERN @@ -105,4 +105,4 @@ FAR struct usbhost_connection_s *lpc17_usbhost_initialize(int controller); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USBHOST_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_USBHOST_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_userspace.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.c similarity index 95% rename from arch/arm/src/lpc17xx/lpc17_userspace.c rename to arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.c index ed433eab7ed..a3aa1f6cb33 100644 --- a/arch/arm/src/lpc17xx/lpc17_userspace.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17xx/lpc17_userspace.c + * arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,8 +44,8 @@ #include -#include "lpc17_mpuinit.h" -#include "lpc17_userspace.h" +#include "lpc17_40_mpuinit.h" +#include "lpc17_40_userspace.h" #ifdef CONFIG_BUILD_PROTECTED @@ -66,7 +66,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_userspace + * Name: lpc17_40_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -76,7 +76,7 @@ * ****************************************************************************/ -void lpc17_userspace(void) +void lpc17_40_userspace(void) { uint8_t *src; uint8_t *dest; @@ -112,7 +112,7 @@ void lpc17_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - lpc17_mpuinitialize(); + lpc17_40_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/lpc17xx/lpc17_userspace.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.h similarity index 91% rename from arch/arm/src/lpc17xx/lpc17_userspace.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.h index 5adb8771cb6..752be52cc45 100644 --- a/arch/arm/src/lpc17xx/lpc17_userspace.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_userspace.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_userspace.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_USERSPACE_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_USERSPACE_H /************************************************************************************ * Included Files @@ -59,7 +59,7 @@ ************************************************************************************/ /**************************************************************************** - * Name: lpc17_userspace + * Name: lpc17_40_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -70,7 +70,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void lpc17_userspace(void); +void lpc17_40_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_USERSPACE_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_qei.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h similarity index 92% rename from arch/arm/src/lpc17xx/lpc17_qei.h rename to arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h index dfa01ff3ffc..ce7a3d5d227 100644 --- a/arch/arm/src/lpc17xx/lpc17_qei.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_qei.h + * arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,15 +33,15 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H +#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_WDT_H +#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_WDT_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "hardware/lpc17_qei.h" +#include "hardware/lpc17_40_wdt.h" /************************************************************************************ * Pre-processor Definitions @@ -59,4 +59,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_WDT_H */ diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 2a99c2a0844..5bb9b120b71 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -4,7 +4,7 @@ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Derived from arch/arm/src/lpc17xx/lpc17xx_i2c.c + * Derived from arch/arm/src/lpc17xx_40xx/lpc17xx_40xx_i2c.c * * Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.h b/arch/arm/src/lpc2378/lpc23xx_i2c.h index 1ae069c5f76..d054b4bf5a8 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.h +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.h @@ -4,7 +4,7 @@ * Copyright (C) 2013 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi * - * Derived arch/arm/src/lpc17xx/lpc17_i2c.h + * Derived arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.h * * Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c index b9006f4e5ce..86021293fb5 100644 --- a/arch/arm/src/lpc2378/lpc23xx_spi.c +++ b/arch/arm/src/lpc2378/lpc23xx_spi.c @@ -4,7 +4,7 @@ * Copyright (C) 2013 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi * - * Derived from arch/arm/src/lpc17xx/lpc17_spi.c + * Derived from arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c * * Copyright (C) 2010, 2012, 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.h b/arch/arm/src/lpc2378/lpc23xx_spi.h index 280c2f44e20..ac0744adf90 100644 --- a/arch/arm/src/lpc2378/lpc23xx_spi.h +++ b/arch/arm/src/lpc2378/lpc23xx_spi.h @@ -4,7 +4,7 @@ * Copyright (C) 2013 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi * - * Derived arch/arm/src/lpc17xx/lpc17_spi.h + * Derived arch/arm/src/lpc17xx_40xx/lpc17_40_spi.h * * Copyright (C) 2010, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c index 3b86cdb3900..017dd728466 100644 --- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c @@ -5,7 +5,7 @@ * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Alan Carvalho de Assis * - * This code is based on arch/arm/src/lpc17xx/lpc17_sdcard.c: + * This code is based on arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c: * * Copyright (C) 2013-2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c index e9564431eaf..6b389ecffad 100644 --- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c +++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c @@ -10,7 +10,7 @@ * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Alan Carvalho de Assis * - * which was itself based on arch/arm/src/lpc17xx/lpc17_sdcard.c: + * which was itself based on arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c: * * Copyright (C) 2013-2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index b9ff2fa1c7a..76cfd3d8baa 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -151,7 +151,7 @@ static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; #endif -/* This describes the state of the LPC17xx uart0 port. */ +/* This describes the state of the NUC1xx uart0 port. */ #ifdef CONFIG_NUC_UART0 static struct nuc_dev_s g_uart0priv = @@ -182,7 +182,7 @@ static uart_dev_t g_uart0port = }; #endif /* CONFIG_NUC_UART0 */ -/* This describes the state of the LPC17xx uart1 port. */ +/* This describes the state of the NUC1xx uart1 port. */ #ifdef CONFIG_NUC_UART1 static struct nuc_dev_s g_uart1priv = @@ -213,7 +213,7 @@ static uart_dev_t g_uart1port = }; #endif /* CONFIG_NUC_UART1 */ -/* This describes the state of the LPC17xx uart1 port. */ +/* This describes the state of the NUC1xx uart1 port. */ #ifdef CONFIG_NUC_UART2 static struct nuc_dev_s g_uart2priv = diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 0ed18256b07..c92b310ea27 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2757,6 +2757,28 @@ config STM32_LCD default n depends on STM32_STM32L15XX +# +# STM32 LCD Clock Selection +# + +if STM32_LCD + +choice + prompt "Segment LCD Clock Source" + default LCD_LSECLOCK + +config LCD_LSICLOCK + bool "Internal Low Speed Clock" + +config LCD_LSECLOCK + bool "External Low Speed Clock" + +config LCD_HSECLOCK + bool "External High Speed Clock" + +endchoice +endif # STM32_LCD + config STM32_IWDG bool "IWDG" default n diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 84ef06053c6..bfbe6550220 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -565,9 +565,8 @@ (ETH_DMACIER_TIE | ETH_DMACIER_TBUE | ETH_DMACIER_RIE | ETH_DMACIER_ERIE) #define ETH_DMAINT_ABNORMAL \ - (ETH_DMACIER_TXSE \ - ETH_DMACIER_RBUE | ETH_DMACIER_RSE | ETH_DMACIER_RWTE | /* ETH_DMACIER_ETIE | */ \ - ETH_DMACIER_FBEE) + (ETH_DMACIER_TXSE | ETH_DMACIER_RBUE | ETH_DMACIER_RSE | \ + ETH_DMACIER_RWTE | /* ETH_DMACIER_ETIE | */ ETH_DMACIER_FBEE) /* Normal receive, transmit, error interrupt enable bit sets */ @@ -576,7 +575,7 @@ #define ETH_DMAINT_XMIT_DISABLE (ETH_DMACIER_TIE) #ifdef CONFIG_DEBUG_NET -# define ETH_DMAINT_ERROR_ENABLE (ETH_DMACIER_AIE | ETH_DMACIER_ABNORMAL) +# define ETH_DMAINT_ERROR_ENABLE (ETH_DMACIER_AIE | ETH_DMAINT_ABNORMAL) #else # define ETH_DMAINT_ERROR_ENABLE (0) #endif diff --git a/arch/avr/src/avr/avr.h b/arch/avr/src/avr/avr.h index 2e0c72ee38f..92fe4cd402e 100644 --- a/arch/avr/src/avr/avr.h +++ b/arch/avr/src/avr/avr.h @@ -161,7 +161,7 @@ FAR struct spi_dev_s *avr_spibus_initialize(int port); * These external functions must be provided by board-specific logic. They are * implementations of the select, status, and cmddata methods of the SPI interface * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including avr_spibus_initialize()) are provided by common LPC17xx logic. To use + * including avr_spibus_initialize()) are provided by common AVR logic. To use * this common SPI logic on your board: * * 1. Provide logic in _boardinitialize() to configure SPI chip select diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index 89e524bd298..0ccb7cb083d 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -744,12 +744,12 @@ static int emac_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) int emac_initialize(int intf) { - struct lpc17_driver_s *priv; + struct emac_driver_s *priv; /* Get the interface structure associated with this interface number. */ DEBUGASSERT(inf < CONFIG_HCS12_NINTERFACES); - priv = &g_ethdrvr[intf]; + priv = &g_emac[intf]; /* Check if a Ethernet chip is recognized at its I/O base */ @@ -773,7 +773,7 @@ int emac_initialize(int intf) priv->d_dev.d_addmac = emac_addmac; /* Add multicast MAC address */ priv->d_dev.d_rmmac = emac_rmmac; /* Remove multicast MAC address */ #endif - priv->d_dev.d_private = (void*)g_emac; /* Used to recover private state from dev */ + priv->d_dev.d_private = priv; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmissions */ diff --git a/arch/x86/src/qemu/qemu.h b/arch/x86/src/qemu/qemu.h index 80eceb18b30..707e3781249 100644 --- a/arch/x86/src/qemu/qemu.h +++ b/arch/x86/src/qemu/qemu.h @@ -89,7 +89,7 @@ struct spi_dev_s; /* Forward reference */ * Name: i486_clockconfig * * Description: - * Called to initialize the LPC17XX. This does whatever setup is needed to put the + * Called to initialize the i486. This does whatever setup is needed to put the * MCU in a usable state. This includes the initialization of clocking using the * settings in board.h. * @@ -219,7 +219,7 @@ FAR struct spi_dev_s *i486_spibus_initialize(int port); * These external functions must be provided by board-specific logic. They are * implementations of the select, status, and cmddata methods of the SPI interface * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including i486_spibus_initialize()) are provided by common LPC17xx logic. To use + * including i486_spibus_initialize()) are provided by common i486 logic. To use * this common SPI logic on your board: * * 1. Provide logic in i486_boardinitialize() to configure SPI/SSP chip select diff --git a/configs/Kconfig b/configs/Kconfig index 783391822f1..b88625a212e 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -409,14 +409,6 @@ config ARCH_BOARD_LM4F120_LAUNCHPAD ---help--- Stellaris LM4F120 LaunchPad. -config ARCH_BOARD_LPCXPRESSO_LPC1115 - bool "NXP LPCXpresso LPC1115" - depends on ARCH_CHIP_LPC1115 - select ARCH_HAVE_LEDS - ---help--- - The Embedded Artists LPCXpresso LPC1115 board featuring the NXP - LPC1115 MCU. - config ARCH_BOARD_LPCXPRESSO bool "NXP LPCExpresso LPC1768" depends on ARCH_CHIP_LPC1768 @@ -443,6 +435,28 @@ config ARCH_BOARD_BAMBINO_200E ---help--- Micromint Bambino board. This board is based on the LPC4330FBD144. +config ARCH_BOARD_LPC4088_DEVKIT + bool "LPC4088 Developer's Kit" + depends on ARCH_CHIP_LPC4088 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Embedded Artists LPC4088 Developer's Kit. See + https://www.embeddedartists.com/products/lpc4088-developers-kit/ + for further information. This board uses the NXP LPC4088FET208 MCU. + +config ARCH_BOARD_LPC4088_QUICKSTART + bool "LPC4088 QuickStart Board" + depends on ARCH_CHIP_LPC4088 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Embedded Artists LPC4088 QuickStart Board. See + https://www.embeddedartists.com/products/lpc4088-quickstart-board/ + for further information. This board uses the NXP LPC4088FET208 MCU. + config ARCH_BOARD_LPC4330_XPLORER bool "NXG LPC4330-Xplorer" depends on ARCH_CHIP_LPC4330FET100 @@ -1881,11 +1895,12 @@ config ARCH_BOARD default "lm3s6965-ek" if ARCH_BOARD_LM3S6965EK default "lm3s8962-ek" if ARCH_BOARD_LM3S8962EK default "lm4f120-launchpad" if ARCH_BOARD_LM4F120_LAUNCHPAD + default "lpc4088-devkit" if ARCH_BOARD_LPC4088_DEVKIT + default "lpc4088-quickstart" if ARCH_BOARD_LPC4088_QUICKSTART default "lpc4330-xplorer" if ARCH_BOARD_LPC4330_XPLORER default "lpc4337-ws" if ARCH_BOARD_LPC4337_WS default "lpc4357-evb" if ARCH_BOARD_LPC4357_EVB default "lpc4370-link2" if ARCH_BOARD_LPC4370_LINK2 - default "lpcxpresso-lpc1115" if ARCH_BOARD_LPCXPRESSO_LPC1115 default "lpcxpresso-lpc1768" if ARCH_BOARD_LPCXPRESSO default "lpcxpresso-lpc54628" if ARCH_BOARD_LPCXPRESSO_LPC54628 default "maple" if ARCH_BOARD_MAPLE @@ -2172,6 +2187,12 @@ endif if ARCH_BOARD_LM3S8962EK source "configs/lm4f120-launchpad/Kconfig" endif +if ARCH_BOARD_LPC4088_DEVKIT +source "configs/lpc4088-devkit/Kconfig" +endif +if ARCH_BOARD_LPC4088_QUICKSTART +source "configs/lpc4088-quickstart/Kconfig" +endif if ARCH_BOARD_LPC4330_XPLORER source "configs/lpc4330-xplorer/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index 2e94e3f80f9..04eaa956d47 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -338,10 +338,6 @@ configs/lm4f120-launchpad platform for ARM® Cortex™-M4F-based microcontrollers from Texas Instruments. -configs/lpcxpresso-lpc1115 - NuttX board support for the Embedded Artists LPCXpresso LPC1115 board - featuring the NXP LPC1115 MCU. - configs/lpcxpresso-lpc1768 Embedded Artists base board with NXP LPCExpresso LPC1768. This board is based on the NXP LPC1768. The Code Red toolchain is used by default. diff --git a/configs/bambino-200e/README.txt b/configs/bambino-200e/README.txt index b7cb0ec47e5..7855135611a 100644 --- a/configs/bambino-200e/README.txt +++ b/configs/bambino-200e/README.txt @@ -306,7 +306,7 @@ Bambino-200e Configuration Options CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY CONFIG_LPC43_AUTONEG - Enable auto-negotion - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb CONFIG_LPC43_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 CONFIG_LPC43_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs @@ -327,7 +327,7 @@ Bambino-200e Configuration Options CONFIG_LPC43_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. CONFIG_LPC43_USBDEV_DMA - Enable lpc17xx-specific DMA support + Enable lpc17xx/lpc40xx-specific DMA support CONFIG_LPC43_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal CONFIG_LPC43_USBDEV_NOLED diff --git a/configs/lincoln60/README.txt b/configs/lincoln60/README.txt index 7147db6049a..5b1a2589236 100644 --- a/configs/lincoln60/README.txt +++ b/configs/lincoln60/README.txt @@ -110,41 +110,41 @@ Lincoln 60 Configuration Options CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. Individual subsystems can be enabled: - CONFIG_LPC17_MAINOSC=y - CONFIG_LPC17_PLL0=y - CONFIG_LPC17_PLL1=n - CONFIG_LPC17_ETHERNET=n - CONFIG_LPC17_USBHOST=n - CONFIG_LPC17_USBOTG=n - CONFIG_LPC17_USBDEV=n - CONFIG_LPC17_UART0=y - CONFIG_LPC17_UART1=n - CONFIG_LPC17_UART2=n - CONFIG_LPC17_UART3=n - CONFIG_LPC17_CAN1=n - CONFIG_LPC17_CAN2=n - CONFIG_LPC17_SPI=n - CONFIG_LPC17_SSP0=n - CONFIG_LPC17_SSP1=n - CONFIG_LPC17_I2C0=n - CONFIG_LPC17_I2C1=n - CONFIG_LPC17_I2S=n - CONFIG_LPC17_TMR0=n - CONFIG_LPC17_TMR1=n - CONFIG_LPC17_TMR2=n - CONFIG_LPC17_TMR3=n - CONFIG_LPC17_RIT=n - CONFIG_LPC17_PWM0=n - CONFIG_LPC17_MCPWM=n - CONFIG_LPC17_QEI=n - CONFIG_LPC17_RTC=n - CONFIG_LPC17_WDT=n - CONFIG_LPC17_ADC=n - CONFIG_LPC17_DAC=n - CONFIG_LPC17_GPDMA=n - CONFIG_LPC17_FLASH=n + CONFIG_LPC17_40_MAINOSC=y + CONFIG_LPC17_40_PLL0=y + CONFIG_LPC17_40_PLL1=n + CONFIG_LPC17_40_ETHERNET=n + CONFIG_LPC17_40_USBHOST=n + CONFIG_LPC17_40_USBOTG=n + CONFIG_LPC17_40_USBDEV=n + CONFIG_LPC17_40_UART0=y + CONFIG_LPC17_40_UART1=n + CONFIG_LPC17_40_UART2=n + CONFIG_LPC17_40_UART3=n + CONFIG_LPC17_40_CAN1=n + CONFIG_LPC17_40_CAN2=n + CONFIG_LPC17_40_SPI=n + CONFIG_LPC17_40_SSP0=n + CONFIG_LPC17_40_SSP1=n + CONFIG_LPC17_40_I2C0=n + CONFIG_LPC17_40_I2C1=n + CONFIG_LPC17_40_I2S=n + CONFIG_LPC17_40_TMR0=n + CONFIG_LPC17_40_TMR1=n + CONFIG_LPC17_40_TMR2=n + CONFIG_LPC17_40_TMR3=n + CONFIG_LPC17_40_RIT=n + CONFIG_LPC17_40_PWM0=n + CONFIG_LPC17_40_MCPWM=n + CONFIG_LPC17_40_QEI=n + CONFIG_LPC17_40_RTC=n + CONFIG_LPC17_40_WDT=n + CONFIG_LPC17_40_ADC=n + CONFIG_LPC17_40_DAC=n + CONFIG_LPC17_40_GPDMA=n + CONFIG_LPC17_40_FLASH=n - LPC17xx specific device driver settings + LPC17xx/LPC40xx specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -157,78 +157,78 @@ Lincoln 60 Configuration Options CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_UARTn_2STOP - Two stop bits - LPC17xx specific CAN device driver settings. These settings all + LPC17xx/LPC40xx specific CAN device driver settings. These settings all require CONFIG_CAN: CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. - CONFIG_LPC17_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 + CONFIG_LPC17_40_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN1 is defined. - CONFIG_LPC17_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 + CONFIG_LPC17_40_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN2 is defined. - CONFIG_LPC17_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN_TSEG1 - The number of CAN time quanta in segment 1. + CONFIG_LPC17_40_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2. + CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 - LPC17xx specific PHY/Ethernet device driver settings. These setting - also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + LPC17xx/LPC40xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_40_ETHERNET. CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY - CONFIG_LPC17_PHY_AUTONEG - Enable auto-negotion - CONFIG_LPC17_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. - CONFIG_LPC17_PHY_FDUPLEX - Select full (vs. half) duplex + CONFIG_LPC17_40_PHY_AUTONEG - Enable auto-negotion + CONFIG_LPC17_40_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_LPC17_40_PHY_FDUPLEX - Select full (vs. half) duplex - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb - CONFIG_LPC17_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 - CONFIG_LPC17_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 - CONFIG_LPC17_ETH_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_WOL - Enable Wake-up on Lan (not fully implemented). CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. Also needs CONFIG_DEBUG_FEATURES. - CONFIG_LPC17_ETH_HASH - Enable receipt of near-perfect match frames. - CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + CONFIG_LPC17_40_ETH_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_40_MULTICAST - Enable receipt of multicast (and unicast) frames. Automatically set if CONFIG_NET_MCASTGROUP is selected. - LPC17xx USB Device Configuration + LPC17xx/LPC40xx USB Device Configuration - CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT Handle USB Start-Of-Frame events. Enable reading SOF from interrupt handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. - CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT Enable high priority interrupts. I have no idea why you might want to do that - CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. - CONFIG_LPC17_USBDEV_DMA - Enable lpc17xx-specific DMA support - CONFIG_LPC17_USBDEV_NOVBUS + CONFIG_LPC17_40_USBDEV_DMA + Enable lpc17xx/lpc40xx-specific DMA support + CONFIG_LPC17_40_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal - CONFIG_LPC17_USBDEV_NOLED + CONFIG_LPC17_40_USBDEV_NOLED Define if the hardware implementation does not support the LED output - LPC17xx USB Host Configuration + LPC17xx/LPC40xx USB Host Configuration - CONFIG_LPC17_OHCIRAM_SIZE + CONFIG_LPC17_40_OHCIRAM_SIZE Total size of OHCI RAM (in AHB SRAM Bank 1) CONFIG_LP17_USBHOST_NEDS Number of endpoint descriptors CONFIG_LP17_USBHOST_NTDS Number of transfer descriptors - CONFIG_LPC17_USBHOST_TDBUFFERS + CONFIG_LPC17_40_USBHOST_TDBUFFERS Number of transfer descriptor buffers - CONFIG_LPC17_USBHOST_TDBUFSIZE + CONFIG_LPC17_40_USBHOST_TDBUFSIZE Size of one transfer descriptor buffer - CONFIG_LPC17_USBHOST_IOBUFSIZE + CONFIG_LPC17_40_USBHOST_IOBUFSIZE Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. @@ -250,7 +250,7 @@ host operations. To make these modifications, do the following: 2. Then edit the top-level .config file to enable USB host. Make the following changes: - CONFIG_LPC17_USBHOST=y + CONFIG_LPC17_40_USBHOST=y CONFIG_USBHOST=y CONFIG_SCHED_WORKQUEUE=y diff --git a/configs/lincoln60/include/board.h b/configs/lincoln60/include/board.h index a7c7acac1f3..9c707e7ee65 100644 --- a/configs/lincoln60/include/board.h +++ b/configs/lincoln60/include/board.h @@ -44,7 +44,7 @@ #include #include -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) # include #endif @@ -53,7 +53,7 @@ ****************************************************************************/ /* Clocking ****************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -69,14 +69,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz*/ +#define LPC17_40_CCLK 80000000 /* 80Mhz*/ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -95,8 +95,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -107,7 +107,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -124,8 +124,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 #define BOARD_FLASHCFG_VALUE 0x0000303a /* Ethernet configuration */ @@ -146,7 +146,7 @@ #define LED_STACKCREATED 3 /* OFF OFF */ /* After the system is booted, this logic will no longer use LEDs 1 & 2. - * They are available for use the application software using lpc17_led + * They are available for use the application software using lpc17_40_led * (prototyped below) */ /* LED1 LED2 LED3 LED4 */ @@ -200,7 +200,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control @@ -209,7 +209,7 @@ extern "C" ****************************************************************************/ #ifdef CONFIG_ARCH_LEDS -void lpc17_led(int lednum, int state); +void lpc17_40_led(int lednum, int state); #endif #undef EXTERN diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index d13f5b84ed1..6ffbe683a50 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lincoln60" CONFIG_ARCH_BOARD_LINCOLN60=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_INTERRUPTSTACK=1536 CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y @@ -19,13 +19,13 @@ CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_ETH0_PHY_KSZ8041=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SSP0=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SSP0=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 46c85664465..1ab2d844126 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -11,13 +11,13 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lincoln60" CONFIG_ARCH_BOARD_LINCOLN60=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_FS_FAT=y -CONFIG_LPC17_SSP0=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_SSP0=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/lincoln60/src/Makefile b/configs/lincoln60/src/Makefile index 07b3b39fde5..f2818c05609 100644 --- a/configs/lincoln60/src/Makefile +++ b/configs/lincoln60/src/Makefile @@ -36,18 +36,18 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c +CSRCS = lpc17_40_boot.c lpc17_40_leds.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += lpc17_buttons.c +CSRCS += lpc17_40_buttons.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/lincoln60/src/lincoln60.h b/configs/lincoln60/src/lincoln60.h index 0f137239801..9b9a50e5b47 100644 --- a/configs/lincoln60/src/lincoln60.h +++ b/configs/lincoln60/src/lincoln60.h @@ -74,7 +74,7 @@ /* Button IRQ numbers */ -#define LINCOLN60_BUT1_IRQ LPC17_IRQ_P0p23 +#define LINCOLN60_BUT1_IRQ LPC17_40_IRQ_P0p23 /**************************************************************************** * microSD PIN SIGNAL NAME diff --git a/configs/lincoln60/src/lpc17_appinit.c b/configs/lincoln60/src/lpc17_40_appinit.c similarity index 98% rename from configs/lincoln60/src/lpc17_appinit.c rename to configs/lincoln60/src/lpc17_40_appinit.c index d5c575da8ec..fed1d0db600 100644 --- a/configs/lincoln60/src/lpc17_appinit.c +++ b/configs/lincoln60/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/lincoln60/src/lpc17_appinit.c + * config/lincoln60/src/lpc17_40_appinit.c * * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/lincoln60/src/lpc17_boot.c b/configs/lincoln60/src/lpc17_40_boot.c similarity index 93% rename from configs/lincoln60/src/lpc17_boot.c rename to configs/lincoln60/src/lpc17_40_boot.c index 36be2b997ad..6653259aafd 100644 --- a/configs/lincoln60/src/lpc17_boot.c +++ b/configs/lincoln60/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/lincoln60/src/lpc17_boot.c + * configs/lincoln60/src/lpc17_40_boot.c * * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -62,16 +62,16 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/lincoln60/src/lpc17_buttons.c b/configs/lincoln60/src/lpc17_40_buttons.c similarity index 95% rename from configs/lincoln60/src/lpc17_buttons.c rename to configs/lincoln60/src/lpc17_40_buttons.c index 7a9981db8d6..fe08e33ccff 100644 --- a/configs/lincoln60/src/lpc17_buttons.c +++ b/configs/lincoln60/src/lpc17_40_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/lincoln60/src/lpc17_buttons.c + * configs/lincoln60/src/lpc17_40_buttons.c * * Copyright (C) 2012-2013, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,7 +48,7 @@ #include -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lincoln60.h" #ifdef CONFIG_ARCH_BUTTONS @@ -69,7 +69,7 @@ static const uint16_t g_buttoncfg[NUM_BUTTONS] = LINCOLN60_BUT1 }; -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) /* This array provides the mapping from button ID numbers to button IRQ * numbers. */ @@ -107,7 +107,7 @@ void board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - lpc17_configgpio(g_buttoncfg[i]); + lpc17_40_configgpio(g_buttoncfg[i]); } } @@ -138,7 +138,7 @@ uint32_t board_buttons(void) { /* A LOW value means that the key is pressed. */ - bool released = lpc17_gpioread(g_buttoncfg[i]); + bool released = lpc17_40_gpioread(g_buttoncfg[i]); /* Accumulate the set of depressed (not released) keys */ @@ -171,7 +171,7 @@ uint32_t board_buttons(void) * ****************************************************************************/ -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { irqstate_t flags; diff --git a/configs/lincoln60/src/lpc17_leds.c b/configs/lincoln60/src/lpc17_40_leds.c similarity index 90% rename from configs/lincoln60/src/lpc17_leds.c rename to configs/lincoln60/src/lpc17_40_leds.c index b1ce7eb8e05..bbb0dd62f8a 100644 --- a/configs/lincoln60/src/lpc17_leds.c +++ b/configs/lincoln60/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/lincoln60/src/lpc17_leds.c + * configs/lincoln60/src/lpc17_40_leds.c * * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lincoln60.h" @@ -63,7 +63,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) lpc17_dumpgpio(LINCOLN60_LED2, m) +# define led_dumpgpio(m) lpc17_40_dumpgpio(LINCOLN60_LED2, m) #else # define led_dumpgpio(m) #endif @@ -87,7 +87,7 @@ IRQSENABLED OFF BLUE STACKCREATED OFF OFF After the system is booted, this logic will no longer use LEDs 1 & 2. They -are available for use by applications using lpc17_led (prototyped below) +are available for use by applications using lpc17_40_led (prototyped below) */ static bool g_initialized; @@ -111,8 +111,8 @@ void board_autoled_initialize(void) led_dumpgpio("board_autoled_initialize() Entry)"); - lpc17_configgpio(LINCOLN60_LED1); - lpc17_configgpio(LINCOLN60_LED2); + lpc17_40_configgpio(LINCOLN60_LED1); + lpc17_40_configgpio(LINCOLN60_LED2); led_dumpgpio("board_autoled_initialize() Exit"); } @@ -144,8 +144,8 @@ void board_autoled_on(int led) case LED_IRQSENABLED: led2 = 1; } - lpc17_led(LINCOLN60_LED1,led1); - lpc17_led(LINCOLN60_LED2,led2); + lpc17_40_led(LINCOLN60_LED1,led1); + lpc17_40_led(LINCOLN60_LED2,led2); } /* We will always control the HB LED */ @@ -156,7 +156,7 @@ void board_autoled_on(int led) case LED_SIGNAL: case LED_ASSERTION: case LED_PANIC: - lpc17_gpiowrite(LINCOLN60_HEARTBEAT, false); + lpc17_40_gpiowrite(LINCOLN60_HEARTBEAT, false); g_nestcount++; default: @@ -174,7 +174,7 @@ void board_autoled_off(int led) if (g_nestcount <= 1) { - lpc17_led(LINCOLN60_HEARTBEAT, true); + lpc17_40_led(LINCOLN60_HEARTBEAT, true); g_nestcount = 0; } else @@ -184,16 +184,16 @@ void board_autoled_off(int led) } /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control the LEDs * ************************************************************************************/ -void lpc17_led(int lednum, int state) +void lpc17_40_led(int lednum, int state) { - lpc17_gpiowrite(lednum, state); + lpc17_40_gpiowrite(lednum, state); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 5e8e00f34ee..6624dbf510f 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lincoln60" CONFIG_ARCH_BOARD_LINCOLN60=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y @@ -28,12 +28,12 @@ CONFIG_FS_UNIONFS=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 -CONFIG_LPC17_EMACRAM_SIZE=9696 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=8 -CONFIG_LPC17_ETH_NTXDESC=8 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=9696 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=8 +CONFIG_LPC17_40_ETH_NTXDESC=8 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/lpc4088-devkit/Kconfig b/configs/lpc4088-devkit/Kconfig new file mode 100644 index 00000000000..d5382839b7d --- /dev/null +++ b/configs/lpc4088-devkit/Kconfig @@ -0,0 +1,18 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_LPC4088_DEVKIT + +config LPC4088_DEVKIT_DJOYSTICK + bool "Discrete Joystick Support" + default n + depends on !ARCH_BUTTONS && DJOYSTICK + +config LPC4088_DEVKIT_DJOYDEV + string "Joystick Device" + default "/dev/djoy0" + depends on LPC4088_DEVKIT_DJOYSTICK + +endif diff --git a/configs/lpc4088-devkit/README.txt b/configs/lpc4088-devkit/README.txt new file mode 100644 index 00000000000..06381f95f05 --- /dev/null +++ b/configs/lpc4088-devkit/README.txt @@ -0,0 +1,383 @@ +README.txt +========== + + This README file discusses the port of NuttX to the Embedded Artists LPC4088 + Developer's Kit board: + See https://www.embeddedartists.com/products/lpc4088-developers-kit/ + This board features the NXP LPC4088FET208 MCU on a carrier board called + the LPC4088 OEM Board. + +CONTENTS +======== + + o LEDs + o Buttons + o Serial Console + o Using OpenOCD with the Olimex ARM-USB-OCD + o Loading Code with the ISP Board + o Configuration + +LEDs +==== + + The LPC4088 OEM board has two user LEDs on GPIO pins: + + LED1 : Connected to P2[26] + LED2 : Connected to P2[27] + + If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + any way using the defitions provided in the board.h header file. + + If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on the + LPC4088 OEM board. The following definitions describe how NuttX controls + the LEDs: + LED1 LED2 LED3 LED4 + LED_STARTED OFF OFF OFF OFF + LED_HEAPALLOCATE ON OFF OFF OFF + LED_IRQSENABLED OFF ON OFF OFF + LED_STACKCREATED ON ON OFF OFF + LED_INIRQ LED3 glows, on while in interrupt + LED_SIGNAL LED3 glows, on while in signal handler + LED_ASSERTION LED3 glows, on while in assertion + LED_PANIC LED3 Flashes at 2Hz + LED_IDLE LED glows: ON while active; OFF while sleeping + + Several additional LEDs are available on a PCA9532 port expander, which is + not currently enabled. +Buttons +======= + + The LPC4088 Developer's Kit supports a button: + + USER1 : Connected to P2[10] + + And a Joystick + + JOY_A : Connected to P2[23] + JOY_B : Connected to P2[25] + JOY_C : Connected to P2[26] + JOY_D : Connected to P2[27] + JOY_CTR : Connected to P2[22] + + These can be accessed using the definitions and interfaces defined in the + board.h header file. + + Several additional buttons are available on a PCA9532 port expander, which is + not currently enabled. + +Serial Console +============== + + By Default, UART0 is used as the serial console in all configurations. This + may be connected to your computer via the onboard FT232 USB to UART chip. + + As an option, UART1 can also be used for the serial console. You might want, + to do this, for example, if you use UART0 for the ISP function and you want + to use a different UART for console output. UART1 can be configured as the + serial console by changing the configuration as follows: + + System Type: + CONFIG_LPC17_40_UART0=n : Disable UART0 if it is no longer used + CONFIG_LPC17_40_UART1=y : Enable UART1 + + Drivers: + CONFIG_UART1_SERIAL_CONSOLE=y : Setup up the UART1 configuration + CONFIG_UART1_RXBUFSIZE=256 + CONFIG_UART1_TXBUFSIZE=256 + CONFIG_UART1_BAUD=115200 + CONFIG_UART1_BITS=8 + CONFIG_UART1_PARITY=0 + CONFIG_UART1_2STOP=0 + + In this configuration using UART1, the jumpers JP12 and JP13 must be set to + short pins 1 and 2. UART 1 will then be available on the DB9 connector J17. + +Using OpenOCD with the Olimex ARM-USB-OCD +========================================= + + Building OpenOCD under Cygwin: + + Refer to configs/olimex-lpc1766stk/README.txt + + Installing OpenOCD in Ubuntu Linux: + + sudo apt-get install openocd + + Helper Scripts. + + I have been using the Olimex ARM-USB-OCD debugger. OpenOCD + requires a configuration file. I keep the one I used last here: + + configs/lpc4088-devkit/tools/lpc4088-devkit.cfg + + However, the "correct" configuration script to use with OpenOCD may + change as the features of OpenOCD evolve. So you should at least + compare that lpc4088-devkit.cfg file with configuration files in + /usr/share/openocd/scripts. As of this writing, the configuration + files of interest were: + + /usr/local/share/openocd/scripts/interface/openocd-usb.cfg + This is the configuration file for the Olimex ARM-USB-OCD + debugger. Select a different file if you are using some + other debugger supported by OpenOCD. + + /usr/local/share/openocd/scripts/board/? + I don't see a board configuration file for the LPC4088 developer's kit. + + /usr/local/share/openocd/scripts/target/lpc40xx.cfg + This is the configuration file for the LPC4088 target. + It just sets up a few parameters then sources lpc1xxx.cfg + + /usr/local/share/openocd/scripts/target/lpc1xxx.cfg + This is the generic LPC configuration for the LPC1xxx + family. It is included by lpc40xx.cfg. + + NOTE: These files could also be located under /usr/share in some + installations. They could be most anywhwere if you are using a + windows version of OpenOCD. + + configs/lpc4088-devkit/tools/lpc4088-devkit.cfg + This is simply openocd-usb.cfg, lpc40xx.cfg, and lpc1xxx.cfg + concatenated into one file for convenience. Don't use it + unless you have to. + + There is also a script on the tools/ directory that I use to start + the OpenOCD daemon on my system called oocd.sh. That script will + probably require some modifications to work in another environment: + + - Possibly the value of OPENOCD_PATH and TARGET_PATH + - It assumes that the correct script to use is the one at + configs/lpc4088-devkit/tools/lpc4088-devkit.cfg + + Starting OpenOCD + + Then you should be able to start the OpenOCD daemon as follows. This + assumes that you have already CD'ed to the NuttX build directory and + that you have set the full path to the configs/lpc4088-devkit/tools in your + PATH environment variable: + + oocd.sh $PWD + + or, if the PATH variable is not so configured: + + configs/lpc4088-devkit/tools/oocd.sh $PWD + + Connecting GDB + + Once the OpenOCD daemon has been started, you can connect to it via + GDB using the following GDB command: + + arm-nuttx-elf-gdb + (gdb) target remote localhost:3333 + + NOTE: The name of your GDB program may differ. For example, with the + CodeSourcery toolchain, the ARM GDB would be called arm-none-eabi-gdb. + + OpenOCD will support several special 'monitor' sub-commands. You can + use the 'monitor' (or simply 'mon') command to invoke these sub- + commands. These GDB commands will send comments to the OpenOCD monitor. + Here are a couple that you will need to use: + + (gdb) monitor reset + (gdb) monitor halt + + NOTES: + + 1. The MCU must be halted using 'monitor halt' prior to loading code. + + 2. 'monitor reset' will restart the processor after loading code. + + 3. The 'monitor' command can be abbreviated as just 'mon'. + + After starting GDB, you can load the NuttX ELF file like this: + + (gdb) mon halt + (gdb) load nuttx + + NOTES: + + 1. NuttX should have been built so that it has debugging symbols + (by setting CONFIG_DEBUG_SYMBOLS=y in the .config file). + + 2. The MCU must be halted prior to loading code. + + 3. I find that there are often undetected write failures when using + the Olimex ARM-USB-OCD debugber and that if you start the program + with a bad FLASH failure, it will lock up OpenOCD. I usually + oad nuttx twice, restarting OpenOCD in between in order to assure + good FLASH contents: + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset + + Exit GDB, kill the OpenOCD server, recycle power on the board, + restart the OpenOCD server and GDB, then: + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset + + Other debuggers may not have these issues and such drastic steps may + not be necessary. + +Loading Code with the ISP Board +=============================== + + Users can also load code onto the board using the UART0 USB VCOM chip. + I use the FlashMagic program for Windows available here: + http://www.flashmagictool.com/ . It is so easy to use that no further + explanation should be necessary: Just select the LPC4088, the ISP COM + port, and the NuttX .hex file and program it. + +CONFIGURATION +============= + +Information Common to All Configurations +---------------------------------------- + + 1. These configurations use the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository + README.txt. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Most (but not all) configurations use the "GNU Tools for ARM + Embedded Processors" that is maintained by ARM: + + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + + unless otherwise stated. + + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + + 3. By Default, UART0 is used as the serial console in all configurations. + This may be connected to your computer via an external RS-232 driver or + via the on board USB VCOM chip. See the section above entitled + "Serial Console" for other options. + + 4. An LCD is available for this board, but I don't have one to test with. + If you wish to use any of the configurations below which utilize the LCD, + you will need to tweak the LCD pin definitions in board.h. + +Configuration Directories +------------------------- + + knsh + ---- + This is identical to the nsh configuration below except that NuttX + is built as a kernel-mode, monolithic module and the user applications + are built separately. Is is recommened to use a special make command; + not just 'make' but make with the following two arguments: + + make pass1 pass2 + + In the normal case (just 'make'), make will attempt to build both user- + and kernel-mode blobs more or less interleaved. This actual works! + However, for me it is very confusing so I prefer the above make command: + Make the user-space binaries first (pass1), then make the kernel-space + binaries (pass2) + + 1. Uses the older, OABI, buildroot toolchain. But that is easily + reconfigured: + + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain + + 2. This configuration has DMA-based SD card support enabled by + default. That support can be disabled as follow: + + CONFIG_LPC17_40_GPDMA=n : No DMA + CONFIG_ARCH_DMA=n + CONFIG_LPC17_40_SDCARD=n : No SD card driver + CONFIG_SDIO_DMA=n : No SD card DMA + CONFIG_MMCSD=n : No MMC/SD driver support + CONFIG_FS_FAT=n : No FAT file system support + + 3. At the end of the build, there will be several files in the top-level + NuttX build directory: + + PASS1: + nuttx_user.elf - The pass1 user-space ELF file + nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) + User.map - Symbols in the user-space ELF file + + PASS2: + nuttx - The pass2 kernel-space ELF file + nuttx.hex - The pass2 Intel HEX file (selected in defconfig) + System.map - Symbols in the kernel-space ELF file + + Loading these .elf files with OpenOCD is tricky. It appears to me + that when nuttx_user.elf is loaded, it destroys the nuttx image + in FLASH. But loading the nuttx ELF does not harm the nuttx_user.elf + in FLASH. Conclusion: Always load nuttx_user.elf before nuttx. + + Just to complicate matters, it is sometimes the case that you need + load objects twice to account for write failures. I have not yet + found a simple foolproof way to reliably get the code into FLASH. + + 4. Combining .hex files. If you plan to use the .hex files with your + debugger or FLASH utility, then you may need to combine the two hex + files into a single .hex file. Here is how you can do that. + + a. The 'tail' of the nuttx.hex file should look something like this + (with my comments added): + + $ tail nuttx.hex + # 00, data records + ... + :10 9DC0 00 01000000000800006400020100001F0004 + :10 9DD0 00 3B005A0078009700B500D400F300110151 + :08 9DE0 00 30014E016D0100008D + # 05, Start Linear Address Record + :04 0000 05 0800 0419 D2 + # 01, End Of File record + :00 0000 01 FF + + Use an editor such as vi to remove the 05 and 01 records. + + b. The 'head' of the nuttx_user.hex file should look something like + this (again with my comments added): + + $ head nuttx_user.hex + # 04, Extended Linear Address Record + :02 0000 04 0801 F1 + # 00, data records + :10 8000 00 BD89 01084C800108C8110208D01102087E + :10 8010 00 0010 00201C1000201C1000203C16002026 + :10 8020 00 4D80 01085D80010869800108ED83010829 + ... + + Nothing needs to be done here. The nuttx_user.hex file should + be fine. + + c. Combine the edited nuttx.hex and un-edited nuttx_user.hex + file to produce a single combined hex file: + + $ cat nuttx.hex nuttx_user.hex >combined.hex + + Then use the combined.hex file with the to write the FLASH image. + If you do this a lot, you will probably want to invest a little time + to develop a tool to automate these steps. + + STATUS: + 2019-04-23: Untested with LPC4088. + + nsh + --- + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables both the serial NSH interface as well as the + telnet interface over ethernet, with an IP address assigned via DHCP. + diff --git a/configs/lpc4088-devkit/include/board.h b/configs/lpc4088-devkit/include/board.h new file mode 100644 index 00000000000..ef49c026cfc --- /dev/null +++ b/configs/lpc4088-devkit/include/board.h @@ -0,0 +1,439 @@ +/************************************************************************************ + * configs/lpc4088-devkit/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_LPC4088_DEVKIT_INCLUDE_BOARD_H +#define __CONFIG_LPC4088_DEVKIT_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Clocking *************************************************************************/ +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here + * because the including C file may not have that file in its include path. + */ + +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ +#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ +#define BOARD_WDTOSC_FREQUENCY (500000) /* WDT oscillator frequency */ + +/* This is the clock setup we configure for: + * + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multipler=10, pre-divider=1 + * CCLCK = 120MHz -> CCLK divider = 1 + */ + +#define LPC17_40_CCLK 120000000 /* 120Mhz */ +#define BOARD_PCLKDIV 2 /* Peripheral clock = LPC17_40_CCLK/2 */ +#define BOARD_PCLK_FREQUENCY (LPC17_40_CCLK / BOARD_PCLKDIV) + +/* Select the main oscillator as the frequency source. SYSCLK is then the frequency + * of the main oscillator. + * + * If BOARD_XTAL_FREQUENCY > 15000000, then the SCS OSCRS bit (bit 4) should also + * be set in the BOARD_SCS_VALUE. + */ + +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 +#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN + +/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. + * The input to the divider (PLLCLK) will be determined by the PLL output. + */ + +#define BOARD_CCLKSEL_DIVIDER 1 +#define BOARD_CCLKSEL_VALUE (BOARD_CCLKSEL_DIVIDER | SYSCON_CCLKSEL_CCLKSEL) + +/* PLL0. PLL0 is used to generate the CPU clock (PLLCLK). + * + * Source clock: Main oscillator + * PLL0 Multiplier value (M): 10 + * PLL0 Pre-divider value (P): 1 + * + * PLL0CLK = (M * SYSCLK) = 120MHz + */ + +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 +#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN + +#define BOARD_PLL0CFG_MSEL 10 +#define BOARD_PLL0CFG_PSEL 1 +#define BOARD_PLL0CFG_VALUE \ + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) + +/* PLL1 : PLL1 is used to generate clock for the USB */ + +#undef CONFIG_LPC17_40_PLL1 +#define BOARD_PLL1CFG_MSEL 4 +#define BOARD_PLL1CFG_PSEL 2 +#define BOARD_PLL1CFG_VALUE \ + (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) + +#ifdef CONFIG_LPC17_40_EMC +/* EMC clock selection. + * + * The EMC clock should not be driven above 80MHz. As a result the EMC + * uses the CPU clock divided by two. + */ + +# define BOARD_EMCCLKSEL_DIVIDER 2 +# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV2 +# define LPC17_40_EMCCLK (LPC17_40_CCLK / BOARD_EMCCLKSEL_DIVIDER) +#endif + +#if defined(CONFIG_LPC17_40_USBHOST) || (CONFIG_LPC17_40_USBDEV) +/* USB divider. The output of the PLL is used as the USB clock + * + * USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz + */ + +# define BOARD_USBCLKSEL_DIVIDER 1 +# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \ + SYSCON_USBCLKSEL_USBSEL_PLL1) +#endif + +/* FLASH Configuration */ + +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 + +/* Flash access use 6 CPU clocks - Safe for any allowed conditions */ + +#define BOARD_FLASHCFG_VALUE (SYSCON_FLASHCFG_TIM_5 | 0x03a) + +/* Ethernet configuration */ + +#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV48 + +#ifdef CONFIG_LPC17_40_SDCARD +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * SDCARD_CLOCK=PCLK/(2*(SDCARD_CLKDIV+1)) + */ + +# define SDCARD_CLKDIV_INIT 74 /* 400Khz */ +# define SDCARD_INIT_CLKDIV (SDCARD_CLKDIV_INIT) + +# define SDCARD_NORMAL_CLKDIV 1 /* DMA ON: SDCARD_CLOCK=15MHz */ +#define SDCARD_SLOW_CLKDIV 14 /* DMA OFF: SDCARD_CLOCK=2MHz */ + +# ifdef CONFIG_SDIO_DMA +# define SDCARD_MMCXFR_CLKDIV (SDCARD_NORMAL_CLKDIV) +# else +# define SDCARD_MMCXFR_CLKDIV (SDCARD_SLOW_CLKDIV) +# endif + +# ifdef CONFIG_SDIO_DMA +# define SDCARD_SDXFR_CLKDIV (SDCARD_NORMAL_CLKDIV) +# else +# define SDCARD_SDXFR_CLKDIV (SDCARD_SLOW_CLKDIV) +# endif +#endif + +/* Set EMC delay values: + * + * CMDDLY: Programmable delay value for EMC outputs in command delayed + * mode. The delay amount is roughly CMDDLY * 250 picoseconds. + * FBCLKDLY: Programmable delay value for the feedback clock that controls + * input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250 + * picoseconds. + * CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT0DLY+1) * 250 picoseconds. + * CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT1DLY+1) * 250 picoseconds. + * + * Optimal for NOR: {1,1,1,1} + * Needed for NAND and SDRAM: {17,1,2,1} + */ + +#ifdef CONFIG_LPC17_40_EMC +#if defined(CONFIG_LPC17_40_EXTNAND) || defined(CONFIG_LPC17_40_EXTDRAM) +# define BOARD_CMDDLY 17 +# define BOARD_FBCLKDLY 17 +# define BOARD_CLKOUT0DLY 1 +# define BOARD_CLKOUT1DLY 1 +#else +# define BOARD_CMDDLY 1 +# define BOARD_FBCLKDLY 1 +# define BOARD_CLKOUT0DLY 1 +# define BOARD_CLKOUT1DLY 1 +#endif +#endif + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 : Connected to P2[26] + * LED2 : Connected to P2[27] + * + * These LEDs are connected to ground so a high output value will illuminate them. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the two LEDs + * on the LPC4088 OEM Board. The following definitions describe how NuttX + * controls the LEDs: + */ + /* LED1 LED2 LED3 LED4 */ +#define LED_STARTED 0 /* OFF OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF OFF */ +#define LED_STACKCREATED 3 /* ON ON OFF OFF */ +#define LED_INIRQ 4 /* LED3 glows, on while in interrupt */ +#define LED_SIGNAL 4 /* LED3 glows, on while in signal handler */ +#define LED_ASSERTION 4 /* LED3 glows, on while in assertion */ +#define LED_PANIC 4 /* LED3 Flashes at 2Hz */ +#define LED_IDLE 5 /* LED4 glows: ON while active * + * OFF while sleeping */ + +/* Button definitions ***************************************************************/ +/* The LPC4088 Developer's Kit supports several buttons. All have external + * pullup resistors. When closed, the pins will be pulled to ground. So the buttons + * will read "1" when open and "0" when closed. All are capable of generating interrupts. + * + * USER1 -- Connected to P2[10] + * + * Joystick: + * + * JOY_A -- Connected to P2[23] + * JOY_B -- Connected to P2[25] + * JOY_C -- Connected to P2[26] + * JOY_D -- Connected to P2[27] + * JOY_CTR -- Connected to P2[22] + * + * For the interrupting buttons, interrupts are generated on both edges (press and + * release). + */ + + +#define BOARD_BUTTON_USER1 0 + +#define BOARD_JOYSTICK_A 1 +#define BOARD_JOYSTICK_B 2 +#define BOARD_JOYSTICK_C 3 +#define BOARD_JOYSTICK_D 4 +#define BOARD_JOYSTICK_CTR 5 + +#define NUM_BUTTONS 6 + +#define BOARD_BUTTON_USER1_BIT (1 << BOARD_BUTTON_USER1) + +#define BOARD_JOYSTICK_A_BIT (1 << BOARD_JOYSTICK_A) +#define BOARD_JOYSTICK_B_BIT (1 << BOARD_JOYSTICK_B) +#define BOARD_JOYSTICK_C_BIT (1 << BOARD_JOYSTICK_C) +#define BOARD_JOYSTICK_D_BIT (1 << BOARD_JOYSTICK_D) +#define BOARD_JOYSTICK_CTR_BIT (1 << BOARD_JOYSTICK_CTR) + +/* Alternate pin selections *********************************************************/ + +/* UART0: + * + * TX --- Connected to P0[2] + * RX --- Connected to P0[3] + */ + +#define GPIO_UART0_TXD GPIO_UART0_TXD_2 +#define GPIO_UART0_RXD GPIO_UART0_RXD_2 + +/* UART1: + * + * All pin options are controlled by jumpers on the board. + * RXD is set with JP12, TXD is set with JP13, modem control lines are set with JP11. + * + * RTS --- Connected to P3[30] + * RI --- Connected to P3[22] + * DSR --- Connected to P3[20] + * DCD --- Connected to P3[19] + * CTS --- Connected to P3[18] + * DTR --- Connected to P3[21] + * TXD --- Connected to P3[16] + * RXD --- Connected to P3[17] + */ + +#define GPIO_UART1_RTS GPIO_UART1_RTS_4 +#define GPIO_UART1_RI GPIO_UART1_RI_3 +#define GPIO_UART1_DSR GPIO_UART1_DSR_3 +#define GPIO_UART1_DCD GPIO_UART1_DCD_3 +#define GPIO_UART1_CTS GPIO_UART1_CTS_4 +#define GPIO_UART1_DTR GPIO_UART1_DTR_3 +#define GPIO_UART1_TXD GPIO_UART1_TXD_3 +#define GPIO_UART1_RXD GPIO_UART1_RXD_3 + +/* MCI-SDIO: + * + * D0 --- Connected to P1[6] + * D1 --- Connected to P1[7] + * D2 --- Connected to P1[11] + * D3 --- Connected to P1[12] + * CLK --- Connected to P1[2] + * CMD --- Connected to P1[3] + */ + +#define GPIO_SD_DAT0 GPIO_SD_DAT0_2 +#define GPIO_SD_DAT1 GPIO_SD_DAT1_1 +#define GPIO_SD_DAT2 GPIO_SD_DAT2_1 +#define GPIO_SD_DAT3 GPIO_SD_DAT3_1 +#define GPIO_SD_CLK GPIO_SD_CLK_2 +#define GPIO_SD_CMD GPIO_SD_CMD_2 + +/* Ethernet: + * MDC --- Connected to P1[16] + * MDIO --- Connected to P1[17] + */ + +#define GPIO_ENET_MDC GPIO_ENET_MDC_1 +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1 + + +/* External LCD is currently untested. + * These pins will probably need to be updated before using the LCD. */ + +#if 0 +/* LCD R: + * + * VD0 --- Connected to P0[4] + * VD1 --- Connected to P0[5] + * VD2 --- Connected to P4[28] + * VD3 --- Connected to P4[29] + * VD4 --- Connected to P2[6] + * VD5 --- Connected to P2[7] + * VD6 --- Connected to P2[8] + * VD7 --- Connected to P2[9] + */ + +#define GPIO_LCD_VD0 GPIO_LCD_VD0_1 +#define GPIO_LCD_VD1 GPIO_LCD_VD1_1 +#define GPIO_LCD_VD2 GPIO_LCD_VD2_2 +#define GPIO_LCD_VD3 GPIO_LCD_VD3_3 +#define GPIO_LCD_VD4 GPIO_LCD_VD4_1 +#define GPIO_LCD_VD5 GPIO_LCD_VD5_1 +#define GPIO_LCD_VD6 GPIO_LCD_VD6_2 +#define GPIO_LCD_VD7 GPIO_LCD_VD7_2 + +/* LCD G: + * + * VD8 --- Connected to P0[6] + * VD9 --- Connected to P0[7] + * VD10 --- Connected to P1[20] + * VD11 --- Connected to P1[21] + * VD12 --- Connected to P1[22] + * VD13 --- Connected to P1[23] + * VD14 --- Connected to P1[24] + * VD15 --- Connected to P1[25] + */ + +#define GPIO_LCD_VD8 GPIO_LCD_VD8_1 +#define GPIO_LCD_VD9 GPIO_LCD_VD9_1 +#define GPIO_LCD_VD10 GPIO_LCD_VD10_1 +#define GPIO_LCD_VD11 GPIO_LCD_VD11_1 +#define GPIO_LCD_VD12 GPIO_LCD_VD12_1 +#define GPIO_LCD_VD13 GPIO_LCD_VD13_1 +#define GPIO_LCD_VD14 GPIO_LCD_VD14_1 +#define GPIO_LCD_VD15 GPIO_LCD_VD15_1 + +/* LCD B: + * + * VD16 --- Connected to P0[8] + * VD17 --- Connected to P0[9] + * VD18 --- Connected to P2[12] + * VD19 --- Connected to P2[13] + * VD20 --- Connected to P1[26] + * VD21 --- Connected to P1[27] + * VD22 --- Connected to P1[28] + * VD23 --- Connected to P1[29] + * + * DCLK --- Connected to P2[2] + * LP --- Connected to P2[5] + * FP --- Connected to P2[3] + * ENAB_M --- Connected to P2[4] + * PWR --- Connected to P2[0] + */ + +/* XPT2046 Touchscreen: + * +/* -------------- -------------------- ------------ -------------------------------- + * XTPT2046 Module Module + * Signal Connector Connector + * -------------- -------------------- ------------ --------------------------------- + * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ + * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) + * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY + * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) + * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) + * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 + * -------------- -------------------- ------------ --------------------------------- + */ + + +#define GPIO_SSP1_MISO GPIO_SSP1_MISO_3 +#define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2 +#define GPIO_SSP1_SCK GPIO_SSP1_SCK_2 + +#endif + +#endif /* __CONFIG_LPC4088_DEVKIT_INCLUDE_BOARD_H */ diff --git a/configs/lpc4088-devkit/kernel/.gitignore b/configs/lpc4088-devkit/kernel/.gitignore new file mode 100644 index 00000000000..7bacd5aee3e --- /dev/null +++ b/configs/lpc4088-devkit/kernel/.gitignore @@ -0,0 +1,2 @@ +/nuttx_user.elf + diff --git a/configs/lpc4088-devkit/kernel/Makefile b/configs/lpc4088-devkit/kernel/Makefile new file mode 100644 index 00000000000..d3f84ce4a97 --- /dev/null +++ b/configs/lpc4088-devkit/kernel/Makefile @@ -0,0 +1,122 @@ +############################################################################ +# configs/lpc4088-devkit/kernel/Makefile +# +# Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +# This is the directory for the board-specific header files + +BOARD_INCLUDE = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)include + +# The entry point name (if none is provided in the .config file) + +CONFIG_USER_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_USER_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + USER_LIBPATHS = ${shell for path in $(USERLIBS); do dir=`dirname $(TOPDIR)$(DELIM)$$path`;echo "-L\"`cygpath -w $$dir`\"";done} + USER_LDSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld}" + USER_LDSCRIPT += -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)user-space.ld}" + USER_HEXFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.hex}" + USER_SRECFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.srec}" + USER_BINFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.bin}" +else + # Linux/Cygwin-native toolchain + USER_LIBPATHS = $(addprefix -L$(TOPDIR)$(DELIM),$(dir $(USERLIBS))) + USER_LDSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld + USER_LDSCRIPT += -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)user-space.ld + USER_HEXFILE += "$(TOPDIR)$(DELIM)nuttx_user.hex" + USER_SRECFILE += "$(TOPDIR)$(DELIM)nuttx_user.srec" + USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" +endif + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = lpc17_40_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/configs/lpc4088-devkit/kernel/lpc17_40_userspace.c b/configs/lpc4088-devkit/kernel/lpc17_40_userspace.c new file mode 100644 index 00000000000..f08ed38f82c --- /dev/null +++ b/configs/lpc4088-devkit/kernel/lpc17_40_userspace.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * configs/lpc4088-devkit/kernel/lpc17_40_userspace.c + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x00040000 +# error "CONFIG_NUTTX_USERSPACE must be 0x00040000 to match memory.ld" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. They are + * not actual uint32_t storage locations! They are only used meaningfully in the + * following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declareion extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data (it is + * not!). + * - We can recoved the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +extern uint32_t _stext; /* Start of .text */ +extern uint32_t _etext; /* End_1 of .text + .rodata */ +extern const uint32_t _eronly; /* End+1 of read only section (.text + .rodata) */ +extern uint32_t _sdata; /* Start of .data */ +extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _sbss; /* Start of .bss */ +extern uint32_t _ebss; /* End+1 of .bss */ + +/* This is the user space entry point */ + +int CONFIG_USER_ENTRYPOINT(int argc, char *argv[]); + +const struct userspace_s userspace __attribute__ ((section (".userspace"))) = +{ + /* General memory map */ + + .us_entrypoint = (main_t)CONFIG_USER_ENTRYPOINT, + .us_textstart = (uintptr_t)&_stext, + .us_textend = (uintptr_t)&_etext, + .us_datasource = (uintptr_t)&_eronly, + .us_datastart = (uintptr_t)&_sdata, + .us_dataend = (uintptr_t)&_edata, + .us_bssstart = (uintptr_t)&_sbss, + .us_bssend = (uintptr_t)&_ebss, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = task_startup, +#ifndef CONFIG_DISABLE_PTHREAD + .pthread_startup = pthread_startup, +#endif + + /* Signal handler trampoline */ + +#ifndef CONFIG_DISABLE_SIGNALS + .signal_handler = up_signal_handler, +#endif + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIB_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/configs/lpc4088-devkit/knsh/Make.defs b/configs/lpc4088-devkit/knsh/Make.defs new file mode 100644 index 00000000000..9bf039963a8 --- /dev/null +++ b/configs/lpc4088-devkit/knsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/lpc4088-devkit/knsh/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-m$(DELIM)Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld}" + ARCHSCRIPT += -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)kernel-space.ld}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld + ARCHSCRIPT += -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)kernel-space.ld +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/lpc4088-devkit/knsh/defconfig b/configs/lpc4088-devkit/knsh/defconfig new file mode 100644 index 00000000000..4c2cf1991b9 --- /dev/null +++ b/configs/lpc4088-devkit/knsh/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LPC17_40_EMC is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lpc4088-devkit" +CONFIG_ARCH_BOARD_LPC4088_DEVKIT=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y +CONFIG_ARCH_CHIP_LPC4088=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_OABI_TOOLCHAIN=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +CONFIG_ARM_MPU=y +CONFIG_BCH=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=11934 +CONFIG_BUILD_PROTECTED=y +CONFIG_DEV_LOOP=y +CONFIG_DISABLE_POLL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_DISABLE_DD=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x00040000 +CONFIG_PASS1_BUILDIR="configs/lpc4088-devkit/kernel" +CONFIG_PIPES=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x10000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=11 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2013 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYS_RESERVED=8 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpc4088-devkit/nsh/defconfig b/configs/lpc4088-devkit/nsh/defconfig new file mode 100644 index 00000000000..af9e9a03c4e --- /dev/null +++ b/configs/lpc4088-devkit/nsh/defconfig @@ -0,0 +1,96 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LPC17_40_EMC is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lpc4088-devkit" +CONFIG_ARCH_BOARD_LPC4088_DEVKIT=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y +CONFIG_ARCH_CHIP_LPC4088=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +CONFIG_BCH=y +CONFIG_BOARD_LOOPSPERMSEC=11934 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_LOOP=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_THROTTLE=0 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_MULTICAST=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_UART1=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_DHCPC=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_NETMASK=0xffff0000 +CONFIG_NSH_NOMAC=y +CONFIG_NSH_READLINE=y +CONFIG_NXFLAT=y +CONFIG_PIPES=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x10000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPNTHREADS=5 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPNTHREADS=4 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=176 +CONFIG_SCHED_LPWORKSTACKSIZE=3084 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=23 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2019 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_MDIO=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TCP_NOTIFIER=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpcxpresso-lpc1115/scripts/Make.defs b/configs/lpc4088-devkit/scripts/Make.defs similarity index 73% rename from configs/lpcxpresso-lpc1115/scripts/Make.defs rename to configs/lpc4088-devkit/scripts/Make.defs index 9ffed22e9d8..a37d8ee98fb 100644 --- a/configs/lpcxpresso-lpc1115/scripts/Make.defs +++ b/configs/lpc4088-devkit/scripts/Make.defs @@ -1,7 +1,7 @@ ############################################################################ -# configs/lpcxpresso-lpc1115/scripts/Make.defs +# configs/lpc4088-devkit/scripts/Make.defs # -# Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,20 +35,22 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = lpcxpresso-lpc1115.ld +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-m$(DELIM)Toolchain.defs ifeq ($(WINTOOL),y) # Windows-native toolchains - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)ld.script}" else # Linux/Cygwin-native toolchain - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)ld.script endif CC = $(CROSSDEV)gcc @@ -56,8 +58,8 @@ CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E LD = $(CROSSDEV)ld STRIP = $(CROSSDEV)strip --strip-unneeded -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm OBJCOPY = $(CROSSDEV)objcopy OBJDUMP = $(CROSSDEV)objdump @@ -73,7 +75,7 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y) endif ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHDEFINES = @@ -87,7 +89,7 @@ CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) AFLAGS = $(CFLAGS) -D__ASSEMBLY__ NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections LDNXFLATFLAGS = -e main -s 2048 ASMEXT = .S @@ -107,18 +109,4 @@ HOSTCC = gcc HOSTINCLUDES = -I. HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe HOSTLDFLAGS = -ifeq ($(CONFIG_HOST_WINDOWS),y) - HOSTEXEEXT = .exe -else - HOSTEXEEXT = -endif -ifeq ($(WINTOOL),y) - # Windows-native host tools - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh -else - # Linux/Cygwin-native host tools - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) -endif diff --git a/configs/lpc4088-devkit/scripts/kernel-space.ld b/configs/lpc4088-devkit/scripts/kernel-space.ld new file mode 100644 index 00000000000..46a66376a75 --- /dev/null +++ b/configs/lpc4088-devkit/scripts/kernel-space.ld @@ -0,0 +1,110 @@ +/**************************************************************************** + * configs/lpc4088-devkit/scripts/kernel-space.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpc4088-devkit/scripts/ld.script b/configs/lpc4088-devkit/scripts/ld.script new file mode 100644 index 00000000000..e1b1f6dccef --- /dev/null +++ b/configs/lpc4088-devkit/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * configs/lpc4088-devkit/scripts/ld.script + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC4088 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses + * 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb + * at 0x20004000 on bank1. + * + * Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM + * address range. + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K + AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K + AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > FLASH + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > FLASH + + .ARM.extab : { + *(.ARM.extab*) + } > FLASH + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > FLASH + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > SRAM AT > FLASH + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > SRAM + + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpc4088-devkit/scripts/memory.ld b/configs/lpc4088-devkit/scripts/memory.ld new file mode 100644 index 00000000000..654f51641a2 --- /dev/null +++ b/configs/lpc4088-devkit/scripts/memory.ld @@ -0,0 +1,99 @@ +/**************************************************************************** + * configs/lpc4088-devkit/scripts/memory.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC4088 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96KB of total SRAM: 64KB of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8KB at addresses + * 0x20000000 bank0 first and 8KB at 0x20002000 at bank0 second. And 16KB + * at 0x20004000 on bank1. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 256KB of + * FLASH and 4KB of SRAM. That, of course, can be optimized as needed (See + * also configs/lpc4088-devkit/scripts/kernel-space.ld); 256KB is probably much + * more than is needed by the RTOS! That size is selected only because it + * is available due to alignment issues for the user space FLASH memory. + * + * Alignment of the user space FLASH partition is a critical factor: The + * user space FLASH partition will be spanned with a single region of size + * 2**n bytes. The alignment of the user-space region must be the same. As + * a consequence, as the user-space increases in size, the alignmment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 256KB at it would have to be positioned at + * 0x00400000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 64KB CPU SRAM region is as follows: + * + * 0x10000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x10000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x10000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * ------- ---- Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * 0x10000 8000: Beginning of user heap. Can vary with other settings. + * 0x10001 0000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 256Kb FLASH */ + + kflash (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* More than needed */ + uflash (rx) : ORIGIN = 0x00040000, LENGTH = 256K + + /* 64Kb of SRAM in the CPU block */ + + ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 4K /* May include waste */ + usram (rwx) : ORIGIN = 0x10001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x10002000, LENGTH = 24K /* All used as heap */ + + /* Other peripheral memory (free, nothing is linked here) */ + + ahbram8_b0a(rwx) : ORIGIN = 0x20000000, LENGTH = 8K + ahbram8_b0b(rwx) : ORIGIN = 0x20002000, LENGTH = 8K + ahbram16(rwx) : ORIGIN = 0x20004000, LENGTH = 16K +} diff --git a/configs/lpc4088-devkit/scripts/user-space.ld b/configs/lpc4088-devkit/scripts/user-space.ld new file mode 100644 index 00000000000..c4daf2c62ae --- /dev/null +++ b/configs/lpc4088-devkit/scripts/user-space.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * configs/lpc4088-devkit/scripts/user-space.ld + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpcxpresso-lpc1115/src/.gitignore b/configs/lpc4088-devkit/src/.gitignore similarity index 100% rename from configs/lpcxpresso-lpc1115/src/.gitignore rename to configs/lpc4088-devkit/src/.gitignore diff --git a/configs/lpc4088-devkit/src/Makefile b/configs/lpc4088-devkit/src/Makefile new file mode 100644 index 00000000000..40c46bd7773 --- /dev/null +++ b/configs/lpc4088-devkit/src/Makefile @@ -0,0 +1,79 @@ +############################################################################ +# configs/lpc4088-devkit/src/Makefile +# +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = lpc17_40_boardinitialize.c lpc17_40_bringup.c lpc17_40_ssp.c + +ifeq ($(CONFIG_LPC17_40_EMC),y) +ifeq ($(CONFIG_LPC17_40_EXTNOR),y) + CSRCS += lpc17_40_norinitialize.c +endif + +ifeq ($(CONFIG_LPC17_40_EXTNAND),y) + CSRCS += lpc17_40_nandinitialize.c +endif + +ifeq ($(CONFIG_LPC17_40_EXTDRAM),y) + CSRCS += lpc17_40_sdraminitialize.c +endif +endif + +ifeq ($(CONFIG_LPC17_40_LCD),y) + CSRCS += lpc17_40_lcd.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) + CSRCS += lpc17_40_appinit.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += lpc17_40_autoleds.c +else + CSRCS += lpc17_40_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += lpc17_40_buttons.c +else ifeq ($(CONFIG_LPC4088_DEVKIT_DJOYSTICK),y) + CSRCS += lpc17_40_djoystick.c +endif + +ifeq ($(CONFIG_INPUT_ADS7843E),y) + CSRCS += lpc17_40_touchscreen.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/lpc4088-devkit/src/lpc17_40_appinit.c b/configs/lpc4088-devkit/src/lpc17_40_appinit.c new file mode 100644 index 00000000000..89b5f748ced --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * config/lpc4088-devkit/src/lpc17_40_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "lpc4088-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return lpc4088_devkit_bringup(); +#endif +} diff --git a/configs/lpc4088-devkit/src/lpc17_40_autoleds.c b/configs/lpc4088-devkit/src/lpc17_40_autoleds.c new file mode 100644 index 00000000000..4700a3264b7 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_autoleds.c @@ -0,0 +1,265 @@ +/**************************************************************************** + * configs/lpc4088-devkit/src/lpc17_40_autoleds.c + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_gpio.h" +#include "lpc4088-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 -- Connected to P1[14] + * LED2 -- Connected to P0[16] + * LED3 -- Connected to P1[13] + * LED4 -- Connected to P4[27] + * + * These LEDs are connected to ground so a high output value will illuminate them. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the two LEDs + * on the LPC4088 Developer's Kit. The following definitions describe how NuttX + * controls the LEDs: + * + * LED1 LED2 LED3 LED4 + * LED_STARTED 0 OFF OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF OFF + * LED_STACKCREATED 3 ON ON OFF OFF + * LED_INIRQ 4 LED3 glows, on while in interrupt + * LED_SIGNAL 4 LED3 glows, on while in signal handler + * LED_ASSERTION 4 LED3 glows, on while in assertion + * LED_PANIC 4 LED3 Flashes at 2Hz + * LED_IDLE 5 LED glows, ON while sleeping + */ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LPC4088_DEVKIT_LED1 (1 << 0) +#define LPC4088_DEVKIT_LED2 (1 << 1) +#define LPC4088_DEVKIT_LED3 (1 << 2) +#define LPC4088_DEVKIT_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((LPC4088_DEVKIT_LED1|LPC4088_DEVKIT_LED2|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((LPC4088_DEVKIT_LED1|LPC4088_DEVKIT_LED2|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((LPC4088_DEVKIT_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((LPC4088_DEVKIT_LED2|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((LPC4088_DEVKIT_LED1|LPC4088_DEVKIT_LED2|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((LPC4088_DEVKIT_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((LPC4088_DEVKIT_LED1|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((LPC4088_DEVKIT_LED1) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((LPC4088_DEVKIT_LED2|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((LPC4088_DEVKIT_LED1|LPC4088_DEVKIT_LED2) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((LPC4088_DEVKIT_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((LPC4088_DEVKIT_LED1|LPC4088_DEVKIT_LED3|LPC4088_DEVKIT_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_EVENT_ON_SETBITS ((LPC4088_DEVKIT_LED3) << ON_SETBITS_SHIFT) +#define LED_EVENT_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_EVENT_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_EVENT_OFF_CLRBITS ((LPC4088_DEVKIT_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_IDLE_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_IDLE_ON_CLRBITS ((LPC4088_DEVKIT_LED4) << ON_CLRBITS_SHIFT) +#define LED_IDLE_OFF_SETBITS ((LPC4088_DEVKIT_LED4) << OFF_SETBITS_SHIFT) +#define LED_IDLE_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_EVENT_ON_SETBITS | LED_EVENT_ON_CLRBITS | + LED_EVENT_OFF_SETBITS | LED_EVENT_OFF_CLRBITS), + + (LED_IDLE_ON_SETBITS | LED_IDLE_ON_CLRBITS | + LED_IDLE_OFF_SETBITS | LED_IDLE_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & LPC4088_DEVKIT_LED1) != 0) + { + lpc17_40_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & LPC4088_DEVKIT_LED2) != 0) + { + lpc17_40_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & LPC4088_DEVKIT_LED3) != 0) + { + lpc17_40_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & LPC4088_DEVKIT_LED4) != 0) + { + lpc17_40_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & LPC4088_DEVKIT_LED1) != 0) + { + lpc17_40_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & LPC4088_DEVKIT_LED2) != 0) + { + lpc17_40_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & LPC4088_DEVKIT_LED3) != 0) + { + lpc17_40_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & LPC4088_DEVKIT_LED4) != 0) + { + lpc17_40_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); + lpc17_40_configgpio(GPIO_LED3); + lpc17_40_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} diff --git a/configs/lpc4088-devkit/src/lpc17_40_boardinitialize.c b/configs/lpc4088-devkit/src/lpc17_40_boardinitialize.c new file mode 100644 index 00000000000..571e0ae2ab3 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_boardinitialize.c @@ -0,0 +1,142 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc17_40_boardinitialize.c + * + * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_emc.h" + +#include "lpc4088-devkit.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_40_boardinitialize + * + * Description: + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc17_40_boardinitialize(void) +{ + /* Initialize the EMC, SDRAM, NOR FLASH, and NAND FLASH */ + +#ifdef CONFIG_LPC17_40_EMC + lpc17_40_emcinitialize(); + +#ifdef CONFIG_LPC17_40_EXTDRAM + lpc4088_devkit_sdram_initialize(); +#endif + +#ifdef CONFIG_LPC17_40_EXTNOR + lpc4088_devkit_nor_initialize(); +#endif + +#ifdef CONFIG_LPC17_40_EXTNAND + lpc4088_devkit_nand_initialize(); +#endif +#endif + +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) + /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) + * the weak function lpc4088_devkit_sspdev_initialize() has been brought into + * the link. + */ + + if (lpc4088_devkit_sspdev_initialize) + { + lpc4088_devkit_sspdev_initialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_LPC17_40_LCD + /* Configure the LCD GPIOs if LCD support has been selected. */ + + lpc4088_devkit_lcd_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)lpc4088_devkit_bringup(); +} +#endif diff --git a/configs/lpc4088-devkit/src/lpc17_40_bringup.c b/configs/lpc4088-devkit/src/lpc17_40_bringup.c new file mode 100644 index 00000000000..17d9dd6d0d6 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_bringup.c @@ -0,0 +1,400 @@ +/**************************************************************************** + * config/lpc4088-devkit/src/lpc17_40_bringup.c + * + * Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "lpc17_40_gpio.h" +#include "lpc17_40_sdcard.h" +#include "lpc17_40_usbhost.h" +#include "lpc4088-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#define NSH_HAVE_MMCSD 1 +#define NSH_HAVE_USBHOST 1 +#define NSH_HAVE_USBHDEV 1 + +#undef NSH_HAVE_MMCSD_CD +#undef NSH_HAVE_MMCSD_CDINT + +/* MMC/SD support */ + +#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) +# undef NSH_HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef NSH_HAVE_MMCSD +#endif + +/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# warning "Assuming slot MMC/SD slot 0" +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDMINOR) +# warning "Assuming /dev/mmcsd0" +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +#endif + +/* The SD card detect (CD) signal is on the port expander U8, bit 4. + * The port expander is not currently supported. If support is added, + * this section can be uncommented. + */ +#if 0 +# ifdef NSH_HAVE_MMCSD +# ifdef CONFIG_MMCSD_HAVE_CARDDETECT +# define NSH_HAVE_MMCSD_CD 1 +# ifdef CONFIG_LPC17_40_GPIOIRQ +# define NSH_HAVE_MMCSD_CDINT 1 +# endif +# endif +# endif +#endif + +/* USB Host */ + +#ifndef CONFIG_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifndef CONFIG_LPC17_40_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifdef NSH_HAVE_USBHOST +# ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +# endif +# ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +# endif +#endif + +/* USB Device */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +#ifndef CONFIG_LPC17_40_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif +#ifdef NSH_HAVE_MMCSD +static FAR struct sdio_dev_s *g_sdiodev; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + syslog(LOG_INFO, "nsh_waiter: Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + syslog(LOG_INFO, "nsh_waiter: %s\n", + hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Name: nsh_sdinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD +static int nsh_sdinitialize(void) +{ + int ret; + + /* Enable power to the SD card */ + + lpc17_40_configgpio(GPIO_SD_PWR); + +#ifdef NSH_HAVE_MMCSD_CD + /* Configure the SD card detect GPIO */ + + lpc17_40_configgpio(GPIO_SD_CD); + +#endif + + /* First, get an instance of the SDIO interface */ + + g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdiodev) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Check if there is a card in the slot and inform the SDCARD driver. If + * we do not support the card detect, then let's assume that there is + * one. + */ + +#ifdef NSH_HAVE_MMCSD_CD + sdio_mediachange(g_sdiodev, !lpc17_40_gpioread(GPIO_SD_CD)); +#else + sdio_mediachange(g_sdiodev, true); +#endif + return OK; +} +#else +# define nsh_sdinitialize() (OK) +#endif + +/**************************************************************************** + * Name: nsh_usbhostinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_usbhostinitialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + syslog(LOG_INFO, "Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + syslog(LOG_INFO, "Initialize USB host\n"); + g_usbconn = lpc17_40_usbhost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + syslog(LOG_INFO, "Start nsh_waiter\n"); + + pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + (main_t)nsh_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#else +# define nsh_usbhostinitialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc4088_devkit_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ****************************************************************************/ + +int lpc4088_devkit_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system at the default location, /proc */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs: %d\n", ret); + } +#endif + + /* Initialize SD Card*/ + + ret = nsh_sdinitialize(); + if (ret == OK) + { + /* Initialize USB host */ + + ret = nsh_usbhostinitialize(); + } + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_ADS7843E + /* Initialize the touchscreen */ + + ret = lpc4088_devkit_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc4088_devkit_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LPC4088_DEVKIT_DJOYSTICK + /* Initialize and register the joystick driver */ + + ret = lpc17_40_djoy_initialization(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the joystick driver: %d\n", ret); + return ret; + } +#endif + + return ret; +} diff --git a/configs/lpc4088-devkit/src/lpc17_40_buttons.c b/configs/lpc4088-devkit/src/lpc17_40_buttons.c new file mode 100644 index 00000000000..96a5aee002c --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_buttons.c @@ -0,0 +1,240 @@ +/**************************************************************************** + * configs/lpc4088-devkit/src/lpc17_40_buttons.c + * + * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "lpc17_40_gpio.h" +#include "lpc4088-devkit.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The LPC4088 Developer's Kit supports several buttons. All will read "1" + * when open and "0" when closed + * + * USER1 -- Connected to P4[26] + * USER2 -- Connected to P2[22] + * USER3 -- Connected to P0[10] + * + * And a Joystick + * + * JOY_A -- Connected to P2[25] + * JOY_B -- Connected to P2[26] + * JOY_C -- Connected to P2[23] + * JOY_D -- Connected to P2[19] + * JOY_CTR -- Connected to P0[14] + * + * The switches are all connected to ground and should be pulled up and sensed + * with a value of '0' when closed. + */ + +/* Pin configuration for each LPC4088 Developer's Kit button. This array is + * indexed by the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const lpc17_40_pinset_t g_buttoncfg[NUM_BUTTONS] = +{ + GPIO_USER1, GPIO_JOY_A, GPIO_JOY_B, GPIO_JOY_C, GPIO_JOY_D, GPIO_JOY_CTR +}; + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +/* This array provides the mapping from button ID numbers to button IRQ + * numbers. + */ + +static const uint8_t g_buttonirq[NUM_BUTTONS] = +{ + GPIO_USER2_IRQ, GPIO_JOY_A_IRQ, GPIO_JOY_B_IRQ, GPIO_JOY_C_IRQ, + GPIO_JOY_D_IRQ, GPIO_JOY_CTR_IRQ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as interrupting inputs. */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + lpc17_40_configgpio(g_buttoncfg[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons. + * + * board_buttons() may be called at any time to harvest the state of every + * button. The state of the buttons is returned as a bitset with one + * bit corresponding to each button: If the bit is set, then the button + * is pressed. See the BOARD_BUTTON_*_BIT and BOARD_JOYSTICK_*_BIT + * definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = lpc17_40_gpioread(g_buttoncfg[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_button_irq() may be called to register button + * interrupt handlers. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BOARD_BUTTON_* and BOARD_JOYSTICK_* definitions in board.h for + * the meaning of enumeration values. + * + * Note that board_button_irq() also enables button interrupts. Button + * interrupts will remain enabled after the interrupt handler is attached. + * Interrupts may be disabled (and detached) by calling board_button_irq with + * irqhandler equal to NULL. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + irqstate_t flags; + int ret = -EINVAL; + int irq; + + /* Verify that the button ID is within range */ + + if ((unsigned)id < NUM_BUTTONS) + { + /* Get the IRQ number for the button; A value of zero indicates that + * the button does not support the interrupt function. + */ + + irq = g_buttonirq[id]; + if (irq > 0) + { + /* Disable interrupts until we are done */ + + flags = enter_critical_section(); + + /* Configure the interrupt. Either attach and enable the new + * interrupt or disable and detach the old interrupt handler. + */ + + if (irqhandler) + { + /* Attach then enable the new interrupt handler */ + + (void)irq_attach(irq, irqhandler, arg); + up_enable_irq(irq); + } + else + { + /* Disable then detach the old interrupt handler */ + + up_disable_irq(irq); + (void)irq_detach(irq); + } + + leave_critical_section(flags); + } + + ret = OK; + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/lpc4088-devkit/src/lpc17_40_djoystick.c b/configs/lpc4088-devkit/src/lpc17_40_djoystick.c new file mode 100644 index 00000000000..c864d602b53 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_djoystick.c @@ -0,0 +1,336 @@ +/**************************************************************************** + * configs/lpc4088-devkit/src/lpc17_40_djoystick.c + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "lpc17_40_gpio.h" +#include "lpc4088-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* The LPC4088 Developer's Kit supports several buttons. All will read "1" + * when open and "0" when closed + * + * USER1 -- Connected to P2[10] + * + * Joystick: + * + * JOY_A -- Connected to P2[23] + * JOY_B -- Connected to P2[25] + * JOY_C -- Connected to P2[26] + * JOY_D -- Connected to P2[27] + * JOY_CTR -- Connected to P2[22] + * + * The switches are all connected to ground and should be pulled up and sensed + * with a value of '0' when closed. + * + * Mapping to DJOYSTICK buttons: + * + * DJOY_UP JOY_B + * DJOY_DOWN JOY_C + * DJOY_LEFT JOY_A + * DJOY_RIGHT JOY_D + * DJOY_BUTTON_1 JOY_CTR + * DJOY_BUTTON_2 USER1 + */ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 6 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t djoy_supported(FAR const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower); +static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, FAR void *arg); + + +static void djoy_disable(void); +static int djoy_interrupt(int irq, FAR void *context, FAR void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* Pin configuration for each LPC4088 Developer's Kit joystick "button." + * Indexed using DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const lpc17_40_pinset_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_B, GPIO_JOY_C, GPIO_JOY_A, GPIO_JOY_D, + GPIO_JOY_CTR, GPIO_USER1 +}; + +#ifdef CONFIG_LPC17_40_GPIOIRQ +/* This array provides the mapping from button ID numbers to button IRQ + * numbers. Indexed using DJOY_* definitions in + * include/nuttx/input/djoystick.h. + */ + +static const uint8_t g_buttonirq[DJOY_NGPIOS] = +{ + GPIO_JOY_B_IRQ, GPIO_JOY_C_IRQ, GPIO_JOY_A_IRQ, GPIO_JOY_D_IRQ, + GPIO_JOY_CTR_IRQ, GPIO_USER1_IRQ +}; +#endif + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static FAR void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_supported(FAR const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_ALLBITS); + return (djoy_buttonset_t)DJOY_ALLBITS; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = lpc17_40_gpioread(g_joygpio[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", DJOY_ALLBITS); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, FAR void *arg) +{ +#ifdef CONFIG_LPC17_40_GPIOIRQ + irqstate_t flags; + djoy_buttonset_t either = press | release; + int irq; + int i; + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + /* REVISIT: Currently does not distinguish press/release selections */ + + if (either && handler != NULL) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Attach and enable interrupts each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + irq = g_buttonirq[i]; + if (irq > 0) + { + (void)irq_attach(irq, djoy_interrupt, arg); + up_enable_irq(irq); + } + } + } + + leave_critical_section(flags); +#endif +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ +#ifdef CONFIG_LPC17_40_GPIOIRQ + irqstate_t flags; + int irq; + int i; + + /* Disable and detach all button handlers for each GPIO */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + irq = g_buttonirq[i]; + if (irq > 0) + { + up_disable_irq(irq); + (void)irq_detach(irq); + } + } + + leave_critical_section(flags); +#endif + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, FAR void *context, FAR void *arg) +{ + DEBUGASSERT(g_djoyhandler != NULL); + if (g_djoyhandler != NULL) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_40_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int lpc17_40_djoy_initialization(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by lpc17_40_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + lpc17_40_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register(CONFIG_LPC4088_DEVKIT_DJOYDEV, &g_djoylower); +} diff --git a/configs/lpc4088-devkit/src/lpc17_40_lcd.c b/configs/lpc4088-devkit/src/lpc17_40_lcd.c new file mode 100644 index 00000000000..57491728dc3 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_lcd.c @@ -0,0 +1,88 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc17_40_lcd.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "lpc17_40_lcd.h" +#include "lpc17_40_gpio.h" + +#include "lpc4088-devkit.h" + +#ifdef CONFIG_LPC17_40_LCD + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_devkit_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ************************************************************************************/ + +void lpc4088_devkit_lcd_initialize(void) +{ + /* Configure the LCD backlight (and turn the backlight off) */ +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT + lpc17_40_configgpio(GPIO_LCD_BL); +#endif +} + +/************************************************************************************ + * Name: lpc17_40_backlight + * + * Description: + * If CONFIG_LPC17_40_LCD_BACKLIGHT is defined, then the board-specific logic must + * provide this interface to turn the backlight on and off. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT +void lpc17_40_backlight(bool blon) +{ + lpc17_40_gpiowrite(GPIO_LCD_BL, blon); +} +#endif + +#endif /* CONFIG_LPC17_40_LCD */ diff --git a/configs/lpc4088-devkit/src/lpc17_40_nandinitialize.c b/configs/lpc4088-devkit/src/lpc17_40_nandinitialize.c new file mode 100644 index 00000000000..5924dff0423 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_nandinitialize.c @@ -0,0 +1,93 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc17_40_nandinitialize.c + * arch/arm/src/board/lpc17_40_nandinitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc4088-devkit.h" + +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTNAND) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_devkit_nand_initialize + * + * Description: + * Initialize NAND FLASH + * + ************************************************************************************/ + +void lpc4088_devkit_nand_initialize(void) +{ + uint32_t regval; + + /* Set the memory width and byte lanes */ + + regval = getreg32(LPC17_40_EMC_STATICCONFIG1); + regval &= ~EMC_STATICCONFIG_MW_MASK; + regbal |= (EMC_STATICCONFIG_MW_8BIT | EMC_STATICCONFIG_PB); + putreg32(regval, LPC17_40_EMC_STATICCONFIG1); + + /* Configure timing */ + + putreg32(2, LPC17_40_EMC_STATICWAITWEN1); + putreg32(2, LPC17_40_EMC_STATICWAITOEN1); + putreg32(31, LPC17_40_EMC_STATICWAITRD1); + putreg32(31, LPC17_40_EMC_STATICWAITPAGE1); + putreg32(31, LPC17_40_EMC_STATICWAITWR1); + putreg32(31, LPC17_40_EMC_STATICWAITTURN1); + + /* GPIO P2[21] connects to the Ready/Busy pin of the NAND part. We need to + * reconfigure this pin as normal GPIO input. + */ + + lpc17_40_gpioconfig(GPIO_NAND_RB); +} + +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTNAND */ diff --git a/configs/lpc4088-devkit/src/lpc17_40_norinitialize.c b/configs/lpc4088-devkit/src/lpc17_40_norinitialize.c new file mode 100644 index 00000000000..fd18d5b6d7b --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_norinitialize.c @@ -0,0 +1,89 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc17_40_norinitialize.c + * arch/arm/src/board/lpc17_40_norinitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc4088-devkit.h" + +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTNOR) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_devkit_nor_initialize + * + * Description: + * Initialize NOR FLASH + * + ************************************************************************************/ + +void lpc4088_devkit_nor_initialize(void) +{ + uint32_t regval; + + /* Set the memory width and byte lanes */ + + regval = getreg32(LPC17_40_EMC_STATICCONFIG0); + regval &= ~EMC_STATICCONFIG_MW_MASK; + regbal |= (EMC_STATICCONFIG_MW_16BIT | EMC_STATICCONFIG_PB); + putreg32(regval, LPC17_40_EMC_STATICCONFIG0); + + /* Configure timing */ + + putreg32(2, LPC17_40_EMC_STATICWAITWEN0); + putreg32(2, LPC17_40_EMC_STATICWAITOEN0); + putreg32(31, LPC17_40_EMC_STATICWAITRD0); + putreg32(31, LPC17_40_EMC_STATICWAITPAGE0); + putreg32(31, LPC17_40_EMC_STATICWAITWR0); + putreg32(31, LPC17_40_EMC_STATICWAITTURN0); + + up_mdelay(10); +} + +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTNOR */ diff --git a/configs/lpc4088-devkit/src/lpc17_40_sdraminitialize.c b/configs/lpc4088-devkit/src/lpc17_40_sdraminitialize.c new file mode 100644 index 00000000000..c9d8014a51f --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_sdraminitialize.c @@ -0,0 +1,234 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc17_40_sdraminitialize.c + * arch/arm/src/board/lpc17_40_sdraminitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_emc.h" + +#include "lpc4088-devkit.h" + +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTDRAM) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided), or + * LPC17_40_CCLK / 2 as determined by settings in the board.h header file. + * + * For example: + * LPC17_40_CCLCK = 120,000,000 + * EMCCLKSEL -> LPC17_40_CCLK divided by 2 + * LPC17_40_EMCCLK = 60,000,000 + * LPC17_40_EMCCLK_MHZ = 60 (Rounded to an integer) + * EMC_NSPERCLK = 16.667 (Represented with 4 bits of fraction, 267) + * + * EMC_NS2CLK(63) = ((63 << 4) + 266) / 267 = 4 (actual 3.78) + * EMC_NS2CLK(20) = ((20 << 4) + 266) / 267 = 2 (actual 1.20) + */ + +#define LPC17_40_EMCCLK_MHZ ((LPC17_40_EMCCLK + 500000) / 1000000) +#define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_40_EMCCLK_MHZ >> 1)) / LPC17_40_EMCCLK_MHZ) +#define EMC_NS2CLK(ns) (((ns << 4) + (EMC_NSPERCLK_B4 - 1)) / EMC_NSPERCLK_B4) +#define MDKCFG_RASCAS0VAL 0x00000303 + +/* Set up for 32-bit SDRAM at CS0 */ + +#ifdef CONFIG_LPC17_40_EXTDRAMSIZE +# define SDRAM_SIZE CONFIG_LPC17_40_EXTDRAMSIZE +#endif + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT +# ifndef SDRAM_SIZE +# define SDRAM_SIZE 0x02000000 /* 256Mbit */ +# endif +#else /* if defined(CONFIG_LPC17_40_SDRAM_32BIT) */ +# undef CONFIG_LPC17_40_SDRAM_32BIT +# define CONFIG_LPC17_40_SDRAM_32BIT 1 +# ifndef SDRAM_SIZE +# define SDRAM_SIZE 0x04000000 /* 512Mbit */ +# endif +#endif + +#define SDRAM_BASE 0xa0000000 /* CS0 */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_devkit_sdram_initialize + * + * Description: + * Initialize SDRAM + * + ************************************************************************************/ + +void lpc4088_devkit_sdram_initialize(void) +{ + uint32_t regval; + int i; + + /* Reconfigure delays: + * + * CMDDLY: Programmable delay value for EMC outputs in command delayed + * mode. The delay amount is roughly CMDDLY * 250 picoseconds. + * FBCLKDLY: Programmable delay value for the feedback clock that controls + * input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250 + * picoseconds. + * CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT0DLY+1) * 250 picoseconds. + * CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT1DLY+1) * 250 picoseconds. + */ + + regval = SYSCON_EMCDLYCTL_CMDDLY(32) | + SYSCON_EMCDLYCTL_FBCLKDLY(32) | + SYSCON_EMCDLYCTL_CLKOUT0DLY(1) | + SYSCON_EMCDLYCTL_CLKOUT1DLY(1); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + + /* Configure the SDRAM */ + + putreg32( EMC_NS2CLK(20), LPC17_40_EMC_DYNAMICRP); /* TRP = 20 nS */ + putreg32( 15, LPC17_40_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */ + putreg32( 0, LPC17_40_EMC_DYNAMICSREX); /* TSREX = 1 clock */ + putreg32( 1, LPC17_40_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */ + putreg32(EMC_NS2CLK(20) + 2, LPC17_40_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */ + putreg32( 1, LPC17_40_EMC_DYNAMICWR); /* TWR = 2 clocks */ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */ + putreg32( 15, LPC17_40_EMC_DYNAMICXSR); /* Exit self-refresh to active */ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */ + putreg32( 1, LPC17_40_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */ + + /* Command delayed strategy, using EMCCLKDELAY */ + + putreg32(EMC_DYNAMICREADCONFIG_RD_CMD, LPC17_40_EMC_DYNAMICREADCONFIG); + + /* H57V2562GTR-75C: TCL=3CLK, TRCD = 20ns(min), 3 CLK = 24ns */ + + putreg32(MDKCFG_RASCAS0VAL, LPC17_40_EMC_DYNAMICRASCAS0); + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT + /* For Manley lpc1778 SDRAM: H57V2562GTR-75C, 256Mb, 16Mx16, 4 banks, row=13, column=9: + * + * 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC + */ + + putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13), + LPC17_40_EMC_DYNAMICCONFIG0); + +#elif defined CONFIG_LPC17_40_SDRAM_32BIT + /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ + + putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13) | EMC_DYNAMICCONFIG_AM1, + LPC17_40_EMC_DYNAMICCONFIG0); +#endif + + up_mdelay(100); + + /* Issue NOP command */ + + putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_NOP, + LPC17_40_EMC_DYNAMICCONTROL); + + /* Wait 200 Msec */ + + up_mdelay(200); + + /* Issue PALL command */ + + putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_PALL, + LPC17_40_EMC_DYNAMICCONTROL); + + putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */ + + /* Wait 128 AHB clock cycles */ + + for (i = 0; i < 128; i++); + + /* 64ms/8192 = 7.8125us, nx16x8.33ns < 7.8125us, n < 58.6*/ + + regval = 64000000 / (1 << 13); + regval -= 16; + regval >>= 4; + regval = regval * LPC17_40_EMCCLK_MHZ / 1000; + putreg32(regval, LPC17_40_EMC_DYNAMICREFRESH); + + /* Issue MODE command */ + + putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_MODE, + LPC17_40_EMC_DYNAMICCONTROL); + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT + (void)getreg16(SDRAM_BASE | (0x33 << 12)); /* 8 burst, 3 CAS latency */ +#elif defined CONFIG_LPC17_40_SDRAM_32BIT + (void)getreg32(SDRAM_BASE | (0x32 << 13)); /* 4 burst, 3 CAS latency */ +#endif + + /* Issue NORMAL command */ + + putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); + + /* Enable buffer */ + + regval = getreg32(LPC17_40_EMC_DYNAMICCONFIG0); + regval |= EMC_DYNAMICCONFIG_B; + putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0); + up_mdelay(12); + + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK; + regval |= SYSCON_EMCDLYCTL_CMDDLY(18); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); +} + +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTDRAM */ diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_ssp.c b/configs/lpc4088-devkit/src/lpc17_40_ssp.c similarity index 53% rename from configs/lpcxpresso-lpc1115/src/lpc11_ssp.c rename to configs/lpc4088-devkit/src/lpc17_40_ssp.c index a0ae6871f16..3213e80304c 100644 --- a/configs/lpcxpresso-lpc1115/src/lpc11_ssp.c +++ b/configs/lpc4088-devkit/src/lpc17_40_ssp.c @@ -1,7 +1,8 @@ -/************************************************************************************ - * configs/lpcxpresso-lpc1115/src/lpc11_ssp.c +/**************************************************************************** + * configs/lpc4088-devkit/src/lpc17_40_ssp.c + * arch/arm/src/board/lpc17_40_ssp.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -31,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -44,148 +45,135 @@ #include #include + #include #include "up_arch.h" #include "chip.h" -#include "lpc11_gpio.h" -#include "lpc11_ssp.h" -#include "lpcxpresso_lpc1115.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" +#include "lpc4088-devkit.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_GPIO_INFO -# define ssp_dumpgpio(m) lpc11_dumpgpio(SDCCS_GPIO, m) +# define ssp_dumpgpio(p,m) lpc17_40_dumpgpio(p,m) #else -# define ssp_dumpgpio(m) +# define ssp_dumpgpio(p,m) #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Name: lpcxpresso_sspdev_initialize +/**************************************************************************** + * Name: lpc4088_devkit_sspdev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the LPCXpresso. + * Called to configure SPI chip select GPIO pins for the LPC1766-STK. * - ************************************************************************************/ + ****************************************************************************/ -void weak_function lpcxpresso_sspdev_initialize(void) +void weak_function lpc4088_devkit_sspdev_initialize(void) { - /* Configure the SPI-based microSD CS GPIO */ + /* Configure the SSP0 chip select GPIOs. */ - ssp_dumpgpio("lpcxpresso_sspdev_initialize() Entry)"); - - /* Configure card detect and chip select for the SD slot. NOTE: Jumper J55 must - * be set correctly for the SD slot chip select. - */ - -#ifdef CONFIG_LPC17_SSP1 - (void)lpc11_configgpio(LPCXPRESSO_SD_CS); - (void)lpc11_configgpio(LPCXPRESSO_SD_CD); - - /* Configure chip select for the OLED. For the SPI interface, insert jumpers in - * J42, J43, J45 pin1-2 and J46 pin 1-2. - */ - -#ifdef CONFIG_NX_LCDDRIVER - (void)lpc11_configgpio(LPCXPRESSO_OLED_CS); -#endif +#ifdef CONFIG_LPC17_40_SSP0 #endif - ssp_dumpgpio("lpcxpresso_sspdev_initialize() Exit"); + /* Configure SSP1 chip select GPIOs. This includes the touchscreen on the + * the LCD module. + */ + +#ifdef CONFIG_LPC17_40_SSP1 + ssp_dumpgpio(GPIO_TC_CS, "BEFORE SSP1 Initialization"); + lpc17_40_configgpio(GPIO_TC_CS); + ssp_dumpgpio(GPIO_TC_CS, "AFTER SSP1 Initialization"); +#endif + + /* Configure the SSP2 chip select GPIOs. */ + +#ifdef CONFIG_LPC17_40_SSP2 +#endif } /************************************************************************************ - * Name: lpc11_ssp0/ssp1select and lpc11_ssp0/ssp1status + * Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status * * Description: - * The external functions, lpc11_ssp0/ssp1select and lpc11_ssp0/ssp1status + * The external functions, lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc11_sspbus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc11_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc11_ssp0/ssp1select() and lpc11_ssp0/ssp1status() functions + * 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc11_sspbus_initialize() in your low level application + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc11_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -void lpc11_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc11_ssp0select() Entry"); - -#warning "Assert CS here (false)" - - ssp_dumpgpio("lpc11_ssp0select() Exit"); } -uint8_t lpc11_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) { - spiinfo("Returning SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_LPC17_SSP1 -void lpc11_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc11_ssp1select() Entry"); - - if (devid == SPIDEV_MMCSD(0)) - { - /* Assert/de-assert the CS pin to the card */ - - (void)lpc11_gpiowrite(LPCXPRESSO_SD_CS, !selected); - } -#ifdef CONFIG_NX_LCDDRIVER - else if (devid == SPIDEV_DISPLAY(0)) - { - /* Assert the CS pin to the OLED display */ - - (void)lpc11_gpiowrite(LPCXPRESSO_OLED_CS, !selected); - } -#endif - ssp_dumpgpio("lpc11_ssp1select() Exit"); -} - -uint8_t lpc11_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) -{ - if (devid == SPIDEV_MMCSD(0)) - { - /* Read the state of the card-detect bit */ - - if (lpc11_gpioread(LPCXPRESSO_SD_CD) == 0) - { - spiinfo("Returning SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; - } - } - - spiinfo("Returning zero\n"); + spiinfo("Returning nothing\n"); return 0; } #endif -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + /* Assert/de-assert the CS pin to the touchscreen */ + + ssp_dumpgpio(GPIO_TC_CS, "lpc17_40_ssp1select() Entry"); + lpc17_40_gpiowrite(GPIO_TC_CS, !selected); + ssp_dumpgpio(GPIO_TC_CS, "lpc17_40_ssp1select() Exit"); + } +} + +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#ifdef CONFIG_LPC17_40_SSP2 +void lpc17_40_ssp2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t lpc17_40_ssp2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 || CONFIG_LPC17_40_SSP2 */ diff --git a/configs/lpc4088-devkit/src/lpc17_40_touchscreen.c b/configs/lpc4088-devkit/src/lpc17_40_touchscreen.c new file mode 100644 index 00000000000..0bbd21938a6 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc17_40_touchscreen.c @@ -0,0 +1,314 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc17_40_touchscreen.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" +#include "lpc4088-devkit.h" + +#ifdef CONFIG_INPUT_ADS7843E + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_INPUT +# error "Touchscreen support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_LPC17_40_SSP1 +# error "Touchscreen support requires CONFIG_LPC17_40_SSP1" +#endif + +#ifndef CONFIG_LPC17_40_GPIOIRQ +# error "Touchscreen support requires CONFIG_LPC17_40_GPIOIRQ" +#endif + +#ifndef CONFIG_ADS7843E_FREQUENCY +# define CONFIG_ADS7843E_FREQUENCY 500000 +#endif + +#ifndef CONFIG_ADS7843E_SPIDEV +# define CONFIG_ADS7843E_SPIDEV 1 +#endif + +#if CONFIG_ADS7843E_SPIDEV != 1 +# error "CONFIG_ADS7843E_SPIDEV must be one" +#endif + +#ifndef CONFIG_ADS7843E_DEVMINOR +# define CONFIG_ADS7843E_DEVMINOR 0 +#endif + +/* REVISIT: Currently, XPT2046 reports BUSY all of the time. This is + * probably GPIO setting issues. But there is this cryptic statement in + * the XPT2046 spec: "No DCLK delay required with dedicated serial port." + * + * The busy state is used by the XPT2046 driver to control the delay + * between sending the command, then reading the returned data. + */ + +#define XPT2046_NO_BUSY 1 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the XPT2046 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * attach - Attach the XPT2046 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * pendown - Return the state of the pen down GPIO input + */ + +static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr); +static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable); +static void tsc_clear(FAR struct ads7843e_config_s *state); +static bool tsc_busy(FAR struct ads7843e_config_s *state); +static bool tsc_pendown(FAR struct ads7843e_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the XPT2046 + * driver. This structure provides information about the configuration + * of the XPT2046 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. + */ + +static struct ads7843e_config_s g_tscinfo = +{ + .frequency = CONFIG_ADS7843E_FREQUENCY, + .attach = tsc_attach, + .enable = tsc_enable, + .clear = tsc_clear, + .busy = tsc_busy, + .pendown = tsc_pendown, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the XPT2046 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * attach - Attach the XPT2046 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * pendown - Return the state of the pen down GPIO input + */ + +static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t handler) +{ + /* Attach then enable the touchscreen interrupt handler */ + + (void)irq_attach(LPC17_40_IRQ_PENIRQ, handler, NULL); + return OK; +} + +static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) +{ + iinfo("enable:%d\n", enable); + if (enable) + { + /* Enable PENIRQ interrupts. NOTE: The pin interrupt is enabled from worker thread + * logic after completion of processing of the touchscreen interrupt. + */ + + up_enable_irq(LPC17_40_IRQ_PENIRQ); + } + else + { + /* Disable PENIRQ interrupts. NOTE: The PENIRQ interrupt will be disabled from + * interrupt handling logic. + */ + + up_disable_irq(LPC17_40_IRQ_PENIRQ); + } +} + +static void tsc_clear(FAR struct ads7843e_config_s *state) +{ + /* Does nothing. The interrupt is cleared automatically in the GPIO + * logic for the LPC17xx/LPC40xx family. + */ +} + +static bool tsc_busy(FAR struct ads7843e_config_s *state) +{ +/* The busy state is used by the XPT2046 driver to control the delay + * between sending the command, then reading the returned data. + */ + +#ifdef XPT2046_NO_BUSY +/* REVISIT: Currently, XPT2046 reports BUSY all of the time. This is + * probably GPIO setting issues. But there is this cryptic statement in + * the XPT2046 spec: "No DCLK delay required with dedicated serial port." + */ + + return false; + +#else /* XPT2046_NO_BUSY */ + +#if defined(CONFIG_DEBUG_INPUT) && defined(CONFIG_DEBUG_INFO) + static bool last = (bool)-1; +#endif + + /* REVISIT: This might need to be inverted */ + + bool busy = lpc17_40_gpioread(GPIO_TC_BUSY); +#if defined(CONFIG_DEBUG_INPUT) && defined(CONFIG_DEBUG_INFO) + if (busy != last) + { + iinfo("busy:%d\n", busy); + last = busy; + } +#endif + + return busy; + +#endif /* XPT2046_NO_BUSY */ +} + +static bool tsc_pendown(FAR struct ads7843e_config_s *state) +{ + /* XPT2046 uses an an internal pullup resistor. The PENIRQ output goes low + * due to the current path through the touch screen to ground, which + * initiates an interrupt to the processor via TP_INT. + */ + + bool pendown = !lpc17_40_gpioread(GPIO_TC_PENIRQ); + iinfo("pendown:%d\n", pendown); + return pendown; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc4088_devkit_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int lpc4088_devkit_tsc_setup(int minor) +{ + FAR struct spi_dev_s *dev; + int ret; + + iinfo("minor:%d\n", minor); + DEBUGASSERT(minor == 0); + + /* Configure and enable the XPT2046 PENIRQ pin as an interrupting input. */ + + (void)lpc17_40_configgpio(GPIO_TC_PENIRQ); + + /* Configure the XPT2046 BUSY pin as a normal input. */ + +#ifndef XPT2046_NO_BUSY + (void)lpc17_40_configgpio(GPIO_TC_BUSY); +#endif + + /* Get an instance of the SPI interface */ + + dev = lpc17_40_sspbus_initialize(CONFIG_ADS7843E_SPIDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_ADS7843E_SPIDEV); + return -ENODEV; + } + + /* Initialize and register the SPI touchscreen device */ + + ret = ads7843e_register(dev, &g_tscinfo, CONFIG_ADS7843E_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register touchscreen device minor=%d\n", + CONFIG_ADS7843E_DEVMINOR); + /* up_spiuninitialize(dev); */ + return -ENODEV; + } + + return OK; +} + +#endif /* CONFIG_INPUT_ADS7843E */ diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.c b/configs/lpc4088-devkit/src/lpc17_40_userleds.c similarity index 69% rename from arch/arm/src/lpc11xx/lpc11_gpio.c rename to configs/lpc4088-devkit/src/lpc17_40_userleds.c index ef984351db5..d7f02c1b4bf 100644 --- a/arch/arm/src/lpc11xx/lpc11_gpio.c +++ b/configs/lpc4088-devkit/src/lpc17_40_userleds.c @@ -1,7 +1,8 @@ /**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_gpio.c + * configs/lpc4088-devkit/src/lpc17_40_userleds.c + * arch/arm/src/board/lpc17_40_userleds.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -39,42 +40,81 @@ #include -/* This file is only a thin shell that includes the correct GPIO logic for - * the selected LPC17xx family. The correct file cannot be selected by the - * make system because it needs the intelligence that only exists in chip.h - * that can associate an LPC17xx part number with an LPC17xx family. - */ +#include +#include +#include -#include +#include +#include -#if defined(LPC111x) -# include "lpc111x_gpio.c" -#elif defined(LPC11C) -# include "lpc11c_gpio.c" -#else -# error "Unrecognized LPC11xx family" -#endif +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_gpio.h" +#include "lpc4088-devkit.h" + +#ifndef CONFIG_ARCH_LEDS /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Types - ****************************************************************************/ +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) +#else +# define led_dumpgpio(m) +#endif /**************************************************************************** * Private Data ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ +/* This array maps an LED number to GPIO pin configuration */ -/**************************************************************************** - * Private Functions - ****************************************************************************/ +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2 +}; /**************************************************************************** * Public Functions ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + lpc17_40_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + lpc17_40_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/lpc4088-devkit/src/lpc4088-devkit.h b/configs/lpc4088-devkit/src/lpc4088-devkit.h new file mode 100644 index 00000000000..884e6e4b9c0 --- /dev/null +++ b/configs/lpc4088-devkit/src/lpc4088-devkit.h @@ -0,0 +1,272 @@ +/************************************************************************************ + * configs/lpc4088-devkit/src/lpc4088-devkit.h + * arch/arm/src/board/lpc4088-devkit.h + * + * Copyright (C) 2013, 2017-2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_LPC4088_DEVKIT_SRC_LPC4088_DEVKIT_H +#define _CONFIGS_LPC4088_DEVKIT_SRC_LPC4088_DEVKIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* LPC4088 Developer's Kit GPIO Pin Definitions *************************************/ +/* GPIO P2[21] connects to the Ready/Busy pin of the NAND part. We need to + * reconfigure this pin as normal GPIO input if NAND is used. + */ + +#define GPIO_NAND_RB (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN21) + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 -- Connected to P1[14] + * LED2 -- Connected to P0[16] + * LED3 -- Connected to P1[13] + * LED4 -- Connected to P4[27] + * + * These LEDs are connecte to ground so a high output value will illuminate them. + */ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_LED3 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_LED4 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT4 | GPIO_PIN27) + +/* Button definitions ***************************************************************/ +/* The LPC4088 Developer's Kit supports several buttons. All are pulled up externally. + * When closed, the pins will be pulled to ground. So the buttons will read "1" + * when open and "0" when closed. All are capable of generating + * interrupts. + * + * USER1 -- Connected to P2[10] + * + * Joystick: + * + * JOY_A -- Connected to P2[23] + * JOY_B -- Connected to P2[25] + * JOY_C -- Connected to P2[26] + * JOY_D -- Connected to P2[27] + * JOY_CTR -- Connected to P2[22] + * + * For the interrupting buttons, interrupts are generated on both edges (press and + * release). + */ + +#define GPIO_USER1 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN26) + +#define GPIO_JOY_A (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN25) +#define GPIO_JOY_B (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_JOY_C (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_JOY_D (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN19) +#define GPIO_JOY_CTR (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) + +/* IRQ numbers for the buttons that do support interrupts */ + +#define GPIO_USER1_IRQ LPC17_40_IRQ_P2p10 +#define GPIO_JOY_A_IRQ LPC17_40_IRQ_P2p23 +#define GPIO_JOY_B_IRQ LPC17_40_IRQ_P2p25 +#define GPIO_JOY_C_IRQ LPC17_40_IRQ_P2p26 +#define GPIO_JOY_D_IRQ LPC17_40_IRQ_P2p27 +#define GPIO_JOY_CTR_IRQ LPC17_40_IRQ_P2p22 + +/* SD Card **************************************************************************/ +/* The SD card detect (CD) signal is on bit 4 of the PCA9532 port expander U8. + * Support for this is not currently set up. + * The SD card's power is controlled through a P-channel MOSFET connected to P1[5]. + * This pin must be driven LOW in order to enable the SD card.*/ + +#define GPIO_SD_PWR (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT1 | GPIO_PIN5) + +/* More work is required to complete implementation of LCD support on this board. */ + +#if 0 +/* LCD ******************************************************************************/ +/* Backlight enable, P2[1]. Initial state is OFF (zero) */ + +#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN1) + +/* XPT2046 Touchscreen **************************************************************/ +/* -------------- -------------------- ------------ -------------------------------- + * XTPT2046 Module Module LPC4088 Developer's Kit LED + * Signal Connector Connector + * -------------- -------------------- ------------ --------------------------------- + * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ + * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) + * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY + * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) + * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) + * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 + * -------------- -------------------- ------------ --------------------------------- + * + * Pins should not need to be configured as pull-ups because, according to the LCD + * schematic, the are pulled-up on board the LCD module. + */ + +#define GPIO_TC_PENIRQ (GPIO_INTBOTH | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_TC_BUSY (GPIO_INPUT | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_TC_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN8) + +#define LPC17_40_IRQ_PENIRQ LPC17_40_IRQ_P2p15 + +#endif + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_devkit_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ************************************************************************************/ + +int lpc4088_devkit_bringup(void); + +/************************************************************************************ + * Name: lpc4088_devkit_sspdev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LPC4088 Developer's Kit board. + * + ************************************************************************************/ + +void weak_function lpc4088_devkit_sspdev_initialize(void); + +/************************************************************************************ + * Name: lpc4088_devkit_sdram_initialize + * + * Description: + * Initialize SDRAM + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_EMC +#ifdef CONFIG_LPC17_40_EXTDRAM +void lpc4088_devkit_sdram_initialize(void); +#endif + +/************************************************************************************ + * Name: lpc4088_devkit_nor_initialize + * + * Description: + * Initialize NOR FLASH + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_EXTNOR +void lpc4088_devkit_nor_initialize(void); +#endif + +/************************************************************************************ + * Name: lpc4088_devkit_nand_initialize + * + * Description: + * Initialize NAND FLASH + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_EXTNAND +void lpc4088_devkit_nand_initialize(void); +#endif +#endif /* CONFIG_LPC17_40_EMC */ + +/************************************************************************************ + * Name: lpc4088_devkit_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_LCD +void lpc4088_devkit_lcd_initialize(void); +#endif + +/************************************************************************************ + * Name: lpc4088_devkit_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the touchscreen + * device. This function will register the driver as /dev/inputN where N is the + * minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is returned to + * indicate the nature of the failure. + * + ************************************************************************************/ + +#ifdef CONFIG_INPUT_ADS7843E +int lpc4088_devkit_tsc_setup(int minor); +#endif + +/************************************************************************************ + * Name: lpc17_40_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ************************************************************************************/ + +#ifdef CONFIG_LPC4088_DEVKIT_DJOYSTICK +int lpc17_40_djoy_initialization(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_LPC4088_DEVKIT_SRC_LPC4088_DEVKIT_H */ diff --git a/configs/lpc4088-devkit/tools/lpc4088-devkit.cfg b/configs/lpc4088-devkit/tools/lpc4088-devkit.cfg new file mode 100644 index 00000000000..e2746104dfe --- /dev/null +++ b/configs/lpc4088-devkit/tools/lpc4088-devkit.cfg @@ -0,0 +1,166 @@ +### From /usr/local/share/openocd/scripts/interface/olimex-arm-usb-ocd.cfg +# +# Olimex ARM-USB-OCD +# +# http://www.olimex.com/dev/arm-usb-ocd.html +# + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG A" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +### From /usr/local/share/openocd/scripts/targets/lpc40xx.cfg +# NXP LPC4088 Cortex-M4 with 512kB Flash and 96kB Local On-Chip SRAM +# remember to place in the same folder as lpc17xx.cfg + +set CHIPNAME lpc4088 +set CPUTAPID 0x410fc241 +set CPURAMSIZE 0x18000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 12000 + +### From /usr/local/share/openocd/scripts/targets/lpc17xx.cfg +### With additions to set the operating frequency to 120MHz +# Common LPC17xx logic + +# LPC17xx chips support both JTAG and SWD transports. +# JTAG is hard-coded in this configuration +# Adapt based on what transport is active. +# source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "_CHIPNAME not set" +} + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + set _CCLK $CCLK +} else { + set _CCLK 4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + error "_CPUTAPID not set" +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { + error "_CPURAMSIZE not set" +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { + error "_CPUROMSIZE not set" +} + +#delays on reset lines +adapter_nsrst_delay 500 +jtag_ntrst_delay 500 + +# Use of JTAG is hard-coded +#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME + +# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE + +# The LPC17xx devices have 32/64/128/256/512kB of flash memory, managed by ROM code +# (including a boot loader which verifies the flash exception table's checksum). +# flash bank lpc2000 0 0 [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +adapter_khz 1000 + +$_TARGETNAME configure -event reset-init { + echo "Going to 120MHz" + + # PLL0CON: Disable PLL + mww 0x400FC080 0x00000000 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # CLKSEL: internal 12MHz RC oscillator Div 1. + mww 0x400FC104 0x00000001 + # CLKSRCSEL: Clock source = internal 12MHz RC oscillator + mww 0x400FC10C 0x00000000 + + # PLL0CFG: M=10,P=1 -> PLL=240 MHz + mww 0x400FC084 0x00000009 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # PLL0CON: Enable PLL + mww 0x400FC080 0x00000001 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + sleep 50 + + # PLL0CON: Connect PLL + # CCLKSEL=PLLED(240MHz)/2 (=120 MHz) + mww 0x400FC104 0x00000102 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # Dividing CPU clock by 8 should be pretty conservative + # + # + adapter_khz 1500 + + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + + mww 0x400FC040 0x01 +} + +# if srst is not fitted use VECTRESET to +# perform a soft reset - SYSRESETREQ is not supported +cortex_m3 reset_config vectreset diff --git a/configs/lpc4088-devkit/tools/oocd.sh b/configs/lpc4088-devkit/tools/oocd.sh new file mode 100755 index 00000000000..a89a5e64bc1 --- /dev/null +++ b/configs/lpc4088-devkit/tools/oocd.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# +# See configs/lpc4088-devkit/README.txt for information about +# this file. + +TOPDIR=$1 +USAGE="$0 [-d]" +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + exit 1 +fi + +# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment +# the following to run directly from the build directory + +# OPENOCD_PATH="/home/OpenOCD/openocd/src" +# OPENOCD_PATH="/usr/bin" +OPENOCD_PATH="/usr/local/bin" + +# TARGET_PATH="/home/OpenOCD/openocd/tcl" +# TARGET_PATH="/usr/share/openocd/scripts" +TARGET_PATH="/usr/local/share/openocd/scripts" + +# Assume a Unix development environment. Uncomment to use a Windows +# like environment + +OPENOCD_EXE=openocd.exe +# OPENOCD_EXE=openocd + +OPENOCD_CFG="${TOPDIR}/configs/lpc4088-devkit/tools/lpc4088-devkit.cfg" +OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}" + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +if [ ! -d ${OPENOCD_PATH} ]; then + echo "OpenOCD path does not exist: ${OPENOCD_PATH}" + exit 1 +fi +if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then + echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f ${OPENOCD_CFG} ]; then + echo "OpenOCD config file does not exist: ${OPENOCD_CFG}" + exit 1 +fi + +echo "Starting OpenOCD" +cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; } +${OPENOCD_EXE} ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/configs/lpcxpresso-lpc1115/Kconfig b/configs/lpc4088-quickstart/Kconfig similarity index 80% rename from configs/lpcxpresso-lpc1115/Kconfig rename to configs/lpc4088-quickstart/Kconfig index dc265e82468..07629fa8c9f 100644 --- a/configs/lpcxpresso-lpc1115/Kconfig +++ b/configs/lpc4088-quickstart/Kconfig @@ -3,5 +3,5 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_BOARD_LPCXPRESSO_LPC1115 +if ARCH_BOARD_LPC4088_QUICKSTART endif diff --git a/configs/lpc4088-quickstart/README.txt b/configs/lpc4088-quickstart/README.txt new file mode 100644 index 00000000000..0f6a88fa44d --- /dev/null +++ b/configs/lpc4088-quickstart/README.txt @@ -0,0 +1,456 @@ +README.txt +========== + + This README file discusses the port of NuttX to the Embedded Artists LPC4088 + QuickStart board: See https://www.embeddedartists.com/products/lpc4088-quickstart-board/. + This board features the NXP LPC4088FET208 MCU. + +CONTENTS +======== + + o LEDs + o Buttons + o Serial Console + o Using OpenOCD with the Olimex ARM-USB-OCD + o Loading Code with the ISP Board + o Configuration + +LEDs +==== + + The LCP4088 Quickstart board has four user LEDs + + LED1 : Connected to P1[18] + LED2 : Connected to P0[13] + LED3 : Connected to P1[13] + LED4 : Connected to P2[19] + + If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + any way using the defitions provided in the board.h header file. + + If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on the + LPC4088 QuickStart board. The following definitions describe how NuttX + controls the LEDs: + LED1 LED2 LED3 LED4 + LED_STARTED OFF OFF OFF OFF + LED_HEAPALLOCATE ON OFF OFF OFF + LED_IRQSENABLED OFF ON OFF OFF + LED_STACKCREATED ON ON OFF OFF + LED_INIRQ LED3 glows, on while in interrupt + LED_SIGNAL LED3 glows, on while in signal handler + LED_ASSERTION LED3 glows, on while in assertion + LED_PANIC LED3 Flashes at 2Hz + LED_IDLE LED glows: ON while active; OFF while sleeping + +Buttons +======= + + The LPC4088 QuickStart board supports a single button: + + USER1 : Connected to P2[10] + + This can be accessed using the definitions and interfaces defined in the + board.h header file. + +Serial Console +============== + + By Default, UART0 is used as the serial console in all configurations. This + may be connected to your computer via an external RS-232 driver or via the + onboard MBED interface. + + As an option, UART1 can also be used for the serial console. You might want, + to do this, for example, if you use UART0 for the ISP function and you want + to use a different UART for console output. UART1 can be configured as the + serial console by changing the configuration as follows: + + System Type: + CONFIG_LPC17_40_UART0=n : Disable UART0 if it is no longer used + CONFIG_LPC17_40_UART1=y : Enable UART1 + + Drivers: + CONFIG_UART1_SERIAL_CONSOLE=y : Setup up the UART1 configuration + CONFIG_UART1_RXBUFSIZE=256 + CONFIG_UART1_TXBUFSIZE=256 + CONFIG_UART1_BAUD=115200 + CONFIG_UART1_BITS=8 + CONFIG_UART1_PARITY=0 + CONFIG_UART1_2STOP=0 + +Using OpenOCD with the Olimex ARM-USB-OCD +========================================= + + Building OpenOCD under Cygwin: + + Refer to configs/olimex-lpc1766stk/README.txt + + Installing OpenOCD in Ubuntu Linux: + + sudo apt-get install openocd + + Helper Scripts. + + I have been using the Olimex ARM-USB-OCD debugger. OpenOCD + requires a configuration file. I keep the one I used last here: + + configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg + + However, the "correct" configuration script to use with OpenOCD may + change as the features of OpenOCD evolve. So you should at least + compare that lpc4088-quickstart.cfg file with configuration files in + /usr/share/openocd/scripts. As of this writing, the configuration + files of interest were: + + /usr/local/share/openocd/scripts/interface/openocd-usb.cfg + This is the configuration file for the Olimex ARM-USB-OCD + debugger. Select a different file if you are using some + other debugger supported by OpenOCD. + + /usr/local/share/openocd/scripts/board/? + I don't see a board configuration file for the LPC4088 Quickstart. + + /usr/local/share/openocd/scripts/target/lpc40xx.cfg + This is the configuration file for the LPC4088 target. + It just sets up a few parameters then sources lpc1xxx.cfg + + /usr/local/share/openocd/scripts/target/lpc1xxx.cfg + This is the generic LPC configuration for the LPC1xxx + family. It is included by lpc40xx.cfg. + + NOTE: These files could also be located under /usr/share in some + installations. They could be most anywhwere if you are using a + windows version of OpenOCD. + + configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg + This is simply openocd-usb.cfg, lpc40xx.cfg, and lpc1xxx.cfg + concatenated into one file for convenience. Don't use it + unless you have to. + + There is also a script on the tools/ directory that I use to start + the OpenOCD daemon on my system called oocd.sh. That script will + probably require some modifications to work in another environment: + + - Possibly the value of OPENOCD_PATH and TARGET_PATH + - It assumes that the correct script to use is the one at + configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg + + Starting OpenOCD + + Then you should be able to start the OpenOCD daemon as follows. This + assumes that you have already CD'ed to the NuttX build directory and + that you have set the full path to the configs/lpc4088-quickstart/tools + in your PATH environment variable: + + oocd.sh $PWD + + or, if the PATH variable is not so configured: + + configs/lpc4088-quickstart/tools/oocd.sh $PWD + + Connecting GDB + + Once the OpenOCD daemon has been started, you can connect to it via + GDB using the following GDB command: + + arm-nuttx-elf-gdb + (gdb) target remote localhost:3333 + + NOTE: The name of your GDB program may differ. For example, with the + CodeSourcery toolchain, the ARM GDB would be called arm-none-eabi-gdb. + + OpenOCD will support several special 'monitor' sub-commands. You can + use the 'monitor' (or simply 'mon') command to invoke these sub- + commands. These GDB commands will send comments to the OpenOCD monitor. + Here are a couple that you will need to use: + + (gdb) monitor reset + (gdb) monitor halt + + NOTES: + + 1. The MCU must be halted using 'monitor halt' prior to loading code. + + 2. 'monitor reset' will restart the processor after loading code. + + 3. The 'monitor' command can be abbreviated as just 'mon'. + + After starting GDB, you can load the NuttX ELF file like this: + + (gdb) mon halt + (gdb) load nuttx + + NOTES: + + 1. NuttX should have been built so that it has debugging symbols + (by setting CONFIG_DEBUG_SYMBOLS=y in the .config file). + + 2. The MCU must be halted prior to loading code. + + 3. I find that there are often undetected write failures when using + the Olimex ARM-USB-OCD debugber and that if you start the program + with a bad FLASH failure, it will lock up OpenOCD. I usually + oad nuttx twice, restarting OpenOCD in between in order to assure + good FLASH contents: + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset + + Exit GDB, kill the OpenOCD server, recycle power on the board, + restart the OpenOCD server and GDB, then: + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset + + Other debuggers may not have these issues and such drastic steps may + not be necessary. + +Loading Code with the ISP Board +=============================== + + Users can also load code onto the board using a built-in or external UART + to USB adapter on UART0. I use the FlashMagic program for Windows available + here: http://www.flashmagictool.com/ . It is so easy to use that no further + explanation should be necessary: Just select the LPC4088, the ISP COM + port, and the NuttX .hex file and program it. + +CONFIGURATION +============= + +Information Common to All Configurations +---------------------------------------- + + 1. These configurations use the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository + README.txt. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Most (but not all) configurations use the "GNU Tools for ARM + Embedded Processors" that is maintained by ARM: + + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + + unless otherwise stated. + + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + + 3. By Default, UART0 is used as the serial console in all configurations. + This may be connected to your computer via an external RS-232 driver or + via the onboard MBED interface. See the section above entitled + "Serial Console" for other options. + + 4. An LCD is available for this board, but I don't have one to test with. + If you wish to use any of the configurations below which utilize the LCD, + you will need to tweak the LCD pin definitions in board.h. + +Configuration Directories +------------------------- + + knsh + ---- + This is identical to the nsh configuration below except that NuttX + is built as a kernel-mode, monolithic module and the user applications + are built separately. Is is recommened to use a special make command; + not just 'make' but make with the following two arguments: + + make pass1 pass2 + + In the normal case (just 'make'), make will attempt to build both user- + and kernel-mode blobs more or less interleaved. This actual works! + However, for me it is very confusing so I prefer the above make command: + Make the user-space binaries first (pass1), then make the kernel-space + binaries (pass2) + + 1. Uses the older, OABI, buildroot toolchain. But that is easily + reconfigured: + + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain + + 2. At the end of the build, there will be several files in the top-level + NuttX build directory: + + PASS1: + nuttx_user.elf - The pass1 user-space ELF file + nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) + User.map - Symbols in the user-space ELF file + + PASS2: + nuttx - The pass2 kernel-space ELF file + nuttx.hex - The pass2 Intel HEX file (selected in defconfig) + System.map - Symbols in the kernel-space ELF file + + Loading these .elf files with OpenOCD is tricky. It appears to me + that when nuttx_user.elf is loaded, it destroys the nuttx image + in FLASH. But loading the nuttx ELF does not harm the nuttx_user.elf + in FLASH. Conclusion: Always load nuttx_user.elf before nuttx. + + Just to complicate matters, it is sometimes the case that you need + load objects twice to account for write failures. I have not yet + found a simple foolproof way to reliably get the code into FLASH. + + 3. Combining .hex files. If you plan to use the .hex files with your + debugger or FLASH utility, then you may need to combine the two hex + files into a single .hex file. Here is how you can do that. + + a. The 'tail' of the nuttx.hex file should look something like this + (with my comments added): + + $ tail nuttx.hex + # 00, data records + ... + :10 9DC0 00 01000000000800006400020100001F0004 + :10 9DD0 00 3B005A0078009700B500D400F300110151 + :08 9DE0 00 30014E016D0100008D + # 05, Start Linear Address Record + :04 0000 05 0800 0419 D2 + # 01, End Of File record + :00 0000 01 FF + + Use an editor such as vi to remove the 05 and 01 records. + + b. The 'head' of the nuttx_user.hex file should look something like + this (again with my comments added): + + $ head nuttx_user.hex + # 04, Extended Linear Address Record + :02 0000 04 0801 F1 + # 00, data records + :10 8000 00 BD89 01084C800108C8110208D01102087E + :10 8010 00 0010 00201C1000201C1000203C16002026 + :10 8020 00 4D80 01085D80010869800108ED83010829 + ... + + Nothing needs to be done here. The nuttx_user.hex file should + be fine. + + c. Combine the edited nuttx.hex and un-edited nuttx_user.hex + file to produce a single combined hex file: + + $ cat nuttx.hex nuttx_user.hex >combined.hex + + Then use the combined.hex file with the to write the FLASH image. + If you do this a lot, you will probably want to invest a little time + to develop a tool to automate these steps. + + STATUS: + 2019-04-23: Untested with LPC4088. + + nsh + --- + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables only the serial NSH interface. + + NOTES: + + 1. Uses the older, OABI, buildroot toolchain. But that is easily + reconfigured: + + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain + + 2. This NSH has support for built-in applications enabled, however, + no built-in configurations are built in the defulat configuration. + + 3. This configuration has DMA-based SD card support enabled by + default. That support can be disabled as follow: + + CONFIG_LPC17_40_GPDMA=n : No DMA + CONFIG_ARCH_DMA=n + CONFIG_LPC17_40_SDCARD=n : No SD card driver + CONFIG_SDIO_DMA=n : No SD card DMA + CONFIG_MMCSD=n : No MMC/SD driver support + CONFIG_FS_FAT=n : No FAT file system support + + 4. This configuration has been used for verifying SDRAM by modifying + the configuration in the following ways: + + CONFIG_LPC17_40_EMC=y : Enable the EMC + CONFIG_LPC17_40_EXTDRAM=y : Configure external DRAM + CONFIG_LPC17_40_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB + CONFIG_SYSTEM_RAMTEST=y : Enable the RAM test built-in + + In this configuration, the SDRAM is not added to heap and so is + not excessible to the applications. So the RAM test can be + freely executed against the SRAM memory beginning at address + 0xa000:0000 (CS0). + + 6. This configuration has been used for verifying the touchscreen on + on the 4.3" LCD module. + + a) As of this writing, this touchscreen is still not functional. + Rommel Marcelo has tracked this problem down to noise on the + PENIRQ interrupt. There are so many false interrupts that + the NuttX interrupt-driven touchscreen driver cannot be used. + Other compatible LCDs, however, may not have this issue. + + b) You can enable the touchscreen by modifying the configuration + in the following ways: + + Drivers: + CONFIG_INPUT=y : Enable support for input devices + CONFIG_INPUT_ADS7843E=y : Enable support for the XPT2048 + CONFIG_ADS7843E_SPIDEV=1 : Use SSP1 for communication + CONFIG_SPI=y : Enable SPI support + CONFIG_SPI_EXCHANGE=n : exchange() method is not supported + + System Type: + CONFIG_LPC17_40_GPIOIRQ=y : GPIO interrupt support + CONFIG_LPC17_40_SSP1=y : Enable support for SSP1 + + RTOS Features: + CONFIG_DISABLE_SIGNALS=n : Signals are required + + Library Support: + CONFIG_SCHED_WORKQUEUE=y : Work queue support required + + Applicaton Configuration: + CONFIG_EXAMPLES_TOUCHSCREEN=y : Enable the touchscreen built-int test + + Defaults should be okay for related touchscreen settings. Touchscreen + debug output can be enabled with: + + Build Setup: + CONFIG_DEBUG_FEATURES=y : Enable debug features + CONFIG_DEBUG_INFO=y : Enable verbose debug output + CONFIG_DEBUG_INPUT=y : Enable debug output from input devices + + c) You will also have to disable SD card support to use this test. The + SD card detect (CD) signal is on P0[13]. This signal is shared. It + is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. + There is a jumper on board that enables the CD pin. OR, you can simply + remove the SD module so that it does not drive the CD pin. + + Drivers: + CONFIG_MMCSD=n : No MMC/SD driver support + + System Type: + CONFIG_LPC17_40_GPDMA=n : No DMA + CONFIG_LPC17_40_SDCARD=n : No SD card driver + CONFIG_SDIO_DMA=n : No SD card DMA + CONFIG_ARCH_DMA=n + + File Systems: + CONFIG_FS_FAT=n : No FAT file system support + + For touchscreen debug output: + + Build Setup: + CONFIG_DEBUG_FEATURES=y + CONFIG_DEBUG_INFO=y + CONFIG_DEBUG_INPUT=y + diff --git a/configs/lpc4088-quickstart/include/board.h b/configs/lpc4088-quickstart/include/board.h new file mode 100644 index 00000000000..6815833daeb --- /dev/null +++ b/configs/lpc4088-quickstart/include/board.h @@ -0,0 +1,380 @@ +/************************************************************************************ + * configs/lpc4088-quickstart/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_LPC4088_QUICKSTART_INCLUDE_BOARD_H +#define __CONFIG_LPC4088_QUICKSTART_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Clocking *************************************************************************/ +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here + * because the including C file may not have that file in its include path. + */ + +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ +#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ +#define BOARD_WDTOSC_FREQUENCY (500000) /* WDT oscillator frequency */ + +/* This is the clock setup we configure for: + * + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multipler=10, pre-divider=1 + * CCLCK = 120MHz -> CCLK divider = 1 + */ + +#define LPC17_40_CCLK 120000000 /* 120Mhz */ +#define BOARD_PCLKDIV 2 /* Peripheral clock = LPC17_40_CCLK/2 */ +#define BOARD_PCLK_FREQUENCY (LPC17_40_CCLK / BOARD_PCLKDIV) + +/* Select the main oscillator as the frequency source. SYSCLK is then the frequency + * of the main oscillator. + * + * If BOARD_XTAL_FREQUENCY > 15000000, then the SCS OSCRS bit (bit 4) should also + * be set in the BOARD_SCS_VALUE. + */ + +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 +#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN + +/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. + * The input to the divider (PLLCLK) will be determined by the PLL output. + */ + +#define BOARD_CCLKSEL_DIVIDER 1 +#define BOARD_CCLKSEL_VALUE (BOARD_CCLKSEL_DIVIDER | SYSCON_CCLKSEL_CCLKSEL) + +/* PLL0. PLL0 is used to generate the CPU clock (PLLCLK). + * + * Source clock: Main oscillator + * PLL0 Multiplier value (M): 10 + * PLL0 Pre-divider value (P): 1 + * + * PLL0CLK = (M * SYSCLK) = 120MHz + */ + +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 +#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN + +#define BOARD_PLL0CFG_MSEL 10 +#define BOARD_PLL0CFG_PSEL 1 +#define BOARD_PLL0CFG_VALUE \ + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) + +/* PLL1 : PLL1 is used to generate clock for the USB */ + +#undef CONFIG_LPC17_40_PLL1 +#define BOARD_PLL1CFG_MSEL 4 +#define BOARD_PLL1CFG_PSEL 2 +#define BOARD_PLL1CFG_VALUE \ + (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) + +#ifdef CONFIG_LPC17_40_EMC +/* EMC clock selection. + * + * The EMC clock should not be driven above 80MHz. As a result the EMC + * uses the CPU clock divided by two. + */ + +# define BOARD_EMCCLKSEL_DIVIDER 2 +# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV2 +# define LPC17_40_EMCCLK (LPC17_40_CCLK / BOARD_EMCCLKSEL_DIVIDER) +#endif + +#if defined(CONFIG_LPC17_40_USBHOST) || (CONFIG_LPC17_40_USBDEV) +/* USB divider. The output of the PLL is used as the USB clock + * + * USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz + */ + +# define BOARD_USBCLKSEL_DIVIDER 1 +# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \ + SYSCON_USBCLKSEL_USBSEL_PLL1) +#endif + +/* FLASH Configuration */ + +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 + +/* Flash access use 6 CPU clocks - Safe for any allowed conditions */ + +#define BOARD_FLASHCFG_VALUE (SYSCON_FLASHCFG_TIM_5 | 0x03a) + +/* Ethernet configuration */ + +#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV48 + +/* Set EMC delay values: + * + * CMDDLY: Programmable delay value for EMC outputs in command delayed + * mode. The delay amount is roughly CMDDLY * 250 picoseconds. + * FBCLKDLY: Programmable delay value for the feedback clock that controls + * input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250 + * picoseconds. + * CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT0DLY+1) * 250 picoseconds. + * CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT1DLY+1) * 250 picoseconds. + * + * Optimal for NOR: {1,1,1,1} + * Needed for NAND and SDRAM: {17,1,2,1} + */ + +#ifdef CONFIG_LPC17_40_EMC +#if defined(CONFIG_LPC17_40_EXTNAND) || defined(CONFIG_LPC17_40_EXTDRAM) +# define BOARD_CMDDLY 17 +# define BOARD_FBCLKDLY 17 +# define BOARD_CLKOUT0DLY 1 +# define BOARD_CLKOUT1DLY 1 +#else +# define BOARD_CMDDLY 1 +# define BOARD_FBCLKDLY 1 +# define BOARD_CLKOUT0DLY 1 +# define BOARD_CLKOUT1DLY 1 +#endif +#endif + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 : Connected to P1[18] + * LED2 : Connected to P0[13] + * LED3 : Connected to P1[13] + * LED4 : Connected to P2[19] + * + * These LEDs are connecte to ground so a high output value will illuminate them. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the four LEDs + * on the LPC4088 QuickStart board. The following definitions describe how NuttX + * controls the LEDs: + */ + /* LED1 LED2 LED3 LED4 */ +#define LED_STARTED 0 /* OFF OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF OFF */ +#define LED_STACKCREATED 3 /* ON ON OFF OFF */ +#define LED_INIRQ 4 /* LED3 glows, on while in interrupt */ +#define LED_SIGNAL 4 /* LED3 glows, on while in signal handler */ +#define LED_ASSERTION 4 /* LED3 glows, on while in assertion */ +#define LED_PANIC 4 /* LED3 Flashes at 2Hz */ +#define LED_IDLE 5 /* LED4 glows: ON while active * + * OFF while sleeping */ + +/* Button definitions ***************************************************************/ +/* The LPC4088 QuickStart supports a single button. It must be pulled up by the MCU. + * When closed, the pin will be pulled to ground. So the button will read "1" + * when open and "0" when closed. The button is capable of generating an + * interrupt. + * + * USER1 -- Connected to P2[10] + * + * For the interrupting buttons, interrupts are generated on both edges (press and + * release). + */ + + +#define BOARD_BUTTON_USER1 0 + +#define NUM_BUTTONS 1 + +#define BOARD_BUTTON_USER1_BIT (1 << BOARD_BUTTON_USER1) + +/* Alternate pin selections *********************************************************/ + +/* UART0: + * + * TX --- Connected to P0[2] + * RX --- Connected to P0[3] + */ + +#define GPIO_UART0_TXD GPIO_UART0_TXD_2 +#define GPIO_UART0_RXD GPIO_UART0_RXD_2 + +/* UART1: + * + * RTS --- Connected to P0[22] + * RI --- Connected to P0[21] + * DSR --- Connected to P0[19] + * DCD --- Connected to P0[18] + * CTS --- Connected to P0[17] + * DTR --- Connected to P0[20] + * TXD --- Connected to P0[15] + * RXD --- Connected to P0[16] + */ + +#define GPIO_UART1_RTS GPIO_UART1_RTS_2 +#define GPIO_UART1_RI GPIO_UART1_RI_1 +#define GPIO_UART1_DSR GPIO_UART1_DSR_1 +#define GPIO_UART1_DCD GPIO_UART1_DCD_1 +#define GPIO_UART1_CTS GPIO_UART1_CTS_1 +#define GPIO_UART1_DTR GPIO_UART1_DTR_1 +#define GPIO_UART1_TXD GPIO_UART1_TXD_1 +#define GPIO_UART1_RXD GPIO_UART1_RXD_1 + +/* Ethernet: + * MDC --- Connected to P1[16] + * MDIO --- Connected to P1[17] + */ + +#define GPIO_ENET_MDC GPIO_ENET_MDC_1 +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1 + + +/* External LCD is currently untested. + * These pins will probably need to be updated before using the LCD. */ + +#if 0 +/* LCD R: + * + * VD0 --- Connected to P0[4] + * VD1 --- Connected to P0[5] + * VD2 --- Connected to P4[28] + * VD3 --- Connected to P4[29] + * VD4 --- Connected to P2[6] + * VD5 --- Connected to P2[7] + * VD6 --- Connected to P2[8] + * VD7 --- Connected to P2[9] + */ + +#define GPIO_LCD_VD0 GPIO_LCD_VD0_1 +#define GPIO_LCD_VD1 GPIO_LCD_VD1_1 +#define GPIO_LCD_VD2 GPIO_LCD_VD2_2 +#define GPIO_LCD_VD3 GPIO_LCD_VD3_3 +#define GPIO_LCD_VD4 GPIO_LCD_VD4_1 +#define GPIO_LCD_VD5 GPIO_LCD_VD5_1 +#define GPIO_LCD_VD6 GPIO_LCD_VD6_2 +#define GPIO_LCD_VD7 GPIO_LCD_VD7_2 + +/* LCD G: + * + * VD8 --- Connected to P0[6] + * VD9 --- Connected to P0[7] + * VD10 --- Connected to P1[20] + * VD11 --- Connected to P1[21] + * VD12 --- Connected to P1[22] + * VD13 --- Connected to P1[23] + * VD14 --- Connected to P1[24] + * VD15 --- Connected to P1[25] + */ + +#define GPIO_LCD_VD8 GPIO_LCD_VD8_1 +#define GPIO_LCD_VD9 GPIO_LCD_VD9_1 +#define GPIO_LCD_VD10 GPIO_LCD_VD10_1 +#define GPIO_LCD_VD11 GPIO_LCD_VD11_1 +#define GPIO_LCD_VD12 GPIO_LCD_VD12_1 +#define GPIO_LCD_VD13 GPIO_LCD_VD13_1 +#define GPIO_LCD_VD14 GPIO_LCD_VD14_1 +#define GPIO_LCD_VD15 GPIO_LCD_VD15_1 + +/* LCD B: + * + * VD16 --- Connected to P0[8] + * VD17 --- Connected to P0[9] + * VD18 --- Connected to P2[12] + * VD19 --- Connected to P2[13] + * VD20 --- Connected to P1[26] + * VD21 --- Connected to P1[27] + * VD22 --- Connected to P1[28] + * VD23 --- Connected to P1[29] + * + * DCLK --- Connected to P2[2] + * LP --- Connected to P2[5] + * FP --- Connected to P2[3] + * ENAB_M --- Connected to P2[4] + * PWR --- Connected to P2[0] + */ + +/* XPT2046 Touchscreen: + * +/* -------------- -------------------- ------------ -------------------------------- + * XTPT2046 Module Module + * Signal Connector Connector + * -------------- -------------------- ------------ --------------------------------- + * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ + * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) + * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY + * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) + * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) + * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 + * -------------- -------------------- ------------ --------------------------------- + */ + + +#define GPIO_SSP1_MISO GPIO_SSP1_MISO_3 +#define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2 +#define GPIO_SSP1_SCK GPIO_SSP1_SCK_2 + +#endif + +#endif /* __CONFIG_LPC4088_QUICKSTART_INCLUDE_BOARD_H */ diff --git a/configs/lpc4088-quickstart/kernel/.gitignore b/configs/lpc4088-quickstart/kernel/.gitignore new file mode 100644 index 00000000000..7bacd5aee3e --- /dev/null +++ b/configs/lpc4088-quickstart/kernel/.gitignore @@ -0,0 +1,2 @@ +/nuttx_user.elf + diff --git a/configs/lpc4088-quickstart/kernel/Makefile b/configs/lpc4088-quickstart/kernel/Makefile new file mode 100644 index 00000000000..0d9d4c60afa --- /dev/null +++ b/configs/lpc4088-quickstart/kernel/Makefile @@ -0,0 +1,122 @@ +############################################################################ +# configs/lpc4088-quickstart/kernel/Makefile +# +# Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +# This is the directory for the board-specific header files + +BOARD_INCLUDE = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)include + +# The entry point name (if none is provided in the .config file) + +CONFIG_USER_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_USER_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + USER_LIBPATHS = ${shell for path in $(USERLIBS); do dir=`dirname $(TOPDIR)$(DELIM)$$path`;echo "-L\"`cygpath -w $$dir`\"";done} + USER_LDSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld}" + USER_LDSCRIPT += -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)user-space.ld}" + USER_HEXFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.hex}" + USER_SRECFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.srec}" + USER_BINFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.bin}" +else + # Linux/Cygwin-native toolchain + USER_LIBPATHS = $(addprefix -L$(TOPDIR)$(DELIM),$(dir $(USERLIBS))) + USER_LDSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld + USER_LDSCRIPT += -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)user-space.ld + USER_HEXFILE += "$(TOPDIR)$(DELIM)nuttx_user.hex" + USER_SRECFILE += "$(TOPDIR)$(DELIM)nuttx_user.srec" + USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" +endif + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = lpc17_40_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/configs/lpc4088-quickstart/kernel/lpc17_40_userspace.c b/configs/lpc4088-quickstart/kernel/lpc17_40_userspace.c new file mode 100644 index 00000000000..73997b45b66 --- /dev/null +++ b/configs/lpc4088-quickstart/kernel/lpc17_40_userspace.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/kernel/lpc17_40_userspace.c + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x00040000 +# error "CONFIG_NUTTX_USERSPACE must be 0x00040000 to match memory.ld" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. They are + * not actual uint32_t storage locations! They are only used meaningfully in the + * following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declareion extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data (it is + * not!). + * - We can recoved the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +extern uint32_t _stext; /* Start of .text */ +extern uint32_t _etext; /* End_1 of .text + .rodata */ +extern const uint32_t _eronly; /* End+1 of read only section (.text + .rodata) */ +extern uint32_t _sdata; /* Start of .data */ +extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _sbss; /* Start of .bss */ +extern uint32_t _ebss; /* End+1 of .bss */ + +/* This is the user space entry point */ + +int CONFIG_USER_ENTRYPOINT(int argc, char *argv[]); + +const struct userspace_s userspace __attribute__ ((section (".userspace"))) = +{ + /* General memory map */ + + .us_entrypoint = (main_t)CONFIG_USER_ENTRYPOINT, + .us_textstart = (uintptr_t)&_stext, + .us_textend = (uintptr_t)&_etext, + .us_datasource = (uintptr_t)&_eronly, + .us_datastart = (uintptr_t)&_sdata, + .us_dataend = (uintptr_t)&_edata, + .us_bssstart = (uintptr_t)&_sbss, + .us_bssend = (uintptr_t)&_ebss, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = task_startup, +#ifndef CONFIG_DISABLE_PTHREAD + .pthread_startup = pthread_startup, +#endif + + /* Signal handler trampoline */ + +#ifndef CONFIG_DISABLE_SIGNALS + .signal_handler = up_signal_handler, +#endif + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIB_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/configs/lpc4088-quickstart/knsh/Make.defs b/configs/lpc4088-quickstart/knsh/Make.defs new file mode 100644 index 00000000000..5a907b19594 --- /dev/null +++ b/configs/lpc4088-quickstart/knsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/lpc4088-quickstart/knsh/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-m$(DELIM)Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld}" + ARCHSCRIPT += -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)kernel-space.ld}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld + ARCHSCRIPT += -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)kernel-space.ld +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/lpc4088-quickstart/knsh/defconfig b/configs/lpc4088-quickstart/knsh/defconfig new file mode 100644 index 00000000000..440ceb4281d --- /dev/null +++ b/configs/lpc4088-quickstart/knsh/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LPC17_40_EMC is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lpc4088-quickstart" +CONFIG_ARCH_BOARD_LPC4088_QUICKSTART=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y +CONFIG_ARCH_CHIP_LPC4088=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_OABI_TOOLCHAIN=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +CONFIG_ARM_MPU=y +CONFIG_BCH=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=11934 +CONFIG_BUILD_PROTECTED=y +CONFIG_DEV_LOOP=y +CONFIG_DISABLE_POLL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_UART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_DISABLE_DD=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x00040000 +CONFIG_PASS1_BUILDIR="configs/lpc4088-quickstart/kernel" +CONFIG_PIPES=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x10000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=11 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2013 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYS_RESERVED=8 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpc4088-quickstart/nsh/defconfig b/configs/lpc4088-quickstart/nsh/defconfig new file mode 100644 index 00000000000..8249a698142 --- /dev/null +++ b/configs/lpc4088-quickstart/nsh/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LPC17_40_EMC is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lpc4088-quickstart" +CONFIG_ARCH_BOARD_LPC4088_QUICKSTART=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y +CONFIG_ARCH_CHIP_LPC4088=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +CONFIG_BCH=y +CONFIG_BOARD_LOOPSPERMSEC=11934 +CONFIG_BUILTIN=y +CONFIG_DEV_LOOP=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_UART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PIPES=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x10000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=23 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2019 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpc4088-quickstart/scripts/Make.defs b/configs/lpc4088-quickstart/scripts/Make.defs new file mode 100644 index 00000000000..43dbfbee806 --- /dev/null +++ b/configs/lpc4088-quickstart/scripts/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# configs/lpc4088-quickstart/scripts/Make.defs +# +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-m$(DELIM)Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)ld.script}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/lpc4088-quickstart/scripts/kernel-space.ld b/configs/lpc4088-quickstart/scripts/kernel-space.ld new file mode 100644 index 00000000000..c27292d0667 --- /dev/null +++ b/configs/lpc4088-quickstart/scripts/kernel-space.ld @@ -0,0 +1,110 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/scripts/kernel-space.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpc4088-quickstart/scripts/ld.script b/configs/lpc4088-quickstart/scripts/ld.script new file mode 100644 index 00000000000..223d0974743 --- /dev/null +++ b/configs/lpc4088-quickstart/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/scripts/ld.script + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC4088 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses + * 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb + * at 0x20004000 on bank1. + * + * Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM + * address range. + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K + AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K + AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > FLASH + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > FLASH + + .ARM.extab : { + *(.ARM.extab*) + } > FLASH + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > FLASH + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > SRAM AT > FLASH + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > SRAM + + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpc4088-quickstart/scripts/memory.ld b/configs/lpc4088-quickstart/scripts/memory.ld new file mode 100644 index 00000000000..6cf5900b02e --- /dev/null +++ b/configs/lpc4088-quickstart/scripts/memory.ld @@ -0,0 +1,99 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/scripts/memory.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC4088 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96KB of total SRAM: 64KB of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8KB at addresses + * 0x20000000 bank0 first and 8KB at 0x20002000 at bank0 second. And 16KB + * at 0x20004000 on bank1. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 256KB of + * FLASH and 4KB of SRAM. That, of course, can be optimized as needed (See + * also configs/lpc4088-quickstart/scripts/kernel-space.ld); 256KB is probably much + * more than is needed by the RTOS! That size is selected only because it + * is available due to alignment issues for the user space FLASH memory. + * + * Alignment of the user space FLASH partition is a critical factor: The + * user space FLASH partition will be spanned with a single region of size + * 2**n bytes. The alignment of the user-space region must be the same. As + * a consequence, as the user-space increases in size, the alignmment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 256KB at it would have to be positioned at + * 0x00400000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 64KB CPU SRAM region is as follows: + * + * 0x10000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x10000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x10000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * ------- ---- Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * 0x10000 8000: Beginning of user heap. Can vary with other settings. + * 0x10001 0000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 256Kb FLASH */ + + kflash (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* More than needed */ + uflash (rx) : ORIGIN = 0x00040000, LENGTH = 256K + + /* 64Kb of SRAM in the CPU block */ + + ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 4K /* May include waste */ + usram (rwx) : ORIGIN = 0x10001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x10002000, LENGTH = 24K /* All used as heap */ + + /* Other peripheral memory (free, nothing is linked here) */ + + ahbram8_b0a(rwx) : ORIGIN = 0x20000000, LENGTH = 8K + ahbram8_b0b(rwx) : ORIGIN = 0x20002000, LENGTH = 8K + ahbram16(rwx) : ORIGIN = 0x20004000, LENGTH = 16K +} diff --git a/configs/lpc4088-quickstart/scripts/user-space.ld b/configs/lpc4088-quickstart/scripts/user-space.ld new file mode 100644 index 00000000000..36551857a24 --- /dev/null +++ b/configs/lpc4088-quickstart/scripts/user-space.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/scripts/user-space.ld + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpc4088-quickstart/src/.gitignore b/configs/lpc4088-quickstart/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/configs/lpc4088-quickstart/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/lpcxpresso-lpc1115/src/Makefile b/configs/lpc4088-quickstart/src/Makefile similarity index 76% rename from configs/lpcxpresso-lpc1115/src/Makefile rename to configs/lpc4088-quickstart/src/Makefile index a55c8589293..d68526f0bf7 100644 --- a/configs/lpcxpresso-lpc1115/src/Makefile +++ b/configs/lpc4088-quickstart/src/Makefile @@ -1,7 +1,7 @@ ############################################################################ -# configs/lpcxpresso-lpc1115/src/Makefile +# configs/lpc4088-quickstart/src/Makefile # -# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -36,26 +36,35 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc11_boot.c +CSRCS = lpc17_40_boardinitialize.c lpc17_40_bringup.c lpc17_40_ssp.c + +ifeq ($(CONFIG_LPC17_40_EMC),y) + +ifeq ($(CONFIG_LPC17_40_EXTDRAM),y) + CSRCS += lpc17_40_sdraminitialize.c +endif +endif + +ifeq ($(CONFIG_LPC17_40_LCD),y) + CSRCS += lpc17_40_lcd.c +endif + +ifeq ($(CONFIG_LPC17_40_EXTNAND),y) + CSRCS += lpc17_40_nandinitialize.c +endif ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc11_appinit.c -endif - -ifeq ($(CONFIG_KL_SPI0),y) -CSRCS += lpc11_spi.c -else -ifeq ($(CONFIG_KL_SPI1),y) -CSRCS += lpc11_spi.c -endif + CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += lpc11_leds.c + CSRCS += lpc17_40_autoleds.c +else + CSRCS += lpc17_40_userleds.c endif -ifeq ($(CONFIG_PWM),y) -CSRCS += lpc11_pwm.c +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += lpc17_40_buttons.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/lpc4088-quickstart/src/lpc17_40_appinit.c b/configs/lpc4088-quickstart/src/lpc17_40_appinit.c new file mode 100644 index 00000000000..775d569f1bd --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * config/lpc4088-quickstart/src/lpc17_40_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "lpc4088-quickstart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return lpc4088_quickstart_bringup(); +#endif +} diff --git a/configs/lpc4088-quickstart/src/lpc17_40_autoleds.c b/configs/lpc4088-quickstart/src/lpc17_40_autoleds.c new file mode 100644 index 00000000000..f70b5a53cd5 --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_autoleds.c @@ -0,0 +1,271 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/src/lpc17_40_autoleds.c + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_gpio.h" +#include "lpc4088-quickstart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * These LEDs are driven through a PNP transistor so a low output value will + * illuminate them. + + * LED1 : Connected to P1[18] + * LED2 : Connected to P0[13] + * + * These LEDs are connected to ground so a high output value will illuminate them. + * + * LED3 : Connected to P1[13] + * LED4 : Connected to P2[19] + * + + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the four LEDs + * on the LPC4088 Quickstart Board. The following definitions describe how NuttX + * controls the LEDs: + * + * LED1 LED2 LED3 LED4 + * LED_STARTED 0 OFF OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF OFF + * LED_STACKCREATED 3 ON ON OFF OFF + * LED_INIRQ 4 LED3 glows, on while in interrupt + * LED_SIGNAL 4 LED3 glows, on while in signal handler + * LED_ASSERTION 4 LED3 glows, on while in assertion + * LED_PANIC 4 LED3 Flashes at 2Hz + * LED_IDLE 5 LED4 glows, ON while sleeping + */ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LPC4088_QUICKSTART_LED1 (1 << 0) +#define LPC4088_QUICKSTART_LED2 (1 << 1) +#define LPC4088_QUICKSTART_LED3 (1 << 2) +#define LPC4088_QUICKSTART_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((LPC4088_QUICKSTART_LED1|LPC4088_QUICKSTART_LED2|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((LPC4088_QUICKSTART_LED1|LPC4088_QUICKSTART_LED2|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((LPC4088_QUICKSTART_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((LPC4088_QUICKSTART_LED2|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((LPC4088_QUICKSTART_LED1|LPC4088_QUICKSTART_LED2|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((LPC4088_QUICKSTART_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((LPC4088_QUICKSTART_LED1|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((LPC4088_QUICKSTART_LED1) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((LPC4088_QUICKSTART_LED2|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((LPC4088_QUICKSTART_LED1|LPC4088_QUICKSTART_LED2) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((LPC4088_QUICKSTART_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((LPC4088_QUICKSTART_LED1|LPC4088_QUICKSTART_LED3|LPC4088_QUICKSTART_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_EVENT_ON_SETBITS ((LPC4088_QUICKSTART_LED3) << ON_SETBITS_SHIFT) +#define LED_EVENT_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_EVENT_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_EVENT_OFF_CLRBITS ((LPC4088_QUICKSTART_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_IDLE_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_IDLE_ON_CLRBITS ((LPC4088_QUICKSTART_LED4) << ON_CLRBITS_SHIFT) +#define LED_IDLE_OFF_SETBITS ((LPC4088_QUICKSTART_LED4) << OFF_SETBITS_SHIFT) +#define LED_IDLE_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_EVENT_ON_SETBITS | LED_EVENT_ON_CLRBITS | + LED_EVENT_OFF_SETBITS | LED_EVENT_OFF_CLRBITS), + + (LED_IDLE_ON_SETBITS | LED_IDLE_ON_CLRBITS | + LED_IDLE_OFF_SETBITS | LED_IDLE_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & LPC4088_QUICKSTART_LED1) != 0) + { + lpc17_40_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & LPC4088_QUICKSTART_LED2) != 0) + { + lpc17_40_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & LPC4088_QUICKSTART_LED3) != 0) + { + lpc17_40_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & LPC4088_QUICKSTART_LED4) != 0) + { + lpc17_40_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & LPC4088_QUICKSTART_LED1) != 0) + { + lpc17_40_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & LPC4088_QUICKSTART_LED2) != 0) + { + lpc17_40_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & LPC4088_QUICKSTART_LED3) != 0) + { + lpc17_40_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & LPC4088_QUICKSTART_LED4) != 0) + { + lpc17_40_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); + lpc17_40_configgpio(GPIO_LED3); + lpc17_40_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} diff --git a/configs/lpc4088-quickstart/src/lpc17_40_boardinitialize.c b/configs/lpc4088-quickstart/src/lpc17_40_boardinitialize.c new file mode 100644 index 00000000000..58f24dac9ac --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_boardinitialize.c @@ -0,0 +1,133 @@ +/************************************************************************************ + * configs/lpc4088_quickstart/src/lpc17_40_boardinitialize.c + * + * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_emc.h" + +#include "lpc4088-quickstart.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_40_boardinitialize + * + * Description: + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc17_40_boardinitialize(void) +{ + /* Initialize the EMC, SDRAM, NOR FLASH, and NAND FLASH */ + +#ifdef CONFIG_LPC17_40_EMC + lpc17_40_emcinitialize(); + +#ifdef CONFIG_LPC17_40_EXTDRAM + lpc4088_quickstart_sdram_initialize(); +#endif + +#ifdef CONFIG_LPC17_40_SPIFI + lpc4088_quickstart_flash_initialize(); +#endif +#endif + +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) + /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) + * the weak function lpc4088_quickstart_sspdev_initialize() has been brought + * into the link. + */ + + if (lpc4088_quickstart_sspdev_initialize) + { + lpc4088_quickstart_sspdev_initialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)lpc4088_quickstart_bringup(); +} +#endif diff --git a/configs/lpc4088-quickstart/src/lpc17_40_bringup.c b/configs/lpc4088-quickstart/src/lpc17_40_bringup.c new file mode 100644 index 00000000000..e4cb1a99da6 --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_bringup.c @@ -0,0 +1,403 @@ +/**************************************************************************** + * config/lpc4088_quickstart/src/lpc17_40_bringup.c + * + * Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "lpc17_40_gpio.h" +#include "lpc17_40_sdcard.h" +#include "lpc17_40_usbhost.h" +#include "lpc4088-quickstart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#define NSH_HAVE_MMCSD 0 +#define NSH_HAVE_USBHOST 1 +#define NSH_HAVE_USBHDEV 1 + +#undef NSH_HAVE_MMCSD_CD +#undef NSH_HAVE_MMCSD_CDINT + +/* MMC/SD support */ + +#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) +# undef NSH_HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef NSH_HAVE_MMCSD +#endif + +/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# warning "Assuming slot MMC/SD slot 0" +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDMINOR) +# warning "Assuming /dev/mmcsd0" +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +#endif + +/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also + * used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper + * on board that enables the CD pin. + */ + +#ifdef NSH_HAVE_MMCSD +# ifdef CONFIG_MMCSD_HAVE_CARDDETECT +# define NSH_HAVE_MMCSD_CD 1 +# ifdef CONFIG_LPC17_40_GPIOIRQ +# define NSH_HAVE_MMCSD_CDINT 1 +# endif +# endif +#endif + +#if defined(NSH_HAVE_MMCSD_CD) && \ + (defined(CONFIG_LPC17_40_SSP1) || defined(CONFIG_LPC17_40_USBDEV)) +# warning "Use of SD Card Detect pin conflicts with SSP1 and/or USB device" +#endif + +/* USB Host */ + +#ifndef CONFIG_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifndef CONFIG_LPC17_40_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifdef NSH_HAVE_USBHOST +# ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +# endif +# ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +# endif +#endif + +/* USB Device */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +#ifndef CONFIG_LPC17_40_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif +#ifdef NSH_HAVE_MMCSD +static FAR struct sdio_dev_s *g_sdiodev; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + syslog(LOG_INFO, "nsh_waiter: Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + syslog(LOG_INFO, "nsh_waiter: %s\n", + hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Name: nsh_cdinterrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD_CDINT +static int nsh_cdinterrupt(int irq, FAR void *context, FAR void *arg) +{ + static bool inserted = 0xff; /* Impossible value */ + bool present; + + present = !lpc17_40_gpioread(GPIO_SD_CD); + if (present != inserted) + { + sdio_mediachange(g_sdiodev, present); + inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: nsh_sdinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD +static int nsh_sdinitialize(void) +{ + int ret; + +#ifdef NSH_HAVE_MMCSD_CD + /* Configure the SD card detect GPIO */ + + lpc17_40_configgpio(GPIO_SD_CD); + +#ifdef NSH_HAVE_MMCSD_CDINT + /* Attach an interrupt handler to get notifications when a card is + * inserted or deleted. + */ + + (void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL); + up_enable_irq(LPC17_40_IRQ_P0p13); + +#endif +#endif + + /* First, get an instance of the SDIO interface */ + + g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdiodev) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Check if there is a card in the slot and inform the SDCARD driver. If + * we do not support the card detect, then let's assume that there is + * one. + */ + +#ifdef NSH_HAVE_MMCSD_CD + sdio_mediachange(g_sdiodev, !lpc17_40_gpioread(GPIO_SD_CD)); +#else + sdio_mediachange(g_sdiodev, true); +#endif + return OK; +} +#else +# define nsh_sdinitialize() (OK) +#endif + +/**************************************************************************** + * Name: nsh_usbhostinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_usbhostinitialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + syslog(LOG_INFO, "Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + syslog(LOG_INFO, "Initialize USB host\n"); + g_usbconn = lpc17_40_usbhost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + syslog(LOG_INFO, "Start nsh_waiter\n"); + + pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + (main_t)nsh_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#else +# define nsh_usbhostinitialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc4088_quickstart_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ****************************************************************************/ + +int lpc4088_quickstart_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system at the default location, /proc */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs: %d\n", ret); + } +#endif + + /* Initialize SPI-based microSD */ + + ret = nsh_sdinitialize(); + if (ret == OK) + { + /* Initialize USB host */ + + ret = nsh_usbhostinitialize(); + } + + return ret; +} diff --git a/configs/lpc4088-quickstart/src/lpc17_40_buttons.c b/configs/lpc4088-quickstart/src/lpc17_40_buttons.c new file mode 100644 index 00000000000..cc79367950b --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_buttons.c @@ -0,0 +1,229 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/src/lpc17_40_buttons.c + * + * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "lpc17_40_gpio.h" +#include "lpc4088-quickstart.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The LPC4088 Quickstart supports several buttons. All will read "1" when + * open and "0" when closed + * + * USER1 -- Connected to P2[10] + * + * The switch is connected to ground and should be pulled up and sensed + * with a value of '0' when closed. + */ + +/* Pin configuration for each LPC4088 Quickstart button. This array is + * indexed by the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const lpc17_40_pinset_t g_buttoncfg[NUM_BUTTONS] = +{ + GPIO_USER1 +}; + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +/* This array provides the mapping from button ID numbers to button IRQ + * numbers. + */ + +static const uint8_t g_buttonirq[NUM_BUTTONS] = +{ + GPIO_USER1_IRQ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as interrupting inputs. */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + lpc17_40_configgpio(g_buttoncfg[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons. + * + * board_buttons() may be called at any time to harvest the state of every + * button. The state of the buttons is returned as a bitset with one + * bit corresponding to each button: If the bit is set, then the button + * is pressed. See the BOARD_BUTTON_*_BIT and BOARD_JOYSTICK_*_BIT + * definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = lpc17_40_gpioread(g_buttoncfg[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_button_irq() may be called to register button + * interrupt handlers. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BOARD_BUTTON_* and BOARD_JOYSTICK_* definitions in board.h for + * the meaning of enumeration values. + * + * Note that board_button_irq() also enables button interrupts. Button + * interrupts will remain enabled after the interrupt handler is attached. + * Interrupts may be disabled (and detached) by calling board_button_irq with + * irqhandler equal to NULL. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + irqstate_t flags; + int ret = -EINVAL; + int irq; + + /* Verify that the button ID is within range */ + + if ((unsigned)id < NUM_BUTTONS) + { + /* Get the IRQ number for the button; A value of zero indicates that + * the button does not support the interrupt function. + */ + + irq = g_buttonirq[id]; + if (irq > 0) + { + /* Disable interrupts until we are done */ + + flags = enter_critical_section(); + + /* Configure the interrupt. Either attach and enable the new + * interrupt or disable and detach the old interrupt handler. + */ + + if (irqhandler) + { + /* Attach then enable the new interrupt handler */ + + (void)irq_attach(irq, irqhandler, arg); + up_enable_irq(irq); + } + else + { + /* Disable then detach the old interrupt handler */ + + up_disable_irq(irq); + (void)irq_detach(irq); + } + + leave_critical_section(flags); + } + + ret = OK; + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/lpc4088-quickstart/src/lpc17_40_lcd.c b/configs/lpc4088-quickstart/src/lpc17_40_lcd.c new file mode 100644 index 00000000000..c7ac2f8834a --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_lcd.c @@ -0,0 +1,88 @@ +/************************************************************************************ + * configs/lpc4088-quickstart/src/lpc17_40_lcd.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "lpc17_40_lcd.h" +#include "lpc17_40_gpio.h" + +#include "lpc4088-devkit.h" + +#ifdef CONFIG_LPC17_40_LCD + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_devkit_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ************************************************************************************/ + +void lpc4088_devkit_lcd_initialize(void) +{ + /* Configure the LCD backlight (and turn the backlight off) */ +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT + lpc17_40_configgpio(GPIO_LCD_BL); +#endif +} + +/************************************************************************************ + * Name: lpc17_40_backlight + * + * Description: + * If CONFIG_LPC17_40_LCD_BACKLIGHT is defined, then the board-specific logic must + * provide this interface to turn the backlight on and off. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT +void lpc17_40_backlight(bool blon) +{ + lpc17_40_gpiowrite(GPIO_LCD_BL, blon); +} +#endif + +#endif /* CONFIG_LPC17_40_LCD */ diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_dac.c b/configs/lpc4088-quickstart/src/lpc17_40_nandinitialize.c similarity index 68% rename from configs/lpcxpresso-lpc1115/src/lpc11_dac.c rename to configs/lpc4088-quickstart/src/lpc17_40_nandinitialize.c index 93730ed0782..677f14ffb82 100644 --- a/configs/lpcxpresso-lpc1115/src/lpc11_dac.c +++ b/configs/lpc4088-quickstart/src/lpc17_40_nandinitialize.c @@ -1,12 +1,8 @@ /************************************************************************************ - * configs/lpcxpresso-lpc1115/src/lpc11_dac.c + * configs/lpc4088-quickstart/src/lpc17_40_nandinitialize.c + * arch/arm/src/board/lpc17_40_nandinitialize.c * - * Copyright (C) 2013 Zilogic Systems. All rights reserved. - * Author: Kannan - * - * Based on configs/stm3220g-eval/src/up_dac.c - * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,60 +40,54 @@ #include -#include #include -#include #include #include "up_arch.h" #include "up_internal.h" -#include "lpc11_dac.h" +#include "lpc4088-quickstart.h" -#ifdef CONFIG_DAC +#if defined(CONFIG_LPC17_40_SPIFI) /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: dac_devinit + * Name: lpc4088_quickstart_nand_initialize * * Description: - * All LPC17xx architectures must provide the following interface to work with - * examples/diag. + * Initialize NAND FLASH * ************************************************************************************/ -int dac_devinit(void) +void _lpc4088_quickstart_nand_initialize(void) { - static bool initialized = false; - struct dac_dev_s *dac; - int ret; + uint32_t regval; - if (!initialized) - { - /* Call lpc11_dacinitialize() to get an instance of the dac interface */ + /* Set the memory width and byte lanes */ - dac = lpc11_dacinitialize(); - if (dac == NULL) - { - aerr("ERROR: Failed to get dac interface\n"); - return -ENODEV; - } + regval = getreg32(LPC17_40_EMC_STATICCONFIG1); + regval &= ~EMC_STATICCONFIG_MW_MASK; + regbal |= (EMC_STATICCONFIG_MW_8BIT | EMC_STATICCONFIG_PB); + putreg32(regval, LPC17_40_EMC_STATICCONFIG1); - ret = dac_register("/dev/dac0", dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } + /* Configure timing */ - initialized = true; - } + putreg32(2, LPC17_40_EMC_STATICWAITWEN1); + putreg32(2, LPC17_40_EMC_STATICWAITOEN1); + putreg32(31, LPC17_40_EMC_STATICWAITRD1); + putreg32(31, LPC17_40_EMC_STATICWAITPAGE1); + putreg32(31, LPC17_40_EMC_STATICWAITWR1); + putreg32(31, LPC17_40_EMC_STATICWAITTURN1); - return OK; + /* GPIO P2[21] connects to the Ready/Busy pin of the NAND part. We need to + * reconfigure this pin as normal GPIO input. + */ + + lpc17_40_gpioconfig(GPIO_NAND_RB); } -#endif /* CONFIG_DAC */ +#endif /* CONFIG_LPC17_40_SPIFI */ diff --git a/configs/lpc4088-quickstart/src/lpc17_40_sdraminitialize.c b/configs/lpc4088-quickstart/src/lpc17_40_sdraminitialize.c new file mode 100644 index 00000000000..05ecda87709 --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_sdraminitialize.c @@ -0,0 +1,233 @@ +/************************************************************************************ + * configs/lpc4088-quickstart/src/lpc17_40_sdraminitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_emc.h" + +#include "lpc4088-quickstart.h" + +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTDRAM) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided), or + * LPC17_40_CCLK / 2 as determined by settings in the board.h header file. + * + * For example: + * LPC17_40_CCLCK = 120,000,000 + * EMCCLKSEL -> LPC17_40_CCLK divided by 2 + * LPC17_40_EMCCLK = 60,000,000 + * LPC17_40_EMCCLK_MHZ = 60 (Rounded to an integer) + * EMC_NSPERCLK = 16.667 (Represented with 4 bits of fraction, 267) + * + * EMC_NS2CLK(63) = ((63 << 4) + 266) / 267 = 4 (actual 3.78) + * EMC_NS2CLK(20) = ((20 << 4) + 266) / 267 = 2 (actual 1.20) + */ + +#define LPC17_40_EMCCLK_MHZ ((LPC17_40_EMCCLK + 500000) / 1000000) +#define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_40_EMCCLK_MHZ >> 1)) / LPC17_40_EMCCLK_MHZ) +#define EMC_NS2CLK(ns) (((ns << 4) + (EMC_NSPERCLK_B4 - 1)) / EMC_NSPERCLK_B4) +#define MDKCFG_RASCAS0VAL 0x00000303 + +/* Set up for 32-bit SDRAM at CS0 */ + +#ifdef CONFIG_LPC17_40_EXTDRAMSIZE +# define SDRAM_SIZE CONFIG_LPC17_40_EXTDRAMSIZE +#endif + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT +# ifndef SDRAM_SIZE +# define SDRAM_SIZE 0x02000000 /* 256Mbit */ +# endif +#else /* if defined(CONFIG_LPC17_40_SDRAM_32BIT) */ +# undef CONFIG_LPC17_40_SDRAM_32BIT +# define CONFIG_LPC17_40_SDRAM_32BIT 1 +# ifndef SDRAM_SIZE +# define SDRAM_SIZE 0x04000000 /* 512Mbit */ +# endif +#endif + +#define SDRAM_BASE 0xa0000000 /* CS0 */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc4088_quickstart_sdram_initialize + * + * Description: + * Initialize SDRAM + * + ************************************************************************************/ + +void lpc4088_quickstart_sdram_initialize(void) +{ + uint32_t regval; + int i; + + /* Reconfigure delays: + * + * CMDDLY: Programmable delay value for EMC outputs in command delayed + * mode. The delay amount is roughly CMDDLY * 250 picoseconds. + * FBCLKDLY: Programmable delay value for the feedback clock that controls + * input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250 + * picoseconds. + * CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT0DLY+1) * 250 picoseconds. + * CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT1DLY+1) * 250 picoseconds. + */ + + regval = SYSCON_EMCDLYCTL_CMDDLY(32) | + SYSCON_EMCDLYCTL_FBCLKDLY(32) | + SYSCON_EMCDLYCTL_CLKOUT0DLY(1) | + SYSCON_EMCDLYCTL_CLKOUT1DLY(1); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + + /* Configure the SDRAM */ + + putreg32( EMC_NS2CLK(20), LPC17_40_EMC_DYNAMICRP); /* TRP = 20 nS */ + putreg32( 15, LPC17_40_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */ + putreg32( 0, LPC17_40_EMC_DYNAMICSREX); /* TSREX = 1 clock */ + putreg32( 1, LPC17_40_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */ + putreg32(EMC_NS2CLK(20) + 2, LPC17_40_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */ + putreg32( 1, LPC17_40_EMC_DYNAMICWR); /* TWR = 2 clocks */ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */ + putreg32( 15, LPC17_40_EMC_DYNAMICXSR); /* Exit self-refresh to active */ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */ + putreg32( 1, LPC17_40_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */ + + /* Command delayed strategy, using EMCCLKDELAY */ + + putreg32(EMC_DYNAMICREADCONFIG_RD_CMD, LPC17_40_EMC_DYNAMICREADCONFIG); + + /* H57V2562GTR-75C: TCL=3CLK, TRCD = 20ns(min), 3 CLK = 24ns */ + + putreg32(MDKCFG_RASCAS0VAL, LPC17_40_EMC_DYNAMICRASCAS0); + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT + /* For Manley lpc1778 SDRAM: H57V2562GTR-75C, 256Mb, 16Mx16, 4 banks, row=13, column=9: + * + * 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC + */ + + putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13), + LPC17_40_EMC_DYNAMICCONFIG0); + +#elif defined CONFIG_LPC17_40_SDRAM_32BIT + /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ + + putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13) | EMC_DYNAMICCONFIG_AM1, + LPC17_40_EMC_DYNAMICCONFIG0); +#endif + + up_mdelay(100); + + /* Issue NOP command */ + + putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_NOP, + LPC17_40_EMC_DYNAMICCONTROL); + + /* Wait 200 Msec */ + + up_mdelay(200); + + /* Issue PALL command */ + + putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_PALL, + LPC17_40_EMC_DYNAMICCONTROL); + + putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */ + + /* Wait 128 AHB clock cycles */ + + for (i = 0; i < 128; i++); + + /* 64ms/8192 = 7.8125us, nx16x8.33ns < 7.8125us, n < 58.6*/ + + regval = 64000000 / (1 << 13); + regval -= 16; + regval >>= 4; + regval = regval * LPC17_40_EMCCLK_MHZ / 1000; + putreg32(regval, LPC17_40_EMC_DYNAMICREFRESH); + + /* Issue MODE command */ + + putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_MODE, + LPC17_40_EMC_DYNAMICCONTROL); + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT + (void)getreg16(SDRAM_BASE | (0x33 << 12)); /* 8 burst, 3 CAS latency */ +#elif defined CONFIG_LPC17_40_SDRAM_32BIT + (void)getreg32(SDRAM_BASE | (0x32 << 13)); /* 4 burst, 3 CAS latency */ +#endif + + /* Issue NORMAL command */ + + putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); + + /* Enable buffer */ + + regval = getreg32(LPC17_40_EMC_DYNAMICCONFIG0); + regval |= EMC_DYNAMICCONFIG_B; + putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0); + up_mdelay(12); + + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK; + regval |= SYSCON_EMCDLYCTL_CMDDLY(18); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); +} + +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTDRAM */ diff --git a/configs/lpc4088-quickstart/src/lpc17_40_ssp.c b/configs/lpc4088-quickstart/src/lpc17_40_ssp.c new file mode 100644 index 00000000000..6d0b6601c04 --- /dev/null +++ b/configs/lpc4088-quickstart/src/lpc17_40_ssp.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * configs/lpc4088-quickstart/src/lpc17_40_ssp.c + * arch/arm/src/board/lpc17_40_ssp.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" +#include "lpc4088-quickstart.h" + +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_GPIO_INFO +# define ssp_dumpgpio(p,m) lpc17_40_dumpgpio(p,m) +#else +# define ssp_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc4088_quickstart_sspdev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LPC1766-STK. + * + ****************************************************************************/ + +void weak_function lpc4088_quickstart_sspdev_initialize(void) +{ + /* Configure the SSP0 chip select GPIOs. */ + +#ifdef CONFIG_LPC17_40_SSP0 +#endif + + /* Configure SSP1 chip select GPIOs. This includes the touchscreen on the + * the LCD module. + */ + +#ifdef CONFIG_LPC17_40_SSP1 + ssp_dumpgpio(GPIO_TC_CS, "BEFORE SSP1 Initialization"); + lpc17_40_configgpio(GPIO_TC_CS); + ssp_dumpgpio(GPIO_TC_CS, "AFTER SSP1 Initialization"); +#endif + + /* Configure the SSP2 chip select GPIOs. */ + +#ifdef CONFIG_LPC17_40_SSP2 +#endif +} + +/************************************************************************************ + * Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status + * + * Description: + * The external functions, lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status + * must be provided by board-specific logic. They are implementations of the select + * and status methods of the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your + * board: + * + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select + * pins. + * 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application + * initialization logic + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#ifdef CONFIG_LPC17_40_SSP2 +void lpc17_40_ssp2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t lpc17_40_ssp2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 || CONFIG_LPC17_40_SSP2 */ diff --git a/arch/arm/src/lpc11xx/lpc11_clockconfig.c b/configs/lpc4088-quickstart/src/lpc17_40_userleds.c similarity index 64% rename from arch/arm/src/lpc11xx/lpc11_clockconfig.c rename to configs/lpc4088-quickstart/src/lpc17_40_userleds.c index f906de18dd8..99a9208e5d1 100644 --- a/arch/arm/src/lpc11xx/lpc11_clockconfig.c +++ b/configs/lpc4088-quickstart/src/lpc17_40_userleds.c @@ -1,7 +1,8 @@ /**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_clockconfig.c + * configs/lpc4088-quickstart/src/lpc17_40_userleds.c + * arch/arm/src/board/lpc17_40_userleds.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -40,83 +41,101 @@ #include #include +#include #include -#include #include +#include +#include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lpc11_clockconfig.h" -#include "hardware/lpc11_syscon.h" -#include "hardware/lpc111x_iocon.h" -#include "hardware/lpc11_gpio.h" + +#include "lpc17_40_gpio.h" +#include "lpc4088-quickstart.h" + +#ifndef CONFIG_ARCH_LEDS /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) +#else +# define led_dumpgpio(m) +#endif /**************************************************************************** * Private Data ****************************************************************************/ -/**************************************************************************** - * Private Functions - ****************************************************************************/ +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: lpc11_clockconfig - * - * Description: - * Called to initialize the LPC11xx. This does whatever setup is needed - * to put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * + * Name: board_userled_initialize ****************************************************************************/ -void lpc11_clockconfig(void) +void board_userled_initialize(void) { - int regval; + /* Configure LED1-4 GPIOs for output */ - /* Enable the main oscillator (or not) and the frequency range of the main - * oscillator. - */ - -#ifdef CONFIG_LPC11_INTRCOSC - regval = SYSCON_SYSPLLCLKSEL_IRCOSC; -#else - regval = SYSCON_SYSPLLCLKSEL_SYSOSC; -#endif - putreg32(regval, LPC11_SYSCON_SYSPLLCLKSEL); - - /* MSEL = 3 , PSEL = 1 */ - - putreg32((SYSCON_SYSPLLCTRL_MSEL_DIV(4) | SYSCON_SYSPLLCTRL_PSEL_DIV2), - LPC11_SYSCON_SYSPLLCTRL); - - /* Power UP the PLL */ - - regval = getreg32(LPC11_SYSCON_PDRUNCFG); - regval &= ~(SYSCON_PDRUNCFG_SYSPLL_PD); - putreg32(regval, LPC11_SYSCON_PDRUNCFG); - - /* Inform the core to use PLL as clock */ - - putreg32(SYSCON_MAINCLKSEL_PLLOSC, LPC11_SYSCON_SYSPLLCLKUEN); - - /* Use PLL as main clock */ - - putreg32(SYSCON_MAINCLKSEL_SYSPLLCLKOUT, LPC11_SYSCON_MAINCLKSEL); - - /* Inform the core of clock update */ - - putreg32(SYSCON_MAINCLKUEN_ENA, LPC11_SYSCON_MAINCLKUEN); + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); + lpc17_40_configgpio(GPIO_LED3); + lpc17_40_configgpio(GPIO_LED4); } + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + switch ((unsigned)led) + { + case BOARD_LED1: + + /* LED1 and LED2 are inverted */ + + case BOARD_LED2: + lpc17_40_gpiowrite(g_ledcfg[led], !ledon); + break; + + case BOARD_LED3: + + /* LED3 and LED4 are driven normally */ + + case BOARD_LED4: + lpc17_40_gpiowrite(g_ledcfg[led], ledon); + break; + + default: + break; + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + lpc17_40_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + lpc17_40_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + lpc17_40_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/arch/arm/src/lpc11xx/lpc11_lowputc.h b/configs/lpc4088-quickstart/src/lpc4088-quickstart.h similarity index 50% rename from arch/arm/src/lpc11xx/lpc11_lowputc.h rename to configs/lpc4088-quickstart/src/lpc4088-quickstart.h index 9bf68ec1151..c9bf33bb3d4 100644 --- a/arch/arm/src/lpc11xx/lpc11_lowputc.h +++ b/configs/lpc4088-quickstart/src/lpc4088-quickstart.h @@ -1,7 +1,8 @@ /************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_lowputc.h + * configs/lpc4088-quickstart/src/lpc4088-quickstart.h + * arch/arm/src/board/lpc4088-quickstart.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,52 +34,110 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H +#ifndef _CONFIGS_LPC4088_QUICKSTART_SRC_LPC4088_QUICKSTART_H +#define _CONFIGS_LPC4088_QUICKSTART_SRC_LPC4088_QUICKSTART_H /************************************************************************************ * Included Files ************************************************************************************/ #include +#include /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/************************************************************************************ - * Public Types - ************************************************************************************/ +/* LPC4088 QuickStart GPIO Pin Definitions ****************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 : Connected to P1[18] + * LED2 : Connected to P0[13] + * LED3 : Connected to P1[13] + * LED4 : Connected to P2[19] + * + * These LEDs are driven through a PNP transistor so a low output value will + * illuminate them. + */ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT0 | GPIO_PIN13) + +/* + * These LEDs are connected to ground so a high output value will illuminate them. + */ +#define GPIO_LED3 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_LED4 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT2 | GPIO_PIN19) + +/* Button definitions ***************************************************************/ +/* The LPC4088 QuickStart supports a single button. It must be pulled up by the MCU. + * When closed, the pin will be pulled to ground. So the button will read "1" + * when open and "0" when closed. The button is capable of generating an + * interrupt. + * + * USER1 -- Connected to P2[10] + * For the interrupting buttons, interrupts are generated on both edges (press and + * release). + */ + +#define GPIO_USER1 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) + +/* IRQ numbers for the buttons that do support interrupts */ + +#define GPIO_USER2_IRQ LPC17_40_IRQ_P2p10 /************************************************************************************ - * Public Data + * Public data ************************************************************************************/ #ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: lpc11_lowsetup + * Name: lpc4088_quickstart_bringup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via boardctl() * ************************************************************************************/ -void lpc11_lowsetup(void); +int lpc4088_quickstart_bringup(void); -#ifdef __cplusplus -} +/************************************************************************************ + * Name: lpc4088_quickstart_sdram_initialize + * + * Description: + * Initialize SDRAM + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_EMC +#ifdef CONFIG_LPC17_40_EXTDRAM +void lpc4088_quickstart_sdram_initialize(void); #endif -#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC17_40_EMC */ -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H */ +/************************************************************************************ + * Name: lpc4088_quickstart_flash_initialize + * + * Description: + * Initialize SPIFI FLASH + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_SPIFI +void lpc4088_quickstart_flash_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_LPC4088_QUICKSTART_SRC_LPC4088_QUICKSTART_H */ diff --git a/configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg b/configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg new file mode 100644 index 00000000000..e2746104dfe --- /dev/null +++ b/configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg @@ -0,0 +1,166 @@ +### From /usr/local/share/openocd/scripts/interface/olimex-arm-usb-ocd.cfg +# +# Olimex ARM-USB-OCD +# +# http://www.olimex.com/dev/arm-usb-ocd.html +# + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG A" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +### From /usr/local/share/openocd/scripts/targets/lpc40xx.cfg +# NXP LPC4088 Cortex-M4 with 512kB Flash and 96kB Local On-Chip SRAM +# remember to place in the same folder as lpc17xx.cfg + +set CHIPNAME lpc4088 +set CPUTAPID 0x410fc241 +set CPURAMSIZE 0x18000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 12000 + +### From /usr/local/share/openocd/scripts/targets/lpc17xx.cfg +### With additions to set the operating frequency to 120MHz +# Common LPC17xx logic + +# LPC17xx chips support both JTAG and SWD transports. +# JTAG is hard-coded in this configuration +# Adapt based on what transport is active. +# source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "_CHIPNAME not set" +} + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + set _CCLK $CCLK +} else { + set _CCLK 4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + error "_CPUTAPID not set" +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { + error "_CPURAMSIZE not set" +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { + error "_CPUROMSIZE not set" +} + +#delays on reset lines +adapter_nsrst_delay 500 +jtag_ntrst_delay 500 + +# Use of JTAG is hard-coded +#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME + +# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE + +# The LPC17xx devices have 32/64/128/256/512kB of flash memory, managed by ROM code +# (including a boot loader which verifies the flash exception table's checksum). +# flash bank lpc2000 0 0 [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +adapter_khz 1000 + +$_TARGETNAME configure -event reset-init { + echo "Going to 120MHz" + + # PLL0CON: Disable PLL + mww 0x400FC080 0x00000000 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # CLKSEL: internal 12MHz RC oscillator Div 1. + mww 0x400FC104 0x00000001 + # CLKSRCSEL: Clock source = internal 12MHz RC oscillator + mww 0x400FC10C 0x00000000 + + # PLL0CFG: M=10,P=1 -> PLL=240 MHz + mww 0x400FC084 0x00000009 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # PLL0CON: Enable PLL + mww 0x400FC080 0x00000001 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + sleep 50 + + # PLL0CON: Connect PLL + # CCLKSEL=PLLED(240MHz)/2 (=120 MHz) + mww 0x400FC104 0x00000102 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # Dividing CPU clock by 8 should be pretty conservative + # + # + adapter_khz 1500 + + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + + mww 0x400FC040 0x01 +} + +# if srst is not fitted use VECTRESET to +# perform a soft reset - SYSRESETREQ is not supported +cortex_m3 reset_config vectreset diff --git a/configs/lpc4088-quickstart/tools/oocd.sh b/configs/lpc4088-quickstart/tools/oocd.sh new file mode 100755 index 00000000000..d5e9a0787d9 --- /dev/null +++ b/configs/lpc4088-quickstart/tools/oocd.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# +# See configs/lpc4088-quickstart/README.txt for information about +# this file. + +TOPDIR=$1 +USAGE="$0 [-d]" +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + exit 1 +fi + +# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment +# the following to run directly from the build directory + +# OPENOCD_PATH="/home/OpenOCD/openocd/src" +# OPENOCD_PATH="/usr/bin" +OPENOCD_PATH="/usr/local/bin" + +# TARGET_PATH="/home/OpenOCD/openocd/tcl" +# TARGET_PATH="/usr/share/openocd/scripts" +TARGET_PATH="/usr/local/share/openocd/scripts" + +# Assume a Unix development environment. Uncomment to use a Windows +# like environment + +OPENOCD_EXE=openocd.exe +# OPENOCD_EXE=openocd + +OPENOCD_CFG="${TOPDIR}/configs/lpc4088-quickstart/tools/lpc4088-quickstart.cfg" +OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}" + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +if [ ! -d ${OPENOCD_PATH} ]; then + echo "OpenOCD path does not exist: ${OPENOCD_PATH}" + exit 1 +fi +if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then + echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f ${OPENOCD_CFG} ]; then + echo "OpenOCD config file does not exist: ${OPENOCD_CFG}" + exit 1 +fi + +echo "Starting OpenOCD" +cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; } +${OPENOCD_EXE} ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/configs/lpc4330-xplorer/README.txt b/configs/lpc4330-xplorer/README.txt index 77a6ff50734..a1f3affafef 100644 --- a/configs/lpc4330-xplorer/README.txt +++ b/configs/lpc4330-xplorer/README.txt @@ -61,11 +61,11 @@ Status pin and GPIO configuration, and serial console support. A SPIFI MTD driver is also in place but requires further verification. - - The following drivers have been copied from the LPC17xx port, but + - The following drivers have been copied from the LPC17xx/LPC40xx port, but require integration into the LPC43xx. This integration should consist of: - - Remove LPC17xx power, clocking, and pin configuration logic. + - Remove LPC17xx/LPC40xx power, clocking, and pin configuration logic. - Adding of clock source and frequency to the board.h file. - Adding of LPC43 clock connection and pin configuration logic. @@ -78,7 +78,7 @@ Status - lpc43_spi.c, and - lpc43_ssp.c - These LPC17xx drivers were not brought into the LPC43xx port because + These LPC17xx/LPC40xx drivers were not brought into the LPC43xx port because it appears that these peripherals have been completely redesigned: - CAN, @@ -87,7 +87,7 @@ Status - USB host. The following LPC43xx peripherals are unsupported. Some may be - compatible with the LPC17xx, but there is no LPC17xx driver to be + compatible with the LPC17xx/LPC40xx, but there is no LPC17xx/LPC40xx driver to be ported: - SD/MMC, @@ -558,7 +558,7 @@ LPC4330-Xplorer Configuration Options CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY CONFIG_LPC43_AUTONEG - Enable auto-negotion - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb CONFIG_LPC43_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 CONFIG_LPC43_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs @@ -579,7 +579,7 @@ LPC4330-Xplorer Configuration Options CONFIG_LPC43_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. CONFIG_LPC43_USBDEV_DMA - Enable lpc17xx-specific DMA support + Enable lpc17xx/lpc40xx-specific DMA support CONFIG_LPC43_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal CONFIG_LPC43_USBDEV_NOLED diff --git a/configs/lpc4337-ws/README.txt b/configs/lpc4337-ws/README.txt index 654e6c9e68d..fce06d278bd 100644 --- a/configs/lpc4337-ws/README.txt +++ b/configs/lpc4337-ws/README.txt @@ -57,11 +57,11 @@ Status pin and GPIO configuration, and serial console support. A SPIFI MTD driver is also in place but requires further verification. - - The following drivers have been copied from the LPC17xx port, but + - The following drivers have been copied from the LPC17xx/LPC40xx port, but require integration into the LPC43xx. This integration should consist of: - - Remove LPC17xx power, clocking, and pin configuration logic. + - Remove LPC17xx/LPC40xx power, clocking, and pin configuration logic. - Adding of clock source and frequency to the board.h file. - Adding of LPC43 clock connection and pin configuration logic. @@ -74,7 +74,7 @@ Status - lpc43_spi.c, and - lpc43_ssp.c - These LPC17xx drivers were not brought into the LPC43xx port because + These LPC17xx/LPC40xx drivers were not brought into the LPC43xx port because it appears that these peripherals have been completely redesigned: - CAN, @@ -83,7 +83,7 @@ Status - USB host. The following LPC43xx peripherals are unsupported. Some may be - compatible with the LPC17xx, but there is no LPC17xx driver to be + compatible with the LPC17xx/LPC40xx, but there is no LPC17xx/LPC40xx driver to be ported: - SD/MMC, @@ -597,7 +597,7 @@ LPC4337-ws Configuration Options CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY CONFIG_LPC43__AUTONEG - Enable auto-negotion - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb CONFIG_LPC43_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 CONFIG_LPC43_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs @@ -618,7 +618,7 @@ LPC4337-ws Configuration Options CONFIG_LPC43_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. CONFIG_LPC43_USBDEV_DMA - Enable lpc17xx-specific DMA support + Enable lpc17xx/lpc40xx-specific DMA support CONFIG_LPC43_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal CONFIG_LPC43_USBDEV_NOLED diff --git a/configs/lpc4357-evb/README.txt b/configs/lpc4357-evb/README.txt index 0766f691e92..9cfe19d0034 100644 --- a/configs/lpc4357-evb/README.txt +++ b/configs/lpc4357-evb/README.txt @@ -54,11 +54,11 @@ Status pin and GPIO configuration, and serial console support. A SPIFI MTD driver is also in place but requires further verification. - - The following drivers have been copied from the LPC17xx port, but + - The following drivers have been copied from the LPC17xx/LPC40xx port, but require integration into the LPC43xx. This integration should consist of: - - Remove LPC17xx power, clocking, and pin configuration logic. + - Remove LPC17xx/LPC40xx power, clocking, and pin configuration logic. - Adding of clock source and frequency to the board.h file. - Adding of LPC43 clock connection and pin configuration logic. @@ -71,7 +71,7 @@ Status - lpc43_spi.c, and - lpc43_ssp.c - These LPC17xx drivers were not brought into the LPC43xx port because + These LPC17xx/LPC40xx drivers were not brought into the LPC43xx port because it appears that these peripherals have been completely redesigned: - CAN, @@ -80,7 +80,7 @@ Status - USB host. The following LPC43xx peripherals are unsupported. Some may be - compatible with the LPC17xx, but there is no LPC17xx driver to be + compatible with the LPC17xx/LPC40xx, but there is no LPC17xx/LPC40xx driver to be ported: - SD/MMC, @@ -594,7 +594,7 @@ LPC4357-EVB Configuration Options CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY CONFIG_LPC43_AUTONEG - Enable auto-negotion - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb CONFIG_LPC43_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 CONFIG_LPC43_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs @@ -615,7 +615,7 @@ LPC4357-EVB Configuration Options CONFIG_LPC43_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. CONFIG_LPC43_USBDEV_DMA - Enable lpc17xx-specific DMA support + Enable lpc17xx/lpc40xx-specific DMA support CONFIG_LPC43_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal CONFIG_LPC43_USBDEV_NOLED diff --git a/configs/lpc4370-link2/README.txt b/configs/lpc4370-link2/README.txt index 04e9521b5b0..321ad4294af 100644 --- a/configs/lpc4370-link2/README.txt +++ b/configs/lpc4370-link2/README.txt @@ -57,11 +57,11 @@ Status pin and GPIO configuration, and serial console support. A SPIFI MTD driver is also in place but requires further verification. - - The following drivers have been copied from the LPC17xx port, but + - The following drivers have been copied from the LPC17xx/LPC40xx port, but require integration into the LPC43xx. This integration should consist of: - - Remove LPC17xx power, clocking, and pin configuration logic. + - Remove LPC17xx/LPC40xx power, clocking, and pin configuration logic. - Adding of clock source and frequency to the board.h file. - Adding of LPC43 clock connection and pin configuration logic. @@ -74,7 +74,7 @@ Status - lpc43_spi.c, and - lpc43_ssp.c - These LPC17xx drivers were not brought into the LPC43xx port because + These LPC17xx/LPC40xx drivers were not brought into the LPC43xx port because it appears that these peripherals have been completely redesigned: - CAN, @@ -83,7 +83,7 @@ Status - USB host. The following LPC43xx peripherals are unsupported. Some may be - compatible with the LPC17xx, but there is no LPC17xx driver to be + compatible with the LPC17xx/LPC40xx, but there is no LPC17xx/LPC40xx driver to be ported: - SD/MMC, @@ -597,7 +597,7 @@ LPC4370-Link2 Configuration Options CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY CONFIG_LPC43_AUTONEG - Enable auto-negotion - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb CONFIG_LPC43_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 CONFIG_LPC43_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs @@ -618,7 +618,7 @@ LPC4370-Link2 Configuration Options CONFIG_LPC43_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. CONFIG_LPC43_USBDEV_DMA - Enable lpc17xx-specific DMA support + Enable lpc17xx/lpc40xx-specific DMA support CONFIG_LPC43_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal CONFIG_LPC43_USBDEV_NOLED diff --git a/configs/lpcxpresso-lpc1115/README.txt b/configs/lpcxpresso-lpc1115/README.txt deleted file mode 100644 index 5976255efb1..00000000000 --- a/configs/lpcxpresso-lpc1115/README.txt +++ /dev/null @@ -1,535 +0,0 @@ -README -^^^^^^ - -README for NuttX port to the Embedded Artists LPCXpresso LPC1115 board -featuring the NXP LPC1115 MCU. - -Contents -^^^^^^^^ - - LCPXpresso LPC1115 Board - Code Red IDE - Using OpenOCD - LEDs - LPCXpresso Configuration Options - Configurations - -LCPXpresso LPC1115 Board -^^^^^^^^^^^^^^^^^^^^^^^^ - - Pin Description Connector - -------------------------------- --------- - - P0[0]/RD1/TXD3/SDA1 J6-9 - P0[1]/TD1/RXD3/SCL J6-10 - P0[2]/TXD0/AD0[7] J6-21 - P0[3]/RXD0/AD0[6] J6-22 - P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 - P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 - P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 - P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 - P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 - P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 - P0[10] J6-40 - P0[11] J6-41 - - P1[0]/ENET-TXD0 J6-34? - P1[1]/ENET_TXD1 J6-35? - P1[4]/ENET_TX_EN - P1[8]/ENET_CRS - P1[9]/ENET_RXD0 - P1[10]/ENET_RXD1 - - P2[0]/PWM1.1/TXD1 - P2[1]/PWM1.2/RXD1 J6-43 - P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 - P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 - P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 - P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 - P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 - P2[7]/RD2/RTS1 J6-49 - P2[8]/TD2/TXD2 J6-50 - P2[9]/USB_CONNECT/RXD2 PAD19 - P2[10]/EINT0/NMI J6-51 - - P3[25]/MAT0.0/PWM1.2 PAD13 - P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 - -Code Red IDE -^^^^^^^^^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Linux Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc11xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lpc11x/lpc11_vectors.S. - - Using Code Red GNU Tools from Cygwin - ------------------------------------ - - Under Cygwin, the Code Red command line tools (e.g., arm-non-eabi-gcc) cannot - be executed because they only have execute privileges for Administrators. I - worked around this by: - - Opening a native Cygwin RXVT as Administrator (Right click, "Run as administrator"), - then executing 'chmod 755 *.exe' in the following directories: - - /cygdrive/c/nxp/lpcxpreeso_3.6/bin, and - /cygdrive/c/nxp/lpcxpreeso_3.6/Tools/bin - - Command Line Flash Programming - ------------------------------ - - During the port development was used a STLink-v2 SWD programmer with OpenOCD to - write the firmware in the flash and GDB to debug NuttX initialization. - - If using LPCLink as your debug connection, first of all boot the LPC-Link using - the script: - - bin\Scripts\bootLPCXpresso type - - where type = winusb for Windows XP, or type = hid for Windows Vista / 7. - - Now run the flash programming utility with the following options - - flash_utility wire -ptarget -flash-load[-exec]=filename [-load-base=base_address] - - Where flash_utility is one of: - - crt_emu_lpc11_13 (for LPC11xx or LPC13xx parts) - crt_emu_cm3_nxp (for LPC11xx parts) - crt_emu_a7_nxp (for LPC21/22/23/24 parts) - crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts) - crt_emu_cm3_lmi (for TI Stellaris parts) - - wire is one of: - - (empty) (for Red Probe+, Red Probe, RDB1768v1, or TI Stellaris evaluation boards) - -wire=hid (for RDB1768v2 without upgraded firmware) - -wire=winusb (for RDB1768v2 with upgraded firmware) - -wire=winusb (for LPC-Link on Windows XP) - -wire=hid (for LPC-Link on Windows Vista/ Windows 7) - - target is the target chip name. For example LPC1343, LPC1114/301, LPC1115 etc. - - filename is the file to flash program. It may be an executable (axf) or a binary - (bin) file. If using a binary file, the base_address must be specified. - - base_address is the base load address when flash programming a binary file. It - should be specified as a hex value with a leading 0x. - - Note: - - flash-load will leave the processor in a stopped state - - flash-load-exec will start execution of application as soon as download has - completed. - - Examples - To load the executable file app.axf and start it executing on an LPC1158 - target using Red Probe, use the following command line: - - crt_emu_cm3_nxp -pLPC1158 -flash-load-exec=app.axf - - To load the binary file binary.bin to address 0x1000 to an LPC1343 target - using LPC-Link on Windows XP, use the following command line: - - crt_emu_lpc11_13_nxp -wire=hid -pLPC1343 -flash-load=binary.bin -load-base=0x1000 - - tools/flash.sh - -------------- - - All of the above steps are automated in the bash script flash.sh that can - be found in the configs/lpcxpresso/tools directory. - -Using OpenOCD -^^^^^^^^^^^^^ - - https://acassis.wordpress.com/2015/03/29/using-openocd-to-program-the-lpc1115-lpcxpresso-board/ - - Using OpenOCD to program the LPC1115 LPCXpresso board - March 29, 2015 by acassis - - Unfortunately NXP uses a built-in programmer in the LPCXpresso board - called LPCLink that is not supported by OpenOCD and there is not (AFAIK) - an option to replace its firmware. - - Then I decided to cut the board to separate the “LPCXpresso LPC1115 REV A†- from the LPCLink programmer. - - So I used a simple and low cost STLink-v2 programmer board that is - supported by OpenOCD. In order to use OpenOCD to reprogram the LPC1115 - board we need to connect four wires from STLink-v2 to LPC1115 board: - - STLink-v2 | LPC1115 Board - ------------------------------ - GND GND - 3V3 3V3 - IO AD4 - CLK P0.10 - - - Also we need to instruct OpenOCD to use SWD protocol. You can do it - creating the following config openocd.cfg file: - - # LPC1115 LPCXpresso Target - - # Using stlink as SWD programmer - source [find interface/stlink-v2.cfg] - - # SWD as transport - transport select hla_swd - - # Use LPC1115 target - set WORKAREASIZE 0x4000 - source [find target/lpc11xx.cfg] - - Now execute OpenOCD using the created config file: - - $ sudo openocd -f openocd.cfg - Open On-Chip Debugger 0.9.0-dev-00251-g1fa4c72 (2015-01-28-20:08) - Licensed under GNU GPL v2 - For bug reports, read - http://openocd.sourceforge.net/doc/doxygen/bugs.html - Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD - adapter speed: 10 kHz - adapter_nsrst_delay: 200 - Info : Unable to match requested speed 10 kHz, using 5 kHz - Info : Unable to match requested speed 10 kHz, using 5 kHz - Info : clock speed 5 kHz - Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748 - Info : using stlink api v2 - Info : Target voltage: 3.137636 - Info : lpc11xx.cpu: hardware has 4 breakpoints, 2 watchpoints - - Connect to OpenOCD server: - - $ telnet 127.0.0.1 4444 - - Reset the CPU and flash the lpc1115_blink.bin file: - - > reset halt - target state: halted - target halted due to debug-request, current mode: Thread - xPSR: 0xc1000000 pc: 0x1fff0040 msp: 0x10000ffc - - > flash probe 0 - flash 'lpc2000' found at 0x00000000 - - > flash write_image erase blink_lpc1115.bin 0x00000000 - auto erase enabled - target state: halted - target halted due to breakpoint, current mode: Thread - xPSR: 0x01000000 pc: 0x10000108 msp: 0x100001b8 - Verification will fail since checksum in image (0x00000000) to be written to flash is different from calculated vector checksum (0xefffebe9). - To remove this warning modify build tools on developer PC to inject correct LPC vector checksum. - wrote 4096 bytes from file blink_lpc1115.bin in 0.592621s (6.750 KiB/s) - - > reset run - - The checksum warning message could be removed if you add the checksum to - binary, read this post: - - http://sigalrm.blogspot.com.br/2011/10/cortex-m3-exception-vector-checksum.html. - - The blink LED sample I got from Frank Duignan’s page: - - http://eleceng.dit.ie/frank/arm/BareMetalLPC1114/index.html - - Edit Makefile and configure LIBSPEC to point out to the right path: - - LIBSPEC=-L /usr/lib/gcc/arm-none-eabi/4.8/armv6-m - - $ make - - To generate the final binary I used objcopy: - - $ arm-none-eabi-objcopy -O binary main.elf blink_lpc1115.bin - - https://acassis.wordpress.com/2015/05/22/using-openocd-and-gdb-to-debug-my-nuttx-port-to-lpc11xx/ - - Using OpenOCD and gdb to debug my NuttX port to LPC11xx - May 22, 2015 by acassis - - I’m porting NuttX to LPC11xx (using the LPCXpresso LPC1115 board) and - these are the steps I used to get OpenOCD and GDB working to debug my firmware: - - The openocd.cfg to use with STLink-v2 SWD programmer: - - # LPC1115 LPCXpresso Target - - # Using stlink as SWD programmer - source [find interface/stlink-v2.cfg] - - # SWD as transport - transport select hla_swd - - # Use LPC1115 target - set WORKAREASIZE 0x4000 - source [find target/lpc11xx.cfg] - - You need to execute “reset halt†from OpenOCD telnet server to get - “monitor reset halt†working on gdb: - - $ telnet 127.0.0.1 4444Trying 127.0.0.1... - Connected to 127.0.0.1. - Escape character is '^]'. - Open On-Chip Debugger - - > reset halt - target state: halted - target halted due to debug-request, current mode: Thread - xPSR: 0xc1000000 pc: 0x1fff0040 msp: 0x10000ffc - - > exit - - Now execute the command arm-none-eabi-gdb (from Debian/Ubuntu package - “gdb-arm-none-eabiâ€) passing the nuttx ELF file: - - $ arm-none-eabi-gdb nuttx - GNU gdb (7.7.1+dfsg-1+6) 7.7.1 - Reading symbols from nuttx...done. - - (gdb) target remote localhost:3333 - Remote debugging using localhost:3333 - 0x1fff0040 in ?? () - - (gdb) monitor reset halt - target state: halted - target halted due to debug-request, current mode: Thread - xPSR: 0xc1000000 pc: 0x1fff0040 msp: 0x10000ffc - - (gdb) load - Loading section .vectors, size 0xc0 lma 0x0 - Loading section .text, size 0x9197 lma 0x410 - Loading section .ARM.exidx, size 0x8 lma 0x95a8 - Loading section .data, size 0x48 lma 0x95b0 - Start address 0x410, load size 37543 - Transfer rate: 9 KB/sec, 6257 bytes/write. - - (gdb) b __start - Breakpoint 1 at 0x410: file chip/lpc11_start.c, line 109. - - (gdb) step - - Note: automatically using hardware breakpoints for read-only addresses. - - Breakpoint 1, __start () at chip/lpc11_start.c:109 - 109 { - - (gdb) - 115 lpc11_clockconfig(); - - (gdb) - lpc11_clockconfig () at chip/lpc11_clockconfig.c:93 - 93 putreg32(SYSCON_SYSPLLCLKSEL_IRCOSC, LPC11_SYSCON_SYSPLLCLKSEL); - - (gdb) - 96 putreg32((SYSCON_SYSPLLCTRL_MSEL_DIV(4) | SYSCON_SYSPLLCTRL_PSEL_DIV2), LPC11_SYSCON_SYSPLLCTRL); - - (gdb) p /x *0x40048008 <--- this is the LPC11_SYSCON_SYSPLLCTRL register address - $2 = 0x23 - (gdb) - - You can use breakpoints, steps and many other GDB features. - - That is it! - -LEDs -^^^^ - - If CONFIG_ARCH_LEDS is defined, then support for the LPCXpresso LEDs will be - included in the build. See: - - - configs/lpcxpresso-lpc1115/include/board.h - Defines LED constants, types and - prototypes the LED interface functions. - - - configs/lpcxpresso-lpc1115/src/lpcxpresso-lpc1115.h - GPIO settings for the LEDs. - - - configs/lpcxpresso-lpc1115/src/up_leds.c - LED control logic. - - The LPCXpresso LPC1115 has a single LEDs. Usage this single LED by NuttX - is as follows: - - - The LED is not illuminated until the LPCXpresso completes initialization. - - If the LED is stuck in the OFF state, this means that the LPCXpresso did not - complete initializeation. - - - Each time the OS enters an interrupt (or a signal) it will turn the LED OFF and - restores its previous stated upon return from the interrupt (or signal). - - The normal state, after initialization will be a dull glow. The brightness of - the glow will be inversely related to the proportion of time spent within interrupt - handling logic. The glow may decrease in brightness when the system is very - busy handling device interrupts and increase in brightness as the system becomes - idle. - - Stuck in the OFF state suggests that that the system never completed - initialization; Stuck in the ON state would indicated that the system - intialialized, but is not takint interrupts. - - - If a fatal assertion or a fatal unhandled exception occurs, the LED will flash - strongly as a slow, 2Hz rate. - -LPCXpresso Configuration Options -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - General Architecture Settings: - - CONFIG_ARCH - Identifies the arch/ subdirectory. This should - be set to: - - CONFIG_ARCH=arm - - CONFIG_ARCH_family - For use in C code: - - CONFIG_ARCH_ARM=y - - CONFIG_ARCH_architecture - For use in C code: - - CONFIG_ARCH_CORTEXM0=y - - CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory - - CONFIG_ARCH_CHIP=lpc11xx - - CONFIG_ARCH_CHIP_name - For use in C code to identify the exact - chip: - - CONFIG_ARCH_CHIP_LPC1115=y - - CONFIG_ARCH_BOARD - Identifies the configs subdirectory and - hence, the board that supports the particular chip or SoC. - - CONFIG_ARCH_BOARD=lpcxpresso-lpc1115 - - CONFIG_ARCH_BOARD_name - For use in C code - - CONFIG_ARCH_BOARD_LPCEXPRESSO=y - - CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation - of delay loops - - CONFIG_ENDIAN_BIG - define if big endian (default is little - endian) - - CONFIG_RAM_SIZE - Describes the installed DRAM (CPU SRAM in this case): - - CONFIG_RAM_SIZE=(8*1024) (8Kb) - - There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1. - - CONFIG_RAM_START - The start address of installed DRAM - - CONFIG_RAM_START=0x10000000 - - CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that - have LEDs - - CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt - stack. If defined, this symbol is the size of the interrupt - stack in bytes. If not defined, the user task stacks will be - used during interrupt handling. - - CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions - - CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. - - Individual subsystems can be enabled: - CONFIG_LPC11_MAINOSC=y - CONFIG_LPC11_PLL0=y - CONFIG_LPC11_UART0=y - CONFIG_LPC11_CAN1=n - CONFIG_LPC11_SPI=n - CONFIG_LPC11_SSP0=n - CONFIG_LPC11_SSP1=n - CONFIG_LPC11_I2C0=n - CONFIG_LPC11_I2S=n - CONFIG_LPC11_TMR0=n - CONFIG_LPC11_TMR1=n - CONFIG_LPC11_PWM0=n - CONFIG_LPC11_ADC=n - CONFIG_LPC11_FLASH=n - - LPC11xx specific device driver settings - - CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the - console and ttys0 (default is the UART0). - CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. - This specific the size of the receive buffer - CONFIG_UARTn_TXBUFSIZE - Characters are buffered before - being sent. This specific the size of the transmit buffer - CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be - CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. - CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity - CONFIG_UARTn_2STOP - Two stop bits - - LPC11xx specific CAN device driver settings. These settings all - require CONFIG_CAN: - - CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default - Standard 11-bit IDs. - CONFIG_LPC11_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC11_CAN1 - is defined. - CONFIG_LPC11_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this - number. (the CCLK frequency is divided by this number to get the CAN - clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC11_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - -Configurations -^^^^^^^^^^^^^^ - -Each LPCXpresso configuration is maintained in a sub-directory and can be -selected as follow: - - tools/configure.sh lpcxpresso-lpc1115/ - -Where is one of the following: - - nsh: - --- - - Configures the NuttShell (nsh) located at apps/examples/nsh. The - Configuration enables both the serial and telnet NSH interfaces. - - NOTES: - - 1. This configuration uses the mconf-based configuration tool. To - change this configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. This configuration has been used for testing the microSD card. - This support is, however, disabled in the base configuration. - - At last attempt, the SPI-based mircroSD does not work at - higher fequencies. Setting the SPI frequency to 400000 - removes the problem. There must be some more optimal - value that could be determined with additional experimetnation. - - Jumpers: J55 must be set to provide chip select PIO1_11 signal as - the SD slot chip select. diff --git a/configs/lpcxpresso-lpc1115/include/board.h b/configs/lpcxpresso-lpc1115/include/board.h deleted file mode 100644 index 338a405632e..00000000000 --- a/configs/lpcxpresso-lpc1115/include/board.h +++ /dev/null @@ -1,206 +0,0 @@ -/************************************************************************************ - * configs/lpcxpresso-lpc1115/include/board.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __CONFIG_LPCXPRESSO_LPC1115_INCLUDE_BOARD_H -#define __CONFIG_LPCXPRESSO_LPC1115_INCLUDE_BOARD_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc11_syscon.h. It is not included here - * because the including C file may not have that file in its include path. - */ - -#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ -#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ -#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ -#define BOARD_INTRCOSC_FREQUENCY (1200000) /* Internal RC oscillator frequency */ - -/* This is the clock setup we configure for: - * - * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 - * MCLK = 480MHz / 6 = 80MHz -> MCLK divider = 6 - */ - -#define LPC11_MCLK 48000000 /* 48Mhz */ - -/* Select the internal RC oscillator as the frequency source. SYSCLK is then the frequency - * of the main oscillator. - */ - -#undef CONFIG_LPC11_INTRCOSC -#define CONFIG_LPC11_INTRCOSC 1 -#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN - -/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. - * The input to the divider (PLLCLK) will be determined by the PLL output. - */ - -#define BOARD_CCLKCFG_DIVIDER 6 -#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) - -/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). - * - * Source clock: Main oscillator - * PLL0 Multiplier value (M): 20 - * PLL0 Pre-divider value (N): 1 - * - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz - */ - -#undef CONFIG_LPC11_PLL0 -#define CONFIG_LPC11_PLL0 1 -#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN - -#define BOARD_PLL0CFG_MSEL 20 -#define BOARD_PLL0CFG_NSEL 1 -#define BOARD_PLL0CFG_VALUE \ - (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ - ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) - -/* PLL1 -- Not used. */ - -#undef CONFIG_LPC11_PLL1 -#define BOARD_PLL1CFG_MSEL 36 -#define BOARD_PLL1CFG_NSEL 1 -#define BOARD_PLL1CFG_VALUE \ - (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ - ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) - -/* USB divider. This divider is used when PLL1 is not enabled to get the - * USB clock from PLL0: - * - * USBCLK = PLL0CLK / 10 = 48MHz - */ - -#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10 - -/* FLASH Configuration */ - -#undef CONFIG_LPC11_FLASH -#define CONFIG_LPC11_FLASH 1 -#define BOARD_FLASHCFG_VALUE 0x0000303a - -/* LED definitions ******************************************************************/ -/* The LPCXpresso LPC1115 board has a single red LED (there are additional LEDs on - * the base board not considered here). - */ - /* ON OFF */ -#define LED_STARTED 0 /* OFF ON (never happens) */ -#define LED_HEAPALLOCATE 0 /* OFF ON (never happens) */ -#define LED_IRQSENABLED 0 /* OFF ON (never happens) */ -#define LED_STACKCREATED 1 /* ON ON (never happens) */ -#define LED_INIRQ 2 /* OFF NC (momentary) */ -#define LED_SIGNAL 2 /* OFF NC (momentary) */ -#define LED_ASSERTION 2 /* OFF NC (momentary) */ -#define LED_PANIC 0 /* OFF ON (1Hz flashing) */ - -/* Alternate pin selections *********************************************************/ -/* Pin Description Connector On Board Base Board - * -------------------------------- --------- -------------- --------------------- - * P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1 - * P0[1]/TD1/RXD3/SCL J6-10 RXD3/SCL1 - * P0[2]/TXD0/AD0[7] J6-21 - * P0[3]/RXD0/AD0[6] J6-22 - * P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2 - * P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2 - * P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1, OLED CS - * P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1, OLED SCK - * P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1 - * P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1, OLED data in - * P0[10] J6-40 TXD2/SDA2 - * P0[11] J6-41 RXD2/SCL2 - */ - -#define GPIO_UART3_TXD GPIO_UART3_TXD_1 -#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 -#define GPIO_UART3_RXD GPIO_UART3_RXD_1 -#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 -#define GPIO_SSP1_SCK GPIO_SSP1_SCK_1 -#define GPIO_UART2_TXD GPIO_UART2_TXD_1 -#define GPIO_UART2_RXD GPIO_UART2_RXD_1 -#define GPIO_UART1_TXD GPIO_UART1_TXD_1 -#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 -#define GPIO_UART1_RXD GPIO_UART1_RXD_1 -#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1 -#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1 -#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1 - -/* P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY) - * P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY) - * P1[4]/ENET_TX_EN TXEN N/A - * P1[8]/ENET_CRS CRS_DV/MODE2 N/A - * P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY) - * P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY) - */ - -#define GPIO_ENET_MDC GPIO_ENET_MDC_1 -#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1 - -/* P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 / RGB LED / RS422 RX - * P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 / OLED voltage / RGB LED / RS422 RX - * P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3 - * P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4 - * P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5 - * P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6 - * P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 - * P2[7]/RD2/RTS1 J6-49 OLED command/data - * P2[8]/TD2/TXD2 J6-50 - * P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A - * P2[10]/EINT0/NMI J6-51 - * P2[11]/EINT1/I2STX_CLK J6-52 - */ - -#define GPIO_PWM1p1 GPIO_PWM1p1_2 -#define GPIO_PWM1p2 GPIO_PWM1p2_2 -#define GPIO_PWM1p3 GPIO_PWM1p3_2 -#define GPIO_PWM1p4 GPIO_PWM1p4_2 -#define GPIO_PWM1p5 GPIO_PWM1p5_2 -#define GPIO_PWM1p6 GPIO_PWM1p6_2 - -/* P3[25]/MAT0.0/PWM1.2 PAD13 N/A - * P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A - */ - -#endif /* __CONFIG_LPCXPRESSO_LPC1115_INCLUDE_BOARD_H */ diff --git a/configs/lpcxpresso-lpc1115/scripts/lpcxpresso-lpc1115.ld b/configs/lpcxpresso-lpc1115/scripts/lpcxpresso-lpc1115.ld deleted file mode 100644 index d317b218feb..00000000000 --- a/configs/lpcxpresso-lpc1115/scripts/lpcxpresso-lpc1115.ld +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * configs/lpcxpresso-lpc1115/scripts/lpcxpresso-lpc1115.ld - * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* The LPC1115 has 64Kb of FLASH beginning at address 0x00000000 and - * 8Kb of SRAM at address 0x10000000. - */ - -MEMORY -{ - vectflash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00c0 - progflash (rx) : ORIGIN = 0x00000410, LENGTH = 64k - datasram (rwx) : ORIGIN = 0x10000000, LENGTH = 8K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -EXTERN(_cfmconfig) -ENTRY(_stext) -SECTIONS -{ - .vectors : { - _svectors = ABSOLUTE(.); - *(.vectors) - _evectors = ABSOLUTE(.); - } > vectflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > progflash - - .init_section : { - _sinit = ABSOLUTE(.); - *(.init_array .init_array.*) - _einit = ABSOLUTE(.); - } > progflash - - .ARM.extab : { - *(.ARM.extab*) - } > progflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > progflash - __exidx_end = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > datasram AT > progflash - - _eronly = LOADADDR(.data); - - .ramfunc ALIGN(4): { - _sramfuncs = ABSOLUTE(.); - *(.ramfunc .ramfunc.*) - _eramfuncs = ABSOLUTE(.); - } > datasram AT > progflash - - _framfuncs = LOADADDR(.ramfunc); - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > datasram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_adc.c b/configs/lpcxpresso-lpc1115/src/lpc11_adc.c deleted file mode 100644 index 75936ee338f..00000000000 --- a/configs/lpcxpresso-lpc1115/src/lpc11_adc.c +++ /dev/null @@ -1,122 +0,0 @@ -/************************************************************************************ - * configs/lpcexpresso-lpc1115/src/lpc11_adc.c - * - * Copyright (C) 2013 Zilogic Systems. All rights reserved. - * Author: Kannan - * - * Based on configs/stm3220g-eval/src/up_adc.c - * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "up_arch.h" - -#include "lpc11_adc.h" -#include "lpcxpresso_lpc1115.h" - -#ifdef CONFIG_ADC - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: adc_devinit - * - * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ - -int adc_devinit(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Call lpc11_adcinitialize() to get an instance of the ADC interface */ - - adc = lpc11_adcinitialize(); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC */ diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_appinit.c b/configs/lpcxpresso-lpc1115/src/lpc11_appinit.c deleted file mode 100644 index b4e7be5c1d8..00000000000 --- a/configs/lpcxpresso-lpc1115/src/lpc11_appinit.c +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * config/lpcxpresso-lpc1115/src/lpc11_appinit.c - * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PORT and SLOT number probably depend on the board configuration */ - -#define NSH_HAVEUSBDEV 1 -#ifdef CONFIG_LPC17_SSP1 -# define NSH_HAVEMMCSD 1 -#else -# undef NSH_HAVEMMCSD -#endif - -/* Do we have SPI support for MMC/SD? */ - -#ifdef NSH_HAVEMMCSD -#ifdef CONFIG_NSH_ARCHINIT -# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1 -# error "The LPCXpresso MMC/SD is on SSP1" -# undef CONFIG_NSH_MMCSDSPIPORTNO -# define CONFIG_NSH_MMCSDSPIPORTNO 1 -# endif -# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0 -# error "The LPCXpresso MMC/SD has only one slot (0)" -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#else -# undef CONFIG_NSH_MMCSDSPIPORTNO -# define CONFIG_NSH_MMCSDSPIPORTNO 1 -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -#endif -#endif - -/* Can't support USB device features if USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef NSH_HAVEUSBDEV -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef NSH_HAVEMMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform architecture specific initialization - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the - * matching application logic. The value cold be such things as a - * mode enumeration value, a set of DIP switch switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef NSH_HAVEMMCSD - FAR struct spi_dev_s *ssp; - int ret; - - /* Get the SSP port */ - - ssp = lpc11_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); - if (!ssp) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", - CONFIG_NSH_MMCSDSPIPORTNO); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SSP port %d\n", - CONFIG_NSH_MMCSDSPIPORTNO); - - /* Bind the SSP port to the slot */ - - ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, CONFIG_NSH_MMCSDSLOTNO, ssp); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to bind SSP port %d to MMC/SD slot %d: %d\n", - CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO, ret); - return ret; - } - - syslog(LOG_INFO, "Successfuly bound SSP port %d to MMC/SD slot %d\n", - CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO); -#endif - return OK; -} diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_boot.c b/configs/lpcxpresso-lpc1115/src/lpc11_boot.c deleted file mode 100644 index 21bec4c9504..00000000000 --- a/configs/lpcxpresso-lpc1115/src/lpc11_boot.c +++ /dev/null @@ -1,93 +0,0 @@ -/************************************************************************************ - * configs/lpcxpresso-lpc1115/src/lpc11_boot.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "lpc11_ssp.h" -#include "lpcxpresso_lpc1115.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc11_boardinitialize - * - * Description: - * All LPC11xx architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc11_boardinitialize(void) -{ - /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak - * function lpcxpresso_sspdev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) - if (lpcxpresso_sspdev_initialize) - { - lpcxpresso_sspdev_initialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_leds.c b/configs/lpcxpresso-lpc1115/src/lpc11_leds.c deleted file mode 100644 index 2c032cd0873..00000000000 --- a/configs/lpcxpresso-lpc1115/src/lpc11_leds.c +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * configs/lpcxpresso-lpc1115/src/lpc11_leds.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "lpc11_gpio.h" -#include "lpcxpresso_lpc1115.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static bool g_ncstate; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure all LED GPIO lines */ - - lpc11_configgpio(LPCXPRESSO_LED); - g_ncstate = true; -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - bool off; - - switch (led) - { - case 0: - case 2: - off = true; - break; - - case 1: - off = false; - g_ncstate = false; - break; - - default: - return; - } - - lpc11_gpiowrite(LPCXPRESSO_LED, off); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - bool off; - - switch (led) - { - case 0: - case 1: - off = false; - break; - - case 2: - off = g_ncstate; - break; - - default: - return; - } - - lpc11_gpiowrite(LPCXPRESSO_LED, off); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/lpcxpresso-lpc1115/src/lpc11_pwm.c b/configs/lpcxpresso-lpc1115/src/lpc11_pwm.c deleted file mode 100644 index 9ecbfcf85e8..00000000000 --- a/configs/lpcxpresso-lpc1115/src/lpc11_pwm.c +++ /dev/null @@ -1,152 +0,0 @@ -/************************************************************************************ - * configs/lpcexpresso-lpc1115/lpc11_pwm.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "up_arch.h" -#include "lpc11_pwm.h" -#include "lpc11_timer.h" -#include "lpcxpresso_lpc1115.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#ifdef CONFIG_PWM - -FAR struct pwm_lowerhalf_s *lpc11_pwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc11_mcpwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer); - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: pwm_devinit - * - * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/pwm. - * - ************************************************************************************/ - -int pwm_devinit(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - struct pwm_lowerhalf_s *mcpwm; - struct pwm_lowerhalf_s *timer; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call lpc11_pwminitialize() to get an instance of the PWM interface */ - - pwm = lpc11_pwminitialize(0); - if (!pwm) - { - aerr("ERROR: Failed to get the LPC17XX PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - mcpwm = lpc11_mcpwminitialize(0); - if (!mcpwm) - { - aerr("ERROR: Failed to get the LPC17XX MOTOR PWM lower half\n"); - return -ENODEV; - } - - /* Register the MOTOR CONTROL PWM driver at "/dev/mcpwm0" */ - - ret = pwm_register("/dev/mcpwm0", mcpwm); - if (ret < 0) - { - aerr("ERROR: mcpwm_register failed: %d\n", ret); - return ret; - } - - timer = lpc11_timerinitialize(0); - if (!timer) - { - aerr("ERROR: Failed to get the LPC17XX TIMER lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/timer0" */ - - ret = pwm_register("/dev/timer0", timer); - if (ret < 0) - { - aerr("ERROR: timer_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/configs/lpcxpresso-lpc1115/src/lpcxpresso_lpc1115.h b/configs/lpcxpresso-lpc1115/src/lpcxpresso_lpc1115.h deleted file mode 100644 index 4f523e26b29..00000000000 --- a/configs/lpcxpresso-lpc1115/src/lpcxpresso_lpc1115.h +++ /dev/null @@ -1,234 +0,0 @@ -/************************************************************************************ - * configs/lpcxpresso-lpc1115/src/lpcxpresso_lpc1115.h - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef _CONFIGS_LPCXPRESSO_LPC1115_SRC_LPCXPRESSO_LPC1115L_H -#define _CONFIGS_LPCXPRESSO_LPC1115_SRC_LPCXPRESSO_LPC1115L_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* LPCXpresso LPC1115 board pin usage ***********************************************/ -/* Pin Description Connector On Board Base Board - * -------------------------------- --------- -------------- --------------------- - * P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1 - * P0[1]/TD1/RXD3/SCL J6-10 RXD2/SCL1 - * P0[2]/TXD0/AD0[7] J6-21 - * P0[3]/RXD0/AD0[6] J6-22 - * P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2 - * P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2 - * P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1 - * P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1 - * P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1 - * P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1 - * P0[10] J6-40 TXD2/SDA2 - * P0[11] J6-41 RXD2/SCL2 - * P0[15]/TXD1/SCK0/SCK J6-13 TXD1/SCK0 - * P0[16]/RXD1/SSEL0/SSEL J6-14 RXD1/SSEL0 - * P0[17]/CTS1/MISO0/MISO J6-12 MISO0 - * P0[18]/DCD1/MOSI0/MOSI J6-11 MOSI0 - * P0[19]/DSR1/SDA1 PAD17 N/A - * P0[20]/DTR1/SCL1 PAD18 I2C E2PROM SCL N/A - * P0[21]/RI1/MCIPWR/RD1 J6-23 - * P0[22]/RTS1/TD1 J6-24 LED - * P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] J6-15 AD0.0 - * P0[24]/AD0[1]/I2SRX_WS/CAP3[1] J6-16 AD0.1 - * P0[25]/AD0[2]/I2SRX_SDA/TXD3 J6-17 AD0.2 - * P0[26]/AD0[3]/AOUT/RXD3 J6-18 AD0.3/AOUT - * P0[27]/SDA0/USB_SDA J6-25 - * P0[28]/SCL0 J6-26 - * P0[29]/USB_D+ J6-37 USB_D+ - * P0[30]/USB_D- J6-36 USB_D- - */ - -#define LPCXPRESSO_I2C1_EPROM_SDA GPIO_I2C1_SDA_1 -#define LPCXPRESSO_I2C1_EPROM_SDL GPIO_I2C1_SCL_2 -#define LPCXPRESSO_LED (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT0 | GPIO_PIN7) - -/* P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY) - * P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY) - * P1[4]/ENET_TX_EN TXEN N/A - * P1[8]/ENET_CRS CRS_DV/MODE2 N/A - * P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY) - * P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY) - * P1[14]/ENET_RX_ER RXER/PHYAD0 N/A - * P1[15]/ENET_REF_CLK REFCLK N/A - * P1[16]/ENET_MDC MDC N/A - * P1[17]/ENET_MDIO MDIO N/A - * P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] PAD1 N/A - * P1[19]/MC0A/USB_PPWR/N_CAP1.1 PAD2 N/A - * P1[20]/MCFB0/PWM1.2/SCK0 PAD3 N/A - * P1[21]/MCABORT/PWM1.3/SSEL0 PAD4 N/A - * P1[22]/MC0B/USB-PWRD/MAT1.0 PAD5 N/A - * P1[23]/MCFB1/PWM1.4/MISO0 PAD6 N/A - * P1[24]/MCFB2/PWM1.5/MOSI0 PAD7 N/A - * P1[25]/MC1A/MAT1.1 PAD8 N/A - * P1[26]/MC1B/PWM1.6/CAP0.0 PAD9 N/A - * P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 PAD10 N/A - * P1[28]/MC2A/PCAP1.0/MAT0.0 PAD11 N/A - * P1[29]/MC2B/PCAP1.1/MAT0.1 PAD12 N/A - * P1[30]/VBUS/AD0[4] J6-19 AD0.4 - * P1[31]/SCK1/AD0[5] J6-20 AD0.5 - * - * P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 - * P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 - * P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3 - * P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4 - * P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5 - * P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6 - * P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 - * P2[7]/RD2/RTS1 J6-49 - * P2[8]/TD2/TXD2 J6-50 - * P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A - * P2[10]/EINT0/NMI J6-51 - * P2[11]/EINT1/I2STX_CLK J6-52 - * P2[12]/EINT2/I2STX_WS J6-53 - * P2[13]/EINT3/I2STX_SDA J6-27 - */ - -#define LPCXPRESSO_USB_PULLUP (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN9) - -/* P3[25]/MAT0.0/PWM1.2 PAD13 N/A - * P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A - * - * P4[28]/RX-MCLK/MAT2.0/TXD3 PAD15 N/A - * P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A - */ - -/* SD Slot - * - * Base-board J4/J6 LPC1115 - * SD Signal Pin Pin - * --- ----------- ----- -------- - * CS PIO1_11* 55 P2.2 (See LPCXPRESSO_SD_CS) - * DIN PIO0_9-MOSI 5 P0.9 MOSI1 (See GPIO_SSP1_MOSI in chip/lpc11_ssp.h) - * DOUT PIO0_8-MISO 6 P0.8 MISO1 (See GPIO_SSP1_MISO in chip/lpc11_ssp.h) - * CLK PIO2_11-SCK 7 P0.9 SCK1 (See GPIO_SSP1_SCK in board.h) - * CD PIO2_10 52 P2.11 (See LPCXPRESSO_SD_CD) - */ - -#define LPCXPRESSO_SD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT2 | GPIO_PIN2) -#ifdef CONFIG_LPC11_GPIOIRQ -# define LPCXPRESSO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) -#else -# define LPCXPRESSO_SD_CD (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) -#endif - -/* USB: - * - * Base-board J4/J6 LPC1115 - * Signal Pin Pin - * ------------------- ----- -------- - * USB_DM 36 P0.30/USB-D- - * USB_DP 37 P0.29/USB-D+ - * N/C N/C P1.18/USB-UP-LED/PWM1.1/CAP1.0 - * PIO1_3 (not used) 19 P1.30/VBUS/AD0.4 - * N/C N/C P2.9/USB-CONNECT/RXD2 (See Notes) - * ------------------- ----- -------- - * PIO0_6-USB_CONNECT* 23 P0.21/RI1/RD1 - * PIO0_3-VBUS_SENSE 39 P0.5/I2SRX-WS/TD2/CAP2.1 - * - * Notes: - * - The standard USB CONNECT (P0.9) provides USB D+ pullup on board the - * LPCXpresso card; it should be un-necessary to use the based board - * version of the pullup. - * - No changes to jumper settings are required. There are few USB- - * related jumpers on the based board, but none are required: - * - J14 must be set to permit GPIO control of the base board USB - * connect pin. NOT USED - * - J12 must be set to permit GPIO control of the USB vbus sense pin - * - The standard VBUS (P1.30) is not connected. As a consequence, the - * USB driver will not correctly respond to USB insertion or removal - * events. - * - The standard USB LED (P1.18) is not connected. - */ - -#define LPCXPRESSO_USB_CONNECT (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN21) -#ifdef CONFIG_LPC11_GPIOIRQ -# define LPCXPRESSO_USB_VBUSSENSE (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#else -# define LPCXPRESSO_USB_VBUSSENSE (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#endif - -/* 96x64 White OLED with I2C/SPI interface - * - * ----------------------------+-------+-------------- ----------------------------- - * LPC1758 Pin | J4/6 | Base Board Description - * ----------------------------+-------+-------------- ----------------------------- - * P2.1/PWM1.2/RXD1 | 43 | PIO1_10 FAN5331 Power Control (SHDN#) - * P0.6/I2SRX-SDA/SSEL1/MAT2.0 | 8 | PIO0_2 OLED chip select (CS#) - * P2.7/RD2/RTS1 | 49 | PIO2_7 OLED command/data (D/C#) - * P0.7/I2STX-CLK/SCK1/MAT2.1 | 7 | PIO2_11-SCK OLED clock (D0) - * P0.9/I2STX-SDA/MOSI1/MAT2.3 | 5 | PIO0_9-MOSI OLED data in (D1) - * ----------------------------+-------+-------------- ----------------------------- - */ - -#define LPCXPRESSO_OLED_POWER (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN1) -#define LPCXPRESSO_OLED_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN6) -#define LPCXPRESSO_OLED_DC (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN7) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpcxpresso_sspdev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LPCXpresso board. - * - ************************************************************************************/ - -void weak_function lpcxpresso_sspdev_initialize(void); - -#endif /* __ASSEMBLY__ */ -#endif /* _CONFIGS_LPCXPRESSO_LPC1115_SRC_LPCXPRESSO_LPC1115L_H */ diff --git a/configs/lpcxpresso-lpc1768/README.txt b/configs/lpcxpresso-lpc1768/README.txt index 61af7185db2..6dc54cf5d38 100644 --- a/configs/lpcxpresso-lpc1768/README.txt +++ b/configs/lpcxpresso-lpc1768/README.txt @@ -244,13 +244,13 @@ Code Red IDE 2) Start the NuttX build at least one time from the Cygwin command line before trying to create your project. This is necessary to create certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx, + 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx_40xx, arch/arm/src/common, arch/arm/src/armv7-m, and sched/. 4) All assembly files need to have the definition option -D __ASSEMBLY__ on the command line. Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lpc17x/lpc17_vectors.S. + is arch/arm/src/lpc17x/lpc17_40_vectors.S. Using Code Red GNU Tools from Cygwin ------------------------------------ @@ -282,7 +282,7 @@ Code Red IDE Where flash_utility is one of: crt_emu_lpc11_13 (for LPC11xx or LPC13xx parts) - crt_emu_cm3_nxp (for LPC17xx parts) + crt_emu_cm3_nxp (for LPC17xx/LPC40xx parts) crt_emu_a7_nxp (for LPC21/22/23/24 parts) crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts) crt_emu_cm3_lmi (for TI Stellaris parts) @@ -428,41 +428,41 @@ LPCXpresso Configuration Options CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. Individual subsystems can be enabled: - CONFIG_LPC17_MAINOSC=y - CONFIG_LPC17_PLL0=y - CONFIG_LPC17_PLL1=n - CONFIG_LPC17_ETHERNET=n - CONFIG_LPC17_USBHOST=n - CONFIG_LPC17_USBOTG=n - CONFIG_LPC17_USBDEV=n - CONFIG_LPC17_UART0=y - CONFIG_LPC17_UART1=n - CONFIG_LPC17_UART2=n - CONFIG_LPC17_UART3=n - CONFIG_LPC17_CAN1=n - CONFIG_LPC17_CAN2=n - CONFIG_LPC17_SPI=n - CONFIG_LPC17_SSP0=n - CONFIG_LPC17_SSP1=n - CONFIG_LPC17_I2C0=n - CONFIG_LPC17_I2C1=n - CONFIG_LPC17_I2S=n - CONFIG_LPC17_TMR0=n - CONFIG_LPC17_TMR1=n - CONFIG_LPC17_TMR2=n - CONFIG_LPC17_TMR3=n - CONFIG_LPC17_RIT=n - CONFIG_LPC17_PWM0=n - CONFIG_LPC17_MCPWM=n - CONFIG_LPC17_QEI=n - CONFIG_LPC17_RTC=n - CONFIG_LPC17_WDT=n - CONFIG_LPC17_ADC=n - CONFIG_LPC17_DAC=n - CONFIG_LPC17_GPDMA=n - CONFIG_LPC17_FLASH=n + CONFIG_LPC17_40_MAINOSC=y + CONFIG_LPC17_40_PLL0=y + CONFIG_LPC17_40_PLL1=n + CONFIG_LPC17_40_ETHERNET=n + CONFIG_LPC17_40_USBHOST=n + CONFIG_LPC17_40_USBOTG=n + CONFIG_LPC17_40_USBDEV=n + CONFIG_LPC17_40_UART0=y + CONFIG_LPC17_40_UART1=n + CONFIG_LPC17_40_UART2=n + CONFIG_LPC17_40_UART3=n + CONFIG_LPC17_40_CAN1=n + CONFIG_LPC17_40_CAN2=n + CONFIG_LPC17_40_SPI=n + CONFIG_LPC17_40_SSP0=n + CONFIG_LPC17_40_SSP1=n + CONFIG_LPC17_40_I2C0=n + CONFIG_LPC17_40_I2C1=n + CONFIG_LPC17_40_I2S=n + CONFIG_LPC17_40_TMR0=n + CONFIG_LPC17_40_TMR1=n + CONFIG_LPC17_40_TMR2=n + CONFIG_LPC17_40_TMR3=n + CONFIG_LPC17_40_RIT=n + CONFIG_LPC17_40_PWM0=n + CONFIG_LPC17_40_MCPWM=n + CONFIG_LPC17_40_QEI=n + CONFIG_LPC17_40_RTC=n + CONFIG_LPC17_40_WDT=n + CONFIG_LPC17_40_ADC=n + CONFIG_LPC17_40_DAC=n + CONFIG_LPC17_40_GPDMA=n + CONFIG_LPC17_40_FLASH=n - LPC17xx specific device driver settings + LPC17xx/LPC40xx specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -475,78 +475,78 @@ LPCXpresso Configuration Options CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_UARTn_2STOP - Two stop bits - LPC17xx specific CAN device driver settings. These settings all + LPC17xx/LPC40xx specific CAN device driver settings. These settings all require CONFIG_CAN: CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. - CONFIG_LPC17_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 + CONFIG_LPC17_40_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN1 is defined. - CONFIG_LPC17_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 + CONFIG_LPC17_40_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN2 is defined. - CONFIG_LPC17_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN_TSEG1 - The number of CAN time quanta in segment 1. + CONFIG_LPC17_40_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2. + CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 - LPC17xx specific PHY/Ethernet device driver settings. These setting - also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + LPC17xx/LPC40xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_40_ETHERNET. CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY - CONFIG_LPC17_PHY_AUTONEG - Enable auto-negotion - CONFIG_LPC17_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. - CONFIG_LPC17_PHY_FDUPLEX - Select full (vs. half) duplex + CONFIG_LPC17_40_PHY_AUTONEG - Enable auto-negotion + CONFIG_LPC17_40_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_LPC17_40_PHY_FDUPLEX - Select full (vs. half) duplex - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb - CONFIG_LPC17_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 - CONFIG_LPC17_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 - CONFIG_LPC17_ETH_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_WOL - Enable Wake-up on Lan (not fully implemented). CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. Also needs CONFIG_DEBUG_FEATURES. - CONFIG_LPC17_ETH_HASH - Enable receipt of near-perfect match frames. - CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + CONFIG_LPC17_40_ETH_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_40_MULTICAST - Enable receipt of multicast (and unicast) frames. Automatically set if CONFIG_NET_MCASTGROUP is selected. - LPC17xx USB Device Configuration + LPC17xx/LPC40xx USB Device Configuration - CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT Handle USB Start-Of-Frame events. Enable reading SOF from interrupt handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. - CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT Enable high priority interrupts. I have no idea why you might want to do that - CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. - CONFIG_LPC17_USBDEV_DMA - Enable lpc17xx-specific DMA support - CONFIG_LPC17_USBDEV_NOVBUS + CONFIG_LPC17_40_USBDEV_DMA + Enable lpc17xx/lpc40xx-specific DMA support + CONFIG_LPC17_40_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal - CONFIG_LPC17_USBDEV_NOLED + CONFIG_LPC17_40_USBDEV_NOLED Define if the hardware implementation does not support the LED output - LPC17xx USB Host Configuration (the LPCXpresso does not support USB Host) + LPC17xx/LPC40xx USB Host Configuration (the LPCXpresso does not support USB Host) - CONFIG_LPC17_OHCIRAM_SIZE + CONFIG_LPC17_40_OHCIRAM_SIZE Total size of OHCI RAM (in AHB SRAM Bank 1) CONFIG_LP17_USBHOST_NEDS Number of endpoint descriptors CONFIG_LP17_USBHOST_NTDS Number of transfer descriptors - CONFIG_LPC17_USBHOST_TDBUFFERS + CONFIG_LPC17_40_USBHOST_TDBUFFERS Number of transfer descriptor buffers - CONFIG_LPC17_USBHOST_TDBUFSIZE + CONFIG_LPC17_40_USBHOST_TDBUFSIZE Size of one transfer descriptor buffer - CONFIG_LPC17_USBHOST_IOBUFSIZE + CONFIG_LPC17_40_USBHOST_IOBUFSIZE Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index e74d98b38bb..c4c4e21bebe 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lpcxpresso-lpc1768" CONFIG_ARCH_BOARD_LPCXPRESSO=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y CONFIG_BOARD_LOOPSPERMSEC=8079 @@ -23,10 +23,10 @@ CONFIG_EXAMPLES_DHCPD=y CONFIG_EXAMPLES_DHCPD_IPADDR=0x0a000001 CONFIG_EXAMPLES_DHCPD_NOMAC=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=15776 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART3=y +CONFIG_LPC17_40_EMACRAM_SIZE=15776 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART3=y CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y diff --git a/configs/lpcxpresso-lpc1768/include/board.h b/configs/lpcxpresso-lpc1768/include/board.h index 6fa06314c45..af5d73f94a0 100644 --- a/configs/lpcxpresso-lpc1768/include/board.h +++ b/configs/lpcxpresso-lpc1768/include/board.h @@ -48,7 +48,7 @@ ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -64,14 +64,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz */ +#define LPC17_40_CCLK 80000000 /* 80Mhz */ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -90,8 +90,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -102,7 +102,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -119,8 +119,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 #define BOARD_FLASHCFG_VALUE 0x0000303a /* Ethernet configuration */ diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 7e6d02bc2c5..d519dd5d052 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -15,20 +15,20 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lpcxpresso-lpc1768" CONFIG_ARCH_BOARD_LPCXPRESSO=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y CONFIG_BOARD_LOOPSPERMSEC=8079 CONFIG_ETH0_PHY_LAN8720=y CONFIG_FS_FAT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART3=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART3=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 435500e3784..8e5e4cfbae3 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lpcxpresso-lpc1768" CONFIG_ARCH_BOARD_LPCXPRESSO=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y CONFIG_BOARD_LOOPSPERMSEC=8079 @@ -33,8 +33,8 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_MAXPOWER=2 CONFIG_LCD_UG9664HSWAG01=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART3=y +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART3=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/lpcxpresso-lpc1768/src/Makefile b/configs/lpcxpresso-lpc1768/src/Makefile index 24441d8eb35..7314ad70b31 100644 --- a/configs/lpcxpresso-lpc1768/src/Makefile +++ b/configs/lpcxpresso-lpc1768/src/Makefile @@ -36,26 +36,26 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_dac.c +CSRCS = lpc17_40_boot.c lpc17_40_leds.c lpc17_40_ssp.c lpc17_40_dac.c ifeq ($(CONFIG_PWM),y) -CSRCS += lpc17_pwm.c +CSRCS += lpc17_40_pwm.c endif ifeq ($(CONFIG_ADC),y) -CSRCS += lpc17_adc.c +CSRCS += lpc17_40_adc.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_NX_LCDDRIVER),y) -CSRCS += lpc17_oled.c +CSRCS += lpc17_40_oled.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_adc.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_adc.c similarity index 93% rename from configs/lpcxpresso-lpc1768/src/lpc17_adc.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_adc.c index e76f67ff20e..cc863cc02f1 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_adc.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_adc.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/lpcexpresso-1768/src/lpc17_adc.c + * configs/lpcexpresso-1768/src/lpc17_40_adc.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * Based on configs/stm3220g-eval/src/lpc17_adc.c + * Based on configs/stm3220g-eval/src/lpc17_40_adc.c * * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,7 +54,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_adc.h" +#include "lpc17_40_adc.h" #include "lpcxpresso-lpc1768.h" #ifdef CONFIG_ADC @@ -81,9 +81,9 @@ int lpcxpresso_adc_setup(void) if (!initialized) { - /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + /* Call lpc17_40_adcinitialize() to get an instance of the ADC interface */ - adc = lpc17_adcinitialize(); + adc = lpc17_40_adcinitialize(); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_appinit.c similarity index 97% rename from configs/lpcxpresso-lpc1768/src/lpc17_appinit.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_appinit.c index 47f66e95555..2a0120446db 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/lpcxpresso-lpc1768/src/lpc17_appinit.c + * config/lpcxpresso-lpc1768/src/lpc17_40_appinit.c * * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include #include -#include "lpc17_ssp.h" +#include "lpc17_40_ssp.h" /**************************************************************************** * Pre-processor Definitions @@ -60,7 +60,7 @@ /* PORT and SLOT number probably depend on the board configuration */ #define NSH_HAVEUSBDEV 1 -#ifdef CONFIG_LPC17_SSP1 +#ifdef CONFIG_LPC17_40_SSP1 # define NSH_HAVEMMCSD 1 #else # undef NSH_HAVEMMCSD @@ -147,7 +147,7 @@ int board_app_initialize(uintptr_t arg) #ifdef NSH_HAVEMMCSD /* Get the SSP port */ - ssp = lpc17_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); + ssp = lpc17_40_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); if (!ssp) { syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_boot.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_boot.c similarity index 91% rename from configs/lpcxpresso-lpc1768/src/lpc17_boot.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_boot.c index 24ba6ebe7bd..23011f6b10a 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_boot.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/lpcxpresso-lpc1768/src/lpc17_boot.c + * configs/lpcxpresso-lpc1768/src/lpc17_40_boot.c * * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_ssp.h" +#include "lpc17_40_ssp.h" #include "lpcxpresso-lpc1768.h" /************************************************************************************ @@ -63,22 +63,22 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak * function lpcxpresso_sspdev_initialize() has been brought into the link. */ -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) if (lpcxpresso_sspdev_initialize) { lpcxpresso_sspdev_initialize(); diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_dac.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_dac.c similarity index 90% rename from configs/lpcxpresso-lpc1768/src/lpc17_dac.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_dac.c index 1948b4312c2..34d038efe88 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_dac.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_dac.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_dac.c + * configs/zkit-arm-1769/src/lpc17_40_dac.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * Based on configs/stm3220g-eval/src/lpc17_dac.c + * Based on configs/stm3220g-eval/src/lpc17_40_dac.c * * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,7 +53,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_dac.h" +#include "lpc17_40_dac.h" #ifdef CONFIG_DAC @@ -61,7 +61,7 @@ * Name: dac_devinit * * Description: - * All LPC17xx architectures must provide the following interface to work with + * All LPC17xx/LPC40xx architectures must provide the following interface to work with * examples/diag. * ************************************************************************************/ @@ -74,9 +74,9 @@ int dac_devinit(void) if (!initialized) { - /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ - dac = lpc17_dacinitialize(); + dac = lpc17_40_dacinitialize(); if (dac == NULL) { aerr("ERROR: Failed to get dac interface\n"); diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_leds.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_leds.c similarity index 94% rename from configs/lpcxpresso-lpc1768/src/lpc17_leds.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_leds.c index c0ed65821f7..7dfeeac3835 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_leds.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/lpcxpresso-lpc1768/src/lpc17_leds.c + * configs/lpcxpresso-lpc1768/src/lpc17_40_leds.c * * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lpcxpresso-lpc1768.h" #ifdef CONFIG_ARCH_LEDS @@ -70,7 +70,7 @@ void board_autoled_initialize(void) { /* Configure all LED GPIO lines */ - lpc17_configgpio(LPCXPRESSO_LED); + lpc17_40_configgpio(LPCXPRESSO_LED); g_ncstate = true; } @@ -98,7 +98,7 @@ void board_autoled_on(int led) return; } - lpc17_gpiowrite(LPCXPRESSO_LED, off); + lpc17_40_gpiowrite(LPCXPRESSO_LED, off); } /**************************************************************************** @@ -124,7 +124,7 @@ void board_autoled_off(int led) return; } - lpc17_gpiowrite(LPCXPRESSO_LED, off); + lpc17_40_gpiowrite(LPCXPRESSO_LED, off); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_oled.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_oled.c similarity index 88% rename from configs/lpcxpresso-lpc1768/src/lpc17_oled.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_oled.c index 62050a2297c..0cfe4ddc4ff 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_oled.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_oled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/lpcxpresso-lpc1768/src/lpc17_oled.c + * config/lpcxpresso-lpc1768/src/lpc17_40_oled.c * * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,8 +48,8 @@ #include #include -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "lpcxpresso-lpc1768.h" /**************************************************************************** @@ -60,8 +60,8 @@ * case, it would be an error if SSP1 is not also enabled. */ -#ifndef CONFIG_LPC17_SSP1 -# error "The OLED driver requires CONFIG_LPC17_SSP1 in the configuration" +#ifndef CONFIG_LPC17_40_SSP1 +# error "The OLED driver requires CONFIG_LPC17_40_SSP1 in the configuration" #endif #ifndef CONFIG_UG9664HSWAG01_POWER @@ -71,8 +71,8 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_LCD -# define oleddc_dumpgpio(m) lpc17_dumpgpio(LPCXPRESSO_OLED_POWER, m) -# define oledcs_dumpgpio(m) lpc17_dumpgpio(LPCXPRESSO_OLED_CS, m) +# define oleddc_dumpgpio(m) lpc17_40_dumpgpio(LPCXPRESSO_OLED_POWER, m) +# define oledcs_dumpgpio(m) lpc17_40_dumpgpio(LPCXPRESSO_OLED_CS, m) #else # define oleddc_dumpgpio(m) # define oledcs_dumpgpio(m) @@ -102,14 +102,14 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno) oledcs_dumpgpio("board_graphics_setup: After OLED CS setup"); oleddc_dumpgpio("board_graphics_setup: On entry"); - (void)lpc17_configgpio(LPCXPRESSO_OLED_POWER); /* OLED 11V power */ - (void)lpc17_configgpio(LPCXPRESSO_OLED_DC); /* OLED Command/Data */ + (void)lpc17_40_configgpio(LPCXPRESSO_OLED_POWER); /* OLED 11V power */ + (void)lpc17_40_configgpio(LPCXPRESSO_OLED_DC); /* OLED Command/Data */ oleddc_dumpgpio("board_graphics_setup: After OLED Power/DC setup"); /* Get the SPI1 port (configure as a Freescale SPI port) */ - spi = lpc17_sspbus_initialize(1); + spi = lpc17_40_sspbus_initialize(1); if (!spi) { gerr("ERROR: Failed to initialize SPI port 1\n"); @@ -137,7 +137,7 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno) } /**************************************************************************** - * Name: lpc17_ssp1cmddata + * Name: lpc17_40_ssp1cmddata * * Description: * Set or clear the SD1329 D/Cn bit to select data (true) or command @@ -159,13 +159,13 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno) * ****************************************************************************/ -int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +int lpc17_40_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { if (devid == SPIDEV_DISPLAY(0)) { /* Set GPIO to 1 for data, 0 for command */ - (void)lpc17_gpiowrite(LPCXPRESSO_OLED_DC, !cmd); + (void)lpc17_40_gpiowrite(LPCXPRESSO_OLED_DC, !cmd); return OK; } return -ENODEV; @@ -194,6 +194,6 @@ int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) void ug_power(unsigned int devno, bool on) { ginfo("power %s\n", on ? "ON" : "OFF"); - (void)lpc17_gpiowrite(LPCXPRESSO_OLED_POWER, on); + (void)lpc17_40_gpiowrite(LPCXPRESSO_OLED_POWER, on); } #endif diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_pwm.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_pwm.c similarity index 85% rename from configs/lpcxpresso-lpc1768/src/lpc17_pwm.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_pwm.c index 27f122c27b0..169a02c6596 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_pwm.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_pwm.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/lpcexpresso-lpc1768/lpc17_pwm.c + * configs/lpcexpresso-lpc1768/lpc17_40_pwm.c * * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,8 +50,8 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_pwm.h" -#include "lpc17_timer.h" +#include "lpc17_40_pwm.h" +#include "lpc17_40_timer.h" #include "lpcxpresso-lpc1768.h" /************************************************************************************ @@ -60,9 +60,9 @@ #ifdef CONFIG_PWM -FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_mcpwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_timerinitialize(int timer); /************************************************************************************ * Public Functions @@ -88,12 +88,12 @@ int lpcexpresso_pwm_setup(void) if (!initialized) { - /* Call lpc17_pwminitialize() to get an instance of the PWM interface */ + /* Call lpc17_40_pwminitialize() to get an instance of the PWM interface */ - pwm = lpc17_pwminitialize(0); + pwm = lpc17_40_pwminitialize(0); if (!pwm) { - aerr("ERROR: Failed to get the LPC17XX PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX PWM lower half\n"); return -ENODEV; } @@ -106,10 +106,10 @@ int lpcexpresso_pwm_setup(void) return ret; } - mcpwm = lpc17_mcpwminitialize(0); + mcpwm = lpc17_40_mcpwminitialize(0); if (!mcpwm) { - aerr("ERROR: Failed to get the LPC17XX MOTOR PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX MOTOR PWM lower half\n"); return -ENODEV; } @@ -122,10 +122,10 @@ int lpcexpresso_pwm_setup(void) return ret; } - timer = lpc17_timerinitialize(0); + timer = lpc17_40_timerinitialize(0); if (!timer) { - aerr("ERROR: Failed to get the LPC17XX TIMER lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX TIMER lower half\n"); return -ENODEV; } diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_ssp.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_ssp.c similarity index 74% rename from configs/lpcxpresso-lpc1768/src/lpc17_ssp.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_ssp.c index 4aace2c26cc..b2c4cfb7746 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_ssp.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_ssp.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/lpcxpresso-lpc1768/src/lpc17_ssp.c + * configs/lpcxpresso-lpc1768/src/lpc17_40_ssp.c * * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,11 +48,11 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "lpcxpresso-lpc1768.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) /************************************************************************************ * Pre-processor Definitions @@ -61,7 +61,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_GPIO_INFO -# define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) +# define ssp_dumpgpio(m) lpc17_40_dumpgpio(SDCCS_GPIO, m) #else # define ssp_dumpgpio(m) #endif @@ -88,16 +88,16 @@ void weak_function lpcxpresso_sspdev_initialize(void) * be set correctly for the SD slot chip select. */ -#ifdef CONFIG_LPC17_SSP1 - (void)lpc17_configgpio(LPCXPRESSO_SD_CS); - (void)lpc17_configgpio(LPCXPRESSO_SD_CD); +#ifdef CONFIG_LPC17_40_SSP1 + (void)lpc17_40_configgpio(LPCXPRESSO_SD_CS); + (void)lpc17_40_configgpio(LPCXPRESSO_SD_CD); /* Configure chip select for the OLED. For the SPI interface, insert jumpers in * J42, J43, J45 pin1-2 and J46 pin 1-2. */ #ifdef CONFIG_NX_LCDDRIVER - (void)lpc17_configgpio(LPCXPRESSO_OLED_CS); + (void)lpc17_40_configgpio(LPCXPRESSO_OLED_CS); #endif #endif @@ -105,78 +105,78 @@ void weak_function lpcxpresso_sspdev_initialize(void) } /************************************************************************************ - * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * Name: lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * * Description: - * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * The external functions, lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc17_sspbus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * 2. Provide lpc17_40_ssp0/ssp1select() and lpc17_40_ssp0/ssp1status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc17_sspbus_initialize() in your low level application + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_ssp0select() Entry"); + ssp_dumpgpio("lpc17_40_ssp0select() Entry"); #warning "Assert CS here (false)" - ssp_dumpgpio("lpc17_ssp0select() Exit"); + ssp_dumpgpio("lpc17_40_ssp0select() Exit"); } -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; } #endif -#ifdef CONFIG_LPC17_SSP1 -void lpc17_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_ssp1select() Entry"); + ssp_dumpgpio("lpc17_40_ssp1select() Entry"); if (devid == SPIDEV_MMCSD(0)) { /* Assert/de-assert the CS pin to the card */ - (void)lpc17_gpiowrite(LPCXPRESSO_SD_CS, !selected); + (void)lpc17_40_gpiowrite(LPCXPRESSO_SD_CS, !selected); } #ifdef CONFIG_NX_LCDDRIVER else if (devid == SPIDEV_DISPLAY(0)) { /* Assert the CS pin to the OLED display */ - (void)lpc17_gpiowrite(LPCXPRESSO_OLED_CS, !selected); + (void)lpc17_40_gpiowrite(LPCXPRESSO_OLED_CS, !selected); } #endif - ssp_dumpgpio("lpc17_ssp1select() Exit"); + ssp_dumpgpio("lpc17_40_ssp1select() Exit"); } -uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) { if (devid == SPIDEV_MMCSD(0)) { /* Read the state of the card-detect bit */ - if (lpc17_gpioread(LPCXPRESSO_SD_CD) == 0) + if (lpc17_40_gpioread(LPCXPRESSO_SD_CD) == 0) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; @@ -188,4 +188,4 @@ uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) } #endif -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 */ diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_usbmsc.c b/configs/lpcxpresso-lpc1768/src/lpc17_40_usbmsc.c similarity index 81% rename from configs/lpcxpresso-lpc1768/src/lpc17_usbmsc.c rename to configs/lpcxpresso-lpc1768/src/lpc17_40_usbmsc.c index 84d8b65eb53..f4c7f3ca8a5 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_usbmsc.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_40_usbmsc.c @@ -1,10 +1,10 @@ /**************************************************************************** - * configs/lpcxpresso-lpc1768/src/lpc17_usbmsc.c + * configs/lpcxpresso-lpc1768/src/lpc17_40_usbmsc.c * * Copyright (C) 2011, 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Configure and register the LPC17xx MMC/SD SPI block driver. + * Configure and register the LPC17xx/LPC40xx MMC/SD SPI block driver. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -49,7 +49,7 @@ #include #include -#include "lpc17_ssp.h" +#include "lpc17_40_ssp.h" /**************************************************************************** * Pre-processor Definitions @@ -64,13 +64,13 @@ /* PORT and SLOT number probably depend on the board configuration */ #ifdef CONFIG_ARCH_BOARD_LPCXPRESSO -# undef LPC17XX_MMCSDSPIPORTNO -# define LPC17XX_MMCSDSPIPORTNO 1 -# undef LPC17XX_MMCSDSLOTNO -# define LPC17XX_MMCSDSLOTNO 0 +# undef LPC17XX_40XX_MMCSDSPIPORTNO +# define LPC17XX_40XX_MMCSDSPIPORTNO 1 +# undef LPC17XX_40XX_MMCSDSLOTNO +# define LPC17XX_40XX_MMCSDSLOTNO 0 #else - /* Add configuration for new LPC17xx boards here */ -# error "Unrecognized LPC17xx board" + /* Add configuration for new LPC17xx/LPC40xx boards here */ +# error "Unrecognized LPC17xx/LPC40xx board" #endif /**************************************************************************** @@ -92,34 +92,34 @@ int board_usbmsc_initialize(int port) /* Get the SPI port */ - syslog(LOG_INFO, "Initializing SPI port %d\n", LPC17XX_MMCSDSPIPORTNO); + syslog(LOG_INFO, "Initializing SPI port %d\n", LPC17XX_40XX_MMCSDSPIPORTNO); - spi = lpc17_sspbus_initialize(LPC17XX_MMCSDSPIPORTNO); + spi = lpc17_40_sspbus_initialize(LPC17XX_40XX_MMCSDSPIPORTNO); if (!spi) { syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); return -ENODEV; } syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); /* Bind the SPI port to the slot */ syslog(LOG_INFO, "Binding SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); - ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, LPC17XX_MMCSDSLOTNO, spi); + ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, LPC17XX_40XX_MMCSDSLOTNO, spi); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO, ret); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO, ret); return ret; } syslog(LOG_INFO, "Successfully bound SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); return OK; } diff --git a/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h b/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h index ecde0db1213..ac48799b599 100644 --- a/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h +++ b/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h @@ -147,7 +147,7 @@ */ #define LPCXPRESSO_SD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT2 | GPIO_PIN2) -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ # define LPCXPRESSO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) #else # define LPCXPRESSO_SD_CD (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) @@ -183,7 +183,7 @@ */ #define LPCXPRESSO_USB_CONNECT (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN21) -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ # define LPCXPRESSO_USB_VBUSSENSE (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) #else # define LPCXPRESSO_USB_VBUSSENSE (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index 350226f7222..926b6e07879 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lpcxpresso-lpc1768" CONFIG_ARCH_BOARD_LPCXPRESSO=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y CONFIG_BOARD_LOOPSPERMSEC=8079 @@ -22,10 +22,10 @@ CONFIG_EXAMPLES_THTTPD=y CONFIG_EXAMPLES_THTTPD_NOMAC=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=15776 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART3=y +CONFIG_LPC17_40_EMACRAM_SIZE=15776 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART3=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index cbef1483aff..ab468ee883b 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -11,18 +11,18 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lpcxpresso-lpc1768" CONFIG_ARCH_BOARD_LPCXPRESSO=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y CONFIG_BOARD_LOOPSPERMSEC=8079 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART3=y -CONFIG_LPC17_USBDEV=y -CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0 -CONFIG_LPC17_USBDEV_NOLED=y -CONFIG_LPC17_USBDEV_NOVBUS=y +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART3=y +CONFIG_LPC17_40_USBDEV=y +CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS=0 +CONFIG_LPC17_40_USBDEV_NOLED=y +CONFIG_LPC17_40_USBDEV_NOVBUS=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/mbed/README.txt b/configs/mbed/README.txt index f8019072c23..79d2c9b44fd 100644 --- a/configs/mbed/README.txt +++ b/configs/mbed/README.txt @@ -73,41 +73,41 @@ mbed Configuration Options CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. Individual subsystems can be enabled: - CONFIG_LPC17_MAINOSC=y - CONFIG_LPC17_PLL0=y - CONFIG_LPC17_PLL1=n - CONFIG_LPC17_ETHERNET=n - CONFIG_LPC17_USBHOST=n - CONFIG_LPC17_USBOTG=n - CONFIG_LPC17_USBDEV=n - CONFIG_LPC17_UART0=y - CONFIG_LPC17_UART1=n - CONFIG_LPC17_UART2=n - CONFIG_LPC17_UART3=n - CONFIG_LPC17_CAN1=n - CONFIG_LPC17_CAN2=n - CONFIG_LPC17_SPI=n - CONFIG_LPC17_SSP0=n - CONFIG_LPC17_SSP1=n - CONFIG_LPC17_I2C0=n - CONFIG_LPC17_I2C1=n - CONFIG_LPC17_I2S=n - CONFIG_LPC17_TMR0=n - CONFIG_LPC17_TMR1=n - CONFIG_LPC17_TMR2=n - CONFIG_LPC17_TMR3=n - CONFIG_LPC17_RIT=n - CONFIG_LPC17_PWM0=n - CONFIG_LPC17_MCPWM=n - CONFIG_LPC17_QEI=n - CONFIG_LPC17_RTC=n - CONFIG_LPC17_WDT=n - CONFIG_LPC17_ADC=n - CONFIG_LPC17_DAC=n - CONFIG_LPC17_GPDMA=n - CONFIG_LPC17_FLASH=n + CONFIG_LPC17_40_MAINOSC=y + CONFIG_LPC17_40_PLL0=y + CONFIG_LPC17_40_PLL1=n + CONFIG_LPC17_40_ETHERNET=n + CONFIG_LPC17_40_USBHOST=n + CONFIG_LPC17_40_USBOTG=n + CONFIG_LPC17_40_USBDEV=n + CONFIG_LPC17_40_UART0=y + CONFIG_LPC17_40_UART1=n + CONFIG_LPC17_40_UART2=n + CONFIG_LPC17_40_UART3=n + CONFIG_LPC17_40_CAN1=n + CONFIG_LPC17_40_CAN2=n + CONFIG_LPC17_40_SPI=n + CONFIG_LPC17_40_SSP0=n + CONFIG_LPC17_40_SSP1=n + CONFIG_LPC17_40_I2C0=n + CONFIG_LPC17_40_I2C1=n + CONFIG_LPC17_40_I2S=n + CONFIG_LPC17_40_TMR0=n + CONFIG_LPC17_40_TMR1=n + CONFIG_LPC17_40_TMR2=n + CONFIG_LPC17_40_TMR3=n + CONFIG_LPC17_40_RIT=n + CONFIG_LPC17_40_PWM0=n + CONFIG_LPC17_40_MCPWM=n + CONFIG_LPC17_40_QEI=n + CONFIG_LPC17_40_RTC=n + CONFIG_LPC17_40_WDT=n + CONFIG_LPC17_40_ADC=n + CONFIG_LPC17_40_DAC=n + CONFIG_LPC17_40_GPDMA=n + CONFIG_LPC17_40_FLASH=n - LPC17xx specific device driver settings + LPC17xx/LPC40xx specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -120,78 +120,78 @@ mbed Configuration Options CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_UARTn_2STOP - Two stop bits - LPC17xx specific CAN device driver settings. These settings all + LPC17xx/LPC40xx specific CAN device driver settings. These settings all require CONFIG_CAN: CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. - CONFIG_LPC17_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 + CONFIG_LPC17_40_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN1 is defined. - CONFIG_LPC17_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 + CONFIG_LPC17_40_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN2 is defined. - CONFIG_LPC17_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN_TSEG1 - The number of CAN time quanta in segment 1. + CONFIG_LPC17_40_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2. + CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 - LPC17xx specific PHY/Ethernet device driver settings. These setting - also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + LPC17xx/LPC40xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_40_ETHERNET. CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY - CONFIG_LPC17_PHY_AUTONEG - Enable auto-negotion - CONFIG_LPC17_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. - CONFIG_LPC17_PHY_FDUPLEX - Select full (vs. half) duplex + CONFIG_LPC17_40_PHY_AUTONEG - Enable auto-negotion + CONFIG_LPC17_40_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_LPC17_40_PHY_FDUPLEX - Select full (vs. half) duplex - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb - CONFIG_LPC17_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 - CONFIG_LPC17_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 - CONFIG_LPC17_ETH_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_WOL - Enable Wake-up on Lan (not fully implemented). CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. Also needs CONFIG_DEBUG_FEATURES. - CONFIG_LPC17_ETH_HASH - Enable receipt of near-perfect match frames. - CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + CONFIG_LPC17_40_ETH_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_40_MULTICAST - Enable receipt of multicast (and unicast) frames. Automatically set if CONFIG_NET_MCASTGROUP is selected. - LPC17xx USB Device Configuration + LPC17xx/LPC40xx USB Device Configuration - CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT Handle USB Start-Of-Frame events. Enable reading SOF from interrupt handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. - CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT Enable high priority interrupts. I have no idea why you might want to do that - CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. - CONFIG_LPC17_USBDEV_DMA - Enable lpc17xx-specific DMA support - CONFIG_LPC17_USBDEV_NOVBUS + CONFIG_LPC17_40_USBDEV_DMA + Enable lpc17xx/lpc40xx-specific DMA support + CONFIG_LPC17_40_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal - CONFIG_LPC17_USBDEV_NOLED + CONFIG_LPC17_40_USBDEV_NOLED Define if the hardware implementation does not support the LED output - LPC17xx USB Host Configuration + LPC17xx/LPC40xx USB Host Configuration - CONFIG_LPC17_OHCIRAM_SIZE + CONFIG_LPC17_40_OHCIRAM_SIZE Total size of OHCI RAM (in AHB SRAM Bank 1) CONFIG_LP17_USBHOST_NEDS Number of endpoint descriptors CONFIG_LP17_USBHOST_NTDS Number of transfer descriptors - CONFIG_LPC17_USBHOST_TDBUFFERS + CONFIG_LPC17_40_USBHOST_TDBUFFERS Number of transfer descriptor buffers - CONFIG_LPC17_USBHOST_TDBUFSIZE + CONFIG_LPC17_40_USBHOST_TDBUFSIZE Size of one transfer descriptor buffer - CONFIG_LPC17_USBHOST_IOBUFSIZE + CONFIG_LPC17_40_USBHOST_IOBUFSIZE Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. @@ -213,8 +213,8 @@ USB Host Configuration 2. Then edit the top-level .config file to enable USB host. Make the following changes using 'make menuconfig': - System Type -> LPC17xx Peripheral Support - CONFIG_LPC17_USBHOST=y : USB host controller driver support + System Type -> LPC17xx/LPC40xx Peripheral Support + CONFIG_LPC17_40_USBHOST=y : USB host controller driver support Device Drivers -> USB Host Driver Support CONFIG_USBHOST=y : USB host support diff --git a/configs/mbed/include/board.h b/configs/mbed/include/board.h index add4e960950..34545c73350 100644 --- a/configs/mbed/include/board.h +++ b/configs/mbed/include/board.h @@ -47,7 +47,7 @@ ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -63,14 +63,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz*/ +#define LPC17_40_CCLK 80000000 /* 80Mhz*/ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -89,8 +89,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -101,7 +101,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -118,8 +118,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 #define BOARD_FLASHCFG_VALUE 0x0000303a /* Ethernet configuration */ @@ -142,7 +142,7 @@ /* After the system is booted, this logic will no longer use LEDs 1 & 2. They * are available together with LED3 for use the application software using - * lpc17_led (prototyped below) + * lpc17_40_led (prototyped below) */ /* LED1 LED2 LED3 LED4 */ #define LED_INIRQ 4 /* NC NC NC ON (momentary) */ @@ -297,7 +297,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control LEDs 1, 2 & 3 @@ -305,7 +305,7 @@ extern "C" ************************************************************************************/ #ifdef CONFIG_ARCH_LEDS -void lpc17_led(int lednum, int state); +void lpc17_40_led(int lednum, int state); #endif #undef EXTERN diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index b9a5de39557..3433fead4b7 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -17,13 +17,13 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mbed" CONFIG_ARCH_BOARD_MBED=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_FS_FAT=y -CONFIG_LPC17_SSP0=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_SSP0=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/mbed/src/Makefile b/configs/mbed/src/Makefile index 6ad1d5ff114..6090e2859b6 100644 --- a/configs/mbed/src/Makefile +++ b/configs/mbed/src/Makefile @@ -36,22 +36,22 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_dac.c +CSRCS = lpc17_40_boot.c lpc17_40_leds.c lpc17_40_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif ifeq ($(CONFIG_PWM),y) -CSRCS += lpc17_pwm.c +CSRCS += lpc17_40_pwm.c endif ifeq ($(CONFIG_ADC),y) -CSRCS += lpc17_adc.c +CSRCS += lpc17_40_adc.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/mbed/src/lpc17_adc.c b/configs/mbed/src/lpc17_40_adc.c similarity index 93% rename from configs/mbed/src/lpc17_adc.c rename to configs/mbed/src/lpc17_40_adc.c index 059e63de000..ad24a170197 100644 --- a/configs/mbed/src/lpc17_adc.c +++ b/configs/mbed/src/lpc17_40_adc.c @@ -1,12 +1,12 @@ /************************************************************************************ - * configs/mbed/src/lpc17_adc.c + * configs/mbed/src/lpc17_40_adc.c * * Based on configs/zkit-arm-176/src/up-adc * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * Based on configs/lpc1720g-eval/src/lpc17_adc.c + * Based on configs/lpc1720g-eval/src/lpc17_40_adc.c * * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -56,7 +56,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_adc.h" +#include "lpc17_40_adc.h" #include "mbed.h" #ifdef CONFIG_ADC @@ -83,9 +83,9 @@ int mbed_adc_setup(void) if (!initialized) { - /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + /* Call lpc17_40_adcinitialize() to get an instance of the ADC interface */ - adc = lpc17_adcinitialize(); + adc = lpc17_40_adcinitialize(); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/configs/mbed/src/lpc17_appinit.c b/configs/mbed/src/lpc17_40_appinit.c similarity index 99% rename from configs/mbed/src/lpc17_appinit.c rename to configs/mbed/src/lpc17_40_appinit.c index e99d177894b..e0d4e9d9748 100644 --- a/configs/mbed/src/lpc17_appinit.c +++ b/configs/mbed/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/mbed/src/lpc17_appinit.c + * config/mbed/src/lpc17_40_appinit.c * * Copyright (C) 2010, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/mbed/src/lpc17_boot.c b/configs/mbed/src/lpc17_40_boot.c similarity index 94% rename from configs/mbed/src/lpc17_boot.c rename to configs/mbed/src/lpc17_40_boot.c index ee1796628df..282ba4944ad 100644 --- a/configs/mbed/src/lpc17_boot.c +++ b/configs/mbed/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/mbed/src/lpc17_boot.c + * configs/mbed/src/lpc17_40_boot.c * * Copyright (C) 2010, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -62,16 +62,16 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/mbed/src/lpc17_dac.c b/configs/mbed/src/lpc17_40_dac.c similarity index 90% rename from configs/mbed/src/lpc17_dac.c rename to configs/mbed/src/lpc17_40_dac.c index dccdbb92f5a..6e616d87a26 100644 --- a/configs/mbed/src/lpc17_dac.c +++ b/configs/mbed/src/lpc17_40_dac.c @@ -1,7 +1,7 @@ /************************************************************************************ - * configs/mbed/src/lpc17_dac.c + * configs/mbed/src/lpc17_40_dac.c * - * Based on configs/zkit-arm-1769/src/lpc17_dac.c + * Based on configs/zkit-arm-1769/src/lpc17_40_dac.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan @@ -55,7 +55,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_dac.h" +#include "lpc17_40_dac.h" #ifdef CONFIG_DAC @@ -63,7 +63,7 @@ * Name: dac_devinit * * Description: - * All LPC17xx architectures must provide the following interface to work with + * All LPC17xx/LPC40xx architectures must provide the following interface to work with * examples/diag. * ************************************************************************************/ @@ -76,9 +76,9 @@ int dac_devinit(void) if (!initialized) { - /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ - dac = lpc17_dacinitialize(); + dac = lpc17_40_dacinitialize(); if (dac == NULL) { aerr("ERROR: Failed to get dac interface\n"); diff --git a/configs/mbed/src/lpc17_leds.c b/configs/mbed/src/lpc17_40_leds.c similarity index 91% rename from configs/mbed/src/lpc17_leds.c rename to configs/mbed/src/lpc17_40_leds.c index f1f9978d40c..21c019105f1 100644 --- a/configs/mbed/src/lpc17_leds.c +++ b/configs/mbed/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/mbed/src/lpc17_leds.c + * configs/mbed/src/lpc17_40_leds.c * * Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "mbed.h" @@ -63,7 +63,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) lpc17_dumpgpio(MBED_LED3, m) +# define led_dumpgpio(m) lpc17_40_dumpgpio(MBED_LED3, m) #else # define led_dumpgpio(m) #endif @@ -88,7 +88,7 @@ STACKCREATED OFF OFF After the system is booted, this logic will no longer use LEDs 1 & 2. They are available together with LED3 for use the application software using -lpc17_led (prototyped below) +lpc17_40_led (prototyped below) */ static bool g_initialized; @@ -112,10 +112,10 @@ void board_autoled_initialize(void) led_dumpgpio("board_autoled_initialize() Entry)"); - lpc17_configgpio(MBED_LED1); - lpc17_configgpio(MBED_LED2); - lpc17_configgpio(MBED_LED3); - lpc17_configgpio(MBED_LED4); + lpc17_40_configgpio(MBED_LED1); + lpc17_40_configgpio(MBED_LED2); + lpc17_40_configgpio(MBED_LED3); + lpc17_40_configgpio(MBED_LED4); led_dumpgpio("board_autoled_initialize() Exit"); } @@ -147,8 +147,8 @@ void board_autoled_on(int led) case LED_IRQSENABLED: led2 = 1; } - lpc17_led(MBED_LED1,led1); - lpc17_led(MBED_LED2,led2); + lpc17_40_led(MBED_LED1,led1); + lpc17_40_led(MBED_LED2,led2); } /* We will always control the HB LED */ @@ -159,7 +159,7 @@ void board_autoled_on(int led) case LED_SIGNAL: case LED_ASSERTION: case LED_PANIC: - lpc17_gpiowrite(MBED_HEARTBEAT, false); + lpc17_40_gpiowrite(MBED_HEARTBEAT, false); g_nestcount++; default: @@ -177,7 +177,7 @@ void board_autoled_off(int led) if (g_nestcount <= 1) { - lpc17_led(MBED_HEARTBEAT, true); + lpc17_40_led(MBED_HEARTBEAT, true); g_nestcount = 0; } else @@ -187,16 +187,16 @@ void board_autoled_off(int led) } /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control the LEDs * ************************************************************************************/ -void lpc17_led(int lednum, int state) +void lpc17_40_led(int lednum, int state) { - lpc17_gpiowrite(lednum, state); + lpc17_40_gpiowrite(lednum, state); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/mbed/src/lpc17_pwm.c b/configs/mbed/src/lpc17_40_pwm.c similarity index 84% rename from configs/mbed/src/lpc17_pwm.c rename to configs/mbed/src/lpc17_40_pwm.c index 6ed91a0c20d..7396a6ca7a8 100644 --- a/configs/mbed/src/lpc17_pwm.c +++ b/configs/mbed/src/lpc17_40_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ - * configs/mbed/lpc17_pwm.c + * configs/mbed/lpc17_40_pwm.c * - * Based on onfigs/lpcexpresso-lpc1768/lpc17_pwm.c + * Based on onfigs/lpcexpresso-lpc1768/lpc17_40_pwm.c * * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,8 +52,8 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_pwm.h" -#include "lpc17_timer.h" +#include "lpc17_40_pwm.h" +#include "lpc17_40_timer.h" #include "mbed.h" /************************************************************************************ @@ -62,9 +62,9 @@ #ifdef CONFIG_PWM -FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_mcpwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_timerinitialize(int timer); /************************************************************************************ * Public Functions @@ -90,12 +90,12 @@ int mbed_pwm_setup(void) if (!initialized) { - /* Call lpc17_pwminitialize() to get an instance of the PWM interface */ + /* Call lpc17_40_pwminitialize() to get an instance of the PWM interface */ - pwm = lpc17_pwminitialize(0); + pwm = lpc17_40_pwminitialize(0); if (!pwm) { - aerr("ERROR: Failed to get the LPC17XX PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX PWM lower half\n"); return -ENODEV; } @@ -108,10 +108,10 @@ int mbed_pwm_setup(void) return ret; } - mcpwm = lpc17_mcpwminitialize(0); + mcpwm = lpc17_40_mcpwminitialize(0); if (!mcpwm) { - aerr("ERROR: Failed to get the LPC17XX MOTOR PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX MOTOR PWM lower half\n"); return -ENODEV; } @@ -124,10 +124,10 @@ int mbed_pwm_setup(void) return ret; } - timer = lpc17_timerinitialize(0); + timer = lpc17_40_timerinitialize(0); if (!timer) { - aerr("ERROR: Failed to get the LPC17XX TIMER lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX TIMER lower half\n"); return -ENODEV; } diff --git a/configs/mcb1700/README.txt b/configs/mcb1700/README.txt index adc0fb692d8..25f747ceb5f 100644 --- a/configs/mcb1700/README.txt +++ b/configs/mcb1700/README.txt @@ -74,41 +74,41 @@ mcb1700 Configuration Options CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. Individual subsystems can be enabled: - CONFIG_LPC17_MAINOSC=y - CONFIG_LPC17_PLL0=y - CONFIG_LPC17_PLL1=n - CONFIG_LPC17_ETHERNET=n - CONFIG_LPC17_USBHOST=n - CONFIG_LPC17_USBOTG=n - CONFIG_LPC17_USBDEV=n - CONFIG_LPC17_UART0=y - CONFIG_LPC17_UART1=n - CONFIG_LPC17_UART2=n - CONFIG_LPC17_UART3=n - CONFIG_LPC17_CAN1=n - CONFIG_LPC17_CAN2=n - CONFIG_LPC17_SPI=n - CONFIG_LPC17_SSP0=n - CONFIG_LPC17_SSP1=n - CONFIG_LPC17_I2C0=n - CONFIG_LPC17_I2C1=n - CONFIG_LPC17_I2S=n - CONFIG_LPC17_TMR0=n - CONFIG_LPC17_TMR1=n - CONFIG_LPC17_TMR2=n - CONFIG_LPC17_TMR3=n - CONFIG_LPC17_RIT=n - CONFIG_LPC17_PWM0=n - CONFIG_LPC17_MCPWM=n - CONFIG_LPC17_QEI=n - CONFIG_LPC17_RTC=n - CONFIG_LPC17_WDT=n - CONFIG_LPC17_ADC=n - CONFIG_LPC17_DAC=n - CONFIG_LPC17_GPDMA=n - CONFIG_LPC17_FLASH=n + CONFIG_LPC17_40_MAINOSC=y + CONFIG_LPC17_40_PLL0=y + CONFIG_LPC17_40_PLL1=n + CONFIG_LPC17_40_ETHERNET=n + CONFIG_LPC17_40_USBHOST=n + CONFIG_LPC17_40_USBOTG=n + CONFIG_LPC17_40_USBDEV=n + CONFIG_LPC17_40_UART0=y + CONFIG_LPC17_40_UART1=n + CONFIG_LPC17_40_UART2=n + CONFIG_LPC17_40_UART3=n + CONFIG_LPC17_40_CAN1=n + CONFIG_LPC17_40_CAN2=n + CONFIG_LPC17_40_SPI=n + CONFIG_LPC17_40_SSP0=n + CONFIG_LPC17_40_SSP1=n + CONFIG_LPC17_40_I2C0=n + CONFIG_LPC17_40_I2C1=n + CONFIG_LPC17_40_I2S=n + CONFIG_LPC17_40_TMR0=n + CONFIG_LPC17_40_TMR1=n + CONFIG_LPC17_40_TMR2=n + CONFIG_LPC17_40_TMR3=n + CONFIG_LPC17_40_RIT=n + CONFIG_LPC17_40_PWM0=n + CONFIG_LPC17_40_MCPWM=n + CONFIG_LPC17_40_QEI=n + CONFIG_LPC17_40_RTC=n + CONFIG_LPC17_40_WDT=n + CONFIG_LPC17_40_ADC=n + CONFIG_LPC17_40_DAC=n + CONFIG_LPC17_40_GPDMA=n + CONFIG_LPC17_40_FLASH=n - LPC17xx specific device driver settings + LPC17xx/LPC40xx specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -121,78 +121,78 @@ mcb1700 Configuration Options CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_UARTn_2STOP - Two stop bits - LPC17xx specific CAN device driver settings. These settings all + LPC17xx/LPC40xx specific CAN device driver settings. These settings all require CONFIG_CAN: CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. - CONFIG_LPC17_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 + CONFIG_LPC17_40_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN1 is defined. - CONFIG_LPC17_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 + CONFIG_LPC17_40_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN2 is defined. - CONFIG_LPC17_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN_TSEG1 - The number of CAN time quanta in segment 1. + CONFIG_LPC17_40_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2. + CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 - LPC17xx specific PHY/Ethernet device driver settings. These setting - also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + LPC17xx/LPC40xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_40_ETHERNET. CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY - CONFIG_LPC17_PHY_AUTONEG - Enable auto-negotion - CONFIG_LPC17_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. - CONFIG_LPC17_PHY_FDUPLEX - Select full (vs. half) duplex + CONFIG_LPC17_40_PHY_AUTONEG - Enable auto-negotion + CONFIG_LPC17_40_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_LPC17_40_PHY_FDUPLEX - Select full (vs. half) duplex - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb - CONFIG_LPC17_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 - CONFIG_LPC17_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 - CONFIG_LPC17_ETH_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_WOL - Enable Wake-up on Lan (not fully implemented). CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. Also needs CONFIG_DEBUG_FEATURES. - CONFIG_LPC17_ETH_HASH - Enable receipt of near-perfect match frames. - CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + CONFIG_LPC17_40_ETH_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_40_MULTICAST - Enable receipt of multicast (and unicast) frames. Automatically set if CONFIG_NET_MCASTGROUP is selected. - LPC17xx USB Device Configuration + LPC17xx/LPC40xx USB Device Configuration - CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT Handle USB Start-Of-Frame events. Enable reading SOF from interrupt handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. - CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT Enable high priority interrupts. I have no idea why you might want to do that - CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. - CONFIG_LPC17_USBDEV_DMA - Enable lpc17xx-specific DMA support - CONFIG_LPC17_USBDEV_NOVBUS + CONFIG_LPC17_40_USBDEV_DMA + Enable lpc17xx/lpc40xx-specific DMA support + CONFIG_LPC17_40_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal - CONFIG_LPC17_USBDEV_NOLED + CONFIG_LPC17_40_USBDEV_NOLED Define if the hardware implementation does not support the LED output - LPC17xx USB Host Configuration + LPC17xx/LPC40xx USB Host Configuration - CONFIG_LPC17_OHCIRAM_SIZE + CONFIG_LPC17_40_OHCIRAM_SIZE Total size of OHCI RAM (in AHB SRAM Bank 1) CONFIG_LP17_USBHOST_NEDS Number of endpoint descriptors CONFIG_LP17_USBHOST_NTDS Number of transfer descriptors - CONFIG_LPC17_USBHOST_TDBUFFERS + CONFIG_LPC17_40_USBHOST_TDBUFFERS Number of transfer descriptor buffers - CONFIG_LPC17_USBHOST_TDBUFSIZE + CONFIG_LPC17_40_USBHOST_TDBUFSIZE Size of one transfer descriptor buffer - CONFIG_LPC17_USBHOST_IOBUFSIZE + CONFIG_LPC17_40_USBHOST_IOBUFSIZE Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. @@ -214,8 +214,8 @@ USB Host Configuration 2. Then edit the top-level .config file to enable USB host. Make the following changes using 'make menuconfig': - System Type -> LPC17xx Peripheral Support - CONFIG_LPC17_USBHOST=y : USB host controller driver support + System Type -> LPC17xx/LPC40xx Peripheral Support + CONFIG_LPC17_40_USBHOST=y : USB host controller driver support Device Drivers -> USB Host Driver Support CONFIG_USBHOST=y : USB host support diff --git a/configs/mcb1700/include/board.h b/configs/mcb1700/include/board.h index b57f4862e8b..e07c5b9b8ff 100644 --- a/configs/mcb1700/include/board.h +++ b/configs/mcb1700/include/board.h @@ -47,7 +47,7 @@ ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -63,14 +63,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz*/ +#define LPC17_40_CCLK 80000000 /* 80Mhz*/ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -89,8 +89,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -101,7 +101,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -118,8 +118,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 #define BOARD_FLASHCFG_VALUE 0x0000303a /* Ethernet configuration */ @@ -142,7 +142,7 @@ /* After the system is booted, this logic will no longer use LEDs 1 & 2. They * are available together with LED3 for use the application software using - * lpc17_led (prototyped below) + * lpc17_40_led (prototyped below) */ /* LED1 LED2 LED3 LED4 */ #define LED_INIRQ 4 /* NC NC NC ON (momentary) */ @@ -297,7 +297,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control LEDs 1, 2 & 3 @@ -305,7 +305,7 @@ extern "C" ************************************************************************************/ #ifdef CONFIG_ARCH_LEDS -void lpc17_led(int lednum, int state); +void lpc17_40_led(int lednum, int state); #endif #undef EXTERN diff --git a/configs/mcb1700/nsh/defconfig b/configs/mcb1700/nsh/defconfig index ebccbd12ef5..e15c2fc0527 100644 --- a/configs/mcb1700/nsh/defconfig +++ b/configs/mcb1700/nsh/defconfig @@ -17,13 +17,13 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mcb1700" CONFIG_ARCH_BOARD_MCB1700=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_FS_FAT=y -CONFIG_LPC17_SSP0=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_SSP0=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/mcb1700/src/Makefile b/configs/mcb1700/src/Makefile index 508ef323b17..defd96fdc57 100644 --- a/configs/mcb1700/src/Makefile +++ b/configs/mcb1700/src/Makefile @@ -36,22 +36,22 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_bringup.c lpc17_leds.c lpc17_dac.c +CSRCS = lpc17_40_boot.c lpc17_40_bringup.c lpc17_40_leds.c lpc17_40_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif ifeq ($(CONFIG_PWM),y) -CSRCS += lpc17_pwm.c +CSRCS += lpc17_40_pwm.c endif ifeq ($(CONFIG_ADC),y) -CSRCS += lpc17_adc.c +CSRCS += lpc17_40_adc.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/mcb1700/src/lpc17_adc.c b/configs/mcb1700/src/lpc17_40_adc.c similarity index 93% rename from configs/mcb1700/src/lpc17_adc.c rename to configs/mcb1700/src/lpc17_40_adc.c index ab25ba6c373..2a8bb33913b 100644 --- a/configs/mcb1700/src/lpc17_adc.c +++ b/configs/mcb1700/src/lpc17_40_adc.c @@ -1,12 +1,12 @@ /************************************************************************************ - * configs/mcb1700/src/lpc17_adc.c + * configs/mcb1700/src/lpc17_40_adc.c * * Based on configs/zkit-arm-176/src/up-adc * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * Based on configs/lpc1720g-eval/src/lpc17_adc.c + * Based on configs/lpc1720g-eval/src/lpc17_40_adc.c * * Copyright (C) 2012, 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -56,7 +56,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_adc.h" +#include "lpc17_40_adc.h" #include "mcb1700.h" #ifdef CONFIG_ADC @@ -83,9 +83,9 @@ int mcb1700_adc_setup(void) if (!initialized) { - /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + /* Call lpc17_40_adcinitialize() to get an instance of the ADC interface */ - adc = lpc17_adcinitialize(); + adc = lpc17_40_adcinitialize(); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/configs/mcb1700/src/lpc17_appinit.c b/configs/mcb1700/src/lpc17_40_appinit.c similarity index 98% rename from configs/mcb1700/src/lpc17_appinit.c rename to configs/mcb1700/src/lpc17_40_appinit.c index 3499c0d0b9a..ef0570697c4 100644 --- a/configs/mcb1700/src/lpc17_appinit.c +++ b/configs/mcb1700/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/mcb1700/src/lpc17_appinit.c + * config/mcb1700/src/lpc17_40_appinit.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/mcb1700/src/lpc17_boot.c b/configs/mcb1700/src/lpc17_40_boot.c similarity index 94% rename from configs/mcb1700/src/lpc17_boot.c rename to configs/mcb1700/src/lpc17_40_boot.c index 981deb5e87d..72642c60707 100644 --- a/configs/mcb1700/src/lpc17_boot.c +++ b/configs/mcb1700/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/mcb1700/src/lpc17_boot.c + * configs/mcb1700/src/lpc17_40_boot.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,16 +54,16 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/mcb1700/src/lpc17_bringup.c b/configs/mcb1700/src/lpc17_40_bringup.c similarity index 94% rename from configs/mcb1700/src/lpc17_bringup.c rename to configs/mcb1700/src/lpc17_40_bringup.c index be818078b9a..c095d7a68bd 100644 --- a/configs/mcb1700/src/lpc17_bringup.c +++ b/configs/mcb1700/src/lpc17_40_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/mcb1700/src/lpc17_bringup.c + * config/mcb1700/src/lpc17_40_bringup.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,9 +51,9 @@ #include #include -#include "lpc17_ssp.h" -#include "lpc17_gpio.h" -#include "lpc17_usbhost.h" +#include "lpc17_40_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_usbhost.h" #include "mcb1700.h" @@ -94,7 +94,7 @@ /* Can't support MMC/SD is SSP1 is not enabled */ -#ifndef CONFIG_LPC17_SSP1 +#ifndef CONFIG_LPC17_40_SSP1 # undef HAVE_MMCSD #endif @@ -107,18 +107,18 @@ /* USB Host */ #ifdef CONFIG_USBHOST -# ifndef CONFIG_LPC17_USBHOST -# error "CONFIG_LPC17_USBHOST is not selected" +# ifndef CONFIG_LPC17_40_USBHOST +# error "CONFIG_LPC17_40_USBHOST is not selected" # endif #endif -#ifdef CONFIG_LPC17_USBHOST +#ifdef CONFIG_LPC17_40_USBHOST # ifndef CONFIG_USBHOST # warning "CONFIG_USBHOST is not selected" # endif #endif -#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_USBHOST) +#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_40_USBHOST) # undef HAVE_USBHOST #endif @@ -196,11 +196,11 @@ static int nsh_sdinitialize(void) /* Enable power to the SD/MMC via a GPIO. LOW enables SD/MMC. */ - lpc17_gpiowrite(MCB1700_MMC_PWR, false); + lpc17_40_gpiowrite(MCB1700_MMC_PWR, false); /* Get the SSP port. MMC/SD is on SSP port 1. */ - ssp = lpc17_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); + ssp = lpc17_40_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); if (!ssp) { syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", @@ -233,7 +233,7 @@ static int nsh_sdinitialize(void) /* Disable power to the SD/MMC via a GPIO. HIGH disables SD/MMC. */ errout: - lpc17_gpiowrite(MCB1700_MMC_PWR, true); + lpc17_40_gpiowrite(MCB1700_MMC_PWR, true); return ret; } #else @@ -295,7 +295,7 @@ static int nsh_usbhostinitialize(void) /* Then get an instance of the USB host interface */ syslog(LOG_INFO, "Initialize USB host\n"); - g_usbconn = lpc17_usbhost_initialize(0); + g_usbconn = lpc17_40_usbhost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ diff --git a/configs/mcb1700/src/lpc17_dac.c b/configs/mcb1700/src/lpc17_40_dac.c similarity index 90% rename from configs/mcb1700/src/lpc17_dac.c rename to configs/mcb1700/src/lpc17_40_dac.c index f64abe1ab9c..6fe599257aa 100644 --- a/configs/mcb1700/src/lpc17_dac.c +++ b/configs/mcb1700/src/lpc17_40_dac.c @@ -1,7 +1,7 @@ /************************************************************************************ - * configs/mcb1700/src/lpc17_dac.c + * configs/mcb1700/src/lpc17_40_dac.c * - * Based on configs/zkit-arm-1769/src/lpc17_dac.c + * Based on configs/zkit-arm-1769/src/lpc17_40_dac.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan @@ -55,7 +55,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_dac.h" +#include "lpc17_40_dac.h" #ifdef CONFIG_DAC @@ -63,7 +63,7 @@ * Name: dac_devinit * * Description: - * All LPC17xx architectures must provide the following interface to work with + * All LPC17xx/LPC40xx architectures must provide the following interface to work with * examples/diag. * ************************************************************************************/ @@ -76,9 +76,9 @@ int dac_devinit(void) if (!initialized) { - /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ - dac = lpc17_dacinitialize(); + dac = lpc17_40_dacinitialize(); if (dac == NULL) { aerr("ERROR: Failed to get dac interface\n"); diff --git a/configs/mcb1700/src/lpc17_leds.c b/configs/mcb1700/src/lpc17_40_leds.c similarity index 90% rename from configs/mcb1700/src/lpc17_leds.c rename to configs/mcb1700/src/lpc17_40_leds.c index ac4075e7db2..236a5f9237d 100644 --- a/configs/mcb1700/src/lpc17_leds.c +++ b/configs/mcb1700/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/mcb1700/src/lpc17_leds.c + * configs/mcb1700/src/lpc17_40_leds.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "mcb1700.h" @@ -63,7 +63,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) lpc17_dumpgpio(MCB1700_LED3, m) +# define led_dumpgpio(m) lpc17_40_dumpgpio(MCB1700_LED3, m) #else # define led_dumpgpio(m) #endif @@ -88,7 +88,7 @@ * * After the system is booted, this logic will no longer use LEDs 1 & 2. * They are available together with LED3 for use the application software - * using lpc17_led (prototyped below) + * using lpc17_40_led (prototyped below) */ static bool g_initialized; @@ -108,10 +108,10 @@ void board_autoled_initialize(void) led_dumpgpio("board_autoled_initialize() Entry)"); - lpc17_configgpio(MCB1700_LED1); - lpc17_configgpio(MCB1700_LED2); - lpc17_configgpio(MCB1700_LED3); - lpc17_configgpio(MCB1700_LED4); + lpc17_40_configgpio(MCB1700_LED1); + lpc17_40_configgpio(MCB1700_LED2); + lpc17_40_configgpio(MCB1700_LED3); + lpc17_40_configgpio(MCB1700_LED4); led_dumpgpio("board_autoled_initialize() Exit"); } @@ -145,8 +145,8 @@ void board_autoled_on(int led) led2 = 1; } - lpc17_led(MCB1700_LED1,led1); - lpc17_led(MCB1700_LED2,led2); + lpc17_40_led(MCB1700_LED1,led1); + lpc17_40_led(MCB1700_LED2,led2); } /* We will always control the HB LED */ @@ -157,7 +157,7 @@ void board_autoled_on(int led) case LED_SIGNAL: case LED_ASSERTION: case LED_PANIC: - lpc17_gpiowrite(MCB1700_HEARTBEAT, false); + lpc17_40_gpiowrite(MCB1700_HEARTBEAT, false); g_nestcount++; default: @@ -175,7 +175,7 @@ void board_autoled_off(int led) if (g_nestcount <= 1) { - lpc17_led(MCB1700_HEARTBEAT, true); + lpc17_40_led(MCB1700_HEARTBEAT, true); g_nestcount = 0; } else @@ -185,16 +185,16 @@ void board_autoled_off(int led) } /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control the LEDs * ************************************************************************************/ -void lpc17_led(int lednum, int state) +void lpc17_40_led(int lednum, int state) { - lpc17_gpiowrite(lednum, state); + lpc17_40_gpiowrite(lednum, state); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/mcb1700/src/lpc17_pwm.c b/configs/mcb1700/src/lpc17_40_pwm.c similarity index 84% rename from configs/mcb1700/src/lpc17_pwm.c rename to configs/mcb1700/src/lpc17_40_pwm.c index f7e241c20ab..08ddeaa7d14 100644 --- a/configs/mcb1700/src/lpc17_pwm.c +++ b/configs/mcb1700/src/lpc17_40_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ - * configs/mcb1700/lpc17_pwm.c + * configs/mcb1700/lpc17_40_pwm.c * - * Based on configs/lpcexpresso-lpc1768/lpc17_pwm.c + * Based on configs/lpcexpresso-lpc1768/lpc17_40_pwm.c * * Copyright (C) 2014-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,8 +52,8 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_pwm.h" -#include "lpc17_timer.h" +#include "lpc17_40_pwm.h" +#include "lpc17_40_timer.h" #include "mcb1700.h" /************************************************************************************ @@ -62,9 +62,9 @@ #ifdef CONFIG_PWM -FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_mcpwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_timerinitialize(int timer); /************************************************************************************ * Public Functions @@ -90,12 +90,12 @@ int mcb1700_pwm_setup(void) if (!initialized) { - /* Call lpc17_pwminitialize() to get an instance of the PWM interface */ + /* Call lpc17_40_pwminitialize() to get an instance of the PWM interface */ - pwm = lpc17_pwminitialize(0); + pwm = lpc17_40_pwminitialize(0); if (!pwm) { - aerr("ERROR: Failed to get the LPC17XX PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX PWM lower half\n"); return -ENODEV; } @@ -108,10 +108,10 @@ int mcb1700_pwm_setup(void) return ret; } - mcpwm = lpc17_mcpwminitialize(0); + mcpwm = lpc17_40_mcpwminitialize(0); if (!mcpwm) { - aerr("ERROR: Failed to get the LPC17XX MOTOR PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX MOTOR PWM lower half\n"); return -ENODEV; } @@ -124,10 +124,10 @@ int mcb1700_pwm_setup(void) return ret; } - timer = lpc17_timerinitialize(0); + timer = lpc17_40_timerinitialize(0); if (!timer) { - aerr("ERROR: Failed to get the LPC17XX TIMER lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX TIMER lower half\n"); return -ENODEV; } diff --git a/configs/olimex-lpc1766stk/README.txt b/configs/olimex-lpc1766stk/README.txt index 535bf52d064..6211b609db4 100644 --- a/configs/olimex-lpc1766stk/README.txt +++ b/configs/olimex-lpc1766stk/README.txt @@ -218,7 +218,7 @@ LEDs software is hung, perhaps in an infinite loop, somewhere inside of an interrupt handler. OFF Flashing Ooops! We crashed before finishing initialization (or, perhaps - after initialization, during an interrupt while the LPC17xx was + after initialization, during an interrupt while the LPC17xx/LPC40xx was sleeping -- see below). ON OFF The system has completed initialization, but is apparently not taking @@ -511,41 +511,41 @@ Olimex LPC1766-STK Configuration Options Individual subsystems can be enabled: - CONFIG_LPC17_MAINOSC=y - CONFIG_LPC17_PLL0=y - CONFIG_LPC17_PLL1=n - CONFIG_LPC17_ETHERNET=n - CONFIG_LPC17_USBHOST=n - CONFIG_LPC17_USBOTG=n - CONFIG_LPC17_USBDEV=n - CONFIG_LPC17_UART0=y - CONFIG_LPC17_UART1=n - CONFIG_LPC17_UART2=n - CONFIG_LPC17_UART3=n - CONFIG_LPC17_CAN1=n - CONFIG_LPC17_CAN2=n - CONFIG_LPC17_SPI=n - CONFIG_LPC17_SSP0=n - CONFIG_LPC17_SSP1=n - CONFIG_LPC17_I2C0=n - CONFIG_LPC17_I2C1=n - CONFIG_LPC17_I2S=n - CONFIG_LPC17_TMR0=n - CONFIG_LPC17_TMR1=n - CONFIG_LPC17_TMR2=n - CONFIG_LPC17_TMR3=n - CONFIG_LPC17_RIT=n - CONFIG_LPC17_PWM0=n - CONFIG_LPC17_MCPWM=n - CONFIG_LPC17_QEI=n - CONFIG_LPC17_RTC=n - CONFIG_LPC17_WDT=n - CONFIG_LPC17_ADC=n - CONFIG_LPC17_DAC=n - CONFIG_LPC17_GPDMA=n - CONFIG_LPC17_FLASH=n + CONFIG_LPC17_40_MAINOSC=y + CONFIG_LPC17_40_PLL0=y + CONFIG_LPC17_40_PLL1=n + CONFIG_LPC17_40_ETHERNET=n + CONFIG_LPC17_40_USBHOST=n + CONFIG_LPC17_40_USBOTG=n + CONFIG_LPC17_40_USBDEV=n + CONFIG_LPC17_40_UART0=y + CONFIG_LPC17_40_UART1=n + CONFIG_LPC17_40_UART2=n + CONFIG_LPC17_40_UART3=n + CONFIG_LPC17_40_CAN1=n + CONFIG_LPC17_40_CAN2=n + CONFIG_LPC17_40_SPI=n + CONFIG_LPC17_40_SSP0=n + CONFIG_LPC17_40_SSP1=n + CONFIG_LPC17_40_I2C0=n + CONFIG_LPC17_40_I2C1=n + CONFIG_LPC17_40_I2S=n + CONFIG_LPC17_40_TMR0=n + CONFIG_LPC17_40_TMR1=n + CONFIG_LPC17_40_TMR2=n + CONFIG_LPC17_40_TMR3=n + CONFIG_LPC17_40_RIT=n + CONFIG_LPC17_40_PWM0=n + CONFIG_LPC17_40_MCPWM=n + CONFIG_LPC17_40_QEI=n + CONFIG_LPC17_40_RTC=n + CONFIG_LPC17_40_WDT=n + CONFIG_LPC17_40_ADC=n + CONFIG_LPC17_40_DAC=n + CONFIG_LPC17_40_GPDMA=n + CONFIG_LPC17_40_FLASH=n - LPC17xx specific device driver settings + LPC17xx/LPC40xx specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -558,77 +558,77 @@ Olimex LPC1766-STK Configuration Options CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_UARTn_2STOP - Two stop bits - LPC17xx specific CAN device driver settings. These settings all + LPC17xx/LPC40xx specific CAN device driver settings. These settings all require CONFIG_CAN: CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. - CONFIG_LPC17_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 + CONFIG_LPC17_40_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN1 is defined. - CONFIG_LPC17_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 + CONFIG_LPC17_40_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN2 is defined. - CONFIG_LPC17_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN_TSEG1 - The number of CAN time quanta in segment 1. + CONFIG_LPC17_40_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2. + CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 - LPC17xx specific PHY/Ethernet device driver settings. These setting - also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + LPC17xx/LPC40xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_40_ETHERNET. CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY - CONFIG_LPC17_PHY_AUTONEG - Enable auto-negotion - CONFIG_LPC17_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. - CONFIG_LPC17_PHY_FDUPLEX - Select full (vs. half) duplex + CONFIG_LPC17_40_PHY_AUTONEG - Enable auto-negotion + CONFIG_LPC17_40_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_LPC17_40_PHY_FDUPLEX - Select full (vs. half) duplex - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb - CONFIG_LPC17_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 - CONFIG_LPC17_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 - CONFIG_LPC17_ETH_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_WOL - Enable Wake-up on Lan (not fully implemented). CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. Also needs CONFIG_DEBUG_FEATURES. - CONFIG_LPC17_ETH_HASH - Enable receipt of near-perfect match frames. - CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + CONFIG_LPC17_40_ETH_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_40_MULTICAST - Enable receipt of multicast (and unicast) frames. Automatically set if CONFIG_NET_MCASTGROUP is selected. - LPC17xx USB Device Configuration + LPC17xx/LPC40xx USB Device Configuration - CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT Handle USB Start-Of-Frame events. Enable reading SOF from interrupt handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. - CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT Enable high priority interrupts. I have no idea why you might want to do that - CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. - CONFIG_LPC17_USBDEV_DMA - Enable lpc17xx-specific DMA support - CONFIG_LPC17_USBDEV_NOVBUS + CONFIG_LPC17_40_USBDEV_DMA + Enable lpc17xx/lpc40xx-specific DMA support + CONFIG_LPC17_40_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal - CONFIG_LPC17_USBDEV_NOLED + CONFIG_LPC17_40_USBDEV_NOLED Define if the hardware implementation does not support the LED output - LPC17xx USB Host Configuration - CONFIG_LPC17_OHCIRAM_SIZE + LPC17xx/LPC40xx USB Host Configuration + CONFIG_LPC17_40_OHCIRAM_SIZE Total size of OHCI RAM (in AHB SRAM Bank 1) CONFIG_LP17_USBHOST_NEDS Number of endpoint descriptors CONFIG_LP17_USBHOST_NTDS Number of transfer descriptors - CONFIG_LPC17_USBHOST_TDBUFFERS + CONFIG_LPC17_40_USBHOST_TDBUFFERS Number of transfer descriptor buffers - CONFIG_LPC17_USBHOST_TDBUFSIZE + CONFIG_LPC17_40_USBHOST_TDBUFSIZE Size of one transfer descriptor buffer - CONFIG_LPC17_USBHOST_IOBUFSIZE + CONFIG_LPC17_40_USBHOST_IOBUFSIZE Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. @@ -650,8 +650,8 @@ USB host operations. To make these modifications, do the following: Make the following changes: - System Type -> LPC17xx Peripheral Support - CONFIG_LPC17_USBHOST=y + System Type -> LPC17xx/LPC40xx Peripheral Support + CONFIG_LPC17_40_USBHOST=y Device Drivers-> USB Host Driver Support CONFIG_USBHOST=y @@ -792,7 +792,7 @@ Configuration Sub-Directories nettest: This configuration directory may be used to enable networking using the - LPC17xx's Ethernet controller. It uses apps/examples/nettest to excercise the + LPC17xx/LPC40xx's Ethernet controller. It uses apps/examples/nettest to excercise the TCP/IP network. nsh: @@ -946,7 +946,7 @@ Configuration Sub-Directories configurations here. However, UART1 is also enabled for performing the Zmodem transfers. - CONFIG_LPC17XX_UART1=y + CONFIG_LPC17XX_40XX_UART1=y CONFIG_UART1_ISUART=y CONFIG_UART1_RXBUFSIZE=1024 CONFIG_UART1_TXBUFSIZE=256 @@ -958,7 +958,7 @@ Configuration Sub-Directories 2. Hardware Flow Control In principle, Zmodem transfers could be performed on the any serial - device, including the console device. However, only the LPC17xx + device, including the console device. However, only the LPC17xx/LPC40xx UART1 supports hardware flow control which is required for Zmodem transfers. Also, this configuration permits debug output on the serial console while the transfer is in progress without interfering @@ -968,7 +968,7 @@ Configuration Sub-Directories of data overrun. This should be unnecessary if buffering and hardware flow control are set up correctly. - However, in the LPC17xx serial driver, hardware flow control only + However, in the LPC17xx/LPC40xx serial driver, hardware flow control only protects the hardware RX FIFO: Data will not be lost in the hardware FIFO but can still be lost when it is taken from the FIFO. We can still overflow the serial driver's RX buffer even with hardware flow @@ -1150,7 +1150,7 @@ Configuration Sub-Directories I have verified that with debug off and at lower serial BAUD (2400), the transfers of large files succeed without errors. I do not consider this a "solution" to the problem. I also found that - the LPC17xx hardware flow control causes strange hangs; Zmodem works + the LPC17xx/LPC40xx hardware flow control causes strange hangs; Zmodem works much better with hardware flow control disabled. At this lower BAUD, RX buffer sizes could probably be reduced; Or @@ -1169,5 +1169,5 @@ Configuration Sub-Directories been verified as of this writing). CONCLUSION: You really do need proper hardware flow control to - use zmodem. That is not currently implemented in the LPC17xx + use zmodem. That is not currently implemented in the LPC17xx/LPC40xx family. diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index f779ff9188e..d03bdbb840d 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8111 CONFIG_BUILTIN=y @@ -24,13 +24,13 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=8512 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=7 -CONFIG_LPC17_ETH_NTXDESC=7 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=8512 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=7 +CONFIG_LPC17_40_ETH_NTXDESC=7 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/olimex-lpc1766stk/hidkbd/defconfig b/configs/olimex-lpc1766stk/hidkbd/defconfig index 7cd63887e92..9ff33003fda 100644 --- a/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8111 CONFIG_BUILTIN=y @@ -24,9 +24,9 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_INPUT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBHOST=y -CONFIG_LPC17_USBHOST_TDBUFFERS=3 +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBHOST=y +CONFIG_LPC17_40_USBHOST_TDBUFFERS=3 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index ec6e0a65542..bf3a0dc206c 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y CONFIG_BOARD_LOOPSPERMSEC=8111 @@ -27,8 +27,8 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBHOST=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBHOST=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/olimex-lpc1766stk/include/board.h b/configs/olimex-lpc1766stk/include/board.h index ef1a1701b64..d223137f3db 100644 --- a/configs/olimex-lpc1766stk/include/board.h +++ b/configs/olimex-lpc1766stk/include/board.h @@ -45,7 +45,7 @@ #include -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) # include #endif @@ -53,7 +53,7 @@ * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -69,14 +69,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz */ +#define LPC17_40_CCLK 80000000 /* 80Mhz */ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -95,8 +95,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -107,7 +107,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -124,8 +124,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 #define BOARD_FLASHCFG_VALUE 0x0000303a /* Ethernet configuration */ diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index 1b9148575fe..e761d3eab2f 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -23,12 +23,12 @@ CONFIG_ETH0_PHY_KS8721=y CONFIG_EXAMPLES_NETTEST=y CONFIG_EXAMPLES_NETTEST_NOMAC=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index f10cf27e109..a97bdb7667e 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -28,13 +28,13 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index 258c6cb54e7..05e212d02db 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=8111 @@ -21,8 +21,8 @@ CONFIG_EXAMPLES_THTTPD=y CONFIG_EXAMPLES_THTTPD_NOMAC=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_UART1=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_UART1=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/olimex-lpc1766stk/src/Makefile b/configs/olimex-lpc1766stk/src/Makefile index 5f731acc6eb..87ec324a9df 100644 --- a/configs/olimex-lpc1766stk/src/Makefile +++ b/configs/olimex-lpc1766stk/src/Makefile @@ -36,22 +36,22 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_bringup.c lpc17_leds.c lpc17_ssp.c +CSRCS = lpc17_40_boot.c lpc17_40_bringup.c lpc17_40_leds.c lpc17_40_ssp.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += lpc17_buttons.c +CSRCS += lpc17_40_buttons.c endif ifeq ($(CONFIG_CAN),y) -CSRCS += lpc17_can.c +CSRCS += lpc17_40_can.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/olimex-lpc1766stk/src/lpc1766stk.h b/configs/olimex-lpc1766stk/src/lpc1766stk.h index 83547e91b33..461c75b1f15 100644 --- a/configs/olimex-lpc1766stk/src/lpc1766stk.h +++ b/configs/olimex-lpc1766stk/src/lpc1766stk.h @@ -154,9 +154,9 @@ /* Button IRQ numbers */ -#define LPC1766STK_BUT1_IRQ LPC17_IRQ_P0p23 -#define LPC1766STK_BUT2_IRQ LPC17_IRQ_P2p13 -#define LPC1766STK_WAKEUP_IRQ LPC17_IRQ_P2p12 +#define LPC1766STK_BUT1_IRQ LPC17_40_IRQ_P0p23 +#define LPC1766STK_BUT2_IRQ LPC17_40_IRQ_P2p13 +#define LPC1766STK_WAKEUP_IRQ LPC17_40_IRQ_P2p12 /* Joystick GPIO PIN SIGNAL NAME * -------------------------------- ---- -------------- @@ -182,11 +182,11 @@ /* Joystick IRQ numbers */ -#define LPC1766STK_CENTER_IRQ LPC17_IRQ_P0p5 -#define LPC1766STK_UP_IRQ LPC17_IRQ_P2p0 -#define LPC1766STK_DOWN_IRQ LPC17_IRQ_P2p1 -#define LPC1766STK_LEFT_IRQ LPC17_IRQ_P2p7 -#define LPC1766STK_RIGHT_IRQ LPC17_IRQ_P2p8 +#define LPC1766STK_CENTER_IRQ LPC17_40_IRQ_P0p5 +#define LPC1766STK_UP_IRQ LPC17_40_IRQ_P2p0 +#define LPC1766STK_DOWN_IRQ LPC17_40_IRQ_P2p1 +#define LPC1766STK_LEFT_IRQ LPC17_40_IRQ_P2p7 +#define LPC1766STK_RIGHT_IRQ LPC17_40_IRQ_P2p8 /* Nokia LCD GPIO PIN SIGNAL NAME * -------------------------------- ---- -------------- @@ -251,7 +251,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_bringup + * Name: lpc17_40_bringup * * Description: * Perform architecture-specific initialization @@ -264,7 +264,7 @@ * ************************************************************************************/ -int lpc17_bringup(void); +int lpc17_40_bringup(void); /************************************************************************************ * Name: lpc1766stk_sspdev_initialize diff --git a/configs/olimex-lpc1766stk/src/lpc17_appinit.c b/configs/olimex-lpc1766stk/src/lpc17_40_appinit.c similarity index 98% rename from configs/olimex-lpc1766stk/src/lpc17_appinit.c rename to configs/olimex-lpc1766stk/src/lpc17_40_appinit.c index cd252c741d4..689cad1091f 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_appinit.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/olimex-lpc1766stk/src/lpc17_appinit.c + * config/olimex-lpc1766stk/src/lpc17_40_appinit.c * * Copyright (C) 2010, 2013-2016, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -89,7 +89,7 @@ int board_app_initialize(uintptr_t arg) /* Did we already initialize via board_late_initialize()? */ #ifndef CONFIG_BOARD_LATE_INITIALIZE - return lpc17_bringup(); + return lpc17_40_bringup(); #else return OK; #endif diff --git a/configs/olimex-lpc1766stk/src/lpc17_boot.c b/configs/olimex-lpc1766stk/src/lpc17_40_boot.c similarity index 92% rename from configs/olimex-lpc1766stk/src/lpc17_boot.c rename to configs/olimex-lpc1766stk/src/lpc17_40_boot.c index 0f8e89be511..442323c52d4 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_boot.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/olimex-lpc1766stk/src/lpc17_boot.c + * configs/olimex-lpc1766stk/src/lpc17_40_boot.c * * Copyright (C) 2010, 2012, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_ssp.h" +#include "lpc17_40_ssp.h" #include "lpc1766stk.h" /************************************************************************************ @@ -63,22 +63,22 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the initialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak * function lpc1766stk_sspdev_initialize() has been brought into the link. */ -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) if (lpc1766stk_sspdev_initialize) { lpc1766stk_sspdev_initialize(); @@ -110,6 +110,6 @@ void board_late_initialize(void) { /* Perform board-specific initialization here if so configured */ - (void)lpc17_bringup(); + (void)lpc17_40_bringup(); } #endif diff --git a/configs/olimex-lpc1766stk/src/lpc17_bringup.c b/configs/olimex-lpc1766stk/src/lpc17_40_bringup.c similarity index 94% rename from configs/olimex-lpc1766stk/src/lpc17_bringup.c rename to configs/olimex-lpc1766stk/src/lpc17_40_bringup.c index 635f3515a77..d3e6e9732bd 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_bringup.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/olimex-lpc1766stk/src/lpc17_bringup.c + * config/olimex-lpc1766stk/src/lpc17_40_bringup.c * * Copyright (C) 2010, 2013-2016, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,9 +50,9 @@ #include #include -#include "lpc17_ssp.h" -#include "lpc17_gpio.h" -#include "lpc17_usbhost.h" +#include "lpc17_40_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_usbhost.h" #include "lpc1766stk.h" @@ -93,7 +93,7 @@ /* Can't support MMC/SD is SSP1 is not enabled */ -#ifndef CONFIG_LPC17_SSP1 +#ifndef CONFIG_LPC17_40_SSP1 # undef HAVE_MMCSD #endif @@ -106,18 +106,18 @@ /* USB Host */ #ifdef CONFIG_USBHOST -# ifndef CONFIG_LPC17_USBHOST -# error "CONFIG_LPC17_USBHOST is not selected" +# ifndef CONFIG_LPC17_40_USBHOST +# error "CONFIG_LPC17_40_USBHOST is not selected" # endif #endif -#ifdef CONFIG_LPC17_USBHOST +#ifdef CONFIG_LPC17_40_USBHOST # ifndef CONFIG_USBHOST # warning "CONFIG_USBHOST is not selected" # endif #endif -#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_USBHOST) +#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_40_USBHOST) # undef HAVE_USBHOST #endif @@ -195,11 +195,11 @@ static int nsh_sdinitialize(void) /* Enable power to the SD/MMC via a GPIO. LOW enables SD/MMC. */ - lpc17_gpiowrite(LPC1766STK_MMC_PWR, false); + lpc17_40_gpiowrite(LPC1766STK_MMC_PWR, false); /* Get the SSP port. MMC/SD is on SSP port 1. */ - ssp = lpc17_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); + ssp = lpc17_40_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); if (!ssp) { syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", @@ -232,7 +232,7 @@ static int nsh_sdinitialize(void) /* Disable power to the SD/MMC via a GPIO. HIGH disables SD/MMC. */ errout: - lpc17_gpiowrite(LPC1766STK_MMC_PWR, true); + lpc17_40_gpiowrite(LPC1766STK_MMC_PWR, true); return ret; } #else @@ -314,7 +314,7 @@ static int nsh_usbhostinitialize(void) /* Then get an instance of the USB host interface */ syslog(LOG_INFO, "Initialize USB host\n"); - g_usbconn = lpc17_usbhost_initialize(0); + g_usbconn = lpc17_40_usbhost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -338,7 +338,7 @@ static int nsh_usbhostinitialize(void) ****************************************************************************/ /************************************************************************************ - * Name: lpc17_bringup + * Name: lpc17_40_bringup * * Description: * Perform architecture-specific initialization @@ -351,7 +351,7 @@ static int nsh_usbhostinitialize(void) * ************************************************************************************/ -int lpc17_bringup(void) +int lpc17_40_bringup(void) { int ret; diff --git a/configs/olimex-lpc1766stk/src/lpc17_buttons.c b/configs/olimex-lpc1766stk/src/lpc17_40_buttons.c similarity index 95% rename from configs/olimex-lpc1766stk/src/lpc17_buttons.c rename to configs/olimex-lpc1766stk/src/lpc17_40_buttons.c index 19e5830432a..7b9c91ceae1 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_buttons.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/olimex-lpc1766stk/src/lpc17_buttons.c + * configs/olimex-lpc1766stk/src/lpc17_40_buttons.c * * Copyright (C) 2011, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,7 +48,7 @@ #include -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lpc1766stk.h" #ifdef CONFIG_ARCH_BUTTONS @@ -70,7 +70,7 @@ static const uint16_t g_buttoncfg[NUM_BUTTONS] = LPC1766STK_UP, LPC1766STK_DOWN, LPC1766STK_LEFT, LPC1766STK_RIGHT }; -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) /* This array provides the mapping from button ID numbers to button IRQ * numbers. */ @@ -110,7 +110,7 @@ void board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - lpc17_configgpio(g_buttoncfg[i]); + lpc17_40_configgpio(g_buttoncfg[i]); } } @@ -141,7 +141,7 @@ uint32_t board_buttons(void) { /* A LOW value means that the key is pressed. */ - bool released = lpc17_gpioread(g_buttoncfg[i]); + bool released = lpc17_40_gpioread(g_buttoncfg[i]); /* Accumulate the set of depressed (not released) keys */ @@ -174,7 +174,7 @@ uint32_t board_buttons(void) * ****************************************************************************/ -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { irqstate_t flags; diff --git a/configs/olimex-lpc1766stk/src/lpc17_can.c b/configs/olimex-lpc1766stk/src/lpc17_40_can.c similarity index 89% rename from configs/olimex-lpc1766stk/src/lpc17_can.c rename to configs/olimex-lpc1766stk/src/lpc17_40_can.c index fcc99e54dd4..3d504dbe20b 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_can.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_can.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/solimex-lpc1766stk/src/lpc17_can.c + * configs/solimex-lpc1766stk/src/lpc17_40_can.c * * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,7 +48,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_can.h" +#include "lpc17_40_can.h" #include "lpc1766stk.h" #ifdef CONFIG_CAN @@ -58,16 +58,16 @@ ************************************************************************************/ /* Configuration ********************************************************************/ -#if defined(CONFIG_LPC17_CAN1) && defined(CONFIG_LPC17_CAN2) +#if defined(CONFIG_LPC17_40_CAN1) && defined(CONFIG_LPC17_40_CAN2) # warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_LPC17_CAN2 +# undef CONFIG_LPC17_40_CAN2 #endif -#ifdef CONFIG_LPC17_CAN2 +#ifdef CONFIG_LPC17_40_CAN2 # warning "CAN2 is not connected on the LPC1766-STK" #endif -#ifdef CONFIG_LPC17_CAN1 +#ifdef CONFIG_LPC17_40_CAN1 # define CAN_PORT 1 #else # define CAN_PORT 2 @@ -87,13 +87,13 @@ int lpc1766stk_can_setup(void) { -#if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) +#if defined(CONFIG_LPC17_40_CAN1) || defined(CONFIG_LPC17_40_CAN2) struct can_dev_s *can; int ret; - /* Call lpc17_caninitialize() to get an instance of the CAN interface */ + /* Call lpc17_40_caninitialize() to get an instance of the CAN interface */ - can = lpc17_caninitialize(CAN_PORT); + can = lpc17_40_caninitialize(CAN_PORT); if (can == NULL) { canerr("ERROR: Failed to get CAN interface\n"); diff --git a/configs/olimex-lpc1766stk/src/lpc17_leds.c b/configs/olimex-lpc1766stk/src/lpc17_40_leds.c similarity index 84% rename from configs/olimex-lpc1766stk/src/lpc17_leds.c rename to configs/olimex-lpc1766stk/src/lpc17_40_leds.c index 14914c0d941..e3417a35045 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_leds.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/olimex-lpc1766stk/src/lpc17_leds.c + * configs/olimex-lpc1766stk/src/lpc17_40_leds.c * * Copyright (C) 2010-2011, 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "lpc1766stk.h" @@ -61,7 +61,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) lpc17_dumpgpio(LPC1766STK_LED1, m) +# define led_dumpgpio(m) lpc17_40_dumpgpio(LPC1766STK_LED1, m) #else # define led_dumpgpio(m) #endif @@ -89,15 +89,15 @@ static bool g_uninitialized = true; #ifndef CONFIG_ARCH_LEDS void board_userled_initialize(void) /* Name when invoked externally */ #else -void board_autoled_initialize(void) /* Name when invoked via lpc17_boot.c */ +void board_autoled_initialize(void) /* Name when invoked via lpc17_40_boot.c */ #endif { /* Configure all LED GPIO lines */ led_dumpgpio("board_*led_initialize() Entry)"); - lpc17_configgpio(LPC1766STK_LED1); - lpc17_configgpio(LPC1766STK_LED2); + lpc17_40_configgpio(LPC1766STK_LED1); + lpc17_40_configgpio(LPC1766STK_LED2); led_dumpgpio("board_*led_initialize() Exit"); } @@ -111,11 +111,11 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LED1) { - lpc17_gpiowrite(LPC1766STK_LED1, !ledon); + lpc17_40_gpiowrite(LPC1766STK_LED1, !ledon); } else if (led == BOARD_LED2) { - lpc17_gpiowrite(LPC1766STK_LED2, !ledon); + lpc17_40_gpiowrite(LPC1766STK_LED2, !ledon); } } #endif @@ -127,8 +127,8 @@ void board_userled(int led, bool ledon) #ifndef CONFIG_ARCH_LEDS void board_userled_all(uint8_t ledset) { - lpc17_gpiowrite(LPC1766STK_LED1, (ledset & BOARD_LED1_BIT) == 0); - lpc17_gpiowrite(LPC1766STK_LED2, (ledset & BOARD_LED2_BIT) == 0); + lpc17_40_gpiowrite(LPC1766STK_LED1, (ledset & BOARD_LED1_BIT) == 0); + lpc17_40_gpiowrite(LPC1766STK_LED2, (ledset & BOARD_LED2_BIT) == 0); } #endif @@ -143,22 +143,22 @@ void board_autoled_on(int led) { default: case 0 : /* STARTED, HEAPALLOCATE, IRQSENABLED */ - lpc17_gpiowrite(LPC1766STK_LED1, true); - lpc17_gpiowrite(LPC1766STK_LED2, true); + lpc17_40_gpiowrite(LPC1766STK_LED1, true); + lpc17_40_gpiowrite(LPC1766STK_LED2, true); break; case 1 : /* STACKCREATED */ - lpc17_gpiowrite(LPC1766STK_LED1, false); - lpc17_gpiowrite(LPC1766STK_LED2, true); + lpc17_40_gpiowrite(LPC1766STK_LED1, false); + lpc17_40_gpiowrite(LPC1766STK_LED2, true); g_uninitialized = false; break; case 2 : /* INIRQ, SIGNAL, ASSERTION, PANIC */ - lpc17_gpiowrite(LPC1766STK_LED2, false); + lpc17_40_gpiowrite(LPC1766STK_LED2, false); break; case 3 : /* IDLE */ - lpc17_gpiowrite(LPC1766STK_LED1, true); + lpc17_40_gpiowrite(LPC1766STK_LED1, true); break; } } @@ -176,14 +176,14 @@ void board_autoled_off(int led) default: case 0 : /* STARTED, HEAPALLOCATE, IRQSENABLED */ case 1 : /* STACKCREATED */ - lpc17_gpiowrite(LPC1766STK_LED1, true); + lpc17_40_gpiowrite(LPC1766STK_LED1, true); case 2 : /* INIRQ, SIGNAL, ASSERTION, PANIC */ - lpc17_gpiowrite(LPC1766STK_LED2, true); + lpc17_40_gpiowrite(LPC1766STK_LED2, true); break; case 3 : /* IDLE */ - lpc17_gpiowrite(LPC1766STK_LED1, g_uninitialized); + lpc17_40_gpiowrite(LPC1766STK_LED1, g_uninitialized); break; } } diff --git a/configs/olimex-lpc1766stk/src/lpc17_ssp.c b/configs/olimex-lpc1766stk/src/lpc17_40_ssp.c similarity index 79% rename from configs/olimex-lpc1766stk/src/lpc17_ssp.c rename to configs/olimex-lpc1766stk/src/lpc17_40_ssp.c index 5ef529f2a7b..b99fbad9366 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_ssp.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_ssp.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/olimex-lpc1766stk/src/lpc17_ssp.c + * configs/olimex-lpc1766stk/src/lpc17_40_ssp.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,11 +53,11 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "lpc1766stk.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) /************************************************************************************ * Pre-processor Definitions @@ -66,8 +66,8 @@ #undef HAVE_SPI_CALLBACK #ifdef CONFIG_SPI_CALLBACK -# ifndef CONFIG_LPC17_GPIOIRQ -# warning "CONFIG_LPC17_GPIOIRQ is required to support CONFIG_SPI_CALLBACK" +# ifndef CONFIG_LPC17_40_GPIOIRQ +# warning "CONFIG_LPC17_40_GPIOIRQ is required to support CONFIG_SPI_CALLBACK" # else # define HAVE_SPI_CALLBACK 1 # endif @@ -77,8 +77,8 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_GPIO_INFO -# define ssp_dumpssp0gpio(m) lpc17_dumpgpio(LPC1766STK_LCD_CS, m) -# define ssp_dumpssp1gpio(m) lpc17_dumpgpio(LPC1766STK_MMC_CS, m) +# define ssp_dumpssp0gpio(m) lpc17_40_dumpgpio(LPC1766STK_LCD_CS, m) +# define ssp_dumpssp1gpio(m) lpc17_40_dumpgpio(LPC1766STK_MMC_CS, m) #else # define ssp_dumpssp0gpio(m) # define ssp_dumpssp1gpio(m) @@ -91,7 +91,7 @@ /* This structure describes on media change callback */ #ifdef HAVE_SPI_CALLBACK -struct lpc17_mediachange_s +struct lpc17_40_mediachange_s { spi_mediachange_t callback; /* The media change callback */ FAR void *arg; /* Callback argument */ @@ -105,11 +105,11 @@ struct lpc17_mediachange_s /* Registered media change callback */ #ifdef HAVE_SPI_CALLBACK -#ifdef CONFIG_LPC17_SSP0 -static struct lpc17_mediachange_s g_ssp0callback; +#ifdef CONFIG_LPC17_40_SSP0 +static struct lpc17_40_mediachange_s g_ssp0callback; #endif -#ifdef CONFIG_LPC17_SSP1 -static struct lpc17_mediachange_s g_ssp1callback; +#ifdef CONFIG_LPC17_40_SSP1 +static struct lpc17_40_mediachange_s g_ssp1callback; #endif #endif @@ -166,7 +166,7 @@ static void ssp_cdirqsetup(int irq, xcpt_t irqhandler) ************************************************************************************/ #if 0 /* ifdef HAVE_SPI_CALLBACK */ -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 static int ssp0_cdinterrupt(int irq, FAR void *context) { /* Invoke the media change callback */ @@ -179,7 +179,7 @@ static int ssp0_cdinterrupt(int irq, FAR void *context) } #endif -#ifdef CONFIG_LPC17_SSP1 +#ifdef CONFIG_LPC17_40_SSP1 static int ssp1_cdinterrupt(int irq, FAR void *context) { /* Invoke the media change callback */ @@ -209,24 +209,24 @@ void weak_function lpc1766stk_sspdev_initialize(void) { /* Configure the SSP0 chip select GPIOs. Only the Nokia LCD is connected to SSP0 */ -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 ssp_dumpssp0gpio("BEFORE SSP0 Initialization"); - lpc17_configgpio(LPC1766STK_LCD_CS); + lpc17_40_configgpio(LPC1766STK_LCD_CS); ssp_dumpssp0gpio("AFTER SSP0 Initialization"); #endif /* Configure SSP1 chip select GPIOs. Only the SD/MMC card slot is connected to SSP1 */ -#ifdef CONFIG_LPC17_SSP1 +#ifdef CONFIG_LPC17_40_SSP1 ssp_dumpssp0gpio("BEFORE SSP1 Initialization"); - lpc17_configgpio(LPC1766STK_MMC_CS); + lpc17_40_configgpio(LPC1766STK_MMC_CS); /* Also configure the SD/MMC power GPIO (but leave power off). This really has * nothing to do with SSP, but does belong with other SD/MMC GPIO configuration * settings. */ - lpc17_configgpio(LPC1766STK_MMC_PWR); + lpc17_40_configgpio(LPC1766STK_MMC_PWR); ssp_dumpssp0gpio("AFTER SSP1 Initialization"); #endif @@ -238,66 +238,66 @@ void weak_function lpc1766stk_sspdev_initialize(void) } /************************************************************************************ - * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * Name: lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * * Description: - * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * The external functions, lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc17_sspbus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * 2. Provide lpc17_40_ssp0/ssp1select() and lpc17_40_ssp0/ssp1status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc17_sspbus_initialize() in your low level application + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); if (devid == SPIDEV_DISPLAY(0)) { /* Assert/de-assert the CS pin to the card */ - ssp_dumpssp0gpio("lpc17_ssp0select() Entry"); - lpc17_gpiowrite(LPC1766STK_LCD_CS, !selected); - ssp_dumpssp0gpio("lpc17_ssp0select() Exit"); + ssp_dumpssp0gpio("lpc17_40_ssp0select() Entry"); + lpc17_40_gpiowrite(LPC1766STK_LCD_CS, !selected); + ssp_dumpssp0gpio("lpc17_40_ssp0select() Exit"); } } -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning nothing\n"); return 0; } #endif -#ifdef CONFIG_LPC17_SSP1 -void lpc17_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); if (devid == SPIDEV_MMCSD(0)) { /* Assert/de-assert the CS pin to the card */ - ssp_dumpssp1gpio("lpc17_ssp1select() Entry"); - lpc17_gpiowrite(LPC1766STK_MMC_CS, !selected); - ssp_dumpssp1gpio("lpc17_ssp1select() Exit"); + ssp_dumpssp1gpio("lpc17_40_ssp1select() Entry"); + lpc17_40_gpiowrite(LPC1766STK_MMC_CS, !selected); + ssp_dumpssp1gpio("lpc17_40_ssp1select() Exit"); } } -uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; @@ -305,7 +305,7 @@ uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif /************************************************************************************ - * Name: lpc17_ssp0/1register + * Name: lpc17_40_ssp0/1register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -325,12 +325,12 @@ uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) ************************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 /* If there were any CD detect pins on the LPC1766-STK, this is how the * would be configured. */ -int lpc17_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) +int lpc17_40_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) { /* Save the callback information */ @@ -346,8 +346,8 @@ int lpc17_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, vo } #endif -#ifdef CONFIG_LPC17_SSP1 -int lpc17_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) +#ifdef CONFIG_LPC17_40_SSP1 +int lpc17_40_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) { /* Save the callback information */ @@ -364,4 +364,4 @@ int lpc17_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, vo #endif #endif -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 */ diff --git a/configs/olimex-lpc1766stk/src/lpc17_usbmsc.c b/configs/olimex-lpc1766stk/src/lpc17_40_usbmsc.c similarity index 80% rename from configs/olimex-lpc1766stk/src/lpc17_usbmsc.c rename to configs/olimex-lpc1766stk/src/lpc17_40_usbmsc.c index 7fe2266714f..115592ae1d1 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_usbmsc.c +++ b/configs/olimex-lpc1766stk/src/lpc17_40_usbmsc.c @@ -1,10 +1,10 @@ /**************************************************************************** - * configs/olimex-lpc1766stk/src/lpc17_usbmsc.c + * configs/olimex-lpc1766stk/src/lpc17_40_usbmsc.c * * Copyright (C) 2010, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Configure and register the LPC17xx MMC/SD SPI block driver. + * Configure and register the LPC17xx/LPC40xx MMC/SD SPI block driver. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -49,8 +49,8 @@ #include #include -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "lpc1766stk.h" /**************************************************************************** @@ -66,13 +66,13 @@ /* PORT and SLOT number probably depend on the board configuration */ #ifdef CONFIG_ARCH_BOARD_LPC1766STK -# undef LPC17XX_MMCSDSPIPORTNO -# define LPC17XX_MMCSDSPIPORTNO 1 -# undef LPC17XX_MMCSDSLOTNO -# define LPC17XX_MMCSDSLOTNO 0 +# undef LPC17XX_40XX_MMCSDSPIPORTNO +# define LPC17XX_40XX_MMCSDSPIPORTNO 1 +# undef LPC17XX_40XX_MMCSDSLOTNO +# define LPC17XX_40XX_MMCSDSLOTNO 0 #else - /* Add configuration for new LPC17xx boards here */ -# error "Unrecognized LPC17xx board" + /* Add configuration for new LPC17xx/LPC40xx boards here */ +# error "Unrecognized LPC17xx/LPC40xx board" #endif /**************************************************************************** @@ -94,48 +94,48 @@ int board_usbmsc_initialize(int port) /* Enable power to the SD/MMC via a GPIO. LOW enables SD/MMC. */ - lpc17_gpiowrite(LPC1766STK_MMC_PWR, false); + lpc17_40_gpiowrite(LPC1766STK_MMC_PWR, false); /* Get the SPI port */ syslog(LOG_INFO, "Initializing SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); - spi = lpc17_sspbus_initialize(LPC17XX_MMCSDSPIPORTNO); + spi = lpc17_40_sspbus_initialize(LPC17XX_40XX_MMCSDSPIPORTNO); if (!spi) { syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); ret = -ENODEV; goto errout; } syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); /* Bind the SPI port to the slot */ syslog(LOG_INFO, "Binding SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, - LPC17XX_MMCSDSLOTNO, spi); + LPC17XX_40XX_MMCSDSLOTNO, spi); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO, ret); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO, ret); goto errout; } syslog(LOG_INFO, "Successfully bound SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); return OK; /* Disable power to the SD/MMC via a GPIO. HIGH disables SD/MMC. */ errout: - lpc17_gpiowrite(LPC1766STK_MMC_PWR, true); + lpc17_40_gpiowrite(LPC1766STK_MMC_PWR, true); return ret; } diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index 4cd6fb0f2a6..dbd894edea5 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y CONFIG_BOARD_LOOPSPERMSEC=8111 @@ -26,10 +26,10 @@ CONFIG_FS_ROMFS=y CONFIG_FS_UNIONFS=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=15776 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=15776 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index 72cde2bc066..ece4a5f6feb 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=8111 @@ -22,10 +22,10 @@ CONFIG_EXAMPLES_THTTPD=y CONFIG_EXAMPLES_THTTPD_NOMAC=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=15776 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=15776 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index 8b78c29702f..a9ec4a034e5 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -13,16 +13,16 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=8111 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBDEV=y -CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0 +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBDEV=y +CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS=0 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 8d243f95d5c..84785ffbb88 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -18,9 +18,9 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXAMPLES_USBSERIAL=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBDEV=y -CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0 +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBDEV=y +CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS=0 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index ce5bffe5360..b37a995b202 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-lpc1766stk" CONFIG_ARCH_BOARD_LPC1766STK=y CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -26,14 +26,14 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SSP1=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_UART1=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SSP1=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_UART1=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/olimex-stm32-e407/README.txt b/configs/olimex-stm32-e407/README.txt index ccb3cbcf985..e85bbe216dc 100644 --- a/configs/olimex-stm32-e407/README.txt +++ b/configs/olimex-stm32-e407/README.txt @@ -1,6 +1,7 @@ README ====== -The Olimex STM32-E407 configuration is based on the configuration olimex-stm32-h407 and stm32f4discovery. +The Olimex STM32-E407 configuration is based on the configuration +olimex-stm32-h407 and stm32f4discovery. Configurations ============== @@ -10,9 +11,11 @@ Configurations Each Olimex-STM32-E407 configuration is maintained in a sub-directory and can be selected as follow: - tools/configure.sh olimex-stm32-e407/ + tools/configure.sh [OPTIONS] olimex-stm32-e407/ - Where is one of the following: + Typical options include -l for a Linux host platform or -c for Cygwin + host platform. See 'tools/configure.sh -h' for other options. And + is one of the sub-directories listed below. Compile Firmware ---------------- @@ -26,8 +29,7 @@ Configurations nuttx.hex nuttx.bin - You can return more kind of files by setting on menuconfig. - + You can return more kinds of files by setting on menuconfig. Flashing the Board ----------------- @@ -58,19 +60,59 @@ Configurations Configures the NuttShell (nsh) located at examples/nsh. This configuration is focused on network testing. - BMP180: + bmp180: ------ - This a configuration example for the BMP180 barometer sensor. This - sensor works with I2C, you need to do the next connections: + This is a configuration example for the BMP180 barometer sensor. This + sensor works with I2C, you need to do the next connections: - BMP180 VIN -> Board 3.3V - BMP180 GND -> Board GND - BMP180 SCL -> Board PB6 (Arduino header D1) - BMP180 SDA -> Board PB7 (Arduino header D0) + BMP180 VIN -> Board 3.3V + BMP180 GND -> Board GND + BMP180 SCL -> Board PB6 (Arduino header D1) + BMP180 SDA -> Board PB7 (Arduino header D0) + + This example is configured to work with the USBNSH instead of UART NSH, so + the console will be shown over the USB_OTG1 connector. + + On the console, type "ls /dev " and if the registration process goes fine, + you should see a device called "press0". Now execute the app + BMP180 to see the ambient pressure value. + + dac: + --- + This is a configuration example to use the DAC1 of the board.The DAC1 is attached + to the PA4 pin (Arduino header D10). + + This example is configured to work with the USBNSH instead of UART NSH, so + the console will be shown over the USB_OTG1 connector. + + On the console, type "ls /dev " and if the registration process goes fine, + you should see a device called "dac0". Now execute the app + dac put a value at the output. + + ina219: + ------ + This is a configuration example for the INA219 DC current sensor. This + sensor works with I2C, you need to do the next connections: + + INA219 VIN -> Board 3.3V + INA219 GND -> Board GND + INA219 SCL -> Board PB6 (Arduino header D1) + INA219 SDA -> Board PB7 (Arduino header D0) + + This example is configured to work with the USBNSH instead of UART NSH, so + the console will be shown over the USB_OTG1 connector. + + On the console, type "ls /dev " and if the registration process goes fine, + you should see a device called "ina219". Now execute the app + ina219 to see the ambient pressure value. + + timer: + ----- + This configuration set the proper configuration to use the timer1 of the board. + This example is configured to work with the USBNSH instead of UART NSH, so + the console will be shown over the USB_OTG1 connector. + + On the console, type "ls /dev " and if the registration process goes fine, + you should see a device called "timer1". - This example is configured to work with the USBNSH instead of UART NSH, so - the console will be shown over the USB_OTG1 connector. - On the console, type "ls /dev " and if the registration process goes fine, - you should see a device called "press0". Now execute the app - BMP180 to see the ambient pressure value. diff --git a/configs/olimex-stm32-e407/dac/defconfig b/configs/olimex-stm32-e407/dac/defconfig new file mode 100644 index 00000000000..77f614d02cd --- /dev/null +++ b/configs/olimex-stm32-e407/dac/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DAC=y +CONFIG_EXAMPLES_DAC=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_BOARDCTL=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/configs/olimex-stm32-e407/ina219/defconfig b/configs/olimex-stm32-e407/ina219/defconfig new file mode 100644 index 00000000000..5a4d22ce25f --- /dev/null +++ b/configs/olimex-stm32-e407/ina219/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_INA219=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SENSORS=y +CONFIG_SENSORS_INA219=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_USBDEV=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/olimex-stm32-e407/src/Makefile b/configs/olimex-stm32-e407/src/Makefile index 44defad9d74..f9342efdc5d 100644 --- a/configs/olimex-stm32-e407/src/Makefile +++ b/configs/olimex-stm32-e407/src/Makefile @@ -84,5 +84,17 @@ ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += stm32_bmp180.c endif +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_SENSORS_INA219),y) +CSRCS += stm32_ina219.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h index af7ef82633e..05b77c18c21 100644 --- a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -233,13 +233,13 @@ int stm32_bringup(void); void weak_function stm32_usbinitialize(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_ADC int stm32_adc_setup(void); @@ -269,7 +269,7 @@ int stm32_sdio_initialize(void); int stm32_can_setup(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_bmp180initialize * * Description: @@ -281,11 +281,68 @@ int stm32_can_setup(void); * Returned Value: * Zero (OK) on success; a negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_BMP180) int stm32_bmp180initialize(FAR const char *devpath); #endif +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC0 of the microcontroller. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_DAC) +int stm32_dac_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_ina219initialize + * + * Description: + * Initialize and register the INA219 voltage/current sensor. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/ina219" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_INA219) +int stm32_ina219initialize(FAR const char *devpath); +#endif + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int stm32_timer_driver_setup(FAR const char *devpath, int timer); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_E407_SRC_INTERNAL_H */ diff --git a/configs/olimex-stm32-e407/src/stm32_adc.c b/configs/olimex-stm32-e407/src/stm32_adc.c index f1e09265fac..4d70ee91805 100644 --- a/configs/olimex-stm32-e407/src/stm32_adc.c +++ b/configs/olimex-stm32-e407/src/stm32_adc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * configs/olimex-stm32-e407/src/stm32_adc.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -52,11 +52,12 @@ #ifdef CONFIG_ADC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ -/* Configuration ********************************************************************/ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 @@ -80,9 +81,10 @@ #define ADC1_NCHANNELS 1//14 -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ + /* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 * ADC123_IN10 */ @@ -105,21 +107,17 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * - ************************************************************************************/ + ****************************************************************************/ int stm32_adc_setup(void) { @@ -171,3 +169,4 @@ int stm32_adc_setup(void) #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ + diff --git a/configs/olimex-stm32-e407/src/stm32_bmp180.c b/configs/olimex-stm32-e407/src/stm32_bmp180.c index e4bc6d55c49..b3d5c30c2ec 100644 --- a/configs/olimex-stm32-e407/src/stm32_bmp180.c +++ b/configs/olimex-stm32-e407/src/stm32_bmp180.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * configs/olimex-stm32-e407/src/stm32_bmp180.c * * Copyright (C) 2019 Acutronics Robotics. All rights reserved. @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -52,17 +52,17 @@ #if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_BMP180) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define BMP180_I2C_PORTNO 1 /* On I2C1 */ -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_bmp180initialize * * Description: @@ -74,7 +74,7 @@ * Returned Value: * Zero (OK) on success; a negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ int stm32_bmp180initialize(FAR const char *devpath) { @@ -104,3 +104,4 @@ int stm32_bmp180initialize(FAR const char *devpath) } #endif /* CONFIG_I2C && CONFIG_SENSORS_BMP180 && CONFIG_STM32_I2C1 */ + diff --git a/configs/olimex-stm32-e407/src/stm32_bringup.c b/configs/olimex-stm32-e407/src/stm32_bringup.c index 2f9becd43a9..f79ccb366a1 100644 --- a/configs/olimex-stm32-e407/src/stm32_bringup.c +++ b/configs/olimex-stm32-e407/src/stm32_bringup.c @@ -229,6 +229,40 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_INA219 + /* Configure and initialize the INA219 sensor */ + + ret = stm32_ina219initialize("/dev/ina219"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ina219initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_TIMER) + /*Initialize the timer, at this moment it's only Timer 1,2,3*/ + + #if defined(CONFIG_STM32_TIM1) + stm32_timer_driver_setup("/dev/timer1", 1); + #endif + #if defined(CONFIG_STM32_TIM2) + stm32_timer_driver_setup("/dev/timer2", 2); + #endif + #if defined(CONFIG_STM32_TIM3) + stm32_timer_driver_setup("/dev/timer3", 3); + #endif +#endif + UNUSED(ret); return OK; } diff --git a/configs/olimex-stm32-e407/src/stm32_can.c b/configs/olimex-stm32-e407/src/stm32_can.c index f4e941bf5a1..7e2c871cc45 100644 --- a/configs/olimex-stm32-e407/src/stm32_can.c +++ b/configs/olimex-stm32-e407/src/stm32_can.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * configs/olimex-stm32-405/src/stm32_can.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -51,10 +51,11 @@ #ifdef CONFIG_CAN -/************************************************************************************ +/***************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) # warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." @@ -67,9 +68,9 @@ # define CAN_PORT 2 #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: stm32_can_setup diff --git a/configs/olimex-stm32-e407/src/stm32_dac.c b/configs/olimex-stm32-e407/src/stm32_dac.c new file mode 100644 index 00000000000..fc801a0f501 --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_dac.c @@ -0,0 +1,111 @@ +/***************************************************************************** + * configs/olimex-stm32-e407/src/stm32_dac.c + * + * Copyright (C) 2019 Acutronics Robotics All rights reserved. + * Authors: Acutronics Robotics (Juan Flores) + * Base on the work of: Juha Niskanen + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "olimex-stm32-e407.h" + +#include + +#if defined(CONFIG_DAC) + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static struct dac_dev_s *g_dac; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + + /************************************************************************************ + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC0 of the microcontroller. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ************************************************************************************/ + +int stm32_dac_setup(void) +{ + static bool initialized = false; + + if (!initialized) + { + + int ret; + + g_dac = stm32_dacinitialize(1); + if (g_dac == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif + diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.h b/configs/olimex-stm32-e407/src/stm32_ina219.c similarity index 65% rename from arch/arm/src/lpc11xx/lpc11_i2c.h rename to configs/olimex-stm32-e407/src/stm32_ina219.c index 27a490b20ef..b900c4650e3 100644 --- a/arch/arm/src/lpc11xx/lpc11_i2c.h +++ b/configs/olimex-stm32-e407/src/stm32_ina219.c @@ -1,8 +1,9 @@ /**************************************************************************** - * arch/arm/src/lpc11xx/lpc11_i2c.h + * configs/olimex-stm32-e407/src/stm32_ina219.c + * + * Copyright (C) 2018 Erle Robotics (Juan Flores Muñoz). All rights reserved. + * Author: Erle Robotics (Juan Flores Muñoz) * - * Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,55 +34,74 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H - /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include "hardware/lpc11_i2c.h" + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_i2c.h" +#include "olimex-stm32-e407.h" + +#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_INA219) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INA219_I2C_PORTNO 1 /* On I2C1 */ /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: lpc11_i2cbus_initialize + * Name: stm32_ina219initialize * * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. + * Initialize and register the INA219 voltage/current sensor. * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/ina219" * * Returned Value: - * Valid I2C device structure reference on succcess; a NULL on failure + * Zero (OK) on success; a negated errno value on failure. * ****************************************************************************/ -FAR struct i2c_master_s *lpc11_i2cbus_initialize(int port); +int stm32_ina219initialize(FAR const char *devpath) +{ + FAR struct i2c_master_s *i2c; + int ret; -/**************************************************************************** - * Name: lpc11_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the lpc11_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ + sninfo("Initializing INA219!\n"); -int lpc11_i2cbus_uninitialize(FAR struct i2c_master_s *dev); + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(INA219_I2C_PORTNO); + + if (!i2c) + { + return -ENODEV; + } + + /* Then register the sensor */ + + ret = ina219_register(devpath, i2c,0x40,100000,0x00); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Error registering hih6130\n"); + } + + return ret; +} + +#endif /* CONFIG_I2C && CONFIG_SENSORS_INA219 */ -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_start.h b/configs/olimex-stm32-e407/src/stm32_timer.c similarity index 69% rename from arch/arm/src/lpc11xx/lpc11_start.h rename to configs/olimex-stm32-e407/src/stm32_timer.c index ebace6f72c8..3392abe2a17 100644 --- a/arch/arm/src/lpc11xx/lpc11_start.h +++ b/configs/olimex-stm32-e407/src/stm32_timer.c @@ -1,8 +1,9 @@ -/************************************************************************************ - * arch/arm/src/lpc11xx/lpc11_start.h +/**************************************************************************** + * config/olimex-stm32-e407/src/stm32_timer.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Modified by: Acutronics Robotics (Juan Flores) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,32 +32,47 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_START_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_START_H - -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include +#include -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ +#include -/************************************************************************************ - * Name: lpc11_boardinitialize +#include "stm32_tim.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup * * Description: - * All LPC11xx architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * Configure the timer driver. * - ************************************************************************************/ + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ -void lpc11_boardinitialize(void); +int stm32_timer_driver_setup(FAR const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_START_H */ diff --git a/configs/olimex-stm32-e407/src/stm32_usb.c b/configs/olimex-stm32-e407/src/stm32_usb.c index 5e28e17faa5..7bb0c441605 100644 --- a/configs/olimex-stm32-e407/src/stm32_usb.c +++ b/configs/olimex-stm32-e407/src/stm32_usb.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * configs/stm32f4discovery/src/stm32_usb.c * * Copyright (C) 2012-2013, 2015-2017 Gregory Nutt. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -59,9 +59,9 @@ #ifdef CONFIG_STM32_OTGFS -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 @@ -78,25 +78,25 @@ # define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 #endif -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST static struct usbhost_connection_s *g_usbconn; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: usbhost_waiter * * Description: * Wait for USB devices to be connected. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST static int usbhost_waiter(int argc, char *argv[]) @@ -127,18 +127,18 @@ static int usbhost_waiter(int argc, char *argv[]) } #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup USB-related - * GPIO pins for the STM32F4Discovery board. + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. * - ************************************************************************************/ + ****************************************************************************/ void stm32_usbinitialize(void) { @@ -153,15 +153,15 @@ void stm32_usbinitialize(void) #endif } -/*********************************************************************************** +/*************************************************************************** * Name: stm32_usbhost_initialize * * Description: - * Called at application startup time to initialize the USB host functionality. - * This function will start a thread that will monitor for device - *nnnn connection/disconnection events. + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor + * for device connection/disconnection events. * - ***********************************************************************************/ + ***************************************************************************/ #ifdef CONFIG_USBHOST int stm32_usbhost_initialize(void) @@ -248,31 +248,34 @@ int stm32_usbhost_initialize(void) } #endif -/*********************************************************************************** +/**************************************************************************** * Name: stm32_usbhost_vbusdrive * * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided be - * each platform that implements the STM32 OTG FS host interface + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface * - * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump - * or, if 5 V are available on the application board, a basic power switch, must - * be added externally to drive the 5 V VBUS line. The external charge pump can - * be driven by any GPIO output. When the application decides to power on VBUS - * using the chosen GPIO, it must also set the port power bit in the host port - * control and status register (PPWR bit in OTG_FS_HPRT). + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). * - * "The application uses this field to control power to this port, and the core - * clears this bit on an overcurrent condition." + * "The application uses this field to control power to this port, andi + * the core clears this bit on an overcurrent condition." * * Input Parameters: - * iface - For future growth to handle multiple USB host interface. Should be zero. + * iface - For future growth to handle multiple USB host interface. + * Should be zero. * enable - true: enable VBUS power; false: disable VBUS power * * Returned Value: * None * - ***********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST void stm32_usbhost_vbusdrive(int iface, bool enable) @@ -294,22 +297,22 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) } #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_setup_overcurrent * * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition is - * detected. + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. * * Input Parameters: * handler - New overcurrent interrupt handler * arg - The argument provided for the interrupt handler * * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is returned - * to indicate the nature of the failure. + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST int stm32_setup_overcurrent(xcpt_t handler, void *arg) @@ -318,16 +321,16 @@ int stm32_setup_overcurrent(xcpt_t handler, void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBDEV void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) @@ -337,3 +340,4 @@ void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) #endif #endif /* CONFIG_STM32_OTGFS */ + diff --git a/configs/olimex-stm32-e407/timer/defconfig b/configs/olimex-stm32-e407/timer/defconfig new file mode 100644 index 00000000000..ab7f171baba --- /dev/null +++ b/configs/olimex-stm32-e407/timer/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_BOARDCTL=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TIMER=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/configs/open1788/README.txt b/configs/open1788/README.txt index 72cf09c1bd6..af9adbaf728 100644 --- a/configs/open1788/README.txt +++ b/configs/open1788/README.txt @@ -75,8 +75,8 @@ Serial Console serial console by changing the configuration as follows: System Type: - CONFIG_LPC17_UART0=n : Disable UART0 if it is no longer used - CONFIG_LPC17_UART1=y : Enable UART1 + CONFIG_LPC17_40_UART0=n : Disable UART0 if it is no longer used + CONFIG_LPC17_40_UART1=y : Enable UART1 Drivers: CONFIG_UART1_SERIAL_CONSOLE=y : Setup up the UART1 configuration @@ -141,7 +141,7 @@ Using OpenOCD with the Olimex ARM-USB-OCD It just sets up a few parameters then sources lpc17xx.cfg /usr/local/share/openocd/scripts/target/lpc17xx.cfg - This is the generic LPC configuration for the LPC17xx + This is the generic LPC configuration for the LPC17xx/LPC40xx family. It is included by lpc1788.cfg. NOTE: These files could also be located under /usr/share in some @@ -321,9 +321,9 @@ Configuration Directories 2. This configuration has DMA-based SD card support enabled by default. That support can be disabled as follow: - CONFIG_LPC17_GPDMA=n : No DMA + CONFIG_LPC17_40_GPDMA=n : No DMA CONFIG_ARCH_DMA=n - CONFIG_LPC17_SDCARD=n : No SD card driver + CONFIG_LPC17_40_SDCARD=n : No SD card driver CONFIG_SDIO_DMA=n : No SD card DMA CONFIG_MMCSD=n : No MMC/SD driver support CONFIG_FS_FAT=n : No FAT file system support @@ -425,9 +425,9 @@ Configuration Directories 3. This configuration has DMA-based SD card support enabled by default. That support can be disabled as follow: - CONFIG_LPC17_GPDMA=n : No DMA + CONFIG_LPC17_40_GPDMA=n : No DMA CONFIG_ARCH_DMA=n - CONFIG_LPC17_SDCARD=n : No SD card driver + CONFIG_LPC17_40_SDCARD=n : No SD card driver CONFIG_SDIO_DMA=n : No SD card DMA CONFIG_MMCSD=n : No MMC/SD driver support CONFIG_FS_FAT=n : No FAT file system support @@ -435,9 +435,9 @@ Configuration Directories 4. This configuration has been used for verifying SDRAM by modifying the configuration in the following ways: - CONFIG_LPC17_EMC=y : Enable the EMC - CONFIG_LPC17_EXTDRAM=y : Configure external DRAM - CONFIG_LPC17_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB + CONFIG_LPC17_40_EMC=y : Enable the EMC + CONFIG_LPC17_40_EXTDRAM=y : Configure external DRAM + CONFIG_LPC17_40_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB CONFIG_SYSTEM_RAMTEST=y : Enable the RAM test built-in In this configuration, the SDRAM is not added to heap and so is @@ -465,8 +465,8 @@ Configuration Directories CONFIG_SPI_EXCHANGE=n : exchange() method is not supported System Type: - CONFIG_LPC17_GPIOIRQ=y : GPIO interrupt support - CONFIG_LPC17_SSP1=y : Enable support for SSP1 + CONFIG_LPC17_40_GPIOIRQ=y : GPIO interrupt support + CONFIG_LPC17_40_SSP1=y : Enable support for SSP1 Library Support: CONFIG_SCHED_WORKQUEUE=y : Work queue support required @@ -492,8 +492,8 @@ Configuration Directories CONFIG_MMCSD=n : No MMC/SD driver support System Type: - CONFIG_LPC17_GPDMA=n : No DMA - CONFIG_LPC17_SDCARD=n : No SD card driver + CONFIG_LPC17_40_GPDMA=n : No DMA + CONFIG_LPC17_40_SDCARD=n : No SD card driver CONFIG_SDIO_DMA=n : No SD card DMA CONFIG_ARCH_DMA=n diff --git a/configs/open1788/fb/defconfig b/configs/open1788/fb/defconfig index 7fb149593c9..35aeec90db7 100644 --- a/configs/open1788/fb/defconfig +++ b/configs/open1788/fb/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y CONFIG_BOARD_LATE_INITIALIZE=y @@ -20,12 +20,12 @@ CONFIG_DEV_LOOP=y CONFIG_DRIVERS_VIDEO=y CONFIG_EXAMPLES_FB=y CONFIG_HOST_WINDOWS=y -CONFIG_LPC17_EXTDRAM=y -CONFIG_LPC17_EXTDRAMSIZE=67108864 -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_LCD=y -CONFIG_LPC17_SDCARD=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EXTDRAM=y +CONFIG_LPC17_40_EXTDRAMSIZE=67108864 +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_LCD=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/include/board.h b/configs/open1788/include/board.h index 86394b1bff5..db99c6f3792 100644 --- a/configs/open1788/include/board.h +++ b/configs/open1788/include/board.h @@ -45,7 +45,7 @@ #include -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) # include #endif @@ -53,7 +53,7 @@ * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -70,9 +70,9 @@ * CCLCK = 120MHz -> CCLK divider = 1 */ -#define LPC17_CCLK 120000000 /* 120Mhz */ -#define BOARD_PCLKDIV 2 /* Peripheral clock = LPC17_CCLK/2 */ -#define BOARD_PCLK_FREQUENCY (LPC17_CCLK / BOARD_PCLKDIV) +#define LPC17_40_CCLK 120000000 /* 120Mhz */ +#define BOARD_PCLKDIV 2 /* Peripheral clock = LPC17_40_CCLK/2 */ +#define BOARD_PCLK_FREQUENCY (LPC17_40_CCLK / BOARD_PCLKDIV) /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. @@ -81,8 +81,8 @@ * be set in the BOARD_SCS_VALUE. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -101,8 +101,8 @@ * PLL0CLK = (M * SYSCLK) = 120MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 10 @@ -113,14 +113,14 @@ /* PLL1 : PLL1 is used to generate clock for the USB */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 4 #define BOARD_PLL1CFG_PSEL 2 #define BOARD_PLL1CFG_VALUE \ (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ ((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) -#ifdef CONFIG_LPC17_EMC +#ifdef CONFIG_LPC17_40_EMC /* EMC clock selection. * * The EMC clock should not be driven above 80MHz. As a result the EMC @@ -129,10 +129,10 @@ # define BOARD_EMCCLKSEL_DIVIDER 2 # define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV2 -# define LPC17_EMCCLK (LPC17_CCLK / BOARD_EMCCLKSEL_DIVIDER) +# define LPC17_40_EMCCLK (LPC17_40_CCLK / BOARD_EMCCLKSEL_DIVIDER) #endif -#if defined(CONFIG_LPC17_USBHOST) || (CONFIG_LPC17_USBDEV) +#if defined(CONFIG_LPC17_40_USBHOST) || (CONFIG_LPC17_40_USBDEV) /* USB divider. The output of the PLL is used as the USB clock * * USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz @@ -145,8 +145,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 /* Flash access use 6 CPU clocks - Safe for any allowed conditions */ @@ -156,7 +156,7 @@ #define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20 -#ifdef CONFIG_LPC17_SDCARD +#ifdef CONFIG_LPC17_40_SDCARD /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. @@ -200,8 +200,8 @@ * Needed for NAND and SDRAM: {17,1,2,1} */ -#ifdef CONFIG_LPC17_EMC -#if defined(CONFIG_LPC17_EXTNAND) || defined(CONFIG_LPC17_EXTDRAM) +#ifdef CONFIG_LPC17_40_EMC +#if defined(CONFIG_LPC17_40_EXTNAND) || defined(CONFIG_LPC17_40_EXTDRAM) # define BOARD_CMDDLY 17 # define BOARD_FBCLKDLY 17 # define BOARD_CLKOUT0DLY 1 diff --git a/configs/open1788/kernel/Makefile b/configs/open1788/kernel/Makefile index b10b3a455d7..e48d10cf558 100644 --- a/configs/open1788/kernel/Makefile +++ b/configs/open1788/kernel/Makefile @@ -71,7 +71,7 @@ USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" # Source files -CSRCS = lpc17_userspace.c +CSRCS = lpc17_40_userspace.c COBJS = $(CSRCS:.c=$(OBJEXT)) OBJS = $(COBJS) diff --git a/configs/open1788/kernel/lpc17_userspace.c b/configs/open1788/kernel/lpc17_40_userspace.c similarity index 99% rename from configs/open1788/kernel/lpc17_userspace.c rename to configs/open1788/kernel/lpc17_40_userspace.c index b108b824ca4..e9aa7c37bc1 100644 --- a/configs/open1788/kernel/lpc17_userspace.c +++ b/configs/open1788/kernel/lpc17_40_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/open1788/kernel/lpc17_userspace.c + * configs/open1788/kernel/lpc17_40_userspace.c * * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index b675ffc1ac3..d01b03b2132 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -5,7 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_LPC17_EMC is not set +# CONFIG_LPC17_40_EMC is not set # CONFIG_NSH_CMDPARMS is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set CONFIG_ARCH="arm" @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -28,9 +28,9 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_SDCARD=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/knxterm/defconfig b/configs/open1788/knxterm/defconfig index 2dcbe5cc478..a01ac9abc36 100644 --- a/configs/open1788/knxterm/defconfig +++ b/configs/open1788/knxterm/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_BCH=y @@ -27,13 +27,13 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EXTDRAM=y -CONFIG_LPC17_EXTDRAMSIZE=67108864 -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_LCD=y -CONFIG_LPC17_LCD_BPP16=y -CONFIG_LPC17_SDCARD=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EXTDRAM=y +CONFIG_LPC17_40_EXTDRAMSIZE=67108864 +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_LCD=y +CONFIG_LPC17_40_LCD_BPP16=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index a6983275198..3fd018e7f24 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -5,14 +5,14 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_LPC17_EMC is not set +# CONFIG_LPC17_40_EMC is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -25,9 +25,9 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_SDCARD=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/nxlines/defconfig b/configs/open1788/nxlines/defconfig index 0fa0b200cff..ace2eb7d499 100644 --- a/configs/open1788/nxlines/defconfig +++ b/configs/open1788/nxlines/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -25,12 +25,12 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EXTDRAM=y -CONFIG_LPC17_EXTDRAMSIZE=67108864 -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_LCD=y -CONFIG_LPC17_SDCARD=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EXTDRAM=y +CONFIG_LPC17_40_EXTDRAMSIZE=67108864 +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_LCD=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/pdcurses/defconfig b/configs/open1788/pdcurses/defconfig index 89c333c4bbc..c41daedc544 100644 --- a/configs/open1788/pdcurses/defconfig +++ b/configs/open1788/pdcurses/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y CONFIG_BOARD_LOOPSPERMSEC=11934 @@ -30,13 +30,13 @@ CONFIG_GRAPHICS_PDCURSES=y CONFIG_HOST_WINDOWS=y CONFIG_INPUT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EXTDRAM=y -CONFIG_LPC17_EXTDRAMSIZE=67108864 -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_GPIOIRQ=y -CONFIG_LPC17_LCD=y -CONFIG_LPC17_SDCARD=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EXTDRAM=y +CONFIG_LPC17_40_EXTDRAMSIZE=67108864 +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_GPIOIRQ=y +CONFIG_LPC17_40_LCD=y +CONFIG_LPC17_40_SDCARD=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/pwfb/defconfig b/configs/open1788/pwfb/defconfig index 2c486a48509..4d4400df96d 100644 --- a/configs/open1788/pwfb/defconfig +++ b/configs/open1788/pwfb/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="open1788" CONFIG_ARCH_BOARD_OPEN1788=y CONFIG_ARCH_CHIP_LPC1788=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_BOARD_LATE_INITIALIZE=y @@ -29,13 +29,13 @@ CONFIG_EXAMPLES_PWFB_FONTCOLOR=0x0000 CONFIG_EXAMPLES_PWFB_FONTID=1 CONFIG_EXAMPLES_PWFB_TBCOLOR=0xad55 CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EXTDRAM=y -CONFIG_LPC17_EXTDRAMHEAP_OFFSET=393216 -CONFIG_LPC17_EXTDRAMSIZE=67108864 -CONFIG_LPC17_GPDMA=y -CONFIG_LPC17_LCD=y -CONFIG_LPC17_LCD_BPP16=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EXTDRAM=y +CONFIG_LPC17_40_EXTDRAMHEAP_OFFSET=393216 +CONFIG_LPC17_40_EXTDRAMSIZE=67108864 +CONFIG_LPC17_40_GPDMA=y +CONFIG_LPC17_40_LCD=y +CONFIG_LPC17_40_LCD_BPP16=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/open1788/src/Makefile b/configs/open1788/src/Makefile index 336d84277a1..e532c9677a6 100644 --- a/configs/open1788/src/Makefile +++ b/configs/open1788/src/Makefile @@ -36,44 +36,44 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boardinitialize.c lpc17_bringup.c lpc17_ssp.c +CSRCS = lpc17_40_boardinitialize.c lpc17_40_bringup.c lpc17_40_ssp.c -ifeq ($(CONFIG_LPC17_EMC),y) -ifeq ($(CONFIG_LPC17_EXTNOR),y) - CSRCS += lpc17_norinitialize.c +ifeq ($(CONFIG_LPC17_40_EMC),y) +ifeq ($(CONFIG_LPC17_40_EXTNOR),y) + CSRCS += lpc17_40_norinitialize.c endif -ifeq ($(CONFIG_LPC17_EXTNAND),y) - CSRCS += lpc17_nandinitialize.c +ifeq ($(CONFIG_LPC17_40_EXTNAND),y) + CSRCS += lpc17_40_nandinitialize.c endif -ifeq ($(CONFIG_LPC17_EXTDRAM),y) - CSRCS += lpc17_sdraminitialize.c +ifeq ($(CONFIG_LPC17_40_EXTDRAM),y) + CSRCS += lpc17_40_sdraminitialize.c endif endif -ifeq ($(CONFIG_LPC17_LCD),y) - CSRCS += lpc17_lcd.c +ifeq ($(CONFIG_LPC17_40_LCD),y) + CSRCS += lpc17_40_lcd.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) - CSRCS += lpc17_appinit.c + CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += lpc17_autoleds.c + CSRCS += lpc17_40_autoleds.c else - CSRCS += lpc17_userleds.c + CSRCS += lpc17_40_userleds.c endif ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += lpc17_buttons.c + CSRCS += lpc17_40_buttons.c else ifeq ($(CONFIG_OPEN1788_DJOYSTICK),y) - CSRCS += lpc17_djoystick.c + CSRCS += lpc17_40_djoystick.c endif ifeq ($(CONFIG_INPUT_ADS7843E),y) - CSRCS += lpc17_touchscreen.c + CSRCS += lpc17_40_touchscreen.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/open1788/src/lpc17_appinit.c b/configs/open1788/src/lpc17_40_appinit.c similarity index 98% rename from configs/open1788/src/lpc17_appinit.c rename to configs/open1788/src/lpc17_40_appinit.c index dfb5b1737b6..3a7a7237e20 100644 --- a/configs/open1788/src/lpc17_appinit.c +++ b/configs/open1788/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/open1877/src/lpc17_appinit.c + * config/open1877/src/lpc17_40_appinit.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/open1788/src/lpc17_autoleds.c b/configs/open1788/src/lpc17_40_autoleds.c similarity index 93% rename from configs/open1788/src/lpc17_autoleds.c rename to configs/open1788/src/lpc17_40_autoleds.c index dc8bdc1522d..08627de7007 100644 --- a/configs/open1788/src/lpc17_autoleds.c +++ b/configs/open1788/src/lpc17_40_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/open1788/src/lpc17_autoleds.c + * configs/open1788/src/lpc17_40_autoleds.c * * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "open1788.h" /**************************************************************************** @@ -138,7 +138,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) lpc17_dumpgpio(???, m) +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) #else # define led_dumpgpio(m) #endif @@ -180,22 +180,22 @@ static inline void led_clrbits(unsigned int clrbits) { if ((clrbits & OPEN1788_LED1) != 0) { - lpc17_gpiowrite(GPIO_LED1, false); + lpc17_40_gpiowrite(GPIO_LED1, false); } if ((clrbits & OPEN1788_LED2) != 0) { - lpc17_gpiowrite(GPIO_LED2, false); + lpc17_40_gpiowrite(GPIO_LED2, false); } if ((clrbits & OPEN1788_LED3) != 0) { - lpc17_gpiowrite(GPIO_LED3, false); + lpc17_40_gpiowrite(GPIO_LED3, false); } if ((clrbits & OPEN1788_LED4) != 0) { - lpc17_gpiowrite(GPIO_LED4, false); + lpc17_40_gpiowrite(GPIO_LED4, false); } } @@ -203,22 +203,22 @@ static inline void led_setbits(unsigned int setbits) { if ((setbits & OPEN1788_LED1) != 0) { - lpc17_gpiowrite(GPIO_LED1, true); + lpc17_40_gpiowrite(GPIO_LED1, true); } if ((setbits & OPEN1788_LED2) != 0) { - lpc17_gpiowrite(GPIO_LED2, true); + lpc17_40_gpiowrite(GPIO_LED2, true); } if ((setbits & OPEN1788_LED3) != 0) { - lpc17_gpiowrite(GPIO_LED3, true); + lpc17_40_gpiowrite(GPIO_LED3, true); } if ((setbits & OPEN1788_LED4) != 0) { - lpc17_gpiowrite(GPIO_LED4, true); + lpc17_40_gpiowrite(GPIO_LED4, true); } } @@ -240,10 +240,10 @@ void board_autoled_initialize(void) { /* Configure LED1-4 GPIOs for output */ - lpc17_configgpio(GPIO_LED1); - lpc17_configgpio(GPIO_LED2); - lpc17_configgpio(GPIO_LED3); - lpc17_configgpio(GPIO_LED4); + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); + lpc17_40_configgpio(GPIO_LED3); + lpc17_40_configgpio(GPIO_LED4); } /**************************************************************************** diff --git a/configs/open1788/src/lpc17_boardinitialize.c b/configs/open1788/src/lpc17_40_boardinitialize.c similarity index 89% rename from configs/open1788/src/lpc17_boardinitialize.c rename to configs/open1788/src/lpc17_40_boardinitialize.c index 7f232d71711..9f4c1673c33 100644 --- a/configs/open1788/src/lpc17_boardinitialize.c +++ b/configs/open1788/src/lpc17_40_boardinitialize.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/open1788/src/lpc17_boardinitialize.c + * configs/open1788/src/lpc17_40_boardinitialize.c * * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_emc.h" +#include "lpc17_40_emc.h" #include "open1788.h" @@ -64,37 +64,37 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Initialize the EMC, SDRAM, NOR FLASH, and NAND FLASH */ -#ifdef CONFIG_LPC17_EMC - lpc17_emcinitialize(); +#ifdef CONFIG_LPC17_40_EMC + lpc17_40_emcinitialize(); -#ifdef CONFIG_LPC17_EXTDRAM +#ifdef CONFIG_LPC17_40_EXTDRAM open1788_sdram_initialize(); #endif -#ifdef CONFIG_LPC17_EXTNOR +#ifdef CONFIG_LPC17_40_EXTNOR open1788_nor_initialize(); #endif -#ifdef CONFIG_LPC17_EXTNAND +#ifdef CONFIG_LPC17_40_EXTNAND open1788_nand_initialize(); #endif #endif -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) || \ - defined(CONFIG_LPC17_SSP2) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) * the weak function open1788_sspdev_initialize() has been brought into * the link. @@ -112,7 +112,7 @@ void lpc17_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_LPC17_LCD +#ifdef CONFIG_LPC17_40_LCD /* Configure the LCD GPIOs if LCD support has been selected. */ open1788_lcd_initialize(); diff --git a/configs/open1788/src/lpc17_bringup.c b/configs/open1788/src/lpc17_40_bringup.c similarity index 93% rename from configs/open1788/src/lpc17_bringup.c rename to configs/open1788/src/lpc17_40_bringup.c index e9a4f83975c..d4e11d157c8 100644 --- a/configs/open1788/src/lpc17_bringup.c +++ b/configs/open1788/src/lpc17_40_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/open1788/src/lpc17_bringup.c + * config/open1788/src/lpc17_40_bringup.c * * Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,9 +54,9 @@ #include #include -#include "lpc17_gpio.h" -#include "lpc17_sdcard.h" -#include "lpc17_usbhost.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_sdcard.h" +#include "lpc17_40_usbhost.h" #include "open1788.h" /**************************************************************************** @@ -73,7 +73,7 @@ /* MMC/SD support */ -#if !defined(CONFIG_LPC17_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) +#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) # undef NSH_HAVE_MMCSD #endif @@ -107,14 +107,14 @@ #ifdef NSH_HAVE_MMCSD # ifdef CONFIG_MMCSD_HAVE_CARDDETECT # define NSH_HAVE_MMCSD_CD 1 -# ifdef CONFIG_LPC17_GPIOIRQ +# ifdef CONFIG_LPC17_40_GPIOIRQ # define NSH_HAVE_MMCSD_CDINT 1 # endif # endif #endif #if defined(NSH_HAVE_MMCSD_CD) && \ - (defined(CONFIG_LPC17_SSP1) || defined(CONFIG_LPC17_USBDEV)) + (defined(CONFIG_LPC17_40_SSP1) || defined(CONFIG_LPC17_40_USBDEV)) # warning "Use of SD Card Detect pin conflicts with SSP1 and/or USB device" #endif @@ -124,7 +124,7 @@ # undef NSH_HAVE_USBHOST #endif -#ifndef CONFIG_LPC17_USBHOST +#ifndef CONFIG_LPC17_40_USBHOST # undef NSH_HAVE_USBHOST #endif @@ -147,7 +147,7 @@ # undef NSH_HAVE_USBDEV #endif -#ifndef CONFIG_LPC17_USBDEV +#ifndef CONFIG_LPC17_40_USBDEV # undef NSH_HAVE_USBDEV #endif @@ -218,7 +218,7 @@ static int nsh_cdinterrupt(int irq, FAR void *context, FAR void *arg) static bool inserted = 0xff; /* Impossible value */ bool present; - present = !lpc17_gpioread(GPIO_SD_CD); + present = !lpc17_40_gpioread(GPIO_SD_CD); if (present != inserted) { sdio_mediachange(g_sdiodev, present); @@ -245,15 +245,15 @@ static int nsh_sdinitialize(void) #ifdef NSH_HAVE_MMCSD_CD /* Configure the SD card detect GPIO */ - lpc17_configgpio(GPIO_SD_CD); + lpc17_40_configgpio(GPIO_SD_CD); #ifdef NSH_HAVE_MMCSD_CDINT /* Attach an interrupt handler to get notifications when a card is * inserted or deleted. */ - (void)irq_attach(LPC17_IRQ_P0p13, nsh_cdinterrupt, NULL); - up_enable_irq(LPC17_IRQ_P0p13); + (void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL); + up_enable_irq(LPC17_40_IRQ_P0p13); #endif #endif @@ -285,7 +285,7 @@ static int nsh_sdinitialize(void) */ #ifdef NSH_HAVE_MMCSD_CD - sdio_mediachange(g_sdiodev, !lpc17_gpioread(GPIO_SD_CD)); + sdio_mediachange(g_sdiodev, !lpc17_40_gpioread(GPIO_SD_CD)); #else sdio_mediachange(g_sdiodev, true); #endif @@ -338,7 +338,7 @@ static int nsh_usbhostinitialize(void) /* Then get an instance of the USB host interface */ syslog(LOG_INFO, "Initialize USB host\n"); - g_usbconn = lpc17_usbhost_initialize(0); + g_usbconn = lpc17_40_usbhost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -422,7 +422,7 @@ int open1788_bringup(void) #ifdef CONFIG_OPEN1788_DJOYSTICK /* Initialize and register the joystick driver */ - ret = lpc17_djoy_initialization(); + ret = lpc17_40_djoy_initialization(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the joystick driver: %d\n", ret); diff --git a/configs/open1788/src/lpc17_buttons.c b/configs/open1788/src/lpc17_40_buttons.c similarity index 95% rename from configs/open1788/src/lpc17_buttons.c rename to configs/open1788/src/lpc17_40_buttons.c index e35484bad64..2e005f4074a 100644 --- a/configs/open1788/src/lpc17_buttons.c +++ b/configs/open1788/src/lpc17_40_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/open1788/src/lpc17_buttons.c + * configs/open1788/src/lpc17_40_buttons.c * * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,7 +49,7 @@ #include -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "open1788.h" #ifdef CONFIG_ARCH_BUTTONS @@ -81,13 +81,13 @@ * the BUTTON_* and JOYSTICK_* definitions in board.h */ -static const lpc17_pinset_t g_buttoncfg[NUM_BUTTONS] = +static const lpc17_40_pinset_t g_buttoncfg[NUM_BUTTONS] = { GPIO_USER1, GPIO_USER2, GPIO_USER3, GPIO_JOY_A, GPIO_JOY_B, GPIO_JOY_C, GPIO_JOY_D, GPIO_JOY_CTR }; -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) /* This array provides the mapping from button ID numbers to button IRQ * numbers. */ @@ -122,7 +122,7 @@ void board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - lpc17_configgpio(g_buttoncfg[i]); + lpc17_40_configgpio(g_buttoncfg[i]); } } @@ -153,7 +153,7 @@ uint32_t board_buttons(void) { /* A LOW value means that the key is pressed. */ - bool released = lpc17_gpioread(g_buttoncfg[i]); + bool released = lpc17_40_gpioread(g_buttoncfg[i]); /* Accumulate the set of depressed (not released) keys */ @@ -187,7 +187,7 @@ uint32_t board_buttons(void) * ****************************************************************************/ -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { irqstate_t flags; diff --git a/configs/open1788/src/lpc17_djoystick.c b/configs/open1788/src/lpc17_40_djoystick.c similarity index 95% rename from configs/open1788/src/lpc17_djoystick.c rename to configs/open1788/src/lpc17_40_djoystick.c index 6c40f0eb41d..33546895b4b 100644 --- a/configs/open1788/src/lpc17_djoystick.c +++ b/configs/open1788/src/lpc17_40_djoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/open1788/src/lpc17_djoystick.c + * configs/open1788/src/lpc17_40_djoystick.c * * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include #include -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "open1788.h" /**************************************************************************** @@ -108,13 +108,13 @@ static int djoy_interrupt(int irq, FAR void *context, FAR void *arg); * DJOY_* definitions in include/nuttx/input/djoystick.h. */ -static const lpc17_pinset_t g_joygpio[DJOY_NGPIOS] = +static const lpc17_40_pinset_t g_joygpio[DJOY_NGPIOS] = { GPIO_JOY_B, GPIO_JOY_C, GPIO_JOY_A, GPIO_JOY_D, GPIO_JOY_CTR, GPIO_USER1, GPIO_USER2, GPIO_USER3 }; -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ /* This array provides the mapping from button ID numbers to button IRQ * numbers. Indexed using DJOY_* definitions in * include/nuttx/input/djoystick.h. @@ -178,7 +178,7 @@ static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower) { /* A LOW value means that the key is pressed. */ - bool released = lpc17_gpioread(g_joygpio[i]); + bool released = lpc17_40_gpioread(g_joygpio[i]); /* Accumulate the set of depressed (not released) keys */ @@ -205,7 +205,7 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, djoy_buttonset_t press, djoy_buttonset_t release, djoy_interrupt_t handler, FAR void *arg) { -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ irqstate_t flags; djoy_buttonset_t either = press | release; int irq; @@ -259,7 +259,7 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, static void djoy_disable(void) { -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ irqstate_t flags; int irq; int i; @@ -310,24 +310,24 @@ static int djoy_interrupt(int irq, FAR void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc17_djoy_initialization + * Name: lpc17_40_djoy_initialization * * Description: * Initialize and register the discrete joystick driver * ****************************************************************************/ -int lpc17_djoy_initialization(void) +int lpc17_40_djoy_initialization(void) { int i; /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by lpc17_gpiosetevent(). + * interrupting pins since it will also be done by lpc17_40_gpiosetevent(). */ for (i = 0; i < DJOY_NGPIOS; i++) { - lpc17_configgpio(g_joygpio[i]); + lpc17_40_configgpio(g_joygpio[i]); } /* Make sure that all interrupts are disabled */ diff --git a/configs/open1788/src/lpc17_lcd.c b/configs/open1788/src/lpc17_40_lcd.c similarity index 87% rename from configs/open1788/src/lpc17_lcd.c rename to configs/open1788/src/lpc17_40_lcd.c index 2edd1e5627c..8551ab48c52 100644 --- a/configs/open1788/src/lpc17_lcd.c +++ b/configs/open1788/src/lpc17_40_lcd.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/open1788/src/lpc17_lcd.c + * configs/open1788/src/lpc17_40_lcd.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -42,12 +42,12 @@ #include #include -#include "lpc17_lcd.h" -#include "lpc17_gpio.h" +#include "lpc17_40_lcd.h" +#include "lpc17_40_gpio.h" #include "open1788.h" -#ifdef CONFIG_LPC17_LCD +#ifdef CONFIG_LPC17_40_LCD /************************************************************************************ * Public Functions @@ -65,23 +65,23 @@ void open1788_lcd_initialize(void) { /* Configure the LCD backlight (and turn the backlight off) */ - lpc17_configgpio(GPIO_LCD_BL); + lpc17_40_configgpio(GPIO_LCD_BL); } /************************************************************************************ - * Name: lpc17_backlight + * Name: lpc17_40_backlight * * Description: - * If CONFIG_LPC17_LCD_BACKLIGHT is defined, then the board-specific logic must + * If CONFIG_LPC17_40_LCD_BACKLIGHT is defined, then the board-specific logic must * provide this interface to turn the backlight on and off. * ************************************************************************************/ -#ifdef CONFIG_LPC17_LCD_BACKLIGHT -void lpc17_backlight(bool blon) +#ifdef CONFIG_LPC17_40_LCD_BACKLIGHT +void lpc17_40_backlight(bool blon) { - lpc17_gpiowrite(GPIO_LCD_BL, blon); + lpc17_40_gpiowrite(GPIO_LCD_BL, blon); } #endif -#endif /* CONFIG_LPC17_LCD */ +#endif /* CONFIG_LPC17_40_LCD */ diff --git a/configs/open1788/src/lpc17_nandinitialize.c b/configs/open1788/src/lpc17_40_nandinitialize.c similarity index 82% rename from configs/open1788/src/lpc17_nandinitialize.c rename to configs/open1788/src/lpc17_40_nandinitialize.c index 40be0f8cea3..b85fcbcb1e3 100644 --- a/configs/open1788/src/lpc17_nandinitialize.c +++ b/configs/open1788/src/lpc17_40_nandinitialize.c @@ -1,6 +1,6 @@ /************************************************************************************ - * configs/open1788/src/lpc17_nandinitialize.c - * arch/arm/src/board/lpc17_nandinitialize.c + * configs/open1788/src/lpc17_40_nandinitialize.c + * arch/arm/src/board/lpc17_40_nandinitialize.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,7 +49,7 @@ #include "open1788.h" -#if defined(CONFIG_LPC17_EMC) && defined(CONFIG_LPC17_EXTNAND) +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTNAND) /************************************************************************************ * Public Functions @@ -69,25 +69,25 @@ void open1788_nand_initialize(void) /* Set the memory width and byte lanes */ - regval = getreg32(LPC17_EMC_STATICCONFIG1); + regval = getreg32(LPC17_40_EMC_STATICCONFIG1); regval &= ~EMC_STATICCONFIG_MW_MASK; regbal |= (EMC_STATICCONFIG_MW_8BIT | EMC_STATICCONFIG_PB); - putreg32(regval, LPC17_EMC_STATICCONFIG1); + putreg32(regval, LPC17_40_EMC_STATICCONFIG1); /* Configure timing */ - putreg32(2, LPC17_EMC_STATICWAITWEN1); - putreg32(2, LPC17_EMC_STATICWAITOEN1); - putreg32(31, LPC17_EMC_STATICWAITRD1); - putreg32(31, LPC17_EMC_STATICWAITPAGE1); - putreg32(31, LPC17_EMC_STATICWAITWR1); - putreg32(31, LPC17_EMC_STATICWAITTURN1); + putreg32(2, LPC17_40_EMC_STATICWAITWEN1); + putreg32(2, LPC17_40_EMC_STATICWAITOEN1); + putreg32(31, LPC17_40_EMC_STATICWAITRD1); + putreg32(31, LPC17_40_EMC_STATICWAITPAGE1); + putreg32(31, LPC17_40_EMC_STATICWAITWR1); + putreg32(31, LPC17_40_EMC_STATICWAITTURN1); /* GPIO P2[21] connects to the Ready/Busy pin of the NAND part. We need to * reconfigure this pin as normal GPIO input. */ - lpc17_gpioconfig(GPIO_NAND_RB); + lpc17_40_gpioconfig(GPIO_NAND_RB); } -#endif /* CONFIG_LPC17_EMC && CONFIG_LPC17_EXTNAND */ +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTNAND */ diff --git a/configs/open1788/src/lpc17_norinitialize.c b/configs/open1788/src/lpc17_40_norinitialize.c similarity index 82% rename from configs/open1788/src/lpc17_norinitialize.c rename to configs/open1788/src/lpc17_40_norinitialize.c index a942d345c3d..c34ab4abd76 100644 --- a/configs/open1788/src/lpc17_norinitialize.c +++ b/configs/open1788/src/lpc17_40_norinitialize.c @@ -1,6 +1,6 @@ /************************************************************************************ - * configs/open1788/src/lpc17_norinitialize.c - * arch/arm/src/board/lpc17_norinitialize.c + * configs/open1788/src/lpc17_40_norinitialize.c + * arch/arm/src/board/lpc17_40_norinitialize.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,7 +49,7 @@ #include "open1788.h" -#if defined(CONFIG_LPC17_EMC) && defined(CONFIG_LPC17_EXTNOR) +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTNOR) /************************************************************************************ * Public Functions @@ -69,21 +69,21 @@ void open1788_nor_initialize(void) /* Set the memory width and byte lanes */ - regval = getreg32(LPC17_EMC_STATICCONFIG0); + regval = getreg32(LPC17_40_EMC_STATICCONFIG0); regval &= ~EMC_STATICCONFIG_MW_MASK; regbal |= (EMC_STATICCONFIG_MW_16BIT | EMC_STATICCONFIG_PB); - putreg32(regval, LPC17_EMC_STATICCONFIG0); + putreg32(regval, LPC17_40_EMC_STATICCONFIG0); /* Configure timing */ - putreg32(2, LPC17_EMC_STATICWAITWEN0); - putreg32(2, LPC17_EMC_STATICWAITOEN0); - putreg32(31, LPC17_EMC_STATICWAITRD0); - putreg32(31, LPC17_EMC_STATICWAITPAGE0); - putreg32(31, LPC17_EMC_STATICWAITWR0); - putreg32(31, LPC17_EMC_STATICWAITTURN0); + putreg32(2, LPC17_40_EMC_STATICWAITWEN0); + putreg32(2, LPC17_40_EMC_STATICWAITOEN0); + putreg32(31, LPC17_40_EMC_STATICWAITRD0); + putreg32(31, LPC17_40_EMC_STATICWAITPAGE0); + putreg32(31, LPC17_40_EMC_STATICWAITWR0); + putreg32(31, LPC17_40_EMC_STATICWAITTURN0); up_mdelay(10); } -#endif /* CONFIG_LPC17_EMC && CONFIG_LPC17_EXTNOR */ +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTNOR */ diff --git a/configs/open1788/src/lpc17_sdraminitialize.c b/configs/open1788/src/lpc17_40_sdraminitialize.c similarity index 66% rename from configs/open1788/src/lpc17_sdraminitialize.c rename to configs/open1788/src/lpc17_40_sdraminitialize.c index 9a8c772223b..3b5e071d49b 100644 --- a/configs/open1788/src/lpc17_sdraminitialize.c +++ b/configs/open1788/src/lpc17_40_sdraminitialize.c @@ -1,6 +1,6 @@ /************************************************************************************ - * configs/open1788/src/lpc17_sdraminitialize.c - * arch/arm/src/board/lpc17_sdraminitialize.c + * configs/open1788/src/lpc17_40_sdraminitialize.c + * arch/arm/src/board/lpc17_40_sdraminitialize.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,49 +47,49 @@ #include "up_arch.h" #include "up_internal.h" -#include "hardware/lpc17_syscon.h" -#include "lpc17_emc.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_emc.h" #include "open1788.h" -#if defined(CONFIG_LPC17_EMC) && defined(CONFIG_LPC17_EXTDRAM) +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTDRAM) /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* The core clock is LPC17_EMCCLK which may be either LPC17_CCLK* (undivided), or - * LPC17_CCLK / 2 as determined by settings in the board.h header file. +/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided), or + * LPC17_40_CCLK / 2 as determined by settings in the board.h header file. * * For example: - * LPC17_CCLCK = 120,000,000 - * EMCCLKSEL -> LPC17_CCLK divided by 2 - * LPC17_EMCCLK = 60,000,000 - * LPC17_EMCCLK_MHZ = 60 (Rounded to an integer) + * LPC17_40_CCLCK = 120,000,000 + * EMCCLKSEL -> LPC17_40_CCLK divided by 2 + * LPC17_40_EMCCLK = 60,000,000 + * LPC17_40_EMCCLK_MHZ = 60 (Rounded to an integer) * EMC_NSPERCLK = 16.667 (Represented with 4 bits of fraction, 267) * * EMC_NS2CLK(63) = ((63 << 4) + 266) / 267 = 4 (actual 3.78) * EMC_NS2CLK(20) = ((20 << 4) + 266) / 267 = 2 (actual 1.20) */ -#define LPC17_EMCCLK_MHZ ((LPC17_EMCCLK + 500000) / 1000000) -#define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_EMCCLK_MHZ >> 1)) / LPC17_EMCCLK_MHZ) +#define LPC17_40_EMCCLK_MHZ ((LPC17_40_EMCCLK + 500000) / 1000000) +#define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_40_EMCCLK_MHZ >> 1)) / LPC17_40_EMCCLK_MHZ) #define EMC_NS2CLK(ns) (((ns << 4) + (EMC_NSPERCLK_B4 - 1)) / EMC_NSPERCLK_B4) #define MDKCFG_RASCAS0VAL 0x00000303 /* Set up for 32-bit SDRAM at CS0 */ -#ifdef CONFIG_LPC17_EXTDRAMSIZE -# define SDRAM_SIZE CONFIG_LPC17_EXTDRAMSIZE +#ifdef CONFIG_LPC17_40_EXTDRAMSIZE +# define SDRAM_SIZE CONFIG_LPC17_40_EXTDRAMSIZE #endif -#ifdef CONFIG_LPC17_SDRAM_16BIT +#ifdef CONFIG_LPC17_40_SDRAM_16BIT # ifndef SDRAM_SIZE # define SDRAM_SIZE 0x02000000 /* 256Mbit */ # endif -#else /* if defined(CONFIG_LPC17_SDRAM_32BIT) */ -# undef CONFIG_LPC17_SDRAM_32BIT -# define CONFIG_LPC17_SDRAM_32BIT 1 +#else /* if defined(CONFIG_LPC17_40_SDRAM_32BIT) */ +# undef CONFIG_LPC17_40_SDRAM_32BIT +# define CONFIG_LPC17_40_SDRAM_32BIT 1 # ifndef SDRAM_SIZE # define SDRAM_SIZE 0x04000000 /* 512Mbit */ # endif @@ -133,44 +133,44 @@ void open1788_sdram_initialize(void) SYSCON_EMCDLYCTL_FBCLKDLY(32) | SYSCON_EMCDLYCTL_CLKOUT0DLY(1) | SYSCON_EMCDLYCTL_CLKOUT1DLY(1); - putreg32(regval, LPC17_SYSCON_EMCDLYCTL); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); /* Configure the SDRAM */ - putreg32( EMC_NS2CLK(20), LPC17_EMC_DYNAMICRP); /* TRP = 20 nS */ - putreg32( 15, LPC17_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */ - putreg32( 0, LPC17_EMC_DYNAMICSREX); /* TSREX = 1 clock */ - putreg32( 1, LPC17_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */ - putreg32(EMC_NS2CLK(20) + 2, LPC17_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */ - putreg32( 1, LPC17_EMC_DYNAMICWR); /* TWR = 2 clocks */ - putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/ - putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */ - putreg32( 15, LPC17_EMC_DYNAMICXSR); /* Exit self-refresh to active */ - putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */ - putreg32( 1, LPC17_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */ + putreg32( EMC_NS2CLK(20), LPC17_40_EMC_DYNAMICRP); /* TRP = 20 nS */ + putreg32( 15, LPC17_40_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */ + putreg32( 0, LPC17_40_EMC_DYNAMICSREX); /* TSREX = 1 clock */ + putreg32( 1, LPC17_40_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */ + putreg32(EMC_NS2CLK(20) + 2, LPC17_40_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */ + putreg32( 1, LPC17_40_EMC_DYNAMICWR); /* TWR = 2 clocks */ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */ + putreg32( 15, LPC17_40_EMC_DYNAMICXSR); /* Exit self-refresh to active */ + putreg32( EMC_NS2CLK(63), LPC17_40_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */ + putreg32( 1, LPC17_40_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */ /* Command delayed strategy, using EMCCLKDELAY */ - putreg32(EMC_DYNAMICREADCONFIG_RD_CMD, LPC17_EMC_DYNAMICREADCONFIG); + putreg32(EMC_DYNAMICREADCONFIG_RD_CMD, LPC17_40_EMC_DYNAMICREADCONFIG); /* H57V2562GTR-75C: TCL=3CLK, TRCD = 20ns(min), 3 CLK = 24ns */ - putreg32(MDKCFG_RASCAS0VAL, LPC17_EMC_DYNAMICRASCAS0); + putreg32(MDKCFG_RASCAS0VAL, LPC17_40_EMC_DYNAMICRASCAS0); -#ifdef CONFIG_LPC17_SDRAM_16BIT +#ifdef CONFIG_LPC17_40_SDRAM_16BIT /* For Manley lpc1778 SDRAM: H57V2562GTR-75C, 256Mb, 16Mx16, 4 banks, row=13, column=9: * * 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13), - LPC17_EMC_DYNAMICCONFIG0); + LPC17_40_EMC_DYNAMICCONFIG0); -#elif defined CONFIG_LPC17_SDRAM_32BIT +#elif defined CONFIG_LPC17_40_SDRAM_32BIT /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13) | EMC_DYNAMICCONFIG_AM1, - LPC17_EMC_DYNAMICCONFIG0); + LPC17_40_EMC_DYNAMICCONFIG0); #endif up_mdelay(100); @@ -178,7 +178,7 @@ void open1788_sdram_initialize(void) /* Issue NOP command */ putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_NOP, - LPC17_EMC_DYNAMICCONTROL); + LPC17_40_EMC_DYNAMICCONTROL); /* Wait 200 Msec */ @@ -187,9 +187,9 @@ void open1788_sdram_initialize(void) /* Issue PALL command */ putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_PALL, - LPC17_EMC_DYNAMICCONTROL); + LPC17_40_EMC_DYNAMICCONTROL); - putreg32(2, LPC17_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */ + putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */ /* Wait 128 AHB clock cycles */ @@ -200,35 +200,35 @@ void open1788_sdram_initialize(void) regval = 64000000 / (1 << 13); regval -= 16; regval >>= 4; - regval = regval * LPC17_EMCCLK_MHZ / 1000; - putreg32(regval, LPC17_EMC_DYNAMICREFRESH); + regval = regval * LPC17_40_EMCCLK_MHZ / 1000; + putreg32(regval, LPC17_40_EMC_DYNAMICREFRESH); /* Issue MODE command */ putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_MODE, - LPC17_EMC_DYNAMICCONTROL); + LPC17_40_EMC_DYNAMICCONTROL); -#ifdef CONFIG_LPC17_SDRAM_16BIT +#ifdef CONFIG_LPC17_40_SDRAM_16BIT (void)getreg16(SDRAM_BASE | (0x33 << 12)); /* 8 burst, 3 CAS latency */ -#elif defined CONFIG_LPC17_SDRAM_32BIT +#elif defined CONFIG_LPC17_40_SDRAM_32BIT (void)getreg32(SDRAM_BASE | (0x32 << 13)); /* 4 burst, 3 CAS latency */ #endif /* Issue NORMAL command */ - putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_EMC_DYNAMICCONTROL); + putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); /* Enable buffer */ - regval = getreg32(LPC17_EMC_DYNAMICCONFIG0); + regval = getreg32(LPC17_40_EMC_DYNAMICCONFIG0); regval |= EMC_DYNAMICCONFIG_B; - putreg32(regval, LPC17_EMC_DYNAMICCONFIG0); + putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0); up_mdelay(12); - regval = getreg32(LPC17_SYSCON_EMCDLYCTL); + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK; regval |= SYSCON_EMCDLYCTL_CMDDLY(18); - putreg32(regval, LPC17_SYSCON_EMCDLYCTL); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); } -#endif /* CONFIG_LPC17_EMC && CONFIG_LPC17_EXTDRAM */ +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTDRAM */ diff --git a/configs/open1788/src/lpc17_ssp.c b/configs/open1788/src/lpc17_40_ssp.c similarity index 72% rename from configs/open1788/src/lpc17_ssp.c rename to configs/open1788/src/lpc17_40_ssp.c index e904144f246..ef6cf99303d 100644 --- a/configs/open1788/src/lpc17_ssp.c +++ b/configs/open1788/src/lpc17_40_ssp.c @@ -1,6 +1,6 @@ /**************************************************************************** - * configs/open1788/src/lpc17_ssp.c - * arch/arm/src/board/lpc17_ssp.c + * configs/open1788/src/lpc17_40_ssp.c + * arch/arm/src/board/lpc17_40_ssp.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,12 +50,12 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "open1788.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) || \ - defined(CONFIG_LPC17_SSP2) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_GPIO_INFO -# define ssp_dumpgpio(p,m) lpc17_dumpgpio(p,m) +# define ssp_dumpgpio(p,m) lpc17_40_dumpgpio(p,m) #else # define ssp_dumpgpio(p,m) #endif @@ -85,95 +85,95 @@ void weak_function open1788_sspdev_initialize(void) { /* Configure the SSP0 chip select GPIOs. */ -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 #endif /* Configure SSP1 chip select GPIOs. This includes the touchscreen on the * the LCD module. */ -#ifdef CONFIG_LPC17_SSP1 +#ifdef CONFIG_LPC17_40_SSP1 ssp_dumpgpio(GPIO_TC_CS, "BEFORE SSP1 Initialization"); - lpc17_configgpio(GPIO_TC_CS); + lpc17_40_configgpio(GPIO_TC_CS); ssp_dumpgpio(GPIO_TC_CS, "AFTER SSP1 Initialization"); #endif /* Configure the SSP2 chip select GPIOs. */ -#ifdef CONFIG_LPC17_SSP2 +#ifdef CONFIG_LPC17_40_SSP2 #endif } /************************************************************************************ - * Name: lpc17_ssp0/1/2select and lpc17_ssp0/1/2status + * Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status * * Description: - * The external functions, lpc17_ssp0/1/2select and lpc17_ssp0/1/2status + * The external functions, lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc17_sspbus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc17_ssp0/1/2select() and lpc17_ssp0/1/2status() functions + * 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc17_sspbus_initialize() in your low level application + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning nothing\n"); return 0; } #endif -#ifdef CONFIG_LPC17_SSP1 -void lpc17_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); if (devid == SPIDEV_TOUCHSCREEN(0)) { /* Assert/de-assert the CS pin to the touchscreen */ - ssp_dumpgpio(GPIO_TC_CS, "lpc17_ssp1select() Entry"); - lpc17_gpiowrite(GPIO_TC_CS, !selected); - ssp_dumpgpio(GPIO_TC_CS, "lpc17_ssp1select() Exit"); + ssp_dumpgpio(GPIO_TC_CS, "lpc17_40_ssp1select() Entry"); + lpc17_40_gpiowrite(GPIO_TC_CS, !selected); + ssp_dumpgpio(GPIO_TC_CS, "lpc17_40_ssp1select() Exit"); } } -uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning nothing\n"); return 0; } #endif -#ifdef CONFIG_LPC17_SSP2 -void lpc17_ssp2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP2 +void lpc17_40_ssp2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t lpc17_ssp2status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp2status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning nothing\n"); return 0; } #endif -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 || CONFIG_LPC17_SSP2 */ +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 || CONFIG_LPC17_40_SSP2 */ diff --git a/configs/open1788/src/lpc17_touchscreen.c b/configs/open1788/src/lpc17_40_touchscreen.c similarity index 93% rename from configs/open1788/src/lpc17_touchscreen.c rename to configs/open1788/src/lpc17_40_touchscreen.c index 65a0f33faef..c70feb51af0 100644 --- a/configs/open1788/src/lpc17_touchscreen.c +++ b/configs/open1788/src/lpc17_40_touchscreen.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/open1788/src/lpc17_touchscreen.c + * configs/open1788/src/lpc17_40_touchscreen.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,8 +51,8 @@ #include #include -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "open1788.h" #ifdef CONFIG_INPUT_ADS7843E @@ -67,12 +67,12 @@ # error "Touchscreen support requires CONFIG_INPUT" #endif -#ifndef CONFIG_LPC17_SSP1 -# error "Touchscreen support requires CONFIG_LPC17_SSP1" +#ifndef CONFIG_LPC17_40_SSP1 +# error "Touchscreen support requires CONFIG_LPC17_40_SSP1" #endif -#ifndef CONFIG_LPC17_GPIOIRQ -# error "Touchscreen support requires CONFIG_LPC17_GPIOIRQ" +#ifndef CONFIG_LPC17_40_GPIOIRQ +# error "Touchscreen support requires CONFIG_LPC17_40_GPIOIRQ" #endif #ifndef CONFIG_ADS7843E_FREQUENCY @@ -169,7 +169,7 @@ static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t handler) { /* Attach then enable the touchscreen interrupt handler */ - (void)irq_attach(LPC17_IRQ_PENIRQ, handler, NULL); + (void)irq_attach(LPC17_40_IRQ_PENIRQ, handler, NULL); return OK; } @@ -182,7 +182,7 @@ static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) * logic after completion of processing of the touchscreen interrupt. */ - up_enable_irq(LPC17_IRQ_PENIRQ); + up_enable_irq(LPC17_40_IRQ_PENIRQ); } else { @@ -190,14 +190,14 @@ static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) * interrupt handling logic. */ - up_disable_irq(LPC17_IRQ_PENIRQ); + up_disable_irq(LPC17_40_IRQ_PENIRQ); } } static void tsc_clear(FAR struct ads7843e_config_s *state) { /* Does nothing. The interrupt is cleared automatically in the GPIO - * logic for the LPC17xx family. + * logic for the LPC17xx/LPC40xx family. */ } @@ -223,7 +223,7 @@ static bool tsc_busy(FAR struct ads7843e_config_s *state) /* REVISIT: This might need to be inverted */ - bool busy = lpc17_gpioread(GPIO_TC_BUSY); + bool busy = lpc17_40_gpioread(GPIO_TC_BUSY); #if defined(CONFIG_DEBUG_INPUT) && defined(CONFIG_DEBUG_INFO) if (busy != last) { @@ -244,7 +244,7 @@ static bool tsc_pendown(FAR struct ads7843e_config_s *state) * initiates an interrupt to the processor via TP_INT. */ - bool pendown = !lpc17_gpioread(GPIO_TC_PENIRQ); + bool pendown = !lpc17_40_gpioread(GPIO_TC_PENIRQ); iinfo("pendown:%d\n", pendown); return pendown; } @@ -280,17 +280,17 @@ int open1788_tsc_setup(int minor) /* Configure and enable the XPT2046 PENIRQ pin as an interrupting input. */ - (void)lpc17_configgpio(GPIO_TC_PENIRQ); + (void)lpc17_40_configgpio(GPIO_TC_PENIRQ); /* Configure the XPT2046 BUSY pin as a normal input. */ #ifndef XPT2046_NO_BUSY - (void)lpc17_configgpio(GPIO_TC_BUSY); + (void)lpc17_40_configgpio(GPIO_TC_BUSY); #endif /* Get an instance of the SPI interface */ - dev = lpc17_sspbus_initialize(CONFIG_ADS7843E_SPIDEV); + dev = lpc17_40_sspbus_initialize(CONFIG_ADS7843E_SPIDEV); if (!dev) { ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_ADS7843E_SPIDEV); diff --git a/configs/open1788/src/lpc17_userleds.c b/configs/open1788/src/lpc17_40_userleds.c similarity index 86% rename from configs/open1788/src/lpc17_userleds.c rename to configs/open1788/src/lpc17_40_userleds.c index 585ccd08705..552cdee7e06 100644 --- a/configs/open1788/src/lpc17_userleds.c +++ b/configs/open1788/src/lpc17_40_userleds.c @@ -1,6 +1,6 @@ /**************************************************************************** - * configs/open1788/src/lpc17_userleds.c - * arch/arm/src/board/lpc17_userleds.c + * configs/open1788/src/lpc17_40_userleds.c + * arch/arm/src/board/lpc17_40_userleds.c * * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,7 +51,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "open1788.h" #ifndef CONFIG_ARCH_LEDS @@ -63,7 +63,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) lpc17_dumpgpio(???, m) +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) #else # define led_dumpgpio(m) #endif @@ -91,10 +91,10 @@ void board_userled_initialize(void) { /* Configure LED1-4 GPIOs for output */ - lpc17_configgpio(GPIO_LED1); - lpc17_configgpio(GPIO_LED2); - lpc17_configgpio(GPIO_LED3); - lpc17_configgpio(GPIO_LED4); + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); + lpc17_40_configgpio(GPIO_LED3); + lpc17_40_configgpio(GPIO_LED4); } /**************************************************************************** @@ -105,7 +105,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - lpc17_gpiowrite(g_ledcfg[led], ledon); + lpc17_40_gpiowrite(g_ledcfg[led], ledon); } } @@ -115,10 +115,10 @@ void board_userled(int led, bool ledon) void board_userled_all(uint8_t ledset) { - lpc17_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - lpc17_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - lpc17_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - lpc17_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); } #endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/open1788/src/open1788.h b/configs/open1788/src/open1788.h index edaeb592010..b00a7704bc4 100644 --- a/configs/open1788/src/open1788.h +++ b/configs/open1788/src/open1788.h @@ -105,13 +105,13 @@ /* IRQ numbers for the buttons that do support interrupts */ -#define GPIO_USER2_IRQ LPC17_IRQ_P2p22 -#define GPIO_USER3_IRQ LPC17_IRQ_P0p10 -#define GPIO_JOY_A_IRQ LPC17_IRQ_P2p25 -#define GPIO_JOY_B_IRQ LPC17_IRQ_P2p26 -#define GPIO_JOY_C_IRQ LPC17_IRQ_P2p23 -#define GPIO_JOY_D_IRQ LPC17_IRQ_P2p19 -#define GPIO_JOY_CTR_IRQ LPC17_IRQ_P0p14 +#define GPIO_USER2_IRQ LPC17_40_IRQ_P2p22 +#define GPIO_USER3_IRQ LPC17_40_IRQ_P0p10 +#define GPIO_JOY_A_IRQ LPC17_40_IRQ_P2p25 +#define GPIO_JOY_B_IRQ LPC17_40_IRQ_P2p26 +#define GPIO_JOY_C_IRQ LPC17_40_IRQ_P2p23 +#define GPIO_JOY_D_IRQ LPC17_40_IRQ_P2p19 +#define GPIO_JOY_CTR_IRQ LPC17_40_IRQ_P0p14 /* SD Card **************************************************************************/ /* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also @@ -149,7 +149,7 @@ #define GPIO_TC_BUSY (GPIO_INPUT | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN14) #define GPIO_TC_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN8) -#define LPC17_IRQ_PENIRQ LPC17_IRQ_P2p15 +#define LPC17_40_IRQ_PENIRQ LPC17_40_IRQ_P2p15 /************************************************************************************ * Public data @@ -195,8 +195,8 @@ void weak_function open1788_sspdev_initialize(void); * ************************************************************************************/ -#ifdef CONFIG_LPC17_EMC -#ifdef CONFIG_LPC17_EXTDRAM +#ifdef CONFIG_LPC17_40_EMC +#ifdef CONFIG_LPC17_40_EXTDRAM void open1788_sdram_initialize(void); #endif @@ -208,7 +208,7 @@ void open1788_sdram_initialize(void); * ************************************************************************************/ -#ifdef CONFIG_LPC17_EXTNOR +#ifdef CONFIG_LPC17_40_EXTNOR void open1788_nor_initialize(void); #endif @@ -220,10 +220,10 @@ void open1788_nor_initialize(void); * ************************************************************************************/ -#ifdef CONFIG_LPC17_EXTNAND +#ifdef CONFIG_LPC17_40_EXTNAND void open1788_nand_initialize(void); #endif -#endif /* CONFIG_LPC17_EMC */ +#endif /* CONFIG_LPC17_40_EMC */ /************************************************************************************ * Name: open1788_lcd_initialize @@ -233,7 +233,7 @@ void open1788_nand_initialize(void); * ************************************************************************************/ -#ifdef CONFIG_LPC17_LCD +#ifdef CONFIG_LPC17_40_LCD void open1788_lcd_initialize(void); #endif @@ -259,7 +259,7 @@ int open1788_tsc_setup(int minor); #endif /************************************************************************************ - * Name: lpc17_djoy_initialization + * Name: lpc17_40_djoy_initialization * * Description: * Initialize and register the discrete joystick driver @@ -267,7 +267,7 @@ int open1788_tsc_setup(int minor); ************************************************************************************/ #ifdef CONFIG_OPEN1788_DJOYSTICK -int lpc17_djoy_initialization(void); +int lpc17_40_djoy_initialization(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/pnev5180b/Kconfig b/configs/pnev5180b/Kconfig index f98698be6c3..673e2a60b4b 100644 --- a/configs/pnev5180b/Kconfig +++ b/configs/pnev5180b/Kconfig @@ -5,28 +5,28 @@ if ARCH_BOARD_PNEV5180B -config LPC17_ROMFS +config LPC17_40_ROMFS bool "Automount baked-in ROMFS image" default n depends on FS_ROMFS ---help--- - Specify which ROMFS image to mount where via LPC17_ROMFS_IMAGEFILE, - LPC17_ROMFS_DEV_MINOR, and LPC17_ROMFS_MOUNTPOINT. ROMFS images are + Specify which ROMFS image to mount where via LPC17_40_ROMFS_IMAGEFILE, + LPC17_40_ROMFS_DEV_MINOR, and LPC17_40_ROMFS_MOUNTPOINT. ROMFS images are created with the genromfs Linux tool. -config LPC17_ROMFS_DEV_MINOR +config LPC17_40_ROMFS_DEV_MINOR int "Minor for the block device backing the data" - depends on LPC17_ROMFS + depends on LPC17_40_ROMFS default 64 -config LPC17_ROMFS_MOUNTPOINT +config LPC17_40_ROMFS_MOUNTPOINT string "Mountpoint of the custom romfs image" - depends on LPC17_ROMFS + depends on LPC17_40_ROMFS default "/mnt/romfs" -config LPC17_ROMFS_IMAGEFILE +config LPC17_40_ROMFS_IMAGEFILE string "ROMFS image file to include into build" - depends on LPC17_ROMFS + depends on LPC17_40_ROMFS default "../romfs.img" ---help--- The path to specify is relative to the 'src' directory of the diff --git a/configs/pnev5180b/include/board.h b/configs/pnev5180b/include/board.h index bb8e2fc05a5..362093c5f2a 100644 --- a/configs/pnev5180b/include/board.h +++ b/configs/pnev5180b/include/board.h @@ -49,7 +49,7 @@ #include -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) # include #endif @@ -59,7 +59,7 @@ /* Clocking ******************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not * included here because the including C file may not have that file in its * include path. */ @@ -78,14 +78,14 @@ * CCLCK = 480MHz / 4 = 120MHz -> CCLK divider = 4 */ -#define LPC17_CCLK 120000000 /* 120Mhz */ +#define LPC17_40_CCLK 120000000 /* 120Mhz */ /* Select the main oscillator as the frequency source. SYSCLK is then the * frequency of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is @@ -105,8 +105,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -117,7 +117,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -204,20 +204,20 @@ extern "C" *****************************************************************************/ /***************************************************************************** - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This + * All LPC17xx/LPC40xx architectures must provide the following entry point. This * entry point is called early in the initialization -- after all memory * has been configured and mapped but before any devices have been * initialized. * *****************************************************************************/ -void lpc17_boardinitialize(void); +void lpc17_40_boardinitialize(void); /***************************************************************************** - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control LED 1 @@ -225,7 +225,7 @@ void lpc17_boardinitialize(void); *****************************************************************************/ #ifdef CONFIG_ARCH_LEDS -void lpc17_led(int lednum, int state); +void lpc17_40_led(int lednum, int state); #endif #undef EXTERN diff --git a/configs/pnev5180b/kernel/Makefile b/configs/pnev5180b/kernel/Makefile index ad34e6b9178..0ea4ef8fa6d 100644 --- a/configs/pnev5180b/kernel/Makefile +++ b/configs/pnev5180b/kernel/Makefile @@ -76,7 +76,7 @@ USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" # Source files -CSRCS = lpc17_userspace.c +CSRCS = lpc17_40_userspace.c COBJS = $(CSRCS:.c=$(OBJEXT)) OBJS = $(COBJS) diff --git a/configs/pnev5180b/kernel/lpc17_userspace.c b/configs/pnev5180b/kernel/lpc17_40_userspace.c similarity index 97% rename from configs/pnev5180b/kernel/lpc17_userspace.c rename to configs/pnev5180b/kernel/lpc17_40_userspace.c index dcb7b6c2166..1213993c488 100644 --- a/configs/pnev5180b/kernel/lpc17_userspace.c +++ b/configs/pnev5180b/kernel/lpc17_40_userspace.c @@ -1,10 +1,10 @@ /**************************************************************************** - * configs/pnev5180b/kernel/lpc17_userspace.c + * configs/pnev5180b/kernel/lpc17_40_userspace.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung * - * Based on configs/open1788/kernel/lpc17_userspace.c + * Based on configs/open1788/kernel/lpc17_40_userspace.c * * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/pnev5180b/knsh/defconfig b/configs/pnev5180b/knsh/defconfig index 696fa7010c7..f0e07983578 100644 --- a/configs/pnev5180b/knsh/defconfig +++ b/configs/pnev5180b/knsh/defconfig @@ -9,11 +9,11 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="pnev5180b" CONFIG_ARCH_BOARD_PNEV5180B=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARM_MPU=y CONFIG_BOARD_LOOPSPERMSEC=11992 CONFIG_BUILD_PROTECTED=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_UART0=y CONFIG_MM_REGIONS=2 CONFIG_NUTTX_USERSPACE=0x00020000 CONFIG_PASS1_BUILDIR="configs/pnev5180b/kernel" diff --git a/configs/pnev5180b/nsh-cdcecm/defconfig b/configs/pnev5180b/nsh-cdcecm/defconfig index 4ae760914d2..00daf1294ff 100644 --- a/configs/pnev5180b/nsh-cdcecm/defconfig +++ b/configs/pnev5180b/nsh-cdcecm/defconfig @@ -9,16 +9,16 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="pnev5180b" CONFIG_ARCH_BOARD_PNEV5180B=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_BOARD_LOOPSPERMSEC=11992 CONFIG_BUILTIN=y CONFIG_CDCECM_EPBULKIN=5 CONFIG_CDCECM_EPBULKOUT=2 CONFIG_FS_BINFS=y CONFIG_FS_PROCFS=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBDEV=y -CONFIG_LPC17_USBDEV_NOVBUS=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBDEV=y +CONFIG_LPC17_40_USBDEV_NOVBUS=y CONFIG_MM_REGIONS=2 CONFIG_NETINIT_NOMAC=y CONFIG_NET_CDCECM=y diff --git a/configs/pnev5180b/nsh/defconfig b/configs/pnev5180b/nsh/defconfig index 8ca77225835..a2de2ad3df8 100644 --- a/configs/pnev5180b/nsh/defconfig +++ b/configs/pnev5180b/nsh/defconfig @@ -9,9 +9,9 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="pnev5180b" CONFIG_ARCH_BOARD_PNEV5180B=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_BOARD_LOOPSPERMSEC=11992 -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_UART0=y CONFIG_MM_REGIONS=2 CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x10000000 diff --git a/configs/pnev5180b/src/Makefile b/configs/pnev5180b/src/Makefile index 179efe8ad0f..1bb13946aa6 100644 --- a/configs/pnev5180b/src/Makefile +++ b/configs/pnev5180b/src/Makefile @@ -36,34 +36,34 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_bringup.c +CSRCS = lpc17_40_boot.c lpc17_40_bringup.c ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += lpc17_leds.c +CSRCS += lpc17_40_leds.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += lpc17_composite.c +CSRCS += lpc17_40_composite.c endif -ifeq ($(CONFIG_LPC17_SPI),y) -CSRCS += lpc17_spi.c +ifeq ($(CONFIG_LPC17_40_SPI),y) +CSRCS += lpc17_40_spi.c endif ifeq ($(CONFIG_ELF),y) -CSRCS += lpc17_symtab.c +CSRCS += lpc17_40_symtab.c endif ifeq ($(CONFIG_NXFLAT),y) -CSRCS += lpc17_symtab.c +CSRCS += lpc17_40_symtab.c endif -ifeq ($(CONFIG_LPC17_ROMFS),y) -CSRCS += lpc17_romfs.c +ifeq ($(CONFIG_LPC17_40_ROMFS),y) +CSRCS += lpc17_40_romfs.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/pnev5180b/src/lpc17_appinit.c b/configs/pnev5180b/src/lpc17_40_appinit.c similarity index 98% rename from configs/pnev5180b/src/lpc17_appinit.c rename to configs/pnev5180b/src/lpc17_40_appinit.c index 34057b49fb1..88da53390cb 100644 --- a/configs/pnev5180b/src/lpc17_appinit.c +++ b/configs/pnev5180b/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /***************************************************************************** - * config/pnev5180b/src/lpc17_appinit.c + * config/pnev5180b/src/lpc17_40_appinit.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung diff --git a/configs/pnev5180b/src/lpc17_boot.c b/configs/pnev5180b/src/lpc17_40_boot.c similarity index 94% rename from configs/pnev5180b/src/lpc17_boot.c rename to configs/pnev5180b/src/lpc17_40_boot.c index cf9284abddf..a59ac33319f 100644 --- a/configs/pnev5180b/src/lpc17_boot.c +++ b/configs/pnev5180b/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /***************************************************************************** - * configs/pnev5180b/src/lpc17_boot.c + * configs/pnev5180b/src/lpc17_40_boot.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung @@ -54,17 +54,17 @@ *****************************************************************************/ /***************************************************************************** - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This + * All LPC17xx/LPC40xx architectures must provide the following entry point. This * entry point is called early in the initialization -- after all memory * has been configured and mapped but before any devices have been * initialized. * *****************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/pnev5180b/src/lpc17_bringup.c b/configs/pnev5180b/src/lpc17_40_bringup.c similarity index 93% rename from configs/pnev5180b/src/lpc17_bringup.c rename to configs/pnev5180b/src/lpc17_40_bringup.c index a44d5f74813..d4dc6e79818 100644 --- a/configs/pnev5180b/src/lpc17_bringup.c +++ b/configs/pnev5180b/src/lpc17_40_bringup.c @@ -1,5 +1,5 @@ /***************************************************************************** - * config/pnev5180b/src/lpc17_bringup.c + * config/pnev5180b/src/lpc17_40_bringup.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung @@ -67,14 +67,14 @@ # include #endif -#ifdef CONFIG_LPC17_ROMFS -# include "lpc17_romfs.h" +#ifdef CONFIG_LPC17_40_ROMFS +# include "lpc17_40_romfs.h" #endif -#include "lpc17_spi.h" +#include "lpc17_40_spi.h" #include "pnev5180b.h" -#include "lpc17_symtab.h" -#include "lpc17_progmem.h" +#include "lpc17_40_symtab.h" +#include "lpc17_40_progmem.h" /***************************************************************************** * Pre-processor Definitions @@ -163,11 +163,11 @@ int pnev5180b_bringup(void) board_composite_connect(0, 0); #endif -#ifdef CONFIG_LPC17_ROMFS - ret = lpc17_romfs_initialize(); +#ifdef CONFIG_LPC17_40_ROMFS + ret = lpc17_40_romfs_initialize(); if (ret != OK) { - syslog(LOG_ERR, "ERROR: lpc17_romfs_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: lpc17_40_romfs_initialize() failed: %d\n", ret); goto done; } #endif @@ -200,7 +200,7 @@ int pnev5180b_bringup(void) #endif #if defined(CONFIG_ELF) || defined(CONFIG_NXFLAT) - exec_setsymtab(lpc17_exports, lpc17_nexports); + exec_setsymtab(lpc17_40_exports, lpc17_40_nexports); #endif /* To avoid 'unused label' compiler warnings in specific configuration. */ diff --git a/configs/pnev5180b/src/lpc17_composite.c b/configs/pnev5180b/src/lpc17_40_composite.c similarity index 99% rename from configs/pnev5180b/src/lpc17_composite.c rename to configs/pnev5180b/src/lpc17_40_composite.c index ec8ead6929b..ea901309a80 100644 --- a/configs/pnev5180b/src/lpc17_composite.c +++ b/configs/pnev5180b/src/lpc17_40_composite.c @@ -1,5 +1,5 @@ /***************************************************************************** - * configs/pnev5180b/src/lpc17_composite.c + * configs/pnev5180b/src/lpc17_40_composite.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung diff --git a/configs/pnev5180b/src/lpc17_leds.c b/configs/pnev5180b/src/lpc17_40_leds.c similarity index 69% rename from configs/pnev5180b/src/lpc17_leds.c rename to configs/pnev5180b/src/lpc17_40_leds.c index fc737ebd0cf..78f1d5844bd 100644 --- a/configs/pnev5180b/src/lpc17_leds.c +++ b/configs/pnev5180b/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/pnev5180b/src/lpc17_leds.c + * configs/pnev5180b/src/lpc17_40_leds.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung @@ -49,7 +49,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "pnev5180b.h" #ifdef CONFIG_ARCH_LEDS @@ -62,10 +62,10 @@ void pnev5180b_autoled_initialize(void) { /* Configure all LED GPIO lines */ - lpc17_configgpio(PNEV5180B_LED_RED); - lpc17_configgpio(PNEV5180B_LED_ORANGE); - lpc17_configgpio(PNEV5180B_LED_BLUE); - lpc17_configgpio(PNEV5180B_LED_GREEN); + lpc17_40_configgpio(PNEV5180B_LED_RED); + lpc17_40_configgpio(PNEV5180B_LED_ORANGE); + lpc17_40_configgpio(PNEV5180B_LED_BLUE); + lpc17_40_configgpio(PNEV5180B_LED_GREEN); } /**************************************************************************** @@ -77,47 +77,47 @@ void board_autoled_on(int led) switch (led) { case LED_STARTED: - lpc17_gpiowrite(PNEV5180B_LED_RED, true); - lpc17_gpiowrite(PNEV5180B_LED_ORANGE, true); - lpc17_gpiowrite(PNEV5180B_LED_BLUE, true); - lpc17_gpiowrite(PNEV5180B_LED_GREEN, true); + lpc17_40_gpiowrite(PNEV5180B_LED_RED, true); + lpc17_40_gpiowrite(PNEV5180B_LED_ORANGE, true); + lpc17_40_gpiowrite(PNEV5180B_LED_BLUE, true); + lpc17_40_gpiowrite(PNEV5180B_LED_GREEN, true); break; case LED_HEAPALLOCATE: - lpc17_gpiowrite(PNEV5180B_LED_RED, false); - lpc17_gpiowrite(PNEV5180B_LED_ORANGE, false); - lpc17_gpiowrite(PNEV5180B_LED_BLUE, false); - lpc17_gpiowrite(PNEV5180B_LED_GREEN, true); + lpc17_40_gpiowrite(PNEV5180B_LED_RED, false); + lpc17_40_gpiowrite(PNEV5180B_LED_ORANGE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_BLUE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_GREEN, true); break; case LED_IRQSENABLED: - lpc17_gpiowrite(PNEV5180B_LED_RED, false); - lpc17_gpiowrite(PNEV5180B_LED_ORANGE, false); - lpc17_gpiowrite(PNEV5180B_LED_BLUE, true); - lpc17_gpiowrite(PNEV5180B_LED_GREEN, false); + lpc17_40_gpiowrite(PNEV5180B_LED_RED, false); + lpc17_40_gpiowrite(PNEV5180B_LED_ORANGE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_BLUE, true); + lpc17_40_gpiowrite(PNEV5180B_LED_GREEN, false); break; case LED_STACKCREATED: - lpc17_gpiowrite(PNEV5180B_LED_RED, false); - lpc17_gpiowrite(PNEV5180B_LED_ORANGE, false); - lpc17_gpiowrite(PNEV5180B_LED_BLUE, false); - lpc17_gpiowrite(PNEV5180B_LED_GREEN, false); + lpc17_40_gpiowrite(PNEV5180B_LED_RED, false); + lpc17_40_gpiowrite(PNEV5180B_LED_ORANGE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_BLUE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_GREEN, false); break; case LED_INIRQ: - lpc17_gpiowrite(PNEV5180B_LED_GREEN, true); + lpc17_40_gpiowrite(PNEV5180B_LED_GREEN, true); break; case LED_SIGNAL: - lpc17_gpiowrite(PNEV5180B_LED_BLUE, true); + lpc17_40_gpiowrite(PNEV5180B_LED_BLUE, true); break; case LED_ASSERTION: - lpc17_gpiowrite(PNEV5180B_LED_ORANGE, true); + lpc17_40_gpiowrite(PNEV5180B_LED_ORANGE, true); break; case LED_PANIC: - lpc17_gpiowrite(PNEV5180B_LED_RED, true); + lpc17_40_gpiowrite(PNEV5180B_LED_RED, true); break; default: @@ -134,19 +134,19 @@ void board_autoled_off(int led) switch (led) { case LED_INIRQ: - lpc17_gpiowrite(PNEV5180B_LED_GREEN, false); + lpc17_40_gpiowrite(PNEV5180B_LED_GREEN, false); break; case LED_SIGNAL: - lpc17_gpiowrite(PNEV5180B_LED_BLUE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_BLUE, false); break; case LED_ASSERTION: - lpc17_gpiowrite(PNEV5180B_LED_ORANGE, false); + lpc17_40_gpiowrite(PNEV5180B_LED_ORANGE, false); break; case LED_PANIC: - lpc17_gpiowrite(PNEV5180B_LED_RED, false); + lpc17_40_gpiowrite(PNEV5180B_LED_RED, false); break; default: diff --git a/configs/pnev5180b/src/lpc17_romfs.c b/configs/pnev5180b/src/lpc17_40_romfs.c similarity index 83% rename from configs/pnev5180b/src/lpc17_romfs.c rename to configs/pnev5180b/src/lpc17_40_romfs.c index 39a2182b5d0..c42c69df6df 100644 --- a/configs/pnev5180b/src/lpc17_romfs.c +++ b/configs/pnev5180b/src/lpc17_40_romfs.c @@ -1,5 +1,5 @@ /***************************************************************************** - * configs/pnev5180b/src/lpc17_romfs.c + * configs/pnev5180b/src/lpc17_40_romfs.c * This file provides contents of an optional ROMFS volume, mounted at boot. * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -52,26 +52,26 @@ #include #include -#include "lpc17_romfs.h" +#include "lpc17_40_romfs.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_LPC17_ROMFS -# error "CONFIG_LPC17_ROMFS must be defined" +#ifndef CONFIG_LPC17_40_ROMFS +# error "CONFIG_LPC17_40_ROMFS must be defined" #else -#ifndef CONFIG_LPC17_ROMFS_IMAGEFILE -# error "CONFIG_LPC17_ROMFS_IMAGEFILE must be defined" +#ifndef CONFIG_LPC17_40_ROMFS_IMAGEFILE +# error "CONFIG_LPC17_40_ROMFS_IMAGEFILE must be defined" #endif -#ifndef CONFIG_LPC17_ROMFS_DEV_MINOR -# error "CONFIG_LPC17_ROMFS_DEV_MINOR must be defined" +#ifndef CONFIG_LPC17_40_ROMFS_DEV_MINOR +# error "CONFIG_LPC17_40_ROMFS_DEV_MINOR must be defined" #endif -#ifndef CONFIG_LPC17_ROMFS_MOUNTPOINT -# error "CONFIG_LPC17_ROMFS_MOUNTPOINT must be defined" +#ifndef CONFIG_LPC17_40_ROMFS_MOUNTPOINT +# error "CONFIG_LPC17_40_ROMFS_MOUNTPOINT must be defined" #endif #define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) @@ -80,7 +80,7 @@ #define STR(m) STR2(m) #define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_LPC17_ROMFS_DEV_MINOR) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_LPC17_40_ROMFS_DEV_MINOR) /**************************************************************************** * Private Data @@ -91,7 +91,7 @@ __asm__ ( ".balign 16\n" ".globl romfs_data_begin\n" "romfs_data_begin:\n" - ".incbin " STR(CONFIG_LPC17_ROMFS_IMAGEFILE) "\n"\ + ".incbin " STR(CONFIG_LPC17_40_ROMFS_IMAGEFILE) "\n"\ \ ".balign " STR(ROMFS_SECTOR_SIZE) "\n" ".globl romfs_data_end\n" @@ -109,7 +109,7 @@ extern const int romfs_data_size; ****************************************************************************/ /**************************************************************************** - * Name: lpc17_romfs_initialize + * Name: lpc17_40_romfs_initialize * * Description: * Registers the above included binary file as block device, then mounts @@ -124,7 +124,7 @@ extern const int romfs_data_size; * ****************************************************************************/ -int lpc17_romfs_initialize(void) +int lpc17_40_romfs_initialize(void) { uintptr_t romfs_data_len; int ret; @@ -133,7 +133,7 @@ int lpc17_romfs_initialize(void) romfs_data_len = (uintptr_t)&romfs_data_end - (uintptr_t)&romfs_data_begin; - ret = romdisk_register(CONFIG_LPC17_ROMFS_DEV_MINOR, &romfs_data_begin, + ret = romdisk_register(CONFIG_LPC17_40_ROMFS_DEV_MINOR, &romfs_data_begin, NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); if (ret < 0) { @@ -144,18 +144,18 @@ int lpc17_romfs_initialize(void) /* Mount the file system */ finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_LPC17_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + CONFIG_LPC17_40_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - ret = mount(MOUNT_DEVNAME, CONFIG_LPC17_ROMFS_MOUNTPOINT, + ret = mount(MOUNT_DEVNAME, CONFIG_LPC17_40_ROMFS_MOUNTPOINT, "romfs", MS_RDONLY, NULL); if (ret < 0) { ferr("ERROR: mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_LPC17_ROMFS_MOUNTPOINT, errno); + MOUNT_DEVNAME, CONFIG_LPC17_40_ROMFS_MOUNTPOINT, errno); return ret; } return OK; } -#endif /* CONFIG_LPC17_ROMFS */ +#endif /* CONFIG_LPC17_40_ROMFS */ diff --git a/configs/pnev5180b/src/lpc17_romfs.h b/configs/pnev5180b/src/lpc17_40_romfs.h similarity index 89% rename from configs/pnev5180b/src/lpc17_romfs.h rename to configs/pnev5180b/src/lpc17_40_romfs.h index 64117490c95..832037e487d 100644 --- a/configs/pnev5180b/src/lpc17_romfs.h +++ b/configs/pnev5180b/src/lpc17_40_romfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/pnev5180b/src/lpc17_romfs.h + * configs/pnev5180b/src/lpc17_40_romfs.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung (mijung@gmx.net) @@ -38,8 +38,8 @@ * ****************************************************************************/ -#ifndef __CONFIGS_PNEV5180B_SRC_LPC17_ROMFS_H -#define __CONFIGS_PNEV5180B_SRC_LPC17_ROMFS_H +#ifndef __CONFIGS_PNEV5180B_SRC_LPC17_40_ROMFS_H +#define __CONFIGS_PNEV5180B_SRC_LPC17_40_ROMFS_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ #include -#ifdef CONFIG_LPC17_ROMFS +#ifdef CONFIG_LPC17_40_ROMFS /**************************************************************************** * Pre-processor Definitions @@ -60,7 +60,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: lpc17_romfs_initialize + * Name: lpc17_40_romfs_initialize * * Description: * Registers built-in ROMFS image as block device and mounts it. @@ -71,12 +71,12 @@ * Assumptions/Limitations: * Memory addresses [&romfs_data_begin .. &romfs_data_end) should contain * ROMFS volume data, as included in the assembly snippet in - * lpc17_romfs_initialize.c. + * lpc17_40_romfs_initialize.c. * ****************************************************************************/ -int lpc17_romfs_initialize(void); +int lpc17_40_romfs_initialize(void); -#endif /* CONFIG_LPC17_ROMFS */ +#endif /* CONFIG_LPC17_40_ROMFS */ -#endif /* __CONFIGS_PNEV5180B_SRC_LPC17_ROMFS_H */ +#endif /* __CONFIGS_PNEV5180B_SRC_LPC17_40_ROMFS_H */ diff --git a/configs/pnev5180b/src/lpc17_spi.c b/configs/pnev5180b/src/lpc17_40_spi.c similarity index 82% rename from configs/pnev5180b/src/lpc17_spi.c rename to configs/pnev5180b/src/lpc17_40_spi.c index 5367b6c0643..37adb07cb2b 100644 --- a/configs/pnev5180b/src/lpc17_spi.c +++ b/configs/pnev5180b/src/lpc17_40_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/pnev5180b/src/lpc17_spi.c + * configs/pnev5180b/src/lpc17_40_spi.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -49,11 +49,11 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_spi.h" -#include "lpc17_gpio.h" +#include "lpc17_40_spi.h" +#include "lpc17_40_gpio.h" #include "pnev5180b.h" -#if defined(CONFIG_LPC17_SPI) +#if defined(CONFIG_LPC17_40_SPI) /**************************************************************************** * Public Functions @@ -73,42 +73,42 @@ void weak_function pnev5180b_spidev_initialize(void) } /**************************************************************************** - * Name: lpc17_spiselect and lpc17_spistatus + * Name: lpc17_40_spiselect and lpc17_40_spistatus * * Description: - * The external functions, lpc17_spiselect and lpc17_spistatus + * The external functions, lpc17_40_spiselect and lpc17_40_spistatus * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * lpc17_spibus_initialize()) are provided by common LPC17xx logic. To + * lpc17_40_spibus_initialize()) are provided by common LPC17xx/LPC40xx logic. To * use this common SPI logic on your board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip * select * pins. - * 2. Provide lpc17_spiselect and lpc17_spistatus functions + * 2. Provide lpc17_40_spiselect and lpc17_40_spistatus functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to lpc17_spibus_initialize() in your low level + * 3. Add a calls to lpc17_40_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by lpc17_spibus_initialize() may then be used + * 4. The handle returned by lpc17_40_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -void lpc17_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void lpc17_40_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_spistatus(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("devid: %d\n", (int)devid); return 0; } -#endif /* CONFIG_LPC17_SPI */ +#endif /* CONFIG_LPC17_40_SPI */ diff --git a/configs/pnev5180b/src/lpc17_symtab.c b/configs/pnev5180b/src/lpc17_40_symtab.c similarity index 95% rename from configs/pnev5180b/src/lpc17_symtab.c rename to configs/pnev5180b/src/lpc17_40_symtab.c index ff138514514..85503a89cae 100644 --- a/configs/pnev5180b/src/lpc17_symtab.c +++ b/configs/pnev5180b/src/lpc17_40_symtab.c @@ -1,5 +1,5 @@ /***************************************************************************** - * config/pnev5180b/src/lpc17_symtab.c + * config/pnev5180b/src/lpc17_40_symtab.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung @@ -74,7 +74,7 @@ extern void *strcmp; extern void *task_create; extern void *usleep; -const struct symtab_s lpc17_exports[] = +const struct symtab_s lpc17_40_exports[] = { {"exit", &exit}, {"fflush", &fflush}, @@ -107,4 +107,4 @@ const struct symtab_s lpc17_exports[] = {"usleep", &usleep}, }; -const int lpc17_nexports = sizeof(lpc17_exports) / sizeof(struct symtab_s); +const int lpc17_40_nexports = sizeof(lpc17_40_exports) / sizeof(struct symtab_s); diff --git a/configs/pnev5180b/src/lpc17_symtab.h b/configs/pnev5180b/src/lpc17_40_symtab.h similarity index 88% rename from configs/pnev5180b/src/lpc17_symtab.h rename to configs/pnev5180b/src/lpc17_40_symtab.h index 1e43e83e110..2dccdcc0d84 100644 --- a/configs/pnev5180b/src/lpc17_symtab.h +++ b/configs/pnev5180b/src/lpc17_40_symtab.h @@ -1,5 +1,5 @@ /***************************************************************************** - * config/pnev5180b/src/lpc17_symtab.c + * config/pnev5180b/src/lpc17_40_symtab.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung @@ -33,8 +33,8 @@ * *****************************************************************************/ -#ifndef __CONFIGS_PNEV5180B_SRC_LPC17_SYMTAB_H -#define __CONFIGS_PNEV5180B_SRC_LPC17_SYMTAB_H +#ifndef __CONFIGS_PNEV5180B_SRC_LPC17_40_SYMTAB_H +#define __CONFIGS_PNEV5180B_SRC_LPC17_40_SYMTAB_H /***************************************************************************** * Included Files @@ -49,8 +49,8 @@ * Public Data *****************************************************************************/ -extern const struct symtab_s lpc17_exports[]; -extern const int lpc17_nexports; +extern const struct symtab_s lpc17_40_exports[]; +extern const int lpc17_40_nexports; #endif -#endif /* __CONFIGS_PNEV5180B_SRC_LPC17_SYMTAB_H */ +#endif /* __CONFIGS_PNEV5180B_SRC_LPC17_40_SYMTAB_H */ diff --git a/configs/pnev5180b/usbnsh-cdcecm/defconfig b/configs/pnev5180b/usbnsh-cdcecm/defconfig index 9b309b7928f..4d73f77fc86 100644 --- a/configs/pnev5180b/usbnsh-cdcecm/defconfig +++ b/configs/pnev5180b/usbnsh-cdcecm/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="pnev5180b" CONFIG_ARCH_BOARD_PNEV5180B=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_BOARD_LOOPSPERMSEC=11992 CONFIG_BUILTIN=y CONFIG_CDCACM=y @@ -19,9 +19,9 @@ CONFIG_CDCECM_COMPOSITE=y CONFIG_COMPOSITE_IAD=y CONFIG_FS_BINFS=y CONFIG_FS_PROCFS=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBDEV=y -CONFIG_LPC17_USBDEV_NOVBUS=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBDEV=y +CONFIG_LPC17_40_USBDEV_NOVBUS=y CONFIG_MM_REGIONS=2 CONFIG_NETINIT_NOMAC=y CONFIG_NET_CDCECM=y diff --git a/configs/pnev5180b/usbnsh/defconfig b/configs/pnev5180b/usbnsh/defconfig index b3576fb717e..1baacdaf25c 100644 --- a/configs/pnev5180b/usbnsh/defconfig +++ b/configs/pnev5180b/usbnsh/defconfig @@ -9,14 +9,14 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="pnev5180b" CONFIG_ARCH_BOARD_PNEV5180B=y CONFIG_ARCH_CHIP_LPC1769=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_BOARD_LOOPSPERMSEC=11992 CONFIG_CDCACM=y CONFIG_CDCACM_EPBULKIN=5 CONFIG_CDCACM_EPBULKOUT=2 -CONFIG_LPC17_UART0=y -CONFIG_LPC17_USBDEV=y -CONFIG_LPC17_USBDEV_NOVBUS=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_USBDEV=y +CONFIG_LPC17_40_USBDEV_NOVBUS=y CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_USBCONSOLE=y diff --git a/configs/spresense/src/cxd56_leds.c b/configs/spresense/src/cxd56_leds.c index 6140a3cd4e6..e682ac256af 100644 --- a/configs/spresense/src/cxd56_leds.c +++ b/configs/spresense/src/cxd56_leds.c @@ -56,26 +56,6 @@ #ifdef CONFIG_ARCH_LEDS -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const unsigned int g_ledbits[8] = -{ - LED_STARTED, - LED_HEAPALLOCATE, - LED_IRQSENABLED, - LED_STACKCREATED, - LED_INIRQ, - LED_SIGNAL, - LED_ASSERTION, - LED_PANIC -}; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -149,7 +129,7 @@ void board_autoled_initialize(void) void board_autoled_on(int led) { led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_setbits(g_ledbits[led]); + led_setbits(led); } /**************************************************************************** @@ -158,7 +138,7 @@ void board_autoled_on(int led) void board_autoled_off(int led) { - led_clrbits(g_ledbits[led]); + led_clrbits(led); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/spresense/src/cxd56_main.c b/configs/spresense/src/cxd56_main.c index 0424e1edc9e..9894515e5da 100644 --- a/configs/spresense/src/cxd56_main.c +++ b/configs/spresense/src/cxd56_main.c @@ -1,5 +1,5 @@ /**************************************************************************** - * bsp/board/spresense/src/spresense_main.c + * configs/spresense/src/spresense_main.c * * Copyright 2018 Sony Semiconductor Solutions Corporation * diff --git a/configs/stm32f103-minimum/src/stm32_lcd.c b/configs/stm32f103-minimum/src/stm32_lcd.c index 6833d644b7d..ec24b4c7609 100644 --- a/configs/stm32f103-minimum/src/stm32_lcd.c +++ b/configs/stm32f103-minimum/src/stm32_lcd.c @@ -6,7 +6,7 @@ * * I used the JLX12864G-086 LCD module based on ST7567 controller. * - * Based on configs/zkit-arm-1769/src/lpc17_lcd.c + * Based on configs/zkit-arm-1769/src/lpc17_40_lcd.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Manikandan diff --git a/configs/stm32f4discovery/src/stm32_st7567.c b/configs/stm32f4discovery/src/stm32_st7567.c index fa60ae7ffa8..e6396a8a959 100644 --- a/configs/stm32f4discovery/src/stm32_st7567.c +++ b/configs/stm32f4discovery/src/stm32_st7567.c @@ -6,7 +6,7 @@ * * I used the JLX12864G-086 LCD module based on ST7567 controller. * - * Based on configs/zkit-arm-1769/src/lpc17_lcd.c + * Based on configs/zkit-arm-1769/src/lpc17_40_lcd.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Manikandan diff --git a/configs/stm32f769i-disco/README.txt b/configs/stm32f769i-disco/README.txt index 23f3a9eaabe..7261b007a3a 100644 --- a/configs/stm32f769i-disco/README.txt +++ b/configs/stm32f769i-disco/README.txt @@ -36,6 +36,8 @@ Contents STATUS ====== + 2019-06: PWM support has been tested as working. + 2017-07: The basic NSH configuration is functional using a serial console on USART1, which is connected to the "virtual com port" of the ST/LINK USB adapter. @@ -119,7 +121,21 @@ Configuration Directories Support for builtin applications is enabled, but in the base configuration no builtin applications are selected. + 1. This config supports the PWM test (apps/examples/pwm) but this must + be manually enabled by selecting: + + CONFIG_PWM=y : Enable the generic PWM infrastructure + CONFIG_EXAMPLES_PWM=y : Enable the PWM example app + + And these for enabling the STM32 timer PWM channel: + + CONFIG_STM32F7_TIM1=y + CONFIG_STM32F7_TIM1_PWM=y + CONFIG_STM32F7_TIM1_CHANNEL=4 + nsh-ehternet: --- Same as above but a lot more hardware peripherals enabled, in particular ethernet, as well as networking stuff. + + diff --git a/configs/stm32f769i-disco/include/board.h b/configs/stm32f769i-disco/include/board.h index 84732617671..a6db6d5b482 100644 --- a/configs/stm32f769i-disco/include/board.h +++ b/configs/stm32f769i-disco/include/board.h @@ -360,6 +360,14 @@ #define GPIO_USART1_RX GPIO_USART1_RX_1 #define GPIO_USART1_TX GPIO_USART1_TX_1 +/* PWM + * + * The STM32F7 Discovery has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM1 CH4 on PA11. + */ + +#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1 + /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins: * * STM32 F7 BOARD LAN8742A diff --git a/configs/stm32f769i-disco/nsh/defconfig b/configs/stm32f769i-disco/nsh/defconfig index 56b84cd890e..b6257378e3d 100644 --- a/configs/stm32f769i-disco/nsh/defconfig +++ b/configs/stm32f769i-disco/nsh/defconfig @@ -29,6 +29,7 @@ CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=3 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/configs/stm32f769i-disco/src/Makefile b/configs/stm32f769i-disco/src/Makefile index 15a80a56169..3e4430acace 100644 --- a/configs/stm32f769i-disco/src/Makefile +++ b/configs/stm32f769i-disco/src/Makefile @@ -36,7 +36,7 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c stm32_spi.c +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c @@ -56,6 +56,10 @@ ifeq ($(CONFIG_ARCH_FPU),y) CSRCS += stm32_ostest.c endif +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif diff --git a/configs/stm32f769i-disco/src/stm32_appinitialize.c b/configs/stm32f769i-disco/src/stm32_appinitialize.c index 643c4afce25..4376cbf293e 100644 --- a/configs/stm32f769i-disco/src/stm32_appinitialize.c +++ b/configs/stm32f769i-disco/src/stm32_appinitialize.c @@ -38,9 +38,7 @@ ****************************************************************************/ #include -#include -#include "stm32_ccm.h" #include "stm32f769i-disco.h" /**************************************************************************** @@ -59,7 +57,7 @@ * arg - The boardctl() argument is passed to the board_app_initialize() * implementation without modification. The argument has no * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the + * between the board-specific initialization logic and the * matching application logic. The value cold be such things as a * mode enumeration value, a set of DIP switch switch settings, a * pointer to configuration data read from a file or serial FLASH, @@ -74,26 +72,13 @@ int board_app_initialize(uintptr_t arg) { -#ifdef CONFIG_FS_PROCFS - int ret; - -#ifdef CONFIG_STM32_CCM_PROCFS - /* Register the CCM procfs entry. This must be done before the procfs is - * mounted. - */ - - (void)ccm_procfs_register(); -#endif - - /* Mount the procfs file system */ - - ret = mount(NULL, SAMV71_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - SYSLOG("ERROR: Failed to mount procfs at %s: %d\n", - SAMV71_PROCFS_MOUNTPOINT, ret); - } -#endif +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ return OK; +#else + /* Perform board-specific initialization */ + + return stm32_bringup(); +#endif } diff --git a/configs/stm32f769i-disco/src/stm32_boot.c b/configs/stm32f769i-disco/src/stm32_boot.c index ca93c8dc121..03f71f1f8a4 100644 --- a/configs/stm32f769i-disco/src/stm32_boot.c +++ b/configs/stm32f769i-disco/src/stm32_boot.c @@ -115,13 +115,8 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. - */ + /* Perform board-specific initialization */ - (void)board_app_initialize(0); -#endif + (void)stm32_bringup(); } #endif diff --git a/configs/stm32f769i-disco/src/stm32_bringup.c b/configs/stm32f769i-disco/src/stm32_bringup.c new file mode 100644 index 00000000000..b706591d16b --- /dev/null +++ b/configs/stm32f769i-disco/src/stm32_bringup.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * config/stm32f769i-disco/src/stm32_bringup.c + * + * Copyright (C) 2012, 2014-2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include "stm32_ccm.h" +#include "stm32f769i-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_STM32_CCM_PROCFS + /* Register the CCM procfs entry. This must be done before the procfs is + * mounted. + */ + + (void)ccm_procfs_register(); +#endif + + /* Mount the procfs file system */ + + ret = mount(NULL, SAMV71_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + SYSLOG(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + SAMV71_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/configs/stm32f769i-disco/src/stm32_pwm.c b/configs/stm32f769i-disco/src/stm32_pwm.c new file mode 100644 index 00000000000..a22a8928705 --- /dev/null +++ b/configs/stm32f769i-disco/src/stm32_pwm.c @@ -0,0 +1,114 @@ +/************************************************************************************ + * configs/stm32f769i-disco/src/stm32_pwm.c + * + * Copyright (C) 2011, 2016, 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_pwm.h" +#include "stm32f769i-disco.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F769I_DISCO_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/configs/stm32f769i-disco/src/stm32f769i-disco.h b/configs/stm32f769i-disco/src/stm32f769i-disco.h index 7565fa27a5f..a655c7ec1f1 100644 --- a/configs/stm32f769i-disco/src/stm32f769i-disco.h +++ b/configs/stm32f769i-disco/src/stm32f769i-disco.h @@ -88,6 +88,14 @@ #define GPIO_SCHED_RUNNING (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ GPIO_PORTJ | GPIO_PIN0) +/* PWM + * + * The STM32F769 Discovery can be configured to output a pulse train using TIM1 CH4 on PA11. + */ + +#define STM32F769I_DISCO_PWMTIMER 1 +#define STM32F769I_DISCO_PWMCHANNEL 4 + /**************************************************************************************************** * Public data ****************************************************************************************************/ @@ -98,6 +106,34 @@ * Public Functions ****************************************************************************************************/ +/**************************************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_spidev_initialize * diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/stm32ldiscovery/chrono/defconfig similarity index 62% rename from configs/lpcxpresso-lpc1115/nsh/defconfig rename to configs/stm32ldiscovery/chrono/defconfig index d0c0dec232c..cac46e98d14 100644 --- a/configs/lpcxpresso-lpc1115/nsh/defconfig +++ b/configs/stm32ldiscovery/chrono/defconfig @@ -6,60 +6,74 @@ # modifications. # # CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_DF is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_XD is not set CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="lpcxpresso-lpc1115" -CONFIG_ARCH_BOARD_LPCXPRESSO_LPC1115=y -CONFIG_ARCH_CHIP_LPC1115=y -CONFIG_ARCH_CHIP_LPC11XX=y +CONFIG_ARCH_BOARD="stm32ldiscovery" +CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2988 +CONFIG_ARM_LWL_CONSOLE=y +CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_BUILTIN=y +CONFIG_BUTTONS=y +CONFIG_BUTTONS_LOWER=y +CONFIG_CLOCK_MONOTONIC=y CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y -CONFIG_MAX_TASKS=4 +CONFIG_EXAMPLES_CHRONO=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_INPUT=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LIB_SLCDCODEC=y +CONFIG_MAX_TASKS=8 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 +CONFIG_NFILE_DESCRIPTORS=6 +CONFIG_NFILE_STREAMS=6 CONFIG_NPTHREAD_KEYS=0 +CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_CD=y CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DATE=y CONFIG_NSH_DISABLE_MKDIR=y CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y CONFIG_NSH_DISABLE_RM=y CONFIG_NSH_DISABLE_RMDIR=y CONFIG_NSH_DISABLE_UMOUNT=y CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_LINELEN=80 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 CONFIG_PREALLOC_WDOGS=4 CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=8192 -CONFIG_RAM_START=0x10000000 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y -CONFIG_START_DAY=26 -CONFIG_START_MONTH=2 +CONFIG_STANDARD_SERIAL=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LCD=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_UART0_RXBUFSIZE=64 -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART0_TXBUFSIZE=64 CONFIG_USERMAIN_STACKSIZE=1536 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/stm32ldiscovery/include/board.h b/configs/stm32ldiscovery/include/board.h index e4a4646589c..d151f651e54 100644 --- a/configs/stm32ldiscovery/include/board.h +++ b/configs/stm32ldiscovery/include/board.h @@ -46,8 +46,7 @@ # include #endif -#include "stm32_rcc.h" -#include "stm32.h" +#include /************************************************************************************ * Pre-processor Definitions diff --git a/configs/stm32ldiscovery/src/stm32_bringup.c b/configs/stm32ldiscovery/src/stm32_bringup.c index fc2d5b8bf61..092bad05f3f 100644 --- a/configs/stm32ldiscovery/src/stm32_bringup.c +++ b/configs/stm32ldiscovery/src/stm32_bringup.c @@ -42,6 +42,8 @@ #include #include +#include + #include #include "stm32ldiscovery.h" @@ -68,6 +70,16 @@ int stm32_bringup(void) { int ret = OK; +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_STM32_LCD /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */ diff --git a/configs/stm32ldiscovery/src/stm32_buttons.c b/configs/stm32ldiscovery/src/stm32_buttons.c index d985c9f4d3d..f6cf27a61f8 100644 --- a/configs/stm32ldiscovery/src/stm32_buttons.c +++ b/configs/stm32ldiscovery/src/stm32_buttons.c @@ -46,6 +46,7 @@ #include #include +#include "stm32_gpio.h" #include "stm32ldiscovery.h" #ifdef CONFIG_ARCH_BUTTONS diff --git a/configs/stm32ldiscovery/src/stm32ldiscovery.h b/configs/stm32ldiscovery/src/stm32ldiscovery.h index 69ee6afa5c5..bff0545d941 100644 --- a/configs/stm32ldiscovery/src/stm32ldiscovery.h +++ b/configs/stm32ldiscovery/src/stm32ldiscovery.h @@ -45,6 +45,8 @@ #include #include +#include + /**************************************************************************************************** * Pre-processor Definitions ****************************************************************************************************/ diff --git a/configs/u-blox-c027/include/board.h b/configs/u-blox-c027/include/board.h index 6d2d407a50b..7070ce90e12 100644 --- a/configs/u-blox-c027/include/board.h +++ b/configs/u-blox-c027/include/board.h @@ -47,7 +47,7 @@ ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -63,14 +63,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz */ +#define LPC17_40_CCLK 80000000 /* 80Mhz */ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -89,8 +89,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -101,7 +101,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -118,8 +118,8 @@ /* FLASH Configuration */ -#undef CONFIG_LPC17_FLASH -#define CONFIG_LPC17_FLASH 1 +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 #define BOARD_FLASHCFG_VALUE 0x0000303a /* Ethernet configuration */ diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 47680775eff..d38ff5fe0e5 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="u-blox-c027" CONFIG_ARCH_BOARD_U_BLOX_C027=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=8079 @@ -37,18 +37,18 @@ CONFIG_IOB_NBUFFERS=24 CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y CONFIG_LIB_HOSTNAME="c027" -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_I2C0=y -CONFIG_LPC17_I2C1=y -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y -CONFIG_LPC17_UART1=y -CONFIG_LPC17_UART1_RINGINDICATOR=y -CONFIG_LPC17_UART2=y -CONFIG_LPC17_UART3=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_I2C0=y +CONFIG_LPC17_40_I2C1=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y +CONFIG_LPC17_40_UART1=y +CONFIG_LPC17_40_UART1_RINGINDICATOR=y +CONFIG_LPC17_40_UART2=y +CONFIG_LPC17_40_UART3=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/u-blox-c027/src/Makefile b/configs/u-blox-c027/src/Makefile index e76c00febd4..35de2e33133 100644 --- a/configs/u-blox-c027/src/Makefile +++ b/configs/u-blox-c027/src/Makefile @@ -36,26 +36,26 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_dac.c +CSRCS = lpc17_40_boot.c lpc17_40_leds.c lpc17_40_ssp.c lpc17_40_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_PWM),y) -CSRCS += lpc17_pwm.c +CSRCS += lpc17_40_pwm.c endif ifeq ($(CONFIG_ADC),y) -CSRCS += lpc17_adc.c +CSRCS += lpc17_40_adc.c endif ifeq ($(CONFIG_MODEM_U_BLOX),y) -CSRCS += lpc17_ubxmdm.c +CSRCS += lpc17_40_ubxmdm.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/u-blox-c027/src/lpc17_adc.c b/configs/u-blox-c027/src/lpc17_40_adc.c similarity index 91% rename from configs/u-blox-c027/src/lpc17_adc.c rename to configs/u-blox-c027/src/lpc17_40_adc.c index 0321cda7e7c..9cf741f4218 100644 --- a/configs/u-blox-c027/src/lpc17_adc.c +++ b/configs/u-blox-c027/src/lpc17_40_adc.c @@ -1,12 +1,12 @@ /************************************************************************************ - * configs/u-blox-c027/src/lpc17_adc.c + * configs/u-blox-c027/src/lpc17_40_adc.c * - * Derives from configs/stm3220g-eval/src/lpc17_adc.c + * Derives from configs/stm3220g-eval/src/lpc17_40_adc.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * which, in turn, was based on configs/stm3220g-eval/src/lpc17_adc.c + * which, in turn, was based on configs/stm3220g-eval/src/lpc17_40_adc.c * * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -56,7 +56,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_adc.h" +#include "lpc17_40_adc.h" #include "u-blox-c027.h" #ifdef CONFIG_ADC @@ -66,14 +66,14 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_adc_setup + * Name: lpc17_40_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int lpc17_adc_setup(void) +int lpc17_40_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; @@ -83,9 +83,9 @@ int lpc17_adc_setup(void) if (!initialized) { - /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + /* Call lpc17_40_adcinitialize() to get an instance of the ADC interface */ - adc = lpc17_adcinitialize(); + adc = lpc17_40_adcinitialize(); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/configs/u-blox-c027/src/lpc17_appinit.c b/configs/u-blox-c027/src/lpc17_40_appinit.c similarity index 94% rename from configs/u-blox-c027/src/lpc17_appinit.c rename to configs/u-blox-c027/src/lpc17_40_appinit.c index 46ffbfa2f46..a35a4fcd8a6 100644 --- a/configs/u-blox-c027/src/lpc17_appinit.c +++ b/configs/u-blox-c027/src/lpc17_40_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/u-blox-c027/src/lpc17_appinit.c + * config/u-blox-c027/src/lpc17_40_appinit.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,7 +49,7 @@ #include -#include "lpc17_ssp.h" +#include "lpc17_40_ssp.h" /**************************************************************************** * Pre-processor Definitions @@ -63,7 +63,7 @@ #ifdef CONFIG_ARCH_BOARD_U_BLOX_C027 # define NSH_HAVEUSBDEV 1 -# ifdef CONFIG_LPC17_SSP0 +# ifdef CONFIG_LPC17_40_SSP0 # define NSH_HAVEMMCSD 1 # else # undef NSH_HAVEMMCSD @@ -171,7 +171,7 @@ int board_app_initialize(uintptr_t arg) /* Get the SSP port */ - ssp = lpc17_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); + ssp = lpc17_40_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); if (!ssp) { syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", @@ -199,10 +199,10 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = lpc17_pwm_setup(); + ret = lpc17_40_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: lpc17_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: lpc17_40_pwm_setup() failed: %d\n", ret); return ret; } #endif @@ -210,10 +210,10 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_ADC /* Initialize ADC and register the ADC driver. */ - ret = lpc17_adc_setup(); + ret = lpc17_40_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: lpc17_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: lpc17_40_adc_setup failed: %d\n", ret); } #endif diff --git a/configs/u-blox-c027/src/lpc17_boot.c b/configs/u-blox-c027/src/lpc17_40_boot.c similarity index 79% rename from configs/u-blox-c027/src/lpc17_boot.c rename to configs/u-blox-c027/src/lpc17_40_boot.c index 4f20c35678c..113599c5e28 100644 --- a/configs/u-blox-c027/src/lpc17_boot.c +++ b/configs/u-blox-c027/src/lpc17_40_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/u-blox-c027/src/lpc17_boot.c + * configs/u-blox-c027/src/lpc17_40_boot.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,8 +47,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "u-blox-c027.h" /************************************************************************************ @@ -56,22 +56,22 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak * function c027_sspdev_initialize() has been brought into the link. */ -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) if (c027_sspdev_initialize) { c027_sspdev_initialize(); @@ -101,17 +101,17 @@ void lpc17_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { - lpc17_ubxmdm_init(false); + lpc17_40_ubxmdm_init(false); #if 0 - lpc17_configgpio(C027_MDMEN | GPIO_VALUE_ZERO); /* Modem disabled */ - lpc17_configgpio(C027_MDMRST | GPIO_VALUE_ONE); /* Modem reset on */ - lpc17_configgpio(C027_MDMPWR | GPIO_VALUE_ONE); /* Modem power off */ - lpc17_configgpio(C027_GPSEN | GPIO_VALUE_ZERO); /* GPS disabled */ - lpc17_configgpio(C027_GPSRST | GPIO_VALUE_ONE); /* GPS reset on */ - lpc17_configgpio(C027_MDMLVLOE | GPIO_VALUE_ONE); /* UART shifter disabled */ - lpc17_configgpio(C027_MDMILVLOE | GPIO_VALUE_ZERO); /* I2C shifter disabled */ - lpc17_configgpio(C027_MDMUSBDET | GPIO_VALUE_ZERO); /* USB sense off */ + lpc17_40_configgpio(C027_MDMEN | GPIO_VALUE_ZERO); /* Modem disabled */ + lpc17_40_configgpio(C027_MDMRST | GPIO_VALUE_ONE); /* Modem reset on */ + lpc17_40_configgpio(C027_MDMPWR | GPIO_VALUE_ONE); /* Modem power off */ + lpc17_40_configgpio(C027_GPSEN | GPIO_VALUE_ZERO); /* GPS disabled */ + lpc17_40_configgpio(C027_GPSRST | GPIO_VALUE_ONE); /* GPS reset on */ + lpc17_40_configgpio(C027_MDMLVLOE | GPIO_VALUE_ONE); /* UART shifter disabled */ + lpc17_40_configgpio(C027_MDMILVLOE | GPIO_VALUE_ZERO); /* I2C shifter disabled */ + lpc17_40_configgpio(C027_MDMUSBDET | GPIO_VALUE_ZERO); /* USB sense off */ #endif } #endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/configs/u-blox-c027/src/lpc17_dac.c b/configs/u-blox-c027/src/lpc17_40_dac.c similarity index 90% rename from configs/u-blox-c027/src/lpc17_dac.c rename to configs/u-blox-c027/src/lpc17_40_dac.c index c1924c2f309..049595f4770 100644 --- a/configs/u-blox-c027/src/lpc17_dac.c +++ b/configs/u-blox-c027/src/lpc17_40_dac.c @@ -1,12 +1,12 @@ /************************************************************************************ - * configs/u-blox-c027/src/lpc17_dac.c + * configs/u-blox-c027/src/lpc17_40_dac.c * - * Derives from configs/stm3220g-eval/src/lpc17_adc.c + * Derives from configs/stm3220g-eval/src/lpc17_40_adc.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * which, in turn, was based on configs/stm3220g-eval/src/lpc17_adc.c + * which, in turn, was based on configs/stm3220g-eval/src/lpc17_40_adc.c * * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -55,7 +55,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_dac.h" +#include "lpc17_40_dac.h" #ifdef CONFIG_DAC @@ -67,7 +67,7 @@ * Name: dac_devinit * * Description: - * All LPC17xx architectures must provide the following interface to work with + * All LPC17xx/LPC40xx architectures must provide the following interface to work with * examples/diag. * ************************************************************************************/ @@ -80,9 +80,9 @@ int dac_devinit(void) if (!initialized) { - /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ - dac = lpc17_dacinitialize(); + dac = lpc17_40_dacinitialize(); if (dac == NULL) { aerr("ERROR: Failed to get dac interface\n"); diff --git a/configs/u-blox-c027/src/lpc17_leds.c b/configs/u-blox-c027/src/lpc17_40_leds.c similarity index 95% rename from configs/u-blox-c027/src/lpc17_leds.c rename to configs/u-blox-c027/src/lpc17_40_leds.c index d29fe996dd9..bf8ac6fecb6 100644 --- a/configs/u-blox-c027/src/lpc17_leds.c +++ b/configs/u-blox-c027/src/lpc17_40_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/u-blox-c027/src/lpc17_leds.c + * configs/u-blox-c027/src/lpc17_40_leds.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "u-blox-c027.h" #ifdef CONFIG_ARCH_LEDS @@ -70,7 +70,7 @@ void board_autoled_initialize(void) { /* Configure all LED GPIO lines */ - lpc17_configgpio(C027_LED); + lpc17_40_configgpio(C027_LED); g_ncstate = true; } @@ -98,7 +98,7 @@ void board_autoled_on(int led) return; } - lpc17_gpiowrite(C027_LED, off); + lpc17_40_gpiowrite(C027_LED, off); } /**************************************************************************** @@ -124,7 +124,7 @@ void board_autoled_off(int led) return; } - lpc17_gpiowrite(C027_LED, off); + lpc17_40_gpiowrite(C027_LED, off); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/u-blox-c027/src/lpc17_pwm.c b/configs/u-blox-c027/src/lpc17_40_pwm.c similarity index 83% rename from configs/u-blox-c027/src/lpc17_pwm.c rename to configs/u-blox-c027/src/lpc17_40_pwm.c index 3c4630d0f22..fa2f5254a28 100644 --- a/configs/u-blox-c027/src/lpc17_pwm.c +++ b/configs/u-blox-c027/src/lpc17_40_pwm.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/u-blox-c027/lpc17_pwm.c + * configs/u-blox-c027/lpc17_40_pwm.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,8 +50,8 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_pwm.h" -#include "lpc17_timer.h" +#include "lpc17_40_pwm.h" +#include "lpc17_40_timer.h" #include "u-blox-c027.h" /************************************************************************************ @@ -60,23 +60,23 @@ #ifdef CONFIG_PWM -FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); -FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_mcpwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_40_timerinitialize(int timer); /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: lpc17_pwm_setup + * Name: lpc17_40_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ************************************************************************************/ -int lpc17_pwm_setup(void) +int lpc17_40_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -88,12 +88,12 @@ int lpc17_pwm_setup(void) if (!initialized) { - /* Call lpc17_pwminitialize() to get an instance of the PWM interface */ + /* Call lpc17_40_pwminitialize() to get an instance of the PWM interface */ - pwm = lpc17_pwminitialize(0); + pwm = lpc17_40_pwminitialize(0); if (!pwm) { - aerr("ERROR: Failed to get the LPC17XX PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX PWM lower half\n"); return -ENODEV; } @@ -106,10 +106,10 @@ int lpc17_pwm_setup(void) return ret; } - mcpwm = lpc17_mcpwminitialize(0); + mcpwm = lpc17_40_mcpwminitialize(0); if (!mcpwm) { - aerr("ERROR: Failed to get the LPC17XX MOTOR PWM lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX MOTOR PWM lower half\n"); return -ENODEV; } @@ -122,10 +122,10 @@ int lpc17_pwm_setup(void) return ret; } - timer = lpc17_timerinitialize(0); + timer = lpc17_40_timerinitialize(0); if (!timer) { - aerr("ERROR: Failed to get the LPC17XX TIMER lower half\n"); + aerr("ERROR: Failed to get the LPC17XX_40XX TIMER lower half\n"); return -ENODEV; } diff --git a/configs/u-blox-c027/src/lpc17_ssp.c b/configs/u-blox-c027/src/lpc17_40_ssp.c similarity index 73% rename from configs/u-blox-c027/src/lpc17_ssp.c rename to configs/u-blox-c027/src/lpc17_40_ssp.c index 1b4ce631c8a..c9e02b2384f 100644 --- a/configs/u-blox-c027/src/lpc17_ssp.c +++ b/configs/u-blox-c027/src/lpc17_40_ssp.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/u-blox-c027/src/lpc17_ssp.c + * configs/u-blox-c027/src/lpc17_40_ssp.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,11 +48,11 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "u-blox-c027.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) /************************************************************************************ * Pre-processor Definitions @@ -61,7 +61,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_GPIO_INFO -# define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) +# define ssp_dumpgpio(m) lpc17_40_dumpgpio(SDCCS_GPIO, m) #else # define ssp_dumpgpio(m) #endif @@ -86,87 +86,87 @@ void weak_function c027_sspdev_initialize(void) /* Configure card detect and chip select for the SD slot. */ -#if defined(CONFIG_LPC17_SSP0) && defined(CONFIG_MMCSD_SPI) - (void)lpc17_configgpio(C027_SD_CS); - (void)lpc17_configgpio(C027_SD_CD); +#if defined(CONFIG_LPC17_40_SSP0) && defined(CONFIG_MMCSD_SPI) + (void)lpc17_40_configgpio(C027_SD_CS); + (void)lpc17_40_configgpio(C027_SD_CD); #endif ssp_dumpgpio("c027_sspdev_initialize() Exit"); } /************************************************************************************ - * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * Name: lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * * Description: - * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * The external functions, lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc17_sspbus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * 2. Provide lpc17_40_ssp0/ssp1select() and lpc17_40_ssp0/ssp1status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc17_sspbus_initialize() in your low level application + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_ssp0select() Entry"); + ssp_dumpgpio("lpc17_40_ssp0select() Entry"); #warning "Assert CS here (false)" - ssp_dumpgpio("lpc17_ssp0select() Exit"); + ssp_dumpgpio("lpc17_40_ssp0select() Exit"); } -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; } #endif -#ifdef CONFIG_LPC17_SSP1 -void lpc17_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_ssp1select() Entry"); + ssp_dumpgpio("lpc17_40_ssp1select() Entry"); if (devid == SPIDEV_MMCSD(0)) { /* Assert/de-assert the CS pin to the card */ - (void)lpc17_gpiowrite(C027_SD_CS, !selected); + (void)lpc17_40_gpiowrite(C027_SD_CS, !selected); } #ifdef CONFIG_NX_LCDDRIVER else if (devid == SPIDEV_DISPLAY(0)) { /* Assert the CS pin to the OLED display */ - (void)lpc17_gpiowrite(C027_OLED_CS, !selected); + (void)lpc17_40_gpiowrite(C027_OLED_CS, !selected); } #endif - ssp_dumpgpio("lpc17_ssp1select() Exit"); + ssp_dumpgpio("lpc17_40_ssp1select() Exit"); } -uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) { if (devid == SPIDEV_MMCSD(0)) { /* Read the state of the card-detect bit */ - if (lpc17_gpioread(C027_SD_CD) == 0) + if (lpc17_40_gpioread(C027_SD_CD) == 0) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; @@ -178,4 +178,4 @@ uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) } #endif -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 */ diff --git a/configs/u-blox-c027/src/lpc17_ubxmdm.c b/configs/u-blox-c027/src/lpc17_40_ubxmdm.c similarity index 65% rename from configs/u-blox-c027/src/lpc17_ubxmdm.c rename to configs/u-blox-c027/src/lpc17_40_ubxmdm.c index 2e333a8fcb9..32cb1e50022 100644 --- a/configs/u-blox-c027/src/lpc17_ubxmdm.c +++ b/configs/u-blox-c027/src/lpc17_40_ubxmdm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/u-blox-c027/src/lpc17_ubxmdm.c + * config/u-blox-c027/src/lpc17_40_ubxmdm.c * * Copyright (C) 2016 Vladimir Komendantskiy. All rights reserved. * Author: Vladimir Komendantskiy @@ -53,7 +53,7 @@ #include #include -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "u-blox-c027.h" /**************************************************************************** @@ -71,8 +71,8 @@ #endif #define UBXMDM_REGISTER_COUNT \ - (sizeof(lpc17_ubxmdm_name_pins) / \ - sizeof(struct lpc17_name_pin)) + (sizeof(lpc17_40_ubxmdm_name_pins) / \ + sizeof(struct lpc17_40_name_pin)) /**************************************************************************** * Private Types @@ -80,35 +80,35 @@ /* Core interface pin connections. These do not include UART or USB pins. */ -struct lpc17_ubxmdm_pins +struct lpc17_40_ubxmdm_pins { - lpc17_pinset_t ldo_enable; - lpc17_pinset_t power_on_n; - lpc17_pinset_t reset_n; - lpc17_pinset_t shifter_en_n; - lpc17_pinset_t usb_detect; + lpc17_40_pinset_t ldo_enable; + lpc17_40_pinset_t power_on_n; + lpc17_40_pinset_t reset_n; + lpc17_40_pinset_t shifter_en_n; + lpc17_40_pinset_t usb_detect; }; /* This structure type provides the private representation of the "lower-half" * driver state. This type must be coercible to type 'ubxmdm_lower'. */ -struct lpc17_ubxmdm_lower +struct lpc17_40_ubxmdm_lower { FAR const struct ubxmdm_ops* ops; /* Lower half operations */ /* Private, architecture-specific information. */ - FAR const struct lpc17_ubxmdm_pins* pins; + FAR const struct lpc17_40_ubxmdm_pins* pins; bool usb_used; }; /* Pair type for associating a register name to a pin. */ -struct lpc17_name_pin +struct lpc17_40_name_pin { const char name[3]; - const lpc17_pinset_t pin; + const lpc17_40_pinset_t pin; }; /**************************************************************************** @@ -117,25 +117,25 @@ struct lpc17_name_pin /* "Lower half" driver methods **********************************************/ -static int lpc17_poweron (FAR struct ubxmdm_lower* lower); -static int lpc17_poweroff (FAR struct ubxmdm_lower* lower); -static int lpc17_reset (FAR struct ubxmdm_lower* lower); -static int lpc17_getstatus(FAR struct ubxmdm_lower* lower, +static int lpc17_40_poweron (FAR struct ubxmdm_lower* lower); +static int lpc17_40_poweroff (FAR struct ubxmdm_lower* lower); +static int lpc17_40_reset (FAR struct ubxmdm_lower* lower); +static int lpc17_40_getstatus(FAR struct ubxmdm_lower* lower, FAR struct ubxmdm_status* status); -static int lpc17_ioctl (FAR struct ubxmdm_lower* lower, +static int lpc17_40_ioctl (FAR struct ubxmdm_lower* lower, int cmd, unsigned long arg); /* "Lower half" driver state */ -static struct lpc17_ubxmdm_lower lpc17_ubxmdm_lower; +static struct lpc17_40_ubxmdm_lower lpc17_40_ubxmdm_lower; /**************************************************************************** * Private Data ****************************************************************************/ /* "Lower half" driver methods */ -static const struct lpc17_ubxmdm_pins lpc17_ubxmdm_pins = +static const struct lpc17_40_ubxmdm_pins lpc17_40_ubxmdm_pins = { .ldo_enable = C027_MDMLDOEN, .power_on_n = C027_MDMPWR, @@ -144,16 +144,16 @@ static const struct lpc17_ubxmdm_pins lpc17_ubxmdm_pins = .usb_detect = C027_MDMUSBDET, }; -static const struct ubxmdm_ops lpc17_ubxmdm_ops = +static const struct ubxmdm_ops lpc17_40_ubxmdm_ops = { - .poweron = lpc17_poweron, - .poweroff = lpc17_poweroff, - .reset = lpc17_reset, - .getstatus = lpc17_getstatus, - .ioctl = lpc17_ioctl, + .poweron = lpc17_40_poweron, + .poweroff = lpc17_40_poweroff, + .reset = lpc17_40_reset, + .getstatus = lpc17_40_getstatus, + .ioctl = lpc17_40_ioctl, }; -static const struct lpc17_name_pin lpc17_ubxmdm_name_pins[] = +static const struct lpc17_40_name_pin lpc17_40_ubxmdm_name_pins[] = { {{'T','X','D'}, GPIO_UART1_TXD}, {{'R','X','D'}, GPIO_UART1_RXD}, @@ -175,14 +175,14 @@ static const struct lpc17_name_pin lpc17_ubxmdm_name_pins[] = * Private Functions ****************************************************************************/ -static int lpc17_poweron(FAR struct ubxmdm_lower* lower) +static int lpc17_40_poweron(FAR struct ubxmdm_lower* lower) { - FAR struct lpc17_ubxmdm_lower* priv = - (FAR struct lpc17_ubxmdm_lower*) lower; - lpc17_pinset_t usb_detect_val; + FAR struct lpc17_40_ubxmdm_lower* priv = + (FAR struct lpc17_40_ubxmdm_lower*) lower; + lpc17_40_pinset_t usb_detect_val; - lpc17_configgpio(priv->pins->reset_n | GPIO_VALUE_ONE); /* Modem not in reset */ - lpc17_configgpio(priv->pins->power_on_n | GPIO_VALUE_ZERO); /* Switch closed to GND */ + lpc17_40_configgpio(priv->pins->reset_n | GPIO_VALUE_ONE); /* Modem not in reset */ + lpc17_40_configgpio(priv->pins->power_on_n | GPIO_VALUE_ZERO); /* Switch closed to GND */ nxsig_usleep(10 * 1000); /* Min. time for power_on_n being low is 5 ms */ if (priv->usb_used) @@ -194,54 +194,54 @@ static int lpc17_poweron(FAR struct ubxmdm_lower* lower) usb_detect_val = GPIO_VALUE_ZERO; /* USB sense off */ } - lpc17_configgpio(priv->pins->usb_detect | usb_detect_val); + lpc17_40_configgpio(priv->pins->usb_detect | usb_detect_val); - lpc17_configgpio(priv->pins->ldo_enable | GPIO_VALUE_ONE); /* LDO enabled */ + lpc17_40_configgpio(priv->pins->ldo_enable | GPIO_VALUE_ONE); /* LDO enabled */ nxsig_usleep(1 * 1000); /* Delay to obtain correct voltage on shifters */ - lpc17_configgpio(priv->pins->shifter_en_n | GPIO_VALUE_ZERO); /* UART shifter enabled */ -/* lpc17_configgpio(priv->pins->power_on_n | GPIO_VALUE_ONE); * Stop current through switch */ + lpc17_40_configgpio(priv->pins->shifter_en_n | GPIO_VALUE_ZERO); /* UART shifter enabled */ +/* lpc17_40_configgpio(priv->pins->power_on_n | GPIO_VALUE_ONE); * Stop current through switch */ return OK; } -static int lpc17_poweroff(FAR struct ubxmdm_lower* lower) +static int lpc17_40_poweroff(FAR struct ubxmdm_lower* lower) { - FAR struct lpc17_ubxmdm_lower* priv = - (FAR struct lpc17_ubxmdm_lower*) lower; + FAR struct lpc17_40_ubxmdm_lower* priv = + (FAR struct lpc17_40_ubxmdm_lower*) lower; - lpc17_configgpio(priv->pins->ldo_enable | GPIO_VALUE_ZERO); /* LDO disabled */ - lpc17_configgpio(priv->pins->reset_n | GPIO_VALUE_ONE); /* Modem not in reset */ - lpc17_configgpio(priv->pins->power_on_n | GPIO_VALUE_ONE); /* Switch open */ - lpc17_configgpio(priv->pins->shifter_en_n | GPIO_VALUE_ONE); /* UART shifter disabled */ - lpc17_configgpio(priv->pins->usb_detect | GPIO_VALUE_ZERO); /* USB sense off */ + lpc17_40_configgpio(priv->pins->ldo_enable | GPIO_VALUE_ZERO); /* LDO disabled */ + lpc17_40_configgpio(priv->pins->reset_n | GPIO_VALUE_ONE); /* Modem not in reset */ + lpc17_40_configgpio(priv->pins->power_on_n | GPIO_VALUE_ONE); /* Switch open */ + lpc17_40_configgpio(priv->pins->shifter_en_n | GPIO_VALUE_ONE); /* UART shifter disabled */ + lpc17_40_configgpio(priv->pins->usb_detect | GPIO_VALUE_ZERO); /* USB sense off */ return OK; } -static int lpc17_reset(FAR struct ubxmdm_lower* lower) +static int lpc17_40_reset(FAR struct ubxmdm_lower* lower) { - FAR struct lpc17_ubxmdm_lower* priv = - (FAR struct lpc17_ubxmdm_lower*) lower; + FAR struct lpc17_40_ubxmdm_lower* priv = + (FAR struct lpc17_40_ubxmdm_lower*) lower; - lpc17_configgpio(priv->pins->reset_n | GPIO_VALUE_ZERO); /* Modem in reset */ + lpc17_40_configgpio(priv->pins->reset_n | GPIO_VALUE_ZERO); /* Modem in reset */ nxsig_usleep(75 * 1000); /* The minimum reset_n low time is 50 ms */ - lpc17_configgpio(priv->pins->reset_n | GPIO_VALUE_ONE); /* Modem not in reset */ + lpc17_40_configgpio(priv->pins->reset_n | GPIO_VALUE_ONE); /* Modem not in reset */ return OK; } -static int lpc17_getstatus(FAR struct ubxmdm_lower* lower, +static int lpc17_40_getstatus(FAR struct ubxmdm_lower* lower, FAR struct ubxmdm_status* status) { - FAR struct lpc17_ubxmdm_lower* priv = - (FAR struct lpc17_ubxmdm_lower*) lower; + FAR struct lpc17_40_ubxmdm_lower* priv = + (FAR struct lpc17_40_ubxmdm_lower*) lower; int i; status->on = - lpc17_gpioread(priv->pins->ldo_enable) && - lpc17_gpioread(priv->pins->reset_n) && - !lpc17_gpioread(priv->pins->shifter_en_n); + lpc17_40_gpioread(priv->pins->ldo_enable) && + lpc17_40_gpioread(priv->pins->reset_n) && + !lpc17_40_gpioread(priv->pins->shifter_en_n); DEBUGASSERT(status->register_values_size >= UBXMDM_REGISTER_COUNT); status->register_values_size = UBXMDM_REGISTER_COUNT; @@ -249,16 +249,16 @@ static int lpc17_getstatus(FAR struct ubxmdm_lower* lower, for (i = 0; i < UBXMDM_REGISTER_COUNT; i++) { strncpy(status->register_values[i].name, - lpc17_ubxmdm_name_pins[i].name, + lpc17_40_ubxmdm_name_pins[i].name, 3); status->register_values[i].val = - lpc17_gpioread(lpc17_ubxmdm_name_pins[i].pin); + lpc17_40_gpioread(lpc17_40_ubxmdm_name_pins[i].pin); } return OK; } -static int lpc17_ioctl(FAR struct ubxmdm_lower* lower, +static int lpc17_40_ioctl(FAR struct ubxmdm_lower* lower, int cmd, unsigned long arg) { @@ -272,7 +272,7 @@ static int lpc17_ioctl(FAR struct ubxmdm_lower* lower, ****************************************************************************/ /**************************************************************************** - * Name: lpc17_ubxmdm_init + * Name: lpc17_40_ubxmdm_init * * Description: * Initialize the modem. The modem is initialized and @@ -286,9 +286,9 @@ static int lpc17_ioctl(FAR struct ubxmdm_lower* lower, * ****************************************************************************/ -void lpc17_ubxmdm_init(bool usb_used) +void lpc17_40_ubxmdm_init(bool usb_used) { - FAR struct lpc17_ubxmdm_lower* priv = &lpc17_ubxmdm_lower; + FAR struct lpc17_40_ubxmdm_lower* priv = &lpc17_40_ubxmdm_lower; DEBUGASSERT(priv->ops == NULL && priv->pins == NULL); @@ -297,11 +297,11 @@ void lpc17_ubxmdm_init(bool usb_used) * is only called once so it is never necessary to re-zero the structure. */ - priv->ops = &lpc17_ubxmdm_ops; - priv->pins = &lpc17_ubxmdm_pins; + priv->ops = &lpc17_40_ubxmdm_ops; + priv->pins = &lpc17_40_ubxmdm_pins; priv->usb_used = usb_used; - lpc17_poweroff((FAR struct ubxmdm_lower*) priv); + lpc17_40_poweroff((FAR struct ubxmdm_lower*) priv); (void) ubxmdm_register("/dev/ubxmdm", (FAR struct ubxmdm_lower*) priv); } diff --git a/configs/u-blox-c027/src/lpc17_usbmsc.c b/configs/u-blox-c027/src/lpc17_40_usbmsc.c similarity index 81% rename from configs/u-blox-c027/src/lpc17_usbmsc.c rename to configs/u-blox-c027/src/lpc17_40_usbmsc.c index 3a4f54d419a..77d070d20ea 100644 --- a/configs/u-blox-c027/src/lpc17_usbmsc.c +++ b/configs/u-blox-c027/src/lpc17_40_usbmsc.c @@ -1,10 +1,10 @@ /**************************************************************************** - * configs/u-blox-c027/src/lpc17_usbmsc.c + * configs/u-blox-c027/src/lpc17_40_usbmsc.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Configure and register the LPC17xx MMC/SD SPI block driver. + * Configure and register the LPC17xx/LPC40xx MMC/SD SPI block driver. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -49,7 +49,7 @@ #include #include -#include "lpc17_ssp.h" +#include "lpc17_40_ssp.h" /**************************************************************************** * Pre-processor Definitions @@ -64,14 +64,14 @@ /* PORT and SLOT number probably depend on the board configuration */ #ifdef CONFIG_ARCH_BOARD_U_BLOX_C027 -# undef LPC17XX_MMCSDSPIPORTNO -# define LPC17XX_MMCSDSPIPORTNO 0 -# undef LPC17XX_MMCSDSLOTNO -# define LPC17XX_MMCSDSLOTNO 0 +# undef LPC17XX_40XX_MMCSDSPIPORTNO +# define LPC17XX_40XX_MMCSDSPIPORTNO 0 +# undef LPC17XX_40XX_MMCSDSLOTNO +# define LPC17XX_40XX_MMCSDSLOTNO 0 #else - /* Add configuration for new LPC17xx boards here */ + /* Add configuration for new LPC17xx/LPC40xx boards here */ -# error "Unrecognized LPC17xx board" +# error "Unrecognized LPC17xx/LPC40xx board" #endif /**************************************************************************** @@ -94,34 +94,34 @@ int board_usbmsc_initialize(int port) /* Get the SPI port */ - syslog(LOG_INFO, "Initializing SPI port %d\n", LPC17XX_MMCSDSPIPORTNO); + syslog(LOG_INFO, "Initializing SPI port %d\n", LPC17XX_40XX_MMCSDSPIPORTNO); - spi = lpc17_sspbus_initialize(LPC17XX_MMCSDSPIPORTNO); + spi = lpc17_40_sspbus_initialize(LPC17XX_40XX_MMCSDSPIPORTNO); if (!spi) { syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); return -ENODEV; } syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); /* Bind the SPI port to the slot */ syslog(LOG_INFO, "Binding SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); - ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, LPC17XX_MMCSDSLOTNO, spi); + ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, LPC17XX_40XX_MMCSDSLOTNO, spi); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO, ret); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO, ret); return ret; } syslog(LOG_INFO, "Successfully bound SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); return OK; } diff --git a/configs/u-blox-c027/src/u-blox-c027.h b/configs/u-blox-c027/src/u-blox-c027.h index edeb43dbe10..4104efe671a 100644 --- a/configs/u-blox-c027/src/u-blox-c027.h +++ b/configs/u-blox-c027/src/u-blox-c027.h @@ -50,7 +50,7 @@ #define C027_LED (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT3 | GPIO_PIN25) #define C027_SD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT2 | GPIO_PIN2) -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ # define C027_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) #else # define C027_SD_CD (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) @@ -91,7 +91,7 @@ void weak_function c027_sspdev_initialize(void); /************************************************************************************ - * Name: lpc17_ubxmdm_init + * Name: lpc17_40_ubxmdm_init * * Description: * Initialisation function for the u-blox modem. @@ -99,11 +99,11 @@ void weak_function c027_sspdev_initialize(void); ************************************************************************************/ #if defined(CONFIG_MODEM_U_BLOX) -void lpc17_ubxmdm_init(bool usb_used); +void lpc17_40_ubxmdm_init(bool usb_used); #endif /* CONFIG_MODEM_U_BLOX */ /************************************************************************************ - * Name: lpc17_pwm_setup + * Name: lpc17_40_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -111,11 +111,11 @@ void lpc17_ubxmdm_init(bool usb_used); ************************************************************************************/ #ifdef CONFIG_PWM -int lpc17_pwm_setup(void); +int lpc17_40_pwm_setup(void); #endif /************************************************************************************ - * Name: lpc17_adc_setup + * Name: lpc17_40_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -123,7 +123,7 @@ int lpc17_pwm_setup(void); ************************************************************************************/ #ifdef CONFIG_ADC -int lpc17_adc_setup(void); +int lpc17_40_adc_setup(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/zkit-arm-1769/README.txt b/configs/zkit-arm-1769/README.txt index cb3a55b523d..f975c11767f 100644 --- a/configs/zkit-arm-1769/README.txt +++ b/configs/zkit-arm-1769/README.txt @@ -239,41 +239,41 @@ ZKit-ARM Configuration Options CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. Individual subsystems can be enabled: - CONFIG_LPC17_MAINOSC=y - CONFIG_LPC17_PLL0=y - CONFIG_LPC17_PLL1=n - CONFIG_LPC17_ETHERNET=n - CONFIG_LPC17_USBHOST=n - CONFIG_LPC17_USBOTG=n - CONFIG_LPC17_USBDEV=n - CONFIG_LPC17_UART0=y - CONFIG_LPC17_UART1=n - CONFIG_LPC17_UART2=n - CONFIG_LPC17_UART3=n - CONFIG_LPC17_CAN1=n - CONFIG_LPC17_CAN2=n - CONFIG_LPC17_SPI=n - CONFIG_LPC17_SSP0=n - CONFIG_LPC17_SSP1=n - CONFIG_LPC17_I2C0=n - CONFIG_LPC17_I2C1=n - CONFIG_LPC17_I2S=n - CONFIG_LPC17_TMR0=n - CONFIG_LPC17_TMR1=n - CONFIG_LPC17_TMR2=n - CONFIG_LPC17_TMR3=n - CONFIG_LPC17_RIT=n - CONFIG_LPC17_PWM0=n - CONFIG_LPC17_MCPWM=n - CONFIG_LPC17_QEI=n - CONFIG_LPC17_RTC=n - CONFIG_LPC17_WDT=n - CONFIG_LPC17_ADC=n - CONFIG_LPC17_DAC=n - CONFIG_LPC17_GPDMA=n - CONFIG_LPC17_FLASH=n + CONFIG_LPC17_40_MAINOSC=y + CONFIG_LPC17_40_PLL0=y + CONFIG_LPC17_40_PLL1=n + CONFIG_LPC17_40_ETHERNET=n + CONFIG_LPC17_40_USBHOST=n + CONFIG_LPC17_40_USBOTG=n + CONFIG_LPC17_40_USBDEV=n + CONFIG_LPC17_40_UART0=y + CONFIG_LPC17_40_UART1=n + CONFIG_LPC17_40_UART2=n + CONFIG_LPC17_40_UART3=n + CONFIG_LPC17_40_CAN1=n + CONFIG_LPC17_40_CAN2=n + CONFIG_LPC17_40_SPI=n + CONFIG_LPC17_40_SSP0=n + CONFIG_LPC17_40_SSP1=n + CONFIG_LPC17_40_I2C0=n + CONFIG_LPC17_40_I2C1=n + CONFIG_LPC17_40_I2S=n + CONFIG_LPC17_40_TMR0=n + CONFIG_LPC17_40_TMR1=n + CONFIG_LPC17_40_TMR2=n + CONFIG_LPC17_40_TMR3=n + CONFIG_LPC17_40_RIT=n + CONFIG_LPC17_40_PWM0=n + CONFIG_LPC17_40_MCPWM=n + CONFIG_LPC17_40_QEI=n + CONFIG_LPC17_40_RTC=n + CONFIG_LPC17_40_WDT=n + CONFIG_LPC17_40_ADC=n + CONFIG_LPC17_40_DAC=n + CONFIG_LPC17_40_GPDMA=n + CONFIG_LPC17_40_FLASH=n - LPC17xx specific device driver settings + LPC17xx/LPC40xx specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -286,78 +286,78 @@ ZKit-ARM Configuration Options CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_UARTn_2STOP - Two stop bits - LPC17xx specific CAN device driver settings. These settings all + LPC17xx/LPC40xx specific CAN device driver settings. These settings all require CONFIG_CAN: CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. - CONFIG_LPC17_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 + CONFIG_LPC17_40_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN1 is defined. - CONFIG_LPC17_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 + CONFIG_LPC17_40_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_40_CAN2 is defined. - CONFIG_LPC17_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this + CONFIG_LPC17_40_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. - CONFIG_LPC17_CAN_TSEG1 - The number of CAN time quanta in segment 1. + CONFIG_LPC17_40_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 - CONFIG_LPC17_CAN_TSEG2 = the number of CAN time quanta in segment 2. + CONFIG_LPC17_40_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 - LPC17xx specific PHY/Ethernet device driver settings. These setting - also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + LPC17xx/LPC40xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_40_ETHERNET. CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY - CONFIG_LPC17_PHY_AUTONEG - Enable auto-negotion - CONFIG_LPC17_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. - CONFIG_LPC17_PHY_FDUPLEX - Select full (vs. half) duplex + CONFIG_LPC17_40_PHY_AUTONEG - Enable auto-negotion + CONFIG_LPC17_40_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_LPC17_40_PHY_FDUPLEX - Select full (vs. half) duplex - CONFIG_LPC17_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb - CONFIG_LPC17_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 - CONFIG_LPC17_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 - CONFIG_LPC17_ETH_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_LPC17_40_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_LPC17_40_ETH_WOL - Enable Wake-up on Lan (not fully implemented). CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. Also needs CONFIG_DEBUG_FEATURES. - CONFIG_LPC17_ETH_HASH - Enable receipt of near-perfect match frames. - CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + CONFIG_LPC17_40_ETH_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_40_MULTICAST - Enable receipt of multicast (and unicast) frames. Automatically set if CONFIG_NET_MCASTGROUP is selected. - LPC17xx USB Device Configuration + LPC17xx/LPC40xx USB Device Configuration - CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + CONFIG_LPC17_40_USBDEV_FRAME_INTERRUPT Handle USB Start-Of-Frame events. Enable reading SOF from interrupt handler vs. simply reading on demand. Probably a bad idea... Unless there is some issue with sampling the SOF from hardware asynchronously. - CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + CONFIG_LPC17_40_USBDEV_EPFAST_INTERRUPT Enable high priority interrupts. I have no idea why you might want to do that - CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS Number of DMA descriptors to allocate in SRAM. - CONFIG_LPC17_USBDEV_DMA - Enable lpc17xx-specific DMA support - CONFIG_LPC17_USBDEV_NOVBUS + CONFIG_LPC17_40_USBDEV_DMA + Enable lpc17xx/lpc40xx-specific DMA support + CONFIG_LPC17_40_USBDEV_NOVBUS Define if the hardware implementation does not support the VBUS signal - CONFIG_LPC17_USBDEV_NOLED + CONFIG_LPC17_40_USBDEV_NOLED Define if the hardware implementation does not support the LED output - LPC17xx USB Host Configuration (the ZKit-ARM does not support USB Host) + LPC17xx/LPC40xx USB Host Configuration (the ZKit-ARM does not support USB Host) - CONFIG_LPC17_OHCIRAM_SIZE + CONFIG_LPC17_40_OHCIRAM_SIZE Total size of OHCI RAM (in AHB SRAM Bank 1) CONFIG_LP17_USBHOST_NEDS Number of endpoint descriptors CONFIG_LP17_USBHOST_NTDS Number of transfer descriptors - CONFIG_LPC17_USBHOST_TDBUFFERS + CONFIG_LPC17_40_USBHOST_TDBUFFERS Number of transfer descriptor buffers - CONFIG_LPC17_USBHOST_TDBUFSIZE + CONFIG_LPC17_40_USBHOST_TDBUFSIZE Size of one transfer descriptor buffer - CONFIG_LPC17_USBHOST_IOBUFSIZE + CONFIG_LPC17_40_USBHOST_IOBUFSIZE Size of one end-user I/O buffer. This can be zero if the application can guarantee that all end-user I/O buffers reside in AHB SRAM. diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index e3a29584ce6..42ae79093cb 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="zkit-arm-1769" CONFIG_ARCH_BOARD_ZKITARM=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -22,10 +22,10 @@ CONFIG_ETH0_PHY_DP83848C=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=15776 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=15776 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/configs/zkit-arm-1769/include/board.h b/configs/zkit-arm-1769/include/board.h index 0e69f32971b..908e0e61b79 100644 --- a/configs/zkit-arm-1769/include/board.h +++ b/configs/zkit-arm-1769/include/board.h @@ -50,7 +50,7 @@ #include -#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) # include #endif @@ -58,7 +58,7 @@ * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ -/* NOTE: The following definitions require lpc17_syscon.h. It is not included here +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here * because the including C file may not have that file in its include path. */ @@ -74,14 +74,14 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz */ +#define LPC17_40_CCLK 80000000 /* 80Mhz */ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency * of the main oscillator. */ -#undef CONFIG_LPC17_MAINOSC -#define CONFIG_LPC17_MAINOSC 1 +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 #define BOARD_SCS_VALUE SYSCON_SCS_OSCEN /* Select the main oscillator and CCLK divider. The output of the divider is CCLK. @@ -100,8 +100,8 @@ * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ -#undef CONFIG_LPC17_PLL0 -#define CONFIG_LPC17_PLL0 1 +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 @@ -112,7 +112,7 @@ /* PLL1 -- Not used. */ -#undef CONFIG_LPC17_PLL1 +#undef CONFIG_LPC17_40_PLL1 #define BOARD_PLL1CFG_MSEL 36 #define BOARD_PLL1CFG_NSEL 1 #define BOARD_PLL1CFG_VALUE \ @@ -169,7 +169,7 @@ #define LED_STACKCREATED 3 /* OFF OFF */ /* After the system is booted, this logic will no longer use LED 1. - * LED 1 is available for use by application software using lpc17_led + * LED 1 is available for use by application software using lpc17_40_led * (prototyped below) */ /* LED1 LED2 */ @@ -332,7 +332,7 @@ extern "C" { ************************************************************************************/ /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, these functions can be used to control LEDs 1 @@ -340,7 +340,7 @@ extern "C" { ************************************************************************************/ #ifdef CONFIG_ARCH_LEDS -void lpc17_led(int lednum, int state); +void lpc17_40_led(int lednum, int state); #endif #undef EXTERN diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 524f500c05a..fd409df7d92 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="zkit-arm-1769" CONFIG_ARCH_BOARD_ZKITARM=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -28,13 +28,13 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SPI=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SPI=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index ba2777df63b..b421edba1cd 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="zkit-arm-1769" CONFIG_ARCH_BOARD_ZKITARM=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -35,13 +35,13 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_ST7567=y -CONFIG_LPC17_EMACRAM_SIZE=7296 -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=6 -CONFIG_LPC17_ETH_NTXDESC=6 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_SSP0=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_EMACRAM_SIZE=7296 +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=6 +CONFIG_LPC17_40_ETH_NTXDESC=6 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_SSP0=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MMCSD=y diff --git a/configs/zkit-arm-1769/src/Makefile b/configs/zkit-arm-1769/src/Makefile index 9e1a628a184..d72274fa451 100644 --- a/configs/zkit-arm-1769/src/Makefile +++ b/configs/zkit-arm-1769/src/Makefile @@ -41,30 +41,30 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_buttons.c lpc17_lcd.c +CSRCS = lpc17_40_boot.c lpc17_40_leds.c lpc17_40_ssp.c lpc17_40_buttons.c lpc17_40_lcd.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += lpc17_appinit.c +CSRCS += lpc17_40_appinit.c endif ifeq ($(CONFIG_USBMSC),y) -CSRCS += lpc17_usbmsc.c +CSRCS += lpc17_40_usbmsc.c endif ifeq ($(CONFIG_ADC),y) -CSRCS += lpc17_adc.c +CSRCS += lpc17_40_adc.c endif ifeq ($(CONFIG_DAC),y) -CSRCS += lpc17_dac.c +CSRCS += lpc17_40_dac.c endif ifeq ($(CONFIG_CAN),y) -CSRCS += lpc17_can.c +CSRCS += lpc17_40_can.c endif -ifeq ($(CONFIG_LPC17_SPI),y) -CSRCS += lpc17_spi.c +ifeq ($(CONFIG_LPC17_40_SPI),y) +CSRCS += lpc17_40_spi.c endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/zkit-arm-1769/src/lpc17_adc.c b/configs/zkit-arm-1769/src/lpc17_40_adc.c similarity index 94% rename from configs/zkit-arm-1769/src/lpc17_adc.c rename to configs/zkit-arm-1769/src/lpc17_40_adc.c index 207aa83f82c..629e18a3036 100644 --- a/configs/zkit-arm-1769/src/lpc17_adc.c +++ b/configs/zkit-arm-1769/src/lpc17_40_adc.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_adc.c + * configs/zkit-arm-1769/src/lpc17_40_adc.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * Based on configs/stm3220g-eval/src/lpc17_adc.c + * Based on configs/stm3220g-eval/src/lpc17_40_adc.c * * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,7 +54,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_adc.h" +#include "lpc17_40_adc.h" #include "zkit-arm-1769.h" #ifdef CONFIG_ADC @@ -93,9 +93,9 @@ int zkit_adc_setup(void) if (!initialized) { - /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + /* Call lpc17_40_adcinitialize() to get an instance of the ADC interface */ - adc = lpc17_adcinitialize(); + adc = lpc17_40_adcinitialize(); if (adc == NULL) { aerr("ERROR: ERROR: Failed to get ADC interface\n"); diff --git a/configs/zkit-arm-1769/src/lpc17_appinit.c b/configs/zkit-arm-1769/src/lpc17_40_appinit.c similarity index 96% rename from configs/zkit-arm-1769/src/lpc17_appinit.c rename to configs/zkit-arm-1769/src/lpc17_40_appinit.c index 91806952491..aec60f20363 100644 --- a/configs/zkit-arm-1769/src/lpc17_appinit.c +++ b/configs/zkit-arm-1769/src/lpc17_40_appinit.c @@ -1,10 +1,10 @@ /**************************************************************************** - * config/zkit-arm-1769/src/lpc17_appinit.c + * config/zkit-arm-1769/src/lpc17_40_appinit.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: BabuSubashChandar * - * Based on config/lpcxpresso-lpc1768/src/lpc17_appinit.c + * Based on config/lpcxpresso-lpc1768/src/lpc17_40_appinit.c * * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,7 +52,7 @@ #include #include -#include "lpc17_spi.h" +#include "lpc17_40_spi.h" #include "zkit-arm-1769.h" /**************************************************************************** @@ -65,7 +65,7 @@ #ifdef CONFIG_ARCH_BOARD_ZKITARM # define CONFIG_NSH_HAVEUSBDEV 1 -# ifdef CONFIG_LPC17_SPI +# ifdef CONFIG_LPC17_40_SPI # define CONFIG_NSH_HAVEMMCSD 1 # else # undef CONFIG_NSH_HAVEMMCSD @@ -169,7 +169,7 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_NSH_HAVEMMCSD /* Get the SPI port */ - spi = lpc17_spibus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); + spi = lpc17_40_spibus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); if (!spi) { message("board_app_initialize: Failed to initialize SPI port %d\n", diff --git a/configs/zkit-arm-1769/src/lpc17_boot.c b/configs/zkit-arm-1769/src/lpc17_40_boot.c similarity index 91% rename from configs/zkit-arm-1769/src/lpc17_boot.c rename to configs/zkit-arm-1769/src/lpc17_40_boot.c index c1c9d9c0d63..18928c84f08 100644 --- a/configs/zkit-arm-1769/src/lpc17_boot.c +++ b/configs/zkit-arm-1769/src/lpc17_40_boot.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_boot.c + * configs/zkit-arm-1769/src/lpc17_40_boot.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: BabuSubashChandar * - * Based on configs/lpcxpresso-lpc1768/src/lpc17_boot.c + * Based on configs/lpcxpresso-lpc1768/src/lpc17_40_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -67,22 +67,22 @@ ************************************************************************************/ /************************************************************************************ - * Name: lpc17_boardinitialize + * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx architectures must provide the following entry point. This entry point + * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry point * is called early in the intitialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void lpc17_boardinitialize(void) +void lpc17_40_boardinitialize(void) { /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak * function zkit_sspdev_initialize() has been brought into the link. */ -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) if (zkit_sspdev_initialize) { zkit_sspdev_initialize(); diff --git a/configs/zkit-arm-1769/src/lpc17_buttons.c b/configs/zkit-arm-1769/src/lpc17_40_buttons.c similarity index 95% rename from configs/zkit-arm-1769/src/lpc17_buttons.c rename to configs/zkit-arm-1769/src/lpc17_40_buttons.c index 0c0de7dedd4..79e9e6ed2b8 100644 --- a/configs/zkit-arm-1769/src/lpc17_buttons.c +++ b/configs/zkit-arm-1769/src/lpc17_40_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/zkit-arm-1769/src/lpc17_buttons.c + * configs/zkit-arm-1769/src/lpc17_40_buttons.c * * Copyright (C) 2011 Zilogic Systems. All rights reserved. * Author: Kannan @@ -55,7 +55,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "zkit-arm-1769.h" #ifdef CONFIG_ARCH_BUTTONS @@ -101,7 +101,7 @@ void board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - lpc17_configgpio(g_buttons[i]); + lpc17_40_configgpio(g_buttons[i]); } } @@ -119,7 +119,7 @@ uint32_t board_buttons(void) for (i = 0; i < NUM_BUTTONS; i++) { - released = lpc17_gpioread(g_buttons[i]); + released = lpc17_40_gpioread(g_buttons[i]); /* Accumulate set of depressed keys */ @@ -154,7 +154,7 @@ uint32_t board_buttons(void) * ************************************************************************************/ -#if defined CONFIG_ARCH_IRQBUTTONS && CONFIG_LPC17_GPIOIRQ +#if defined CONFIG_ARCH_IRQBUTTONS && CONFIG_LPC17_40_GPIOIRQ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { irqstate_t flags; @@ -172,7 +172,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { /* Configure KEY5 as an interrupting input */ - lpc17_configgpio(ZKITARM_INT_KEY5); + lpc17_40_configgpio(ZKITARM_INT_KEY5); /* Attach the new interrupt handler and enable the interrupt */ @@ -191,7 +191,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Configure KEY5 as a non-interrupting input */ - lpc17_configgpio(ZKITARM_KEY5); + lpc17_40_configgpio(ZKITARM_KEY5); ret = OK; } diff --git a/configs/zkit-arm-1769/src/lpc17_can.c b/configs/zkit-arm-1769/src/lpc17_40_can.c similarity index 88% rename from configs/zkit-arm-1769/src/lpc17_can.c rename to configs/zkit-arm-1769/src/lpc17_40_can.c index 3815c7f1ef8..dbd06134b06 100644 --- a/configs/zkit-arm-1769/src/lpc17_can.c +++ b/configs/zkit-arm-1769/src/lpc17_40_can.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_can.c + * configs/zkit-arm-1769/src/lpc17_40_can.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Raashid Muhammed * - * Based on configs/olimex-lpc1766stk/src/lpc17_can.c + * Based on configs/olimex-lpc1766stk/src/lpc17_40_can.c * * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,7 +53,7 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_can.h" +#include "lpc17_40_can.h" #include "zkit-arm-1769.h" #ifdef CONFIG_CAN @@ -80,14 +80,14 @@ int zkit_can_setup(void) { -#if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) +#if defined(CONFIG_LPC17_40_CAN1) || defined(CONFIG_LPC17_40_CAN2) struct can_dev_s *can; int ret; -#ifdef CONFIG_LPC17_CAN1 - /* Call lpc17_caninitialize() to get an instance of the CAN1 interface */ +#ifdef CONFIG_LPC17_40_CAN1 + /* Call lpc17_40_caninitialize() to get an instance of the CAN1 interface */ - can = lpc17_caninitialize(CAN_PORT1); + can = lpc17_40_caninitialize(CAN_PORT1); if (can == NULL) { canerr("ERROR: Failed to get CAN1 interface\n"); @@ -104,10 +104,10 @@ int zkit_can_setup(void) } #endif -#ifdef CONFIG_LPC17_CAN2 - /* Call lpc17_caninitialize() to get an instance of the CAN2 interface */ +#ifdef CONFIG_LPC17_40_CAN2 + /* Call lpc17_40_caninitialize() to get an instance of the CAN2 interface */ - can = lpc17_caninitialize(CAN_PORT2); + can = lpc17_40_caninitialize(CAN_PORT2); if (can == NULL) { canerr("ERROR: Failed to get CAN2 interface\n"); diff --git a/configs/zkit-arm-1769/src/lpc17_dac.c b/configs/zkit-arm-1769/src/lpc17_40_dac.c similarity index 90% rename from configs/zkit-arm-1769/src/lpc17_dac.c rename to configs/zkit-arm-1769/src/lpc17_40_dac.c index 70616d39a45..d6bd65bbf50 100644 --- a/configs/zkit-arm-1769/src/lpc17_dac.c +++ b/configs/zkit-arm-1769/src/lpc17_40_dac.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_dac.c + * configs/zkit-arm-1769/src/lpc17_40_dac.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan * - * Based on configs/stm3220g-eval/src/lpc17_dac.c + * Based on configs/stm3220g-eval/src/lpc17_40_dac.c * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,7 +54,7 @@ #include "up_internal.h" #include "zkit-arm-1769.h" -#include "lpc17_dac.h" +#include "lpc17_40_dac.h" #ifdef CONFIG_DAC @@ -62,7 +62,7 @@ * Name: dac_devinit * * Description: - * All LPC17xx architectures must provide the following interface to work with + * All LPC17xx/LPC40xx architectures must provide the following interface to work with * examples/diag. * ************************************************************************************/ @@ -75,9 +75,9 @@ int dac_devinit(void) if (!initialized) { - /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ - dac = lpc17_dacinitialize(); + dac = lpc17_40_dacinitialize(); if (dac == NULL) { aerr("ERROR: Failed to get dac interface\n"); diff --git a/configs/zkit-arm-1769/src/lpc17_lcd.c b/configs/zkit-arm-1769/src/lpc17_40_lcd.c similarity index 90% rename from configs/zkit-arm-1769/src/lpc17_lcd.c rename to configs/zkit-arm-1769/src/lpc17_40_lcd.c index 8ae4bfbce07..0e7c55fe900 100644 --- a/configs/zkit-arm-1769/src/lpc17_lcd.c +++ b/configs/zkit-arm-1769/src/lpc17_40_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/zkit-arm-1769/src/lpc17_lcd.c + * configs/zkit-arm-1769/src/lpc17_40_lcd.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Manikandan @@ -58,8 +58,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" -#include "lpc17_ssp.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" #include "zkit-arm-1769.h" #ifdef CONFIG_NX_LCDDRIVER @@ -81,22 +81,22 @@ FAR struct lcd_dev_s *g_lcddev; int board_lcd_initialize(void) { - lpc17_configgpio(ZKITARM_OLED_RST); - lpc17_configgpio(ZKITARM_OLED_RS); - lpc17_gpiowrite(ZKITARM_OLED_RST, 1); - lpc17_gpiowrite(ZKITARM_OLED_RS, 1); + lpc17_40_configgpio(ZKITARM_OLED_RST); + lpc17_40_configgpio(ZKITARM_OLED_RS); + lpc17_40_gpiowrite(ZKITARM_OLED_RST, 1); + lpc17_40_gpiowrite(ZKITARM_OLED_RS, 1); zkit_sspdev_initialize(); - g_spidev = lpc17_sspbus_initialize(0); + g_spidev = lpc17_40_sspbus_initialize(0); if (!g_spidev) { lcderr("ERROR: Failed to initialize SSP port 0\n"); return -ENODEV; } - lpc17_gpiowrite(ZKITARM_OLED_RST, 0); + lpc17_40_gpiowrite(ZKITARM_OLED_RST, 0); up_mdelay(1); - lpc17_gpiowrite(ZKITARM_OLED_RST, 1); + lpc17_40_gpiowrite(ZKITARM_OLED_RST, 1); return OK; } @@ -134,7 +134,7 @@ void board_lcd_uninitialize(void) } /**************************************************************************** - * Name: lpc17_spicmddata + * Name: lpc17_40_spicmddata * * Description: * Set or clear the SD1329 D/Cn bit to select data (true) or command @@ -156,13 +156,13 @@ void board_lcd_uninitialize(void) * ****************************************************************************/ -int lpc17_ssp0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +int lpc17_40_ssp0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { if (devid == SPIDEV_DISPLAY(0)) { /* Set GPIO to 1 for data, 0 for command */ - lpc17_gpiowrite(ZKITARM_OLED_RS, !cmd); + lpc17_40_gpiowrite(ZKITARM_OLED_RS, !cmd); return OK; } diff --git a/configs/zkit-arm-1769/src/lpc17_leds.c b/configs/zkit-arm-1769/src/lpc17_40_leds.c similarity index 90% rename from configs/zkit-arm-1769/src/lpc17_leds.c rename to configs/zkit-arm-1769/src/lpc17_40_leds.c index 59c9fd6d838..74b868e2123 100644 --- a/configs/zkit-arm-1769/src/lpc17_leds.c +++ b/configs/zkit-arm-1769/src/lpc17_40_leds.c @@ -1,10 +1,10 @@ /**************************************************************************** - * configs/zkit-arm-1769/src/lpc17_leds.c + * configs/zkit-arm-1769/src/lpc17_40_leds.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: BabuSubashChandar * - * Based on configs/lpcxpresso-lpc1768/src/lpc17_leds.c + * Based on configs/lpcxpresso-lpc1768/src/lpc17_40_leds.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,7 +53,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_gpio.h" +#include "lpc17_40_gpio.h" #include "zkit-arm-1769.h" #ifdef CONFIG_ARCH_LEDS @@ -77,7 +77,7 @@ * STACKCREATED OFF OFF * * After the system is booted, this logic will no longer use LED 1. LED 1 - * is available for use by applications using lpc17_led (prototyped below) + * is available for use by applications using lpc17_40_led (prototyped below) */ /**************************************************************************** @@ -103,8 +103,8 @@ void board_autoled_initialize(void) { /* Configure all LED GPIO lines */ - lpc17_configgpio(ZKITARM_LED1); - lpc17_configgpio(ZKITARM_LED2); + lpc17_40_configgpio(ZKITARM_LED1); + lpc17_40_configgpio(ZKITARM_LED2); } /**************************************************************************** @@ -137,8 +137,8 @@ void board_autoled_on(int led) break; } - lpc17_gpiowrite(ZKITARM_LED1, led1); - lpc17_gpiowrite(ZKITARM_LED2, led2); + lpc17_40_gpiowrite(ZKITARM_LED1, led1); + lpc17_40_gpiowrite(ZKITARM_LED2, led2); } /* We will always control the HB LED */ @@ -149,7 +149,7 @@ void board_autoled_on(int led) case LED_SIGNAL: case LED_ASSERTION: case LED_PANIC: - lpc17_gpiowrite(ZKITARM_LED2, false); + lpc17_40_gpiowrite(ZKITARM_LED2, false); g_nestcount++; default: @@ -167,7 +167,7 @@ void board_autoled_off(int led) if (g_nestcount <= 1) { - lpc17_gpiowrite(ZKITARM_LED2, true); + lpc17_40_gpiowrite(ZKITARM_LED2, true); g_nestcount = 0; } else @@ -177,16 +177,16 @@ void board_autoled_off(int led) } /************************************************************************************ - * Name: lpc17_led + * Name: lpc17_40_led * * Description: * Once the system has booted, this functions can be used to control LED 1 * ************************************************************************************/ -void lpc17_led(int lednum, int state) +void lpc17_40_led(int lednum, int state) { - lpc17_gpiowrite(ZKITARM_LED1, state); + lpc17_40_gpiowrite(ZKITARM_LED1, state); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/zkit-arm-1769/src/lpc17_spi.c b/configs/zkit-arm-1769/src/lpc17_40_spi.c similarity index 78% rename from configs/zkit-arm-1769/src/lpc17_spi.c rename to configs/zkit-arm-1769/src/lpc17_40_spi.c index ec6d2773f45..198af02cb0a 100644 --- a/configs/zkit-arm-1769/src/lpc17_spi.c +++ b/configs/zkit-arm-1769/src/lpc17_40_spi.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_spi.c + * configs/zkit-arm-1769/src/lpc17_40_spi.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: Kannan @@ -53,11 +53,11 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_spi.h" -#include "lpc17_gpio.h" +#include "lpc17_40_spi.h" +#include "lpc17_40_gpio.h" #include "zkit-arm-1769.h" -#if defined(CONFIG_LPC17_SPI) +#if defined(CONFIG_LPC17_40_SPI) /************************************************************************************ * Pre-processor Definitions @@ -66,7 +66,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_SPI_INFO -# define spi_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) +# define spi_dumpgpio(m) lpc17_40_dumpgpio(SDCCS_GPIO, m) #else # define spi_dumpgpio(m) #endif @@ -92,59 +92,59 @@ void weak_function zkit_spidev_initialize(void) /* Configure card detect and chip select for the SD slot. */ - (void)lpc17_configgpio(ZKITARM_SD_CS); - (void)lpc17_configgpio(ZKITARM_SD_CD); + (void)lpc17_40_configgpio(ZKITARM_SD_CS); + (void)lpc17_40_configgpio(ZKITARM_SD_CD); spi_dumpgpio("zkit_spidev_initialize() Exit"); } /************************************************************************************ - * Name: lpc17_spiselect and lpc17_spistatus + * Name: lpc17_40_spiselect and lpc17_40_spistatus * * Description: - * The external functions, lpc17_spiselect and lpc17_spistatus + * The external functions, lpc17_40_spiselect and lpc17_40_spistatus * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc17_spibus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_spibus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc17_spiselect and lpc17_spistatus functions + * 2. Provide lpc17_40_spiselect and lpc17_40_spistatus functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc17_spibus_initialize() in your low level application + * 3. Add a calls to lpc17_40_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_spibus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_spibus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -void lpc17_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void lpc17_40_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - spi_dumpgpio("lpc17_spiselect() Entry"); + spi_dumpgpio("lpc17_40_spiselect() Entry"); if (devid == SPIDEV_MMCSD(0)) { /* Assert/de-assert the CS pin to the card */ - (void)lpc17_gpiowrite(ZKITARM_SD_CS, !selected); + (void)lpc17_40_gpiowrite(ZKITARM_SD_CS, !selected); } - spi_dumpgpio("lpc17_spiselect() Exit"); + spi_dumpgpio("lpc17_40_spiselect() Exit"); } -uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_spistatus(FAR struct spi_dev_s *dev, uint32_t devid) { if (devid == SPIDEV_MMCSD(0)) { /* Read the state of the card-detect bit */ - if (lpc17_gpioread(ZKITARM_SD_CD) == 0) + if (lpc17_40_gpioread(ZKITARM_SD_CD) == 0) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; @@ -157,16 +157,16 @@ uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA /**************************************************************************** - * Name: lpc17_spicmddata + * Name: lpc17_40_spicmddata * * Description: Dummy Function * ****************************************************************************/ -int lpc17_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +int lpc17_40_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_LPC17_SPI */ +#endif /* CONFIG_LPC17_40_SPI */ diff --git a/configs/zkit-arm-1769/src/lpc17_ssp.c b/configs/zkit-arm-1769/src/lpc17_40_ssp.c similarity index 73% rename from configs/zkit-arm-1769/src/lpc17_ssp.c rename to configs/zkit-arm-1769/src/lpc17_40_ssp.c index b34e102d434..d236e42c601 100644 --- a/configs/zkit-arm-1769/src/lpc17_ssp.c +++ b/configs/zkit-arm-1769/src/lpc17_40_ssp.c @@ -1,10 +1,10 @@ /************************************************************************************ - * configs/zkit-arm-1769/src/lpc17_ssp.c + * configs/zkit-arm-1769/src/lpc17_40_ssp.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: BabuSubashChandar * - * Based on configs/lpcxpresso-lpc1768/src/lpc17_ssp.c + * Based on configs/lpcxpresso-lpc1768/src/lpc17_40_ssp.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,11 +53,11 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_ssp.h" -#include "lpc17_gpio.h" +#include "lpc17_40_ssp.h" +#include "lpc17_40_gpio.h" #include "zkit-arm-1769.h" -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) /************************************************************************************ * Pre-processor Definitions @@ -66,7 +66,7 @@ /* Dump GPIO registers */ #ifdef CONFIG_DEBUG_SPI_INFO -# define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) +# define ssp_dumpgpio(m) lpc17_40_dumpgpio(SDCCS_GPIO, m) #else # define ssp_dumpgpio(m) #endif @@ -91,93 +91,93 @@ void weak_function zkit_sspdev_initialize(void) /* Configure chip select for the LCD. */ -#ifdef CONFIG_LPC17_SSP0 +#ifdef CONFIG_LPC17_40_SSP0 #ifdef CONFIG_NX_LCDDRIVER - (void)lpc17_configgpio(ZKITARM_OLED_CS); + (void)lpc17_40_configgpio(ZKITARM_OLED_CS); #endif -#endif /* CONFIG_LPC17_SSP0 */ +#endif /* CONFIG_LPC17_40_SSP0 */ ssp_dumpgpio("zkit_sspdev_initialize() Exit"); } /************************************************************************************ - * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * Name: lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * * Description: - * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * The external functions, lpc17_40_ssp0/ssp1select and lpc17_40_ssp0/ssp1status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including lpc17_sspbus_initialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx/LPC40xx logic. To use this common SPI logic on your * board: * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * pins. - * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * 2. Provide lpc17_40_ssp0/ssp1select() and lpc17_40_ssp0/ssp1status() functions * in your board-specific logic. These functions will perform chip selection * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to lpc17_sspbus_initialize() in your low level application + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * initialization logic - * 4. The handle returned by lpc17_sspbus_initialize() may then be used to bind the + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -#ifdef CONFIG_LPC17_SSP1 -void lpc17_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_ssp1select() Entry"); + ssp_dumpgpio("lpc17_40_ssp1select() Entry"); #warning "Assert CS here (false)" - ssp_dumpgpio("lpc17_ssp1select() Exit"); + ssp_dumpgpio("lpc17_40_ssp1select() Exit"); } -uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) { spiinfo("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; } /**************************************************************************** - * Name: lpc17_ssp1cmddata + * Name: lpc17_40_ssp1cmddata * * Description: Dummy Function * ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -int weak_function lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, +int weak_function lpc17_40_ssp1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_LPC17_SSP1 */ +#endif /* CONFIG_LPC17_40_SSP1 */ -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_ssp0select() Entry"); + ssp_dumpgpio("lpc17_40_ssp0select() Entry"); #ifdef CONFIG_NX_LCDDRIVER if (devid == SPIDEV_DISPLAY(0)) { /* Assert the CS pin to the OLED display */ - (void)lpc17_gpiowrite(ZKITARM_OLED_CS, !selected); + (void)lpc17_40_gpiowrite(ZKITARM_OLED_CS, !selected); } #endif - ssp_dumpgpio("lpc17_ssp0select() Exit"); + ssp_dumpgpio("lpc17_40_ssp0select() Exit"); } -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) { if (devid == SPIDEV_DISPLAY(0)) { @@ -189,5 +189,5 @@ uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) return 0; } -#endif /* CONFIG_LPC17_SSP0 */ -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +#endif /* CONFIG_LPC17_40_SSP0 */ +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 */ diff --git a/configs/zkit-arm-1769/src/lpc17_usbmsc.c b/configs/zkit-arm-1769/src/lpc17_40_usbmsc.c similarity index 81% rename from configs/zkit-arm-1769/src/lpc17_usbmsc.c rename to configs/zkit-arm-1769/src/lpc17_40_usbmsc.c index 3d51560056d..f229ba59d78 100644 --- a/configs/zkit-arm-1769/src/lpc17_usbmsc.c +++ b/configs/zkit-arm-1769/src/lpc17_40_usbmsc.c @@ -1,15 +1,15 @@ /**************************************************************************** - * configs/zkit-arm-1769/src/lpc17_usbmsc.c + * configs/zkit-arm-1769/src/lpc17_40_usbmsc.c * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: BabuSubashChandar * - * Based on configs/lpcxpresso-lpc1768/src/lpc17_usbmsc.c + * Based on configs/lpcxpresso-lpc1768/src/lpc17_40_usbmsc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Configure and register the LPC17xx MMC/SD SPI block driver. + * Configure and register the LPC17xx/LPC40xx MMC/SD SPI block driver. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,7 +54,7 @@ #include #include -#include "lpc17_spi.h" +#include "lpc17_40_spi.h" #include "zkit-arm-1769.h" /**************************************************************************** @@ -70,13 +70,13 @@ /* PORT and SLOT number probably depend on the board configuration */ #ifdef CONFIG_ARCH_BOARD_ZKITARM -# undef LPC17XX_MMCSDSPIPORTNO -# define LPC17XX_MMCSDSPIPORTNO 0 -# undef LPC17XX_MMCSDSLOTNO -# define LPC17XX_MMCSDSLOTNO 0 +# undef LPC17XX_40XX_MMCSDSPIPORTNO +# define LPC17XX_40XX_MMCSDSPIPORTNO 0 +# undef LPC17XX_40XX_MMCSDSLOTNO +# define LPC17XX_40XX_MMCSDSLOTNO 0 #else - /* Add configuration for new LPC17xx boards here */ -# error "Unrecognized LPC17xx board" + /* Add configuration for new LPC17xx/LPC40xx boards here */ +# error "Unrecognized LPC17xx/LPC40xx board" #endif /**************************************************************************** @@ -100,36 +100,36 @@ int board_usbmsc_initialize(int port) /* Get the SPI port */ syslog(LOG_INFO, "Initializing SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); zkit_spidev_initialize(); - spi = lpc17_spibus_initialize(LPC17XX_MMCSDSPIPORTNO); + spi = lpc17_40_spibus_initialize(LPC17XX_40XX_MMCSDSPIPORTNO); if (!spi) { syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); return -ENODEV; } syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - LPC17XX_MMCSDSPIPORTNO); + LPC17XX_40XX_MMCSDSPIPORTNO); /* Bind the SPI port to the slot */ syslog(LOG_INFO, "Binding SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, - LPC17XX_MMCSDSLOTNO, spi); + LPC17XX_40XX_MMCSDSLOTNO, spi); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO, ret); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO, ret); return ret; } syslog(LOG_INFO, "Successfully bound SPI port %d to MMC/SD slot %d\n", - LPC17XX_MMCSDSPIPORTNO, LPC17XX_MMCSDSLOTNO); + LPC17XX_40XX_MMCSDSPIPORTNO, LPC17XX_40XX_MMCSDSLOTNO); return OK; } diff --git a/configs/zkit-arm-1769/src/zkit-arm-1769.h b/configs/zkit-arm-1769/src/zkit-arm-1769.h index 1928c0bbb8d..a2016a0e47a 100644 --- a/configs/zkit-arm-1769/src/zkit-arm-1769.h +++ b/configs/zkit-arm-1769/src/zkit-arm-1769.h @@ -145,7 +145,7 @@ #define ZKITARM_KEY5 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN13) #define ZKITARM_INT_KEY5 (GPIO_INTFE | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN13) -#define ZKITARM_KEY5_IRQ LPC17_IRQ_P2p13 +#define ZKITARM_KEY5_IRQ LPC17_40_IRQ_P2p13 /* SD Slot * @@ -160,13 +160,13 @@ */ #define ZKITARM_SD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN16) -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ # define ZKITARM_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #else # define ZKITARM_SD_CD (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #endif -#define ZKITARM_SD_CDIRQ LPC17_IRQ_P2p12 +#define ZKITARM_SD_CDIRQ LPC17_40_IRQ_P2p12 /* USB: * @@ -182,7 +182,7 @@ */ #define ZKITARM_USB_CONNECT (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT2 | GPIO_PIN9) -#ifdef CONFIG_LPC17_GPIOIRQ +#ifdef CONFIG_LPC17_40_GPIOIRQ # define ZKITARM_USB_VBUSSENSE (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) #else # define ZKITARM_USB_VBUSSENSE (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index c01fcc96c06..4b34ee8da6f 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="zkit-arm-1769" CONFIG_ARCH_BOARD_ZKITARM=y CONFIG_ARCH_CHIP_LPC1768=y -CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_CHIP_LPC17XX_40XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y @@ -24,11 +24,11 @@ CONFIG_EXAMPLES_THTTPD_DRIPADDR=0xac100002 CONFIG_EXAMPLES_THTTPD_NOMAC=y CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_ETH_NRXDESC=18 -CONFIG_LPC17_ETH_NTXDESC=18 -CONFIG_LPC17_PHY_AUTONEG=y -CONFIG_LPC17_UART0=y +CONFIG_LPC17_40_ETHERNET=y +CONFIG_LPC17_40_ETH_NRXDESC=18 +CONFIG_LPC17_40_ETH_NTXDESC=18 +CONFIG_LPC17_40_PHY_AUTONEG=y +CONFIG_LPC17_40_UART0=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=2 diff --git a/drivers/lcd/README.txt b/drivers/lcd/README.txt index c1e3b1aa7b2..b02ed9da537 100644 --- a/drivers/lcd/README.txt +++ b/drivers/lcd/README.txt @@ -224,7 +224,7 @@ that makes then less re-usable: LCD controllers built-into the MCU: - arch/arm/src/lpc17xx/lpc17_lcd.c and configs/open1788/src/lpc17_lcd.c. + arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c and configs/open1788/src/lpc17_40_lcd.c. RGB LCD display panel. configs/stm32ldiscovery/src/stm32_lcd.c. 1x6 segment LCD with bars using the segment LCD controller built-into the STM32L15X. @@ -247,7 +247,7 @@ that makes then less re-usable: TFT Panel Drivers: - configs/open1788/src/lpc17_lcd.c and arch/arm/src/lpc17xx/lpc17_lcd.c + configs/open1788/src/lpc17_40_lcd.c and arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c configs/sama5d3x-ek/src and configs/sama5d4-ek/src: Use arch/arm/src/sama5/sam_lcd.c diff --git a/include/fixedmath.h b/include/fixedmath.h index 6b906c002a8..603ac24731c 100644 --- a/include/fixedmath.h +++ b/include/fixedmath.h @@ -125,8 +125,8 @@ #define ub8toi(a) ((a) >> 8) /* Conversion to unsigned integer */ #define itob8(i) (((b8_t)(i)) << 8) /* Conversion from integer */ #define uitoub8(i) (((ub8_t)(i)) << 8) /* Conversion from unsigned integer */ -#define b8tof(b) (((float)(b))/256.0) /* Conversion to float */ -#define ftob8(f) (b8_t)(((f)*256.0)) /* Conversion from float */ +#define b8tof(b) (((float)(b))/256.0f) /* Conversion to float */ +#define ftob8(f) (b8_t)(((f)*256.0f)) /* Conversion from float */ #define b8trunc(a) ((a) & 0xff00) /* Truncate to integer b8 */ #define b8round(a) (((a)+0x0080) & 0xff00) /* Round to integer b8 */ #define b8frac(a) ((a) & 0x00ff) /* Take fractional part */ @@ -157,9 +157,9 @@ #define ub16toi(a) ((a) >> 16) /* Conversion to unsgined integer */ #define itob16(i) (((b16_t)(i)) << 16) /* Conversion from integer */ #define uitoub16(i) (((ub16_t)(i)) << 16) /* Conversion from unsigned integer */ -#define b16tof(b) (((float)(b))/65536.0) /* Conversion to float */ -#define ftob16(f) (b16_t)(((f)*65536.0)) /* Conversion from float */ -#define b16tod(b) (((double)(b))/65536.0)) /* Conversion to double */ +#define b16tof(b) (((float)(b))/65536.0f) /* Conversion to float */ +#define ftob16(f) (b16_t)(((f)*65536.0f)) /* Conversion from float */ +#define b16tod(b) (((double)(b))/65536.0) /* Conversion to double */ #define dtob16(f) (b16_t)(((f)*65536.0)) /* Conversion from double */ #define b16trunc(a) ((a) & 0xffff0000) /* Truncate to integer */ #define b16round(a) (((a)+0x00008000) & 0xffff0000) diff --git a/include/nuttx/spi/spi.h b/include/nuttx/spi/spi.h index d53adc87781..060286cf541 100644 --- a/include/nuttx/spi/spi.h +++ b/include/nuttx/spi/spi.h @@ -486,6 +486,7 @@ #define SPIDEV_CANBUS(n) SPIDEV_ID(SPIDEVTYPE_CANBUS, (n)) #define SPIDEV_USBHOST(n) SPIDEV_ID(SPIDEVTYPE_USBHOST, (n)) #define SPIDEV_LPWAN(n) SPIDEV_ID(SPIDEVTYPE_LPWAN, (n)) +#define SPIDEV_ADC(n) SPIDEV_ID(SPIDEVTYPE_ADC, (n)) #define SPIDEV_USER(n) SPIDEV_ID(SPIDEVTYPE_USER, (n)) /**************************************************************************** @@ -524,6 +525,7 @@ enum spi_devtype_e SPIDEVTYPE_CANBUS, /* Select SPI CAN bus controller over SPI */ SPIDEVTYPE_USBHOST, /* Select SPI USB host controller over SPI */ SPIDEVTYPE_LPWAN, /* Select SPI LPWAN controller over SPI */ + SPIDEVTYPE_ADC, /* Select SPI ADC device */ SPIDEVTYPE_USER /* Board-specific values start here * This must always be the last definition. */ }; diff --git a/include/sys/syscall.h b/include/sys/syscall.h index bea4a25b43e..e8ad4c30f54 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -384,16 +384,19 @@ #if !defined(CONFIG_DISABLE_MOUNTPOINT) #if defined(CONFIG_FS_READABLE) -# define SYS_mount (__SYS_mountpoint + 0) +# define SYS_mount (__SYS_mountpoint + 0) +# define __SYS_fs (__SYS_mountpoint + 1) +#else +# define __SYS_fs (__SYS_mountpoint + 0) #endif -# define SYS_fsync (__SYS_mountpoint + 1) -# define SYS_ftruncate (__SYS_mountpoint + 2) -# define SYS_mkdir (__SYS_mountpoint + 3) -# define SYS_rename (__SYS_mountpoint + 4) -# define SYS_rmdir (__SYS_mountpoint + 5) -# define SYS_umount2 (__SYS_mountpoint + 6) -# define SYS_unlink (__SYS_mountpoint + 7) -# define __SYS_shm (__SYS_mountpoint + 8) +# define SYS_fsync (__SYS_fs + 0) +# define SYS_ftruncate (__SYS_fs + 1) +# define SYS_mkdir (__SYS_fs + 2) +# define SYS_rename (__SYS_fs + 3) +# define SYS_rmdir (__SYS_fs + 4) +# define SYS_umount2 (__SYS_fs + 5) +# define SYS_unlink (__SYS_fs + 6) +# define __SYS_shm (__SYS_fs + 7) #else # define __SYS_shm __SYS_mountpoint #endif @@ -401,11 +404,11 @@ /* Shared memory interfaces */ #ifdef CONFIG_MM_SHM -# define SYS_shmget (__SYS_shm + 0) -# define SYS_shmat (__SYS_shm + 1) -# define SYS_shmctl (__SYS_shm + 2) -# define SYS_shmdt (__SYS_shm + 3) -# define __SYS_pthread (__SYS_shm + 4) +# define SYS_shmget (__SYS_shm + 0) +# define SYS_shmat (__SYS_shm + 1) +# define SYS_shmctl (__SYS_shm + 2) +# define SYS_shmdt (__SYS_shm + 3) +# define __SYS_pthread (__SYS_shm + 4) #else # define __SYS_pthread __SYS_shm #endif diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index cb748f778b4..710de4cf1a8 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -299,13 +299,13 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_create, 4, STUB_pthread_create) SYSCALL_LOOKUP(pthread_detach, 1, STUB_pthread_detach) SYSCALL_LOOKUP(pthread_exit, 1, STUB_pthread_exit) + SYSCALL_LOOKUP(pthread_get_stackaddr_np, 1, STUB_pthread_get_stackaddr_np) + SYSCALL_LOOKUP(pthread_get_stacksize_np, 1, STUB_pthread_get_stacksize_np) SYSCALL_LOOKUP(pthread_getschedparam, 3, STUB_pthread_getschedparam) SYSCALL_LOOKUP(pthread_getspecific, 1, STUB_pthread_getspecific) SYSCALL_LOOKUP(pthread_join, 2, STUB_pthread_join) SYSCALL_LOOKUP(pthread_key_create, 2, STUB_pthread_key_create) SYSCALL_LOOKUP(pthread_key_delete, 1, STUB_pthread_key_delete) - SYSCALL_LOOKUP(pthread_get_stackaddr_np, 1, STUB_pthread_get_stackaddr_np) - SYSCALL_LOOKUP(pthread_get_stacksize_np, 1, STUB_pthread_get_stacksize_np) SYSCALL_LOOKUP(pthread_mutex_destroy, 1, STUB_pthread_mutex_destroy) SYSCALL_LOOKUP(pthread_mutex_init, 2, STUB_pthread_mutex_init) SYSCALL_LOOKUP(pthread_mutex_timedlock, 2, STUB_pthread_mutex_timedlock) diff --git a/tools/flash_writer.py b/tools/flash_writer.py index f8d2deff22b..840f10c32f5 100755 --- a/tools/flash_writer.py +++ b/tools/flash_writer.py @@ -1,7 +1,34 @@ #! /usr/bin/env python3 -__copyright__ = ['Copyright (C) 2018 Sony Semiconductor Solutions Corp.'] -__license__ = 'LGPL v2.1' +# Copyright (C) 2018 Sony Semiconductor Solutions Corp. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# import time import sys