mirror of
https://github.com/apache/nuttx.git
synced 2026-05-09 23:12:17 +08:00
boards/stm32l4: migrate to new pinmap
migrate stm32l4 to new pinmap Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Xiang Xiao
@@ -587,7 +587,7 @@
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/* USB */
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#define GPIO_USB_DM_0(GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_USB_DP_0(GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
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#define GPIO_USB_DM_0 (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_USB_DP_0 (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
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#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_PINMAP_H */
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@@ -7,6 +7,7 @@
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#
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="b-l475e-iot01a"
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CONFIG_ARCH_BOARD_B_L475E_IOT01A=y
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@@ -9,6 +9,7 @@
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# CONFIG_NET_IPv4 is not set
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ALLOW_BSD_COMPONENTS=y
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="b-l475e-iot01a"
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@@ -9,6 +9,7 @@
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# CONFIG_NET_IPv4 is not set
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ALLOW_BSD_COMPONENTS=y
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="b-l475e-iot01a"
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@@ -9,6 +9,7 @@
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# CONFIG_NET_IPv4 is not set
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ALLOW_BSD_COMPONENTS=y
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="b-l475e-iot01a"
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@@ -130,8 +130,8 @@
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/* UART4: Connected to arduino compatible pins DO/D1 via PA0, PA1 */
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#define GPIO_UART4_RX GPIO_UART4_RX_1
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#define GPIO_UART4_TX GPIO_UART4_TX_1
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#define GPIO_UART4_RX GPIO_UART4_RX_1
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#define GPIO_UART4_TX GPIO_UART4_TX_1
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/* SPSGRF
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*
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@@ -10,6 +10,7 @@
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
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# CONFIG_NSH_DISABLE_PS is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-l432kc"
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CONFIG_ARCH_BOARD_NUCLEO_L432KC=y
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@@ -6,6 +6,7 @@
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# modifications.
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#
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# CONFIG_STM32L4_SYSCFG is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-l432kc"
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CONFIG_ARCH_BOARD_NUCLEO_L432KC=y
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@@ -10,6 +10,7 @@
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
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# CONFIG_NSH_DISABLE_PS is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ANALOG=y
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-l432kc"
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@@ -87,26 +87,26 @@
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*/
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#if defined(CONFIG_ARCH_BOARD_USART1_RX_PA10)
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# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#elif defined(CONFIG_ARCH_BOARD_USART1_RX_PB7)
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# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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#endif
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#if defined(CONFIG_ARCH_BOARD_USART1_TX_PA9)
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# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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#elif defined(CONFIG_ARCH_BOARD_USART1_TX_PB6)
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# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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#endif
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/* USART2: Connected to STLInk Debug via PA2(TX), PA15(RX) */
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#if defined(CONFIG_ARCH_BOARD_USART2_RX_PA3)
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# define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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# define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#elif defined(CONFIG_ARCH_BOARD_USART2_RX_PA15)
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# define GPIO_USART2_RX GPIO_USART2_RX_2 /* PA15 */
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# define GPIO_USART2_RX GPIO_USART2_RX_2 /* PA15 */
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#endif
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_DE_2
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2
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/* LPUART1 */
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@@ -231,14 +231,14 @@
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* Default is to use timer 5 (32-bit) and encoder on PA0/PA1
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*/
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#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1
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#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1
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#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_3
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#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_3
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#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_3|GPIO_SPEED_50MHz)
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#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_3|GPIO_SPEED_50MHz)
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#define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1
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#define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_1
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#define GPIO_TIM5_CH1IN (GPIO_TIM5_CH1IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM5_CH2IN (GPIO_TIM5_CH2IN_1|GPIO_SPEED_50MHz)
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/* PWM output for full bridge, uses config 1, because port E is N/A on QFP64
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* CH1 | 1(A8) 2(E9)
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@@ -250,13 +250,13 @@
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* CHN3 | 1(B1) 2(B15) 3(E12)
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*/
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#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1
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#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1
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#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1
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#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1
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#define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_1
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#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3OUT_1
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#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1
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#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz)
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/* LPTIM2 PWM output
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* REVISIT : Add support for the other clock sources, LSE, LSI and HSI
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@@ -269,9 +269,9 @@
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#endif
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#if 1
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# define GPIO_LPTIM2_CH1OUT GPIO_LPTIM2_OUT_1
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# define GPIO_LPTIM2_CH1OUT (GPIO_LPTIM2_OUT_1|GPIO_SPEED_50MHz)
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#else
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# define GPIO_LPTIM2_CH1OUT GPIO_LPTIM2_OUT_2
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# define GPIO_LPTIM2_CH1OUT (GPIO_LPTIM2_OUT_2|GPIO_SPEED_50MHz)
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#endif
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/****************************************************************************
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@@ -69,7 +69,7 @@ static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] =
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static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] =
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{
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GPIO_ADC1_IN11, GPIO_ADC1_IN12
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GPIO_ADC1_IN11_0, GPIO_ADC1_IN12_0
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};
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#else
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@@ -84,7 +84,7 @@ static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] =
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static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] =
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{
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GPIO_ADC1_IN11
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GPIO_ADC1_IN11_0
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};
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#endif /* CONFIG_STM32L4_ADC1_DMA */
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@@ -7,6 +7,7 @@
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#
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# CONFIG_ARCH_FPU is not set
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ADC=y
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CONFIG_ANALOG=y
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CONFIG_ARCH="arm"
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@@ -89,14 +89,14 @@
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2
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#define GPIO_USART2_RTS GPIO_USART2_RTS_DE_2
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */
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#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */
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#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */
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#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */
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#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */
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/* I2C
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*
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@@ -204,7 +204,7 @@
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*/
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#define ADC1_MEASURE_CHANNEL 9
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#define GPIO_MEASURE_ADC (GPIO_ADC1_IN9)
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#define GPIO_MEASURE_ADC (GPIO_ADC1_IN9_0)
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/* DAC
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* Default is PA4 (same as ADC, do not use both at the same time)
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@@ -216,14 +216,14 @@
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* Default is to use timer 5 (32-bit) and encoder on PA0/PA1
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*/
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#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1
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#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1
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#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_3
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#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_3
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#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_3|GPIO_SPEED_50MHz)
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#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_3|GPIO_SPEED_50MHz)
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#define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1
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#define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_1
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#define GPIO_TIM5_CH1IN (GPIO_TIM5_CH1IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM5_CH2IN (GPIO_TIM5_CH2IN_1|GPIO_SPEED_50MHz)
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/* PWM output for full bridge, uses config 1, because port E is N/A on QFP64
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* CH1 | 1(A8) 2(E9)
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@@ -232,10 +232,10 @@
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* CHN2 | 1(B0) 2(B14) 3(E10)
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*/
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#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1
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#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1
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#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1
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#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1
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#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_1|GPIO_SPEED_50MHz)
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/****************************************************************************
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* Public Data
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@@ -10,6 +10,7 @@
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
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# CONFIG_NSH_DISABLE_PS is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-l476rg"
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CONFIG_ARCH_BOARD_NUCLEO_L476RG=y
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@@ -11,6 +11,7 @@
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
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# CONFIG_NSH_DISABLE_PS is not set
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# CONFIG_NX_DISABLE_1BPP is not set
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# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-l476rg"
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CONFIG_ARCH_BOARD_NUCLEO_L476RG=y
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@@ -78,8 +78,8 @@
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* PD1
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*/
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#define GPIO_CAN1_RX GPIO_CAN1_RX_1 /* PA11 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_1 /* PA12 */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_1 /* PA11 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_1 /* PA12 */
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/* USART1:
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* RXD: PA10 CN9 pin 3, CN10 pin 33
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@@ -105,7 +105,7 @@
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2
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#define GPIO_USART2_RTS GPIO_USART2_RTS_DE_2
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2
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/* USART3:
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@@ -154,13 +154,13 @@
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/* SPI */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 /* PB4 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_2 /* PB3 */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 /* PB4 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_2 /* PB3 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */
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/* LEDs
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*
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@@ -228,14 +228,14 @@
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* Default is to use timer 5 (32-bit) and encoder on PA0/PA1
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*/
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#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1
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#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1
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#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_3
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#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_3
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#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_3|GPIO_SPEED_50MHz)
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#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_3|GPIO_SPEED_50MHz)
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#define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1
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#define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_1
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#define GPIO_TIM5_CH1IN (GPIO_TIM5_CH1IN_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM5_CH2IN (GPIO_TIM5_CH2IN_1|GPIO_SPEED_50MHz)
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/* PWM output for full bridge, uses config 1, because port E is N/A on QFP64
|
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* CH1 | 1(A8) 2(E9)
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||||
@@ -244,13 +244,13 @@
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* CHN2 | 1(B0) 2(B14) 3(E10)
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*/
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#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1
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#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1
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#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1
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#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1
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#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz)
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#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_1|GPIO_SPEED_50MHz)
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|
||||
#define GPIO_LPTIM1_CH1OUT GPIO_LPTIM1_OUT_1
|
||||
#define GPIO_LPTIM2_CH1OUT GPIO_LPTIM2_OUT_2
|
||||
#define GPIO_LPTIM1_CH1OUT (GPIO_LPTIM1_OUT_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_LPTIM2_CH1OUT (GPIO_LPTIM2_OUT_2|GPIO_SPEED_50MHz)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
||||
@@ -71,8 +71,8 @@ static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] =
|
||||
|
||||
static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] =
|
||||
{
|
||||
GPIO_ADC1_IN1,
|
||||
GPIO_ADC1_IN2
|
||||
GPIO_ADC1_IN1_0,
|
||||
GPIO_ADC1_IN2_0
|
||||
};
|
||||
|
||||
#else
|
||||
@@ -89,7 +89,7 @@ static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] =
|
||||
|
||||
static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] =
|
||||
{
|
||||
GPIO_ADC1_IN1
|
||||
GPIO_ADC1_IN1_0
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ADC_DMA */
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ADC=y
|
||||
CONFIG_ANALOG=y
|
||||
CONFIG_ARCH="arm"
|
||||
|
||||
@@ -445,13 +445,6 @@
|
||||
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SDMMC2)
|
||||
# define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1
|
||||
# define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1
|
||||
# define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1
|
||||
# define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1
|
||||
#endif
|
||||
|
||||
/* DMA Channel/Stream Selections ********************************************/
|
||||
|
||||
/* Stream selections are arbitrary for now but might become important in the
|
||||
@@ -463,13 +456,9 @@
|
||||
* DMAMAP_SDMMC_1 = Channel 4, Stream 7
|
||||
* DMAMAP_SDMMC_2 = Channel 5, Stream 7
|
||||
*
|
||||
* SDMMC2 DMA
|
||||
* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
|
||||
* DMAMAP_SDMMC3_2 = Channel 11, Stream 5
|
||||
*/
|
||||
|
||||
#define DMAMAP_SDMMC1 DMACHAN_SDMMC_1
|
||||
#define DMAMAP_SDMMC2 DMACHAN_SDMMC_2
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
@@ -582,8 +571,8 @@
|
||||
|
||||
/* LPUART1 is connector to Virtual COM port PG6 and PG7. */
|
||||
|
||||
#define GPIO_LPUART1_TX GPIO_LPUART1_TX_3
|
||||
#define GPIO_LPUART1_RX GPIO_LPUART1_RX_3
|
||||
#define GPIO_LPUART1_TX GPIO_LPUART1_TX_3
|
||||
#define GPIO_LPUART1_RX GPIO_LPUART1_RX_3
|
||||
|
||||
/* DMA channels *************************************************************/
|
||||
|
||||
|
||||
@@ -94,7 +94,7 @@ static const uint8_t g_chanlist_adc1[ADC1_NCHANNELS] =
|
||||
|
||||
static const uint32_t g_pinlist_adc1[ADC1_NCHANNELS] =
|
||||
{
|
||||
GPIO_ADC1_IN3
|
||||
GPIO_ADC1_IN3_0
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -107,7 +107,7 @@ static const uint8_t g_chanlist_adc2[ADC2_NCHANNELS] =
|
||||
}; /* IN4, DAC1 and DAC2 */
|
||||
static const uint32_t g_pinlist_adc2[ADC2_NCHANNELS] =
|
||||
{
|
||||
GPIO_ADC1_IN4, 0, 0
|
||||
GPIO_ADC1_IN4_0, 0, 0
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_NSH_DISABLE_IFCONFIG is not set
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="steval-stlcs01v1"
|
||||
CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_NSH_DISABLE_IFCONFIG is not set
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="steval-stlcs01v1"
|
||||
CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y
|
||||
|
||||
@@ -350,4 +350,11 @@
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
|
||||
#define GPIO_SPI2_MISO 0 /* Not used in half-duplex */
|
||||
|
||||
/* USB OTG FS */
|
||||
|
||||
#define GPIO_OTGFS_DM GPIO_OTGFS_DM_0 /* PA11 */
|
||||
#define GPIO_OTGFS_DP GPIO_OTGFS_DP_0 /* PA12 */
|
||||
#define GPIO_OTGFS_ID GPIO_OTGFS_ID_0 /* PA10 */
|
||||
#define GPIO_OTGFS_SOF GPIO_OTGFS_SOF_0 /* PA8 */
|
||||
|
||||
#endif /* __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H */
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32l476-mdk"
|
||||
CONFIG_ARCH_BOARD_STM32L476_MDK=y
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
# CONFIG_SYSTEM_DD is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32l476vg-disco"
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32l476vg-disco"
|
||||
CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y
|
||||
|
||||
@@ -76,8 +76,8 @@
|
||||
*/
|
||||
|
||||
#if 0
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 / * PB7 * /
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 / * PB6 * /
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
#endif
|
||||
|
||||
/* USART2: Connected to STLink Debug via PD5, PD6
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
# CONFIG_SYSTEM_DD is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32l4r9ai-disco"
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_STM32L4_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32l4r9ai-disco"
|
||||
CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y
|
||||
|
||||
@@ -73,7 +73,7 @@
|
||||
*/
|
||||
|
||||
#define ADC1_MEASURE_CHANNEL 12
|
||||
#define GPIO_MEASURE_ADC (GPIO_ADC1_IN12)
|
||||
#define GPIO_MEASURE_ADC (GPIO_ADC1_IN12_0)
|
||||
|
||||
/* Alternate function pin selections ****************************************/
|
||||
|
||||
@@ -88,8 +88,8 @@
|
||||
*/
|
||||
|
||||
#if 0
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 / * PB7 * /
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 / * PB6 * /
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
#endif
|
||||
|
||||
/* USART2: Connected to STLink Debug via PD5, PD6
|
||||
@@ -105,8 +105,8 @@
|
||||
* TXD: PA0 -> CN17 A4
|
||||
*/
|
||||
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */
|
||||
|
||||
/* I2C
|
||||
*
|
||||
|
||||
Reference in New Issue
Block a user