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SAMA5D2: Update PMC definitions; has UART2-4, but not USART0-4
This commit is contained in:
Gregory Nutt
@@ -25,6 +25,34 @@ config SAMA5_HAVE_UART1
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bool
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default n
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config SAMA5_HAVE_UART2
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bool
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default n
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config SAMA5_HAVE_UART3
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bool
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default n
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config SAMA5_HAVE_UART4
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bool
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default n
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config SAMA5_HAVE_USART0
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bool
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default n
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config SAMA5_HAVE_USART1
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bool
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default n
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config SAMA5_HAVE_USART2
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bool
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default n
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config SAMA5_HAVE_USART3
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bool
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default n
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config SAMA5_HAVE_USART4
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bool
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default n
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@@ -130,7 +158,9 @@ config ARCH_CHIP_SAMA5D2
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select SAMA5_HAVE_LCDC
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select SAMA5_HAVE_UART0
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select SAMA5_HAVE_UART1
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select SAMA5_HAVE_USART4
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select SAMA5_HAVE_UART2
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select SAMA5_HAVE_UART3
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select SAMA5_HAVE_UART4
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select SAMA5_HAVE_QSPI
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select SAMA5_HAVE_XDMA
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select SAMA5_HAVE_SAIC
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@@ -144,6 +174,10 @@ config ARCH_CHIP_SAMA5D3
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default n
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select SAMA5_HAVE_DMA
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select SAMA5_HAVE_PIOE
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select SAMA5_HAVE_USART0
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select SAMA5_HAVE_USART1
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select SAMA5_HAVE_USART2
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select SAMA5_HAVE_USART3
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config ARCH_CHIP_SAMA5D4
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bool
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@@ -157,6 +191,10 @@ config ARCH_CHIP_SAMA5D4
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select SAMA5_HAVE_LCDC
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select SAMA5_HAVE_UART0
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select SAMA5_HAVE_UART1
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select SAMA5_HAVE_USART0
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select SAMA5_HAVE_USART1
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select SAMA5_HAVE_USART2
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select SAMA5_HAVE_USART3
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select SAMA5_HAVE_USART4
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select SAMA5_HAVE_XDMA
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select SAMA5_HAVE_PIOE
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@@ -355,27 +393,52 @@ config SAMA5_UART1
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select ARCH_HAVE_UART1
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_UART2
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bool "UART 2"
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default n
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depends on SAMA5_HAVE_UART2
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select ARCH_HAVE_UART2
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_UART3
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bool "UART 3"
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default n
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depends on SAMA5_HAVE_UART3
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select ARCH_HAVE_UART3
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_UART4
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bool "UART 4"
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default n
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depends on SAMA5_HAVE_UART4
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select ARCH_HAVE_UART1
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_USART0
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bool "USART 0"
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default n
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depends on SAMA5_HAVE_USART0
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select ARCH_HAVE_USART0
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_USART1
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bool "USART 1"
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default n
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depends on SAMA5_HAVE_USART1
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select ARCH_HAVE_USART1
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_USART2
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bool "USART 2"
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default n
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depends on SAMA5_HAVE_USART2
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select ARCH_HAVE_USART2
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMA5_USART3
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bool "USART 3"
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default n
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depends on SAMA5_HAVE_USART3
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select ARCH_HAVE_USART3
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select ARCH_HAVE_SERIAL_TERMIOS
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@@ -67,7 +67,11 @@
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#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
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/* 0x0034: Reserved */
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#define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register */
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#define SAM_PMC_SMD_OFFSET 0x003c /* Soft Modem Clock Register */
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#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
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# define SAM_PMC_SMD_OFFSET 0x003c /* Soft Modem Clock Register */
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#endif
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#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
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#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
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#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
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@@ -76,7 +80,12 @@
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#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */
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#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */
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#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */
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/* 0x0070-0x0074: Reserved */
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#ifdef ATSAMA5D2
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# define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */
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# define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */
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#endif
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#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */
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/* 0x007c: Reserved */
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#define SAM_PMC_PLLICPR_OFFSET 0x0080 /* PLL Charge Pump Current Register */
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@@ -89,10 +98,26 @@
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#define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */
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#define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */
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#endif
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#ifdef ATSAMA5D2
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# define SAM_PMC_SLPWK_ER0_OFFSET 0x0114 /* SleepWalking Enable Register 0 */
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# define SAM_PMC_SLPWK_DR0_OFFSET 0x0118 /* SleepWalking Disable Register 0 */
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# define SAM_PMC_SLPWK_SR0_OFFSET 0x011c /* SleepWalking Status Register 0 */
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# define SAM_PMC_SLPWK_ASR0_OFFSET 0x0120 /* SleepWalking Activity Status Register 0 */
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/* 0x0124-0x0130: Reserved */
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# define SAM_PMC_SLPWK_ER1_OFFSET 0x0134 /* SleepWalking Enable Register 1 */
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# define SAM_PMC_SLPWK_DR1_OFFSET 0x0138 /* SleepWalking Disable Register 1 */
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# define SAM_PMC_SLPWK_SR1_OFFSET 0x013c /* SleepWalking Status Register 1 */
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# define SAM_PMC_SLPWK_ASR1_OFFSET 0x0140 /* SleepWalking Activity Status Register 1 */
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# define SAM_PMC_SLPWK_AIPR_OFFSET 0x0144 /* SleepWalking Activity In Progress Register */
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# define SAM_PMC_SLPWKCR_OFFSET 0x0148 /* SleepWalking Control Register */
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# define SAM_PMC_AUDIO_PLL0_OFFSET 0x014c /* Audio PLL Register 0 */
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# define SAM_PMC_AUDIO_PLL1_OFFSET 0x0150 /* Audio PLL Register 1 */
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#endif
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/* PMC register addresses *******************************************************************/
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#define SAM_PMC_SCER (SAM_PMC_VBASE+SAM_PMC_SCER_OFFSET)
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@@ -107,7 +132,11 @@
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#define SAM_PMC_CKGR_PLLAR (SAM_PMC_VBASE+SAM_PMC_CKGR_PLLAR_OFFSET)
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#define SAM_PMC_MCKR (SAM_PMC_VBASE+SAM_PMC_MCKR_OFFSET)
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#define SAM_PMC_USB (SAM_PMC_VBASE+SAM_PMC_USB_OFFSET)
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#define SAM_PMC_SMD (SAM_PMC_VBASE+SAM_PMC_SMD_OFFSET)
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#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
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# define SAM_PMC_SMD (SAM_PMC_VBASE+SAM_PMC_SMD_OFFSET)
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#endif
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#define SAM_PMC_PCK0 (SAM_PMC_VBASE+SAM_PMC_PCK0_OFFSET)
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#define SAM_PMC_PCK1 (SAM_PMC_VBASE+SAM_PMC_PCK1_OFFSET)
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#define SAM_PMC_PCK2 (SAM_PMC_VBASE+SAM_PMC_PCK2_OFFSET)
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@@ -115,6 +144,12 @@
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#define SAM_PMC_IDR (SAM_PMC_VBASE+SAM_PMC_IDR_OFFSET)
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#define SAM_PMC_SR (SAM_PMC_VBASE+SAM_PMC_SR_OFFSET)
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#define SAM_PMC_IMR (SAM_PMC_VBASE+SAM_PMC_IMR_OFFSET)
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#ifdef ATSAMA5D2
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# define SAM_PMC_FSMR (SAM_PMC_VBASE+SAM_PMC_FSMR_OFFSET)
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# define SAM_PMC_FSPR (SAM_PMC_VBASE+SAM_PMC_FSPR_OFFSET)
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#endif
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#define SAM_PMC_FOCR (SAM_PMC_VBASE+SAM_PMC_FOCR_OFFSET)
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#define SAM_PMC_PLLICPR (SAM_PMC_VBASE+SAM_PMC_PLLICPR_OFFSET)
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#define SAM_PMC_WPMR (SAM_PMC_VBASE+SAM_PMC_WPMR_OFFSET)
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@@ -124,23 +159,42 @@
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#define SAM_PMC_PCSR1 (SAM_PMC_VBASE+SAM_PMC_PCSR1_OFFSET)
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#define SAM_PMC_PCR (SAM_PMC_VBASE+SAM_PMC_PCR_OFFSET)
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define SAM_PMC_OCR (SAM_PMC_VBASE+SAM_PMC_OCR_OFFSET)
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#endif
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#ifdef ATSAMA5D2
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# define SAM_PMC_SLPWK_ER0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ER0_OFFSET)
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# define SAM_PMC_SLPWK_DR0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_DR0_OFFSET)
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# define SAM_PMC_SLPWK_SR0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_SR0_OFFSET)
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# define SAM_PMC_SLPWK_ASR0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ASR0_OFFSET)
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# define SAM_PMC_SLPWK_ER1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ER1_OFFSET)
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# define SAM_PMC_SLPWK_DR1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_DR1_OFFSET)
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# define SAM_PMC_SLPWK_SR1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_SR1_OFFSET)
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# define SAM_PMC_SLPWK_ASR1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ASR1_OFFSET)
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# define SAM_PMC_SLPWK_AIPR (SAM_PMC_VBASE+SAM_PMC_SLPWK_AIPR_OFFSET)
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# define SAM_PMC_SLPWKCR (SAM_PMC_VBASE+SAM_PMC_SLPWKCR_OFFSET)
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# define SAM_PMC_AUDIO_PLL0 (SAM_PMC_VBASE+SAM_PMC_AUDIO_PLL0_OFFSET)
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# define SAM_PMC_AUDIO_PLL1 (SAM_PMC_VBASE+SAM_PMC_AUDIO_PLL1_OFFSET)
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#endif
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/* PMC register bit definitions *************************************************************/
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/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
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* Clock Status Register common bit-field definitions
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*/
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define PMC_PCK (1 << 0) /* Bit 0: Processor Clock */
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#endif
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#define PMC_DDRCK (1 << 2) /* Bit 2: DDR Clock */
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#define PMC_LCDCK (1 << 3) /* Bit 3: LCD2x Clock */
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#define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */
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#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
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# define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */
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#endif
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#define PMC_UHP (1 << 6) /* Bit 6: USB Host OHCI Clocks */
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#define PMC_UDP (1 << 7) /* Bit 7: USB Device Clock */
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@@ -149,6 +203,10 @@
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#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output */
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#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output */
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#ifdef ATSAMA5D2
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# define PMC_ISCCK (1 << 18) /* Bit 18: ISC Clock Enable */
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#endif
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/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
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* Peripheral Clock Status Register common bit-field definitions.
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*/
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@@ -201,12 +259,13 @@
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#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
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#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
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#endif
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#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */
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#define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
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#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT)
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# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT)
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@@ -225,10 +284,16 @@
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#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
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#define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */
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#ifdef ATSAMA5D2
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# define PMC_CKGR_MCFR_CCSS (1 << 24) /* Bit 24: Counter Clock Source Selection */
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# define PMC_CKGR_MCFR_CCSS_RCOSC (0) /* Bit 24: 0=MAINF clock is the RC osciallator */
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# define PMC_CKGR_MCFR_CCSS_XOSC (1 << 24) /* Bit 24: 1=MAINF clock is the crystal osciallator */
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#endif
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/* PMC Clock Generator PLLA Register */
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#undef SAMA5_HAVE_PLLAR_DIV
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#if defined(ATSAMA5D3)
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */
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# define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT)
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# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */
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@@ -281,7 +346,7 @@
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# define PMC_MCKR_MDIV_PCKDIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */
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#define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define PMC_MCKR_H32MXDIV (1 << 24) /* Bit 24: AHB 32-bit Matrix Divisor */
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#endif
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@@ -294,13 +359,15 @@
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#define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT)
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# define PMC_USB_USBDIV(a) ((a) << PMC_USB_USBDIV_SHIFT)
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#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
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/* Soft Modem Clock Register */
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#define PMC_SMD_SMDS (1 << 0) /* Bit 0: SMD Input Clock Selection */
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# define PMC_SMD_SMDS_PLLA (0)
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# define PMC_SMD_SMDS_UPLL PMC_SMD_SMDS
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#define PMC_SMD_SMDDIV_SHIFT (8) /* Bits 8-12: Divider for SMD Clock */
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#define PMC_SMD_SMDDIV_MASK (31 << PMC_SMD_SMDDIV_SHIFT)
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# define PMC_SMD_SMDS (1 << 0) /* Bit 0: SMD Input Clock Selection */
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# define PMC_SMD_SMDS_PLLA (0)
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# define PMC_SMD_SMDS_UPLL PMC_SMD_SMDS
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# define PMC_SMD_SMDDIV_SHIFT (8) /* Bits 8-12: Divider for SMD Clock */
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# define PMC_SMD_SMDDIV_MASK (31 << PMC_SMD_SMDDIV_SHIFT)
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#endif
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/* PMC Programmable Clock Register (0,1,2) */
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@@ -311,15 +378,26 @@
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# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_SHIFT) /* PLLA Clock */
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# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_SHIFT) /* UPLL Clock */
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# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_SHIFT) /* Master Clock */
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#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
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#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
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# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */
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# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */
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# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */
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# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */
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# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */
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# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
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# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
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#ifdef ATSAMA5D4
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# define PMC_PCK_CSS_AUDIO (5 << PMC_PCK_CSS_SHIFT) /* Audio PLL Clock */
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#endif
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#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
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# define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
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# define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
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# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */
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# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */
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# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */
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# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */
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# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */
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# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
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# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
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#elif defined(ATSAMA5D2)
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# define PMC_PCK_PRES_SHIFT (4) /* Bits 4-11: Programmable Clock Prescaler */
|
||||
# define PMC_PCK_PRES_MASK (0xff << PMC_PCK_PRES_SHIFT)
|
||||
# define PMC_PCK_PRES(n) ((uint32_t)(n) << PMC_PCK_PRES_SHIFT)
|
||||
#endif
|
||||
|
||||
/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
|
||||
* and PMC Interrupt Mask Register common bit-field definitions
|
||||
@@ -333,7 +411,13 @@
|
||||
#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
|
||||
#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
|
||||
#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */
|
||||
#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
|
||||
|
||||
#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
|
||||
# define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
|
||||
#elif defined(ATSAMA5D2)
|
||||
# define PMC_SR_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status (SR only) */
|
||||
#endif
|
||||
|
||||
#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */
|
||||
#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
|
||||
#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
|
||||
@@ -342,6 +426,45 @@
|
||||
# define PMC_SR_XT32KERR (1 << 21) /* Bit 21: Slow Crystal Oscillator Error Interrupt */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
# define PMC_SR_GCKRDY (1 << 24) /* Bit 24: Generated Clocks Status (SR only) */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* Fast Startup Mode Register */
|
||||
|
||||
# define PMC_FSMR_FSTT(n) (1 << (n)) /* Bits 0-8: Fast Startup Input Enable 0 to 8 */
|
||||
# define PMC_FSMR_FSTT0 (1 << 0) /* Bit 0: Fast Startup Input Enable 0 */
|
||||
# define PMC_FSMR_FSTT1 (1 << 1) /* Bit 1: Fast Startup Input Enable 1 */
|
||||
# define PMC_FSMR_FSTT2 (1 << 2) /* Bit 2: Fast Startup Input Enable 2 */
|
||||
# define PMC_FSMR_FSTT3 (1 << 3) /* Bit 3: Fast Startup Input Enable 3 */
|
||||
# define PMC_FSMR_FSTT4 (1 << 4) /* Bit 4: Fast Startup Input Enable 4 */
|
||||
# define PMC_FSMR_FSTT5 (1 << 5) /* Bit 5: Fast Startup Input Enable 5 */
|
||||
# define PMC_FSMR_FSTT6 (1 << 6) /* Bit 6: Fast Startup Input Enable 6 */
|
||||
# define PMC_FSMR_FSTT7 (1 << 7) /* Bit 7: Fast Startup Input Enable 7 */
|
||||
# define PMC_FSMR_FSTT8 (1 << 8) /* Bit 8: Fast Startup Input Enable 8 */
|
||||
# define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable */
|
||||
# define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable */
|
||||
# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low-power Mode */
|
||||
# define PMC_FSMR_RXLPAL (1 << 24) /* Bit 24: Lower-power Receiver Alarm */
|
||||
# define PMC_FSMR_ACCAL (1 << 25) /* Bit 25: Analog Comparator Controller Alarm */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* Fast Startup Polarity Register */
|
||||
|
||||
# define PMC_FSPR_FSTP(n) (1 << (n)) /* Bits 0-8: Fast Startup Input Polarity 0 to 8 */
|
||||
# define PMC_FSPR_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */
|
||||
# define PMC_FSPR_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */
|
||||
# define PMC_FSPR_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */
|
||||
# define PMC_FSPR_FSTP3 (1 << 3) /* Bit 3: Fast Startup Input Polarity 3 */
|
||||
# define PMC_FSPR_FSTP4 (1 << 4) /* Bit 4: Fast Startup Input Polarity 4 */
|
||||
# define PMC_FSPR_FSTP5 (1 << 5) /* Bit 5: Fast Startup Input Polarity 5 */
|
||||
# define PMC_FSPR_FSTP6 (1 << 6) /* Bit 6: Fast Startup Input Polarity 6 */
|
||||
# define PMC_FSPR_FSTP7 (1 << 7) /* Bit 7: Fast Startup Input Polarity 7 */
|
||||
# define PMC_FSPR_FSTP8 (1 << 8) /* Bit 8: Fast Startup Input Polarity 8 */
|
||||
#endif
|
||||
|
||||
/* PMC Fault Output Clear Register */
|
||||
|
||||
#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */
|
||||
@@ -357,7 +480,7 @@
|
||||
#define PMC_PLLICPR_ICP_PLLU_SHIFT (16) /* Bits 16-17: Charge Pump Current PLL UTMI */
|
||||
#define PMC_PLLICPR_ICP_PLLU_MASK (3 << PMC_PLLICPR_ICP_PLLU_SHIFT)
|
||||
# define PMC_PLLICPR_ICP_PLLU(n) ((uint32_t)(n) << PMC_PLLICPR_ICP_PLLU_SHIFT)
|
||||
#define PMC_PLLICPR_IVCO_PLLU_SHIFT (14) /* Bits 24-15: Voltage Control Output Current PLL UTMI */
|
||||
#define PMC_PLLICPR_IVCO_PLLU_SHIFT (14) /* Bits 24-25: Voltage Control Output Current PLL UTMI */
|
||||
#define PMC_PLLICPR_IVCO_PLLU_MASK (3 << PMC_PLLICPR_IVCO_PLLU_SHIFT)
|
||||
# define PMC_PLLICPR_IVCO_PLLU(n) ((uint32_t)(n) << PMC_PLLICPR_IVCO_PLLU_SHIFT)
|
||||
|
||||
@@ -414,12 +537,27 @@
|
||||
|
||||
/* Peripheral Control Register */
|
||||
|
||||
#define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */
|
||||
#define PMC_PCR_PID_MASK (63 << PMC_PCR_PID_SHIFT)
|
||||
# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT)
|
||||
#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
|
||||
# define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */
|
||||
# define PMC_PCR_PID_MASK (0x3f << PMC_PCR_PID_SHIFT)
|
||||
# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT)
|
||||
#elif defined(ATSAMA5D2)
|
||||
# define PMC_PCR_PID_SHIFT (0) /* Bits 0-6: Peripheral ID */
|
||||
# define PMC_PCR_PID_MASK (0x7f << PMC_PCR_PID_SHIFT)
|
||||
# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT)
|
||||
# define PMC_PCR_GCKCSS_SHIFT (8) /* Bits 8-10: GCK Clock Source Selection */
|
||||
# define PMC_PCR_GCKCSS_MASK (7 << PMC_PCR_GCKCSS_SHIFT)
|
||||
# define PMC_PCR_GCKCSS_SLOW (0 << PMC_PCR_GCKCSS_SHIFT) /* Slow clock is selected */
|
||||
# define PMC_PCR_GCKCSS_MAIN (1 << PMC_PCR_GCKCSS_SHIFT) /* Main clock is selected */
|
||||
# define PMC_PCR_GCKCSS_PLLA (2 << PMC_PCR_GCKCSS_SHIFT) /* PLLACK is selected */
|
||||
# define PMC_PCR_GCKCSS_UPLL (3 << PMC_PCR_GCKCSS_SHIFT) /* UPLL Clock is selected */
|
||||
# define PMC_PCR_GCKCSS_MCK (4 << PMC_PCR_GCKCSS_SHIFT) /* Master Clock is selected */
|
||||
# define PMC_PCR_GCKCSS_AUDIO (5 << PMC_PCR_GCKCSS_SHIFT) /* Audio PLL clock is selected */
|
||||
#endif
|
||||
|
||||
#define PMC_PCR_CMD (1 << 12) /* Bit 12: Command */
|
||||
|
||||
#ifdef ATSAMA5D3
|
||||
#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
|
||||
# define SAMA5_HAVE_PMC_PCR_DIV 1 /* Supports conditional compilation */
|
||||
# define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */
|
||||
# define PMC_PCR_DIV_MASK (3 << PMC_PCR_DIV_SHIFT)
|
||||
@@ -430,9 +568,19 @@
|
||||
# define PMC_PCR_DIV8 (3 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
# define PMC_PCR_GCKDIV_SHIFT (20) /* Bits 20-27: Generated Clock Division Ratio */
|
||||
# define PMC_PCR_GCKDIV_MASK (0xff << PMC_PCR_GCKDIV_SHIFT)
|
||||
# define PMC_PCR_GCKDIV(n) ((uint32_t)(n) << PMC_PCR_GCKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
#define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */
|
||||
|
||||
#ifdef ATSAMA5D3
|
||||
#ifdef ATSAMA5D2
|
||||
# define PMC_PCR_GCKEN (1 << 29) /* Bit 29: GCK Enable */
|
||||
#endif
|
||||
|
||||
#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
|
||||
/* Oscillator Calibration Register */
|
||||
|
||||
# define PMC_OCR_CAL_SHIFT (0) /* Bits 0-6: 12 MHz RC Oscillator Calibration bits */
|
||||
@@ -441,6 +589,83 @@
|
||||
# define PMC_OCR_SEL (1 << 7) /* Bit 7: Selection of RC Oscillator Calibration bits */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* SleepWalking Enable Register 0, SleepWalking Disable Register 0, and SleepWalking
|
||||
* Activity Status Register 0.
|
||||
*/
|
||||
|
||||
# define PMC_SLPWK_ER0(n) (1 << (n)) /* Peripheral n SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID19 (1 << 19) /* Peripheral 19 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID20 (1 << 19) /* Peripheral 20 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID21 (1 << 19) /* Peripheral 21 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID22 (1 << 19) /* Peripheral 22 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID23 (1 << 19) /* Peripheral 23 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID24 (1 << 19) /* Peripheral 24 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID25 (1 << 19) /* Peripheral 25 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID26 (1 << 19) /* Peripheral 26 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID27 (1 << 19) /* Peripheral 27 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID28 (1 << 19) /* Peripheral 28 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID29 (1 << 19) /* Peripheral 29 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER0_PID30 (1 << 19) /* Peripheral 30 SleepWalking Enable */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* SleepWalking Enable Register 1, SleepWalking Disable Register 1, and SleepWalking Status
|
||||
* Register 1, and SleepWalking Activity Status Register 1.
|
||||
*/
|
||||
|
||||
# define PMC_SLPWK_ER1(n) (1 << ((n)-1)) /* Peripheral n SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER1_PID33 (1 << 1) /* Peripheral 33 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER1_PID34 (1 << 2) /* Peripheral 34 SleepWalking Enable */
|
||||
# define PMC_SLPWK_ER1_PID40 (1 << 8) /* Peripheral 40 SleepWalking Enable */
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* SleepWalking Activity In Progress Register */
|
||||
|
||||
# define PMC_SLPWK_AIPR_AIP (1 << 0) /* Bit 0: Activity In Progress */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* SleepWalking Control Register */
|
||||
|
||||
# define PMC_SLPWKCR_PID_SHIFT (0) /* Bits 0-6: Peripheral ID */
|
||||
# define PMC_SLPWKCR_PID_MASK (0x7f << PMC_SLPWKCR_PID_SHIFT)
|
||||
# define PMC_SLPWKCR_PID(n) ((uint32_t)(n) << PMC_SLPWKCR_PID_SHIFT)
|
||||
# define PMC_SLPWKCR_CMD (1 << 12) /* Bit 12: Command */
|
||||
# define PMC_SLPWKCR_CMD_READ (0) /* Bit 12: 0=Read mode */
|
||||
# define PMC_SLPWKCR_CMD_WRITE (1 << 12) /* Bit 12: 1=Write mode */
|
||||
# define PMC_SLPWKCR_ASR (1 << 16) /* Bit 16: Activity Status Register */
|
||||
# define PMC_SLPWKCR_SLPWKSR (1 << 28) /* Bit 28: SleepWalking Status Register */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* Audio PLL Register 0 */
|
||||
|
||||
# define PMC_AUDIO_PLL0_PLLEN (1 << 0) /* Bit 0: PLL Enable */
|
||||
# define PMC_AUDIO_PLL0_PADEN (1 << 1) /* Bit 1: Pad Clock Enable */
|
||||
# define PMC_AUDIO_PLL0_PMCEN (1 << 2) /* Bit 2: PMC Clock Enable */
|
||||
# define PMC_AUDIO_PLL0_RESETN (1 << 3) /* Bit 3: Audio PLL Reset */
|
||||
# define PMC_AUDIO_PLL0_ND_SHIFT (8) /* Bits 8-14: Loop Divider Ratio */
|
||||
# define PMC_AUDIO_PLL0_ND_MASK (0x7f << PMC_AUDIO_PLL0_ND_SHIFT)
|
||||
# define PMC_AUDIO_PLL0_ND(n) ((uint32_t)(n) << PMC_AUDIO_PLL0_ND_SHIFT)
|
||||
# define PMC_AUDIO_PLL0_QDPMC_SHIFT (16) /* Bitx 16-22: Output Divider Ratio for PMC Clock */
|
||||
# define PMC_AUDIO_PLL0_QDPMC_MASK (0x7f << PMC_AUDIO_PLL0_QDPMC_SHIFT)
|
||||
# define PMC_AUDIO_PLL0_QDPMC(n) ((uint32_t)(n) << PMC_AUDIO_PLL0_QDPMC_SHIFT)
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D2
|
||||
/* Audio PLL Register 1 */
|
||||
|
||||
# define PMC_AUDIO_PLL1_FRACR_SHIFT (0) /* Bits 0-21: Fractional Loop Divider Setting */
|
||||
# define PMC_AUDIO_PLL1_FRACR_MASK (0x3fffff << PMC_AUDIO_PLL1_FRACR_SHIFT)
|
||||
# define PMC_AUDIO_PLL1_FRACR(n) ((uint32_t)(n) << PMC_AUDIO_PLL1_FRACR_SHIFT)
|
||||
# define PMC_AUDIO_PLL1_QDAUDIO_SHIFT (24) /* Bits 24-30: Output Divider Ratio for Pad Clock */
|
||||
# define PMC_AUDIO_PLL1_QDAUDIO_MASK (0x7f << PMC_AUDIO_PLL1_QDAUDIO_SHIFT)
|
||||
# define PMC_AUDIO_PLL1_QDAUDIO(n) ((uint32_t)(n) << PMC_AUDIO_PLL1_QDAUDIO_SHIFT)
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
@@ -84,11 +84,14 @@
|
||||
# define SUPPRESS_CONSOLE_CONFIG 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? It could be on UART0-1 or USART0-3 */
|
||||
/* Is there a serial console? It could be on UART0-4 or USART0-3 */
|
||||
|
||||
#if defined(CONFIG_SAMA5_DBGU_CONSOLE) && defined(CONFIG_SAMA5_DBGU)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
@@ -97,6 +100,9 @@
|
||||
#elif defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART0)
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
@@ -105,6 +111,42 @@
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART1)
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART2)
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART3)
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART4)
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
@@ -114,6 +156,9 @@
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
@@ -122,6 +167,9 @@
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
@@ -130,6 +178,9 @@
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
@@ -138,6 +189,9 @@
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
@@ -147,6 +201,9 @@
|
||||
# undef CONFIG_SAMA5_DBGU_CONSOLE
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
@@ -186,6 +243,24 @@
|
||||
# define SAM_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_VBASE SAM_UART2_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_UART2_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_UART2_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_UART2_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_UART2_2STOP
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_VBASE SAM_UART3_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_UART3_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_UART3_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_UART3_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_UART3_2STOP
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_VBASE SAM_UART4_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_VBASE SAM_USART0_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD
|
||||
@@ -382,6 +457,15 @@ void sam_lowsetup(void)
|
||||
#ifdef CONFIG_SAMA5_UART1
|
||||
sam_uart1_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_UART2
|
||||
sam_uart2_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_UART3
|
||||
sam_uart3_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_UART4
|
||||
sam_uart4_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_USART0
|
||||
sam_usart0_enableclk();
|
||||
#endif
|
||||
@@ -407,6 +491,21 @@ void sam_lowsetup(void)
|
||||
(void)sam_configpio(PIO_UART1_TXD);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_UART2
|
||||
(void)sam_configpio(PIO_UART2_RXD);
|
||||
(void)sam_configpio(PIO_UART2_TXD);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_UART3
|
||||
(void)sam_configpio(PIO_UART3_RXD);
|
||||
(void)sam_configpio(PIO_UART3_TXD);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_UART4
|
||||
(void)sam_configpio(PIO_UART4_RXD);
|
||||
(void)sam_configpio(PIO_UART4_TXD);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_USART0
|
||||
(void)sam_configpio(PIO_USART0_RXD);
|
||||
(void)sam_configpio(PIO_USART0_TXD);
|
||||
|
||||
+379
-27
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user