diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 358a6525dfe..146551ca388 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -25,6 +25,34 @@ config SAMA5_HAVE_UART1 bool default n +config SAMA5_HAVE_UART2 + bool + default n + +config SAMA5_HAVE_UART3 + bool + default n + +config SAMA5_HAVE_UART4 + bool + default n + +config SAMA5_HAVE_USART0 + bool + default n + +config SAMA5_HAVE_USART1 + bool + default n + +config SAMA5_HAVE_USART2 + bool + default n + +config SAMA5_HAVE_USART3 + bool + default n + config SAMA5_HAVE_USART4 bool default n @@ -130,7 +158,9 @@ config ARCH_CHIP_SAMA5D2 select SAMA5_HAVE_LCDC select SAMA5_HAVE_UART0 select SAMA5_HAVE_UART1 - select SAMA5_HAVE_USART4 + select SAMA5_HAVE_UART2 + select SAMA5_HAVE_UART3 + select SAMA5_HAVE_UART4 select SAMA5_HAVE_QSPI select SAMA5_HAVE_XDMA select SAMA5_HAVE_SAIC @@ -144,6 +174,10 @@ config ARCH_CHIP_SAMA5D3 default n select SAMA5_HAVE_DMA select SAMA5_HAVE_PIOE + select SAMA5_HAVE_USART0 + select SAMA5_HAVE_USART1 + select SAMA5_HAVE_USART2 + select SAMA5_HAVE_USART3 config ARCH_CHIP_SAMA5D4 bool @@ -157,6 +191,10 @@ config ARCH_CHIP_SAMA5D4 select SAMA5_HAVE_LCDC select SAMA5_HAVE_UART0 select SAMA5_HAVE_UART1 + select SAMA5_HAVE_USART0 + select SAMA5_HAVE_USART1 + select SAMA5_HAVE_USART2 + select SAMA5_HAVE_USART3 select SAMA5_HAVE_USART4 select SAMA5_HAVE_XDMA select SAMA5_HAVE_PIOE @@ -355,27 +393,52 @@ config SAMA5_UART1 select ARCH_HAVE_UART1 select ARCH_HAVE_SERIAL_TERMIOS +config SAMA5_UART2 + bool "UART 2" + default n + depends on SAMA5_HAVE_UART2 + select ARCH_HAVE_UART2 + select ARCH_HAVE_SERIAL_TERMIOS + +config SAMA5_UART3 + bool "UART 3" + default n + depends on SAMA5_HAVE_UART3 + select ARCH_HAVE_UART3 + select ARCH_HAVE_SERIAL_TERMIOS + +config SAMA5_UART4 + bool "UART 4" + default n + depends on SAMA5_HAVE_UART4 + select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS + config SAMA5_USART0 bool "USART 0" default n + depends on SAMA5_HAVE_USART0 select ARCH_HAVE_USART0 select ARCH_HAVE_SERIAL_TERMIOS config SAMA5_USART1 bool "USART 1" default n + depends on SAMA5_HAVE_USART1 select ARCH_HAVE_USART1 select ARCH_HAVE_SERIAL_TERMIOS config SAMA5_USART2 bool "USART 2" default n + depends on SAMA5_HAVE_USART2 select ARCH_HAVE_USART2 select ARCH_HAVE_SERIAL_TERMIOS config SAMA5_USART3 bool "USART 3" default n + depends on SAMA5_HAVE_USART3 select ARCH_HAVE_USART3 select ARCH_HAVE_SERIAL_TERMIOS diff --git a/arch/arm/src/sama5/chip/sam_pmc.h b/arch/arm/src/sama5/chip/sam_pmc.h index 19940593dbb..bc79d25e2da 100644 --- a/arch/arm/src/sama5/chip/sam_pmc.h +++ b/arch/arm/src/sama5/chip/sam_pmc.h @@ -67,7 +67,11 @@ #define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ /* 0x0034: Reserved */ #define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register */ -#define SAM_PMC_SMD_OFFSET 0x003c /* Soft Modem Clock Register */ + +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) +# define SAM_PMC_SMD_OFFSET 0x003c /* Soft Modem Clock Register */ +#endif + #define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ #define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ #define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ @@ -76,7 +80,12 @@ #define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ #define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ #define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ - /* 0x0070-0x0074: Reserved */ + +#ifdef ATSAMA5D2 +# define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +# define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#endif + #define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ /* 0x007c: Reserved */ #define SAM_PMC_PLLICPR_OFFSET 0x0080 /* PLL Charge Pump Current Register */ @@ -89,10 +98,26 @@ #define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */ #define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */ -#ifdef ATSAMA5D3 +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) # define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */ #endif +#ifdef ATSAMA5D2 +# define SAM_PMC_SLPWK_ER0_OFFSET 0x0114 /* SleepWalking Enable Register 0 */ +# define SAM_PMC_SLPWK_DR0_OFFSET 0x0118 /* SleepWalking Disable Register 0 */ +# define SAM_PMC_SLPWK_SR0_OFFSET 0x011c /* SleepWalking Status Register 0 */ +# define SAM_PMC_SLPWK_ASR0_OFFSET 0x0120 /* SleepWalking Activity Status Register 0 */ + /* 0x0124-0x0130: Reserved */ +# define SAM_PMC_SLPWK_ER1_OFFSET 0x0134 /* SleepWalking Enable Register 1 */ +# define SAM_PMC_SLPWK_DR1_OFFSET 0x0138 /* SleepWalking Disable Register 1 */ +# define SAM_PMC_SLPWK_SR1_OFFSET 0x013c /* SleepWalking Status Register 1 */ +# define SAM_PMC_SLPWK_ASR1_OFFSET 0x0140 /* SleepWalking Activity Status Register 1 */ +# define SAM_PMC_SLPWK_AIPR_OFFSET 0x0144 /* SleepWalking Activity In Progress Register */ +# define SAM_PMC_SLPWKCR_OFFSET 0x0148 /* SleepWalking Control Register */ +# define SAM_PMC_AUDIO_PLL0_OFFSET 0x014c /* Audio PLL Register 0 */ +# define SAM_PMC_AUDIO_PLL1_OFFSET 0x0150 /* Audio PLL Register 1 */ +#endif + /* PMC register addresses *******************************************************************/ #define SAM_PMC_SCER (SAM_PMC_VBASE+SAM_PMC_SCER_OFFSET) @@ -107,7 +132,11 @@ #define SAM_PMC_CKGR_PLLAR (SAM_PMC_VBASE+SAM_PMC_CKGR_PLLAR_OFFSET) #define SAM_PMC_MCKR (SAM_PMC_VBASE+SAM_PMC_MCKR_OFFSET) #define SAM_PMC_USB (SAM_PMC_VBASE+SAM_PMC_USB_OFFSET) -#define SAM_PMC_SMD (SAM_PMC_VBASE+SAM_PMC_SMD_OFFSET) + +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) +# define SAM_PMC_SMD (SAM_PMC_VBASE+SAM_PMC_SMD_OFFSET) +#endif + #define SAM_PMC_PCK0 (SAM_PMC_VBASE+SAM_PMC_PCK0_OFFSET) #define SAM_PMC_PCK1 (SAM_PMC_VBASE+SAM_PMC_PCK1_OFFSET) #define SAM_PMC_PCK2 (SAM_PMC_VBASE+SAM_PMC_PCK2_OFFSET) @@ -115,6 +144,12 @@ #define SAM_PMC_IDR (SAM_PMC_VBASE+SAM_PMC_IDR_OFFSET) #define SAM_PMC_SR (SAM_PMC_VBASE+SAM_PMC_SR_OFFSET) #define SAM_PMC_IMR (SAM_PMC_VBASE+SAM_PMC_IMR_OFFSET) + +#ifdef ATSAMA5D2 +# define SAM_PMC_FSMR (SAM_PMC_VBASE+SAM_PMC_FSMR_OFFSET) +# define SAM_PMC_FSPR (SAM_PMC_VBASE+SAM_PMC_FSPR_OFFSET) +#endif + #define SAM_PMC_FOCR (SAM_PMC_VBASE+SAM_PMC_FOCR_OFFSET) #define SAM_PMC_PLLICPR (SAM_PMC_VBASE+SAM_PMC_PLLICPR_OFFSET) #define SAM_PMC_WPMR (SAM_PMC_VBASE+SAM_PMC_WPMR_OFFSET) @@ -124,23 +159,42 @@ #define SAM_PMC_PCSR1 (SAM_PMC_VBASE+SAM_PMC_PCSR1_OFFSET) #define SAM_PMC_PCR (SAM_PMC_VBASE+SAM_PMC_PCR_OFFSET) -#ifdef ATSAMA5D3 +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) # define SAM_PMC_OCR (SAM_PMC_VBASE+SAM_PMC_OCR_OFFSET) #endif +#ifdef ATSAMA5D2 +# define SAM_PMC_SLPWK_ER0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ER0_OFFSET) +# define SAM_PMC_SLPWK_DR0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_DR0_OFFSET) +# define SAM_PMC_SLPWK_SR0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_SR0_OFFSET) +# define SAM_PMC_SLPWK_ASR0 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ASR0_OFFSET) +# define SAM_PMC_SLPWK_ER1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ER1_OFFSET) +# define SAM_PMC_SLPWK_DR1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_DR1_OFFSET) +# define SAM_PMC_SLPWK_SR1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_SR1_OFFSET) +# define SAM_PMC_SLPWK_ASR1 (SAM_PMC_VBASE+SAM_PMC_SLPWK_ASR1_OFFSET) +# define SAM_PMC_SLPWK_AIPR (SAM_PMC_VBASE+SAM_PMC_SLPWK_AIPR_OFFSET) +# define SAM_PMC_SLPWKCR (SAM_PMC_VBASE+SAM_PMC_SLPWKCR_OFFSET) +# define SAM_PMC_AUDIO_PLL0 (SAM_PMC_VBASE+SAM_PMC_AUDIO_PLL0_OFFSET) +# define SAM_PMC_AUDIO_PLL1 (SAM_PMC_VBASE+SAM_PMC_AUDIO_PLL1_OFFSET) +#endif + /* PMC register bit definitions *************************************************************/ /* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System * Clock Status Register common bit-field definitions */ -#ifdef ATSAMA5D3 +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) # define PMC_PCK (1 << 0) /* Bit 0: Processor Clock */ #endif #define PMC_DDRCK (1 << 2) /* Bit 2: DDR Clock */ #define PMC_LCDCK (1 << 3) /* Bit 3: LCD2x Clock */ -#define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */ + +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) +# define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */ +#endif + #define PMC_UHP (1 << 6) /* Bit 6: USB Host OHCI Clocks */ #define PMC_UDP (1 << 7) /* Bit 7: USB Device Clock */ @@ -149,6 +203,10 @@ #define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output */ #define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output */ +#ifdef ATSAMA5D2 +# define PMC_ISCCK (1 << 18) /* Bit 18: ISC Clock Enable */ +#endif + /* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC * Peripheral Clock Status Register common bit-field definitions. */ @@ -201,12 +259,13 @@ #define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ #define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ -#ifdef ATSAMA5D3 +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) # define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ #endif #define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */ #define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT) +# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT) #define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ #define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT) # define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT) @@ -225,10 +284,16 @@ #define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ #define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */ +#ifdef ATSAMA5D2 +# define PMC_CKGR_MCFR_CCSS (1 << 24) /* Bit 24: Counter Clock Source Selection */ +# define PMC_CKGR_MCFR_CCSS_RCOSC (0) /* Bit 24: 0=MAINF clock is the RC osciallator */ +# define PMC_CKGR_MCFR_CCSS_XOSC (1 << 24) /* Bit 24: 1=MAINF clock is the crystal osciallator */ +#endif + /* PMC Clock Generator PLLA Register */ #undef SAMA5_HAVE_PLLAR_DIV -#if defined(ATSAMA5D3) +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) # define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */ # define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT) # define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ @@ -281,7 +346,7 @@ # define PMC_MCKR_MDIV_PCKDIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */ #define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */ -#ifdef ATSAMA5D4 +#if defined(ATSAMA5D2) || defined(ATSAMA5D4) # define PMC_MCKR_H32MXDIV (1 << 24) /* Bit 24: AHB 32-bit Matrix Divisor */ #endif @@ -294,13 +359,15 @@ #define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT) # define PMC_USB_USBDIV(a) ((a) << PMC_USB_USBDIV_SHIFT) +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) /* Soft Modem Clock Register */ -#define PMC_SMD_SMDS (1 << 0) /* Bit 0: SMD Input Clock Selection */ -# define PMC_SMD_SMDS_PLLA (0) -# define PMC_SMD_SMDS_UPLL PMC_SMD_SMDS -#define PMC_SMD_SMDDIV_SHIFT (8) /* Bits 8-12: Divider for SMD Clock */ -#define PMC_SMD_SMDDIV_MASK (31 << PMC_SMD_SMDDIV_SHIFT) +# define PMC_SMD_SMDS (1 << 0) /* Bit 0: SMD Input Clock Selection */ +# define PMC_SMD_SMDS_PLLA (0) +# define PMC_SMD_SMDS_UPLL PMC_SMD_SMDS +# define PMC_SMD_SMDDIV_SHIFT (8) /* Bits 8-12: Divider for SMD Clock */ +# define PMC_SMD_SMDDIV_MASK (31 << PMC_SMD_SMDDIV_SHIFT) +#endif /* PMC Programmable Clock Register (0,1,2) */ @@ -311,15 +378,26 @@ # define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_SHIFT) /* PLLA Clock */ # define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_SHIFT) /* UPLL Clock */ # define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_SHIFT) /* Master Clock */ -#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ -#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) -# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ -# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +#ifdef ATSAMA5D4 +# define PMC_PCK_CSS_AUDIO (5 << PMC_PCK_CSS_SHIFT) /* Audio PLL Clock */ +#endif + +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) +# define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +# define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ +#elif defined(ATSAMA5D2) +# define PMC_PCK_PRES_SHIFT (4) /* Bits 4-11: Programmable Clock Prescaler */ +# define PMC_PCK_PRES_MASK (0xff << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES(n) ((uint32_t)(n) << PMC_PCK_PRES_SHIFT) +#endif /* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, * and PMC Interrupt Mask Register common bit-field definitions @@ -333,7 +411,13 @@ #define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ #define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ #define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ -#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ + +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) +# define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#elif defined(ATSAMA5D2) +# define PMC_SR_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status (SR only) */ +#endif + #define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ #define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ #define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ @@ -342,6 +426,45 @@ # define PMC_SR_XT32KERR (1 << 21) /* Bit 21: Slow Crystal Oscillator Error Interrupt */ #endif +#ifdef ATSAMA5D2 +# define PMC_SR_GCKRDY (1 << 24) /* Bit 24: Generated Clocks Status (SR only) */ +#endif + +#ifdef ATSAMA5D2 +/* Fast Startup Mode Register */ + +# define PMC_FSMR_FSTT(n) (1 << (n)) /* Bits 0-8: Fast Startup Input Enable 0 to 8 */ +# define PMC_FSMR_FSTT0 (1 << 0) /* Bit 0: Fast Startup Input Enable 0 */ +# define PMC_FSMR_FSTT1 (1 << 1) /* Bit 1: Fast Startup Input Enable 1 */ +# define PMC_FSMR_FSTT2 (1 << 2) /* Bit 2: Fast Startup Input Enable 2 */ +# define PMC_FSMR_FSTT3 (1 << 3) /* Bit 3: Fast Startup Input Enable 3 */ +# define PMC_FSMR_FSTT4 (1 << 4) /* Bit 4: Fast Startup Input Enable 4 */ +# define PMC_FSMR_FSTT5 (1 << 5) /* Bit 5: Fast Startup Input Enable 5 */ +# define PMC_FSMR_FSTT6 (1 << 6) /* Bit 6: Fast Startup Input Enable 6 */ +# define PMC_FSMR_FSTT7 (1 << 7) /* Bit 7: Fast Startup Input Enable 7 */ +# define PMC_FSMR_FSTT8 (1 << 8) /* Bit 8: Fast Startup Input Enable 8 */ +# define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable */ +# define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable */ +# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low-power Mode */ +# define PMC_FSMR_RXLPAL (1 << 24) /* Bit 24: Lower-power Receiver Alarm */ +# define PMC_FSMR_ACCAL (1 << 25) /* Bit 25: Analog Comparator Controller Alarm */ +#endif + +#ifdef ATSAMA5D2 +/* Fast Startup Polarity Register */ + +# define PMC_FSPR_FSTP(n) (1 << (n)) /* Bits 0-8: Fast Startup Input Polarity 0 to 8 */ +# define PMC_FSPR_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */ +# define PMC_FSPR_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */ +# define PMC_FSPR_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */ +# define PMC_FSPR_FSTP3 (1 << 3) /* Bit 3: Fast Startup Input Polarity 3 */ +# define PMC_FSPR_FSTP4 (1 << 4) /* Bit 4: Fast Startup Input Polarity 4 */ +# define PMC_FSPR_FSTP5 (1 << 5) /* Bit 5: Fast Startup Input Polarity 5 */ +# define PMC_FSPR_FSTP6 (1 << 6) /* Bit 6: Fast Startup Input Polarity 6 */ +# define PMC_FSPR_FSTP7 (1 << 7) /* Bit 7: Fast Startup Input Polarity 7 */ +# define PMC_FSPR_FSTP8 (1 << 8) /* Bit 8: Fast Startup Input Polarity 8 */ +#endif + /* PMC Fault Output Clear Register */ #define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ @@ -357,7 +480,7 @@ #define PMC_PLLICPR_ICP_PLLU_SHIFT (16) /* Bits 16-17: Charge Pump Current PLL UTMI */ #define PMC_PLLICPR_ICP_PLLU_MASK (3 << PMC_PLLICPR_ICP_PLLU_SHIFT) # define PMC_PLLICPR_ICP_PLLU(n) ((uint32_t)(n) << PMC_PLLICPR_ICP_PLLU_SHIFT) -#define PMC_PLLICPR_IVCO_PLLU_SHIFT (14) /* Bits 24-15: Voltage Control Output Current PLL UTMI */ +#define PMC_PLLICPR_IVCO_PLLU_SHIFT (14) /* Bits 24-25: Voltage Control Output Current PLL UTMI */ #define PMC_PLLICPR_IVCO_PLLU_MASK (3 << PMC_PLLICPR_IVCO_PLLU_SHIFT) # define PMC_PLLICPR_IVCO_PLLU(n) ((uint32_t)(n) << PMC_PLLICPR_IVCO_PLLU_SHIFT) @@ -414,12 +537,27 @@ /* Peripheral Control Register */ -#define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */ -#define PMC_PCR_PID_MASK (63 << PMC_PCR_PID_SHIFT) -# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT) +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) +# define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */ +# define PMC_PCR_PID_MASK (0x3f << PMC_PCR_PID_SHIFT) +# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT) +#elif defined(ATSAMA5D2) +# define PMC_PCR_PID_SHIFT (0) /* Bits 0-6: Peripheral ID */ +# define PMC_PCR_PID_MASK (0x7f << PMC_PCR_PID_SHIFT) +# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT) +# define PMC_PCR_GCKCSS_SHIFT (8) /* Bits 8-10: GCK Clock Source Selection */ +# define PMC_PCR_GCKCSS_MASK (7 << PMC_PCR_GCKCSS_SHIFT) +# define PMC_PCR_GCKCSS_SLOW (0 << PMC_PCR_GCKCSS_SHIFT) /* Slow clock is selected */ +# define PMC_PCR_GCKCSS_MAIN (1 << PMC_PCR_GCKCSS_SHIFT) /* Main clock is selected */ +# define PMC_PCR_GCKCSS_PLLA (2 << PMC_PCR_GCKCSS_SHIFT) /* PLLACK is selected */ +# define PMC_PCR_GCKCSS_UPLL (3 << PMC_PCR_GCKCSS_SHIFT) /* UPLL Clock is selected */ +# define PMC_PCR_GCKCSS_MCK (4 << PMC_PCR_GCKCSS_SHIFT) /* Master Clock is selected */ +# define PMC_PCR_GCKCSS_AUDIO (5 << PMC_PCR_GCKCSS_SHIFT) /* Audio PLL clock is selected */ +#endif + #define PMC_PCR_CMD (1 << 12) /* Bit 12: Command */ -#ifdef ATSAMA5D3 +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) # define SAMA5_HAVE_PMC_PCR_DIV 1 /* Supports conditional compilation */ # define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */ # define PMC_PCR_DIV_MASK (3 << PMC_PCR_DIV_SHIFT) @@ -430,9 +568,19 @@ # define PMC_PCR_DIV8 (3 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */ #endif +#ifdef ATSAMA5D2 +# define PMC_PCR_GCKDIV_SHIFT (20) /* Bits 20-27: Generated Clock Division Ratio */ +# define PMC_PCR_GCKDIV_MASK (0xff << PMC_PCR_GCKDIV_SHIFT) +# define PMC_PCR_GCKDIV(n) ((uint32_t)(n) << PMC_PCR_GCKDIV_SHIFT) +#endif + #define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */ -#ifdef ATSAMA5D3 +#ifdef ATSAMA5D2 +# define PMC_PCR_GCKEN (1 << 29) /* Bit 29: GCK Enable */ +#endif + +#if defined(ATSAMA5D2) || defined(ATSAMA5D3) /* Oscillator Calibration Register */ # define PMC_OCR_CAL_SHIFT (0) /* Bits 0-6: 12 MHz RC Oscillator Calibration bits */ @@ -441,6 +589,83 @@ # define PMC_OCR_SEL (1 << 7) /* Bit 7: Selection of RC Oscillator Calibration bits */ #endif +#ifdef ATSAMA5D2 +/* SleepWalking Enable Register 0, SleepWalking Disable Register 0, and SleepWalking + * Activity Status Register 0. + */ + +# define PMC_SLPWK_ER0(n) (1 << (n)) /* Peripheral n SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID19 (1 << 19) /* Peripheral 19 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID20 (1 << 19) /* Peripheral 20 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID21 (1 << 19) /* Peripheral 21 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID22 (1 << 19) /* Peripheral 22 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID23 (1 << 19) /* Peripheral 23 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID24 (1 << 19) /* Peripheral 24 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID25 (1 << 19) /* Peripheral 25 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID26 (1 << 19) /* Peripheral 26 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID27 (1 << 19) /* Peripheral 27 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID28 (1 << 19) /* Peripheral 28 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID29 (1 << 19) /* Peripheral 29 SleepWalking Enable */ +# define PMC_SLPWK_ER0_PID30 (1 << 19) /* Peripheral 30 SleepWalking Enable */ +#endif + +#ifdef ATSAMA5D2 +/* SleepWalking Enable Register 1, SleepWalking Disable Register 1, and SleepWalking Status + * Register 1, and SleepWalking Activity Status Register 1. + */ + +# define PMC_SLPWK_ER1(n) (1 << ((n)-1)) /* Peripheral n SleepWalking Enable */ +# define PMC_SLPWK_ER1_PID33 (1 << 1) /* Peripheral 33 SleepWalking Enable */ +# define PMC_SLPWK_ER1_PID34 (1 << 2) /* Peripheral 34 SleepWalking Enable */ +# define PMC_SLPWK_ER1_PID40 (1 << 8) /* Peripheral 40 SleepWalking Enable */ +#endif + + +#ifdef ATSAMA5D2 +/* SleepWalking Activity In Progress Register */ + +# define PMC_SLPWK_AIPR_AIP (1 << 0) /* Bit 0: Activity In Progress */ +#endif + +#ifdef ATSAMA5D2 +/* SleepWalking Control Register */ + +# define PMC_SLPWKCR_PID_SHIFT (0) /* Bits 0-6: Peripheral ID */ +# define PMC_SLPWKCR_PID_MASK (0x7f << PMC_SLPWKCR_PID_SHIFT) +# define PMC_SLPWKCR_PID(n) ((uint32_t)(n) << PMC_SLPWKCR_PID_SHIFT) +# define PMC_SLPWKCR_CMD (1 << 12) /* Bit 12: Command */ +# define PMC_SLPWKCR_CMD_READ (0) /* Bit 12: 0=Read mode */ +# define PMC_SLPWKCR_CMD_WRITE (1 << 12) /* Bit 12: 1=Write mode */ +# define PMC_SLPWKCR_ASR (1 << 16) /* Bit 16: Activity Status Register */ +# define PMC_SLPWKCR_SLPWKSR (1 << 28) /* Bit 28: SleepWalking Status Register */ +#endif + +#ifdef ATSAMA5D2 +/* Audio PLL Register 0 */ + +# define PMC_AUDIO_PLL0_PLLEN (1 << 0) /* Bit 0: PLL Enable */ +# define PMC_AUDIO_PLL0_PADEN (1 << 1) /* Bit 1: Pad Clock Enable */ +# define PMC_AUDIO_PLL0_PMCEN (1 << 2) /* Bit 2: PMC Clock Enable */ +# define PMC_AUDIO_PLL0_RESETN (1 << 3) /* Bit 3: Audio PLL Reset */ +# define PMC_AUDIO_PLL0_ND_SHIFT (8) /* Bits 8-14: Loop Divider Ratio */ +# define PMC_AUDIO_PLL0_ND_MASK (0x7f << PMC_AUDIO_PLL0_ND_SHIFT) +# define PMC_AUDIO_PLL0_ND(n) ((uint32_t)(n) << PMC_AUDIO_PLL0_ND_SHIFT) +# define PMC_AUDIO_PLL0_QDPMC_SHIFT (16) /* Bitx 16-22: Output Divider Ratio for PMC Clock */ +# define PMC_AUDIO_PLL0_QDPMC_MASK (0x7f << PMC_AUDIO_PLL0_QDPMC_SHIFT) +# define PMC_AUDIO_PLL0_QDPMC(n) ((uint32_t)(n) << PMC_AUDIO_PLL0_QDPMC_SHIFT) +#endif + +#ifdef ATSAMA5D2 +/* Audio PLL Register 1 */ + +# define PMC_AUDIO_PLL1_FRACR_SHIFT (0) /* Bits 0-21: Fractional Loop Divider Setting */ +# define PMC_AUDIO_PLL1_FRACR_MASK (0x3fffff << PMC_AUDIO_PLL1_FRACR_SHIFT) +# define PMC_AUDIO_PLL1_FRACR(n) ((uint32_t)(n) << PMC_AUDIO_PLL1_FRACR_SHIFT) +# define PMC_AUDIO_PLL1_QDAUDIO_SHIFT (24) /* Bits 24-30: Output Divider Ratio for Pad Clock */ +# define PMC_AUDIO_PLL1_QDAUDIO_MASK (0x7f << PMC_AUDIO_PLL1_QDAUDIO_SHIFT) +# define PMC_AUDIO_PLL1_QDAUDIO(n) ((uint32_t)(n) << PMC_AUDIO_PLL1_QDAUDIO_SHIFT) +#endif + /******************************************************************************************** * Public Types ********************************************************************************************/ diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c index 34942873bc8..e3fa312c7f0 100644 --- a/arch/arm/src/sama5/sam_lowputc.c +++ b/arch/arm/src/sama5/sam_lowputc.c @@ -84,11 +84,14 @@ # define SUPPRESS_CONSOLE_CONFIG 1 #endif -/* Is there a serial console? It could be on UART0-1 or USART0-3 */ +/* Is there a serial console? It could be on UART0-4 or USART0-3 */ #if defined(CONFIG_SAMA5_DBGU_CONSOLE) && defined(CONFIG_SAMA5_DBGU) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -97,6 +100,9 @@ #elif defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART0) # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -105,6 +111,42 @@ #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART1) # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART2) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART3) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART4) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -114,6 +156,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -122,6 +167,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -130,6 +178,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -138,6 +189,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -147,6 +201,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -186,6 +243,24 @@ # define SAM_CONSOLE_BITS CONFIG_UART1_BITS # define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define SAM_CONSOLE_VBASE SAM_UART2_VBASE +# define SAM_CONSOLE_BAUD CONFIG_UART2_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART2_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART2_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART2_2STOP +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define SAM_CONSOLE_VBASE SAM_UART3_VBASE +# define SAM_CONSOLE_BAUD CONFIG_UART3_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART3_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART3_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART3_2STOP +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define SAM_CONSOLE_VBASE SAM_UART4_VBASE +# define SAM_CONSOLE_BAUD CONFIG_UART4_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART4_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART4_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART4_2STOP #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define SAM_CONSOLE_VBASE SAM_USART0_VBASE # define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD @@ -382,6 +457,15 @@ void sam_lowsetup(void) #ifdef CONFIG_SAMA5_UART1 sam_uart1_enableclk(); #endif +#ifdef CONFIG_SAMA5_UART2 + sam_uart2_enableclk(); +#endif +#ifdef CONFIG_SAMA5_UART3 + sam_uart3_enableclk(); +#endif +#ifdef CONFIG_SAMA5_UART4 + sam_uart4_enableclk(); +#endif #ifdef CONFIG_SAMA5_USART0 sam_usart0_enableclk(); #endif @@ -407,6 +491,21 @@ void sam_lowsetup(void) (void)sam_configpio(PIO_UART1_TXD); #endif +#ifdef CONFIG_SAMA5_UART2 + (void)sam_configpio(PIO_UART2_RXD); + (void)sam_configpio(PIO_UART2_TXD); +#endif + +#ifdef CONFIG_SAMA5_UART3 + (void)sam_configpio(PIO_UART3_RXD); + (void)sam_configpio(PIO_UART3_TXD); +#endif + +#ifdef CONFIG_SAMA5_UART4 + (void)sam_configpio(PIO_UART4_RXD); + (void)sam_configpio(PIO_UART4_TXD); +#endif + #ifdef CONFIG_SAMA5_USART0 (void)sam_configpio(PIO_USART0_RXD); (void)sam_configpio(PIO_USART0_TXD); diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index 935ee0e5636..c82df50dfb2 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -95,7 +95,9 @@ /* Is there a USART/USART enabled? */ -#if defined(CONFIG_SAMA5_UART0) || defined(CONFIG_SAMA5_UART1) +#if defined(CONFIG_SAMA5_UART0) || defined(CONFIG_SAMA5_UART1) || \ + defined(CONFIG_SAMA5_UART2) || defined(CONFIG_SAMA5_UART3) || \ + defined(CONFIG_SAMA5_UART4) # define HAVE_UART #endif @@ -110,6 +112,9 @@ #if defined(CONFIG_SAMA5_DBGU_CONSOLE) && defined(CONFIG_SAMA5_DBGU) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -119,6 +124,9 @@ #elif defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART0) # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -128,6 +136,45 @@ #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART1) # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART2) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART3) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART4) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -138,6 +185,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,6 +197,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -156,6 +209,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -165,6 +221,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -174,6 +233,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -184,6 +246,9 @@ # undef CONFIG_SAMA5_DBGU_CONSOLE # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -204,12 +269,26 @@ #undef TTYS4_DEV #undef TTYS5_DEV #undef TTYS6_DEV +#undef TTYS7_DEV +#undef TTYS8_DEV +#undef TTYS9_DEV + +#undef UART0_ASSIGNED +#undef UART1_ASSIGNED +#undef UART2_ASSIGNED +#undef UART3_ASSIGNED +#undef UART4_ASSIGNED +#undef USART0_ASSIGNED +#undef USART1_ASSIGNED +#undef USART2_ASSIGNED +#undef USART3_ASSIGNED +#undef USART4_ASSIGNED #if defined(HAVE_UART) || defined(HAVE_USART) -/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? tty5? tty6? */ +/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? ... tty9? */ -/* First pick the console and ttyS0. This could be any of UART0-1, USART0-4 */ +/* First pick the console and ttyS0. This could be any of UART0-4, USART0-4 */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart0port /* UART0 is console */ @@ -219,6 +298,18 @@ # define CONSOLE_DEV g_uart1port /* UART1 is console */ # define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART2 is console */ +# define TTYS0_DEV g_uart1port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART3 is console */ +# define TTYS0_DEV g_uart1port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART4 is console */ +# define TTYS0_DEV g_uart1port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_usart0port /* USART0 is console */ # define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ @@ -247,6 +338,15 @@ # elif defined(CONFIG_SAMA5_UART1) # define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 +# elif defined(CONFIG_SAMA5_UART2) +# define TTYS0_DEV g_uart1port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +# elif defined(CONFIG_SAMA5_UART3) +# define TTYS0_DEV g_uart1port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +# elif defined(CONFIG_SAMA5_UART4) +# define TTYS0_DEV g_uart1port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 # elif defined(CONFIG_SAMA5_USART0) # define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ # define USART0_ASSIGNED 1 @@ -265,7 +365,7 @@ # endif #endif -/* Pick ttyS1. This could be any of UART0-1, USART0-4 excluding the console UART. */ +/* Pick ttyS1. This could be any of UART0-4, USART0-4 excluding the console UART. */ #if defined(CONFIG_SAMA5_UART0) && !defined(UART0_ASSIGNED) # define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ @@ -273,6 +373,15 @@ #elif defined(CONFIG_SAMA5_UART1) && !defined(UART1_ASSIGNED) # define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ # define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART2) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART3) && !defined(UART3_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART3 is ttyS1 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART4 is ttyS1 */ +# define UART4_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) # define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */ # define USART0_ASSIGNED 1 @@ -290,7 +399,7 @@ # define USART4_ASSIGNED 1 #endif -/* Pick ttys2. This could be one of UART1 or USART0-4. It can't be UART0 +/* Pick ttyS2. This could be one of UART1-4 or USART0-4. It can't be UART0 * because that was either assigned as ttyS0 or ttyS1. One of these * could also be the console. */ @@ -298,6 +407,15 @@ #if defined(CONFIG_SAMA5_UART1) && !defined(UART1_ASSIGNED) # define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ # define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART2) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART3) && !defined(UART3_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART3 is ttyS2 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART4 is ttyS2 */ +# define UART4_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) # define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */ # define USART0_ASSIGNED 1 @@ -315,12 +433,21 @@ # define USART4_ASSIGNED 1 #endif -/* Pick ttys3. This could be one of USART0-4. It can't be UART0-1 because - * those have already been assigned to ttsyS0, 1, or 2. One of - * USART0-4 could also be the console. +/* Pick ttyS3. This could be one of UART2-4 or USART0-4. It can't be + * UART0-1; those have already been assigned to ttsyS0, 1, or 2. One of + * UART2-4 or USART0-4 could also be the console. */ -#if defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) +#if defined(CONFIG_SAMA5_UART2) && !defined(UART2_ASSIGNED) +# define TTYS3_DEV g_uart1port /* UART2 is ttyS3 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART3) && !defined(UART3_ASSIGNED) +# define TTYS3_DEV g_uart1port /* UART3 is ttyS3 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED) +# define TTYS3_DEV g_uart1port /* UART4 is ttyS3 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) # define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */ # define USART0_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART1) && !defined(USART1_ASSIGNED) @@ -337,55 +464,130 @@ # define USART4_ASSIGNED 1 #endif -/* Pick ttyS4. This could be one of USART1-4. It can't be UART0-1 or USART0 - * because those have already been assigned to ttsyS0, 1, 2 or 3. One of +/* Pick ttyS4. This could be one of UART3-4 or USART0-4. It can't be + * UART0-2; those have already been assigned to ttsyS0-3. One of + * UART3-4 or USART0-4 could also be the console. + */ + +#if defined(CONFIG_SAMA5_UART3) && !defined(UART3_ASSIGNED) +# define TTYS4_DEV g_uart1port /* UART3 is ttyS4 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED) +# define TTYS4_DEV g_uart1port /* UART4 is ttyS4 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) +# define TTYS4_DEV g_usart0port /* USART0 is ttyS4 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART1) && !defined(USART1_ASSIGNED) +# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART2) && !defined(USART2_ASSIGNED) +# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART3) && !defined(USART3_ASSIGNED) +# define TTYS4_DEV g_usart3port /* USART3 is ttyS4 */ +# define USART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART4) && !defined(USART4_ASSIGNED) +# define TTYS4_DEV g_usart4port /* USART4 is ttyS4 */ +# define USART4_ASSIGNED 1 +#endif + +/* Pick ttyS5. This could be one of UART4 or USART0-4. It can't be + * UART0-3; those have already been assigned to ttsyS0-4. One of + * UART4 or USART0-4 could also be the console. + */ + +#if defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED) +# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) +# define TTYS5_DEV g_usart0port /* USART0 is ttyS5 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART1) && !defined(USART1_ASSIGNED) +# define TTYS5_DEV g_usart1port /* USART1 is ttyS5 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART2) && !defined(USART2_ASSIGNED) +# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART3) && !defined(USART3_ASSIGNED) +# define TTYS5_DEV g_usart3port /* USART3 is ttyS5 */ +# define USART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART4) && !defined(USART4_ASSIGNED) +# define TTYS5_DEV g_usart4port /* USART4 is ttyS5 */ +# define USART4_ASSIGNED 1 +#endif + +/* Pick ttyS6. This could be one of USART0-4. It can't be UART0-4; + * those have already been assigned to ttsyS0-5. One of USART0-4 + * could also be the console. + */ + +#if defined(CONFIG_SAMA5_USART0) && !defined(USART0_ASSIGNED) +# define TTYS6_DEV g_usart0port /* USART0 is ttyS6 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART1) && !defined(USART1_ASSIGNED) +# define TTYS6_DEV g_usart1port /* USART1 is ttyS6 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART2) && !defined(USART2_ASSIGNED) +# define TTYS6_DEV g_usart2port /* USART2 is ttyS6 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART3) && !defined(USART3_ASSIGNED) +# define TTYS6_DEV g_usart3port /* USART3 is ttyS6 */ +# define USART3_ASSIGNED 1 +#elif defined(CONFIG_SAMA5_USART4) && !defined(USART4_ASSIGNED) +# define TTYS6_DEV g_usart4port /* USART4 is ttyS6 */ +# define USART4_ASSIGNED 1 +#endif + +/* Pick ttyS7. This could be one of USART1-4. It can't be UART0-4 + * or USART0; those have already been assigned to ttsyS0-5. One of * USART1-4 could also be the console. */ #if defined(CONFIG_SAMA5_USART1) && !defined(USART1_ASSIGNED) -# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ +# define TTYS7_DEV g_usart1port /* USART1 is ttyS7 */ # define USART1_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART2) && !defined(USART2_ASSIGNED) -# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ +# define TTYS7_DEV g_usart2port /* USART2 is ttyS7 */ # define USART2_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART3) && !defined(USART3_ASSIGNED) -# define TTYS4_DEV g_usart3port /* USART3 is ttyS4 */ +# define TTYS7_DEV g_usart3port /* USART3 is ttyS7 */ # define USART3_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART4) && !defined(USART4_ASSIGNED) -# define TTYS4_DEV g_usart4port /* USART4 is ttyS4 */ +# define TTYS7_DEV g_usart4port /* USART4 is ttyS7 */ # define USART4_ASSIGNED 1 #endif -/* Pick ttyS5. This could be one of USART2-4. It can't be UART0-1 or - * USART0-1 because those have already been assigned to ttsyS0, 1, 2, - * 3 or 4. One of USART2-4 could also be the console. +/* Pick ttyS8. This could be one of USART2-4. It can't be UART0-4 + * or USART0-1; those have already been assigned to ttsyS0-5. One of + * USART2-4 could also be the console. */ #if defined(CONFIG_SAMA5_USART2) && !defined(USART2_ASSIGNED) -# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ +# define TTYS8_DEV g_usart2port /* USART2 is ttyS8 */ # define USART2_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART3) && !defined(USART3_ASSIGNED) -# define TTYS5_DEV g_usart3port /* USART3 is ttyS5 */ +# define TTYS8_DEV g_usart3port /* USART3 is ttyS8 */ # define USART3_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART4) && !defined(USART4_ASSIGNED) -# define TTYS5_DEV g_usart3port /* USART4 is ttyS5 */ +# define TTYS8_DEV g_usart4port /* USART4 is ttyS8 */ # define USART4_ASSIGNED 1 #endif -/* Pick ttyS6. This could be one of USART3-4. It can't be UART0-1 or - * USART0-2 because those have already been assigned to ttsyS0, 1, 2, - * 3, 4, or 5. One of USART3-4 could also be the console. +/* Pick ttyS9. This could be one of USART3-4. It can't be UART0-4 + * or USART0-2; those have already been assigned to ttsyS0-8. One of + * USART3-4 could also be the console. */ #if defined(CONFIG_SAMA5_USART3) && !defined(USART3_ASSIGNED) -# define TTYS6_DEV g_usart3port /* USART3 is ttyS6 */ +# define TTYS9_DEV g_usart3port /* USART3 is ttyS9 */ # define USART3_ASSIGNED 1 #elif defined(CONFIG_SAMA5_USART4) && !defined(USART4_ASSIGNED) -# define TTYS6_DEV g_usart3port /* USART4 is ttyS6 */ +# define TTYS9_DEV g_usart4port /* USART4 is ttyS9 */ # define USART4_ASSIGNED 1 #endif -/* The UART/USART modules are driven by the peripheral clock (MCK or MCK2). */ + /* The UART/USART modules are driven by the peripheral clock (MCK or MCK2). */ #define SAM_USART_CLOCK BOARD_USART_FREQUENCY /* Frequency of the USART clock */ #define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ @@ -459,6 +661,18 @@ static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #endif +#ifdef CONFIG_SAMA5_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif +#ifdef CONFIG_SAMA5_UART3 +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif +#ifdef CONFIG_SAMA5_UART4 +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif #ifdef CONFIG_SAMA5_USART0 static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE]; @@ -540,6 +754,96 @@ static uart_dev_t g_uart1port = }; #endif +/* This describes the state of the UART2 port. */ + +#ifdef CONFIG_SAMA5_UART2 +static struct up_dev_s g_uart2priv = +{ + .usartbase = SAM_UART2_VBASE, + .baud = CONFIG_UART2_BAUD, + .irq = SAM_IRQ_UART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/* This describes the state of the UART3 port. */ + +#ifdef CONFIG_SAMA5_UART3 +static struct up_dev_s g_uart3priv = +{ + .usartbase = SAM_UART3_VBASE, + .baud = CONFIG_UART3_BAUD, + .irq = SAM_IRQ_UART3, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stopbits2 = CONFIG_UART3_2STOP, +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +/* This describes the state of the UART4 port. */ + +#ifdef CONFIG_SAMA5_UART4 +static struct up_dev_s g_uart4priv = +{ + .usartbase = SAM_UART4_VBASE, + .baud = CONFIG_UART4_BAUD, + .irq = SAM_IRQ_UART4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, +}; + +static uart_dev_t g_uart4port = +{ + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + /* This describes the state of the USART0 port. */ #ifdef CONFIG_SAMA5_USART0 @@ -830,6 +1134,15 @@ static int up_setup(struct uart_dev_s *dev) #endif #if defined(CONFIG_SAMA5_UART1) && priv->usartbase != SAM_UART1_VBASE +#endif +#if defined(CONFIG_SAMA5_UART2) +# warning REVIST +#endif +#if defined(CONFIG_SAMA5_UART3) +# warning REVIST +#endif +#if defined(CONFIG_SAMA5_UART4) +# warning REVIST #endif ) { @@ -995,6 +1308,27 @@ static int up_interrupt(int irq, void *context) } else #endif +#ifdef CONFIG_SAMA5_UART2 + if (g_uart2priv.irq == irq) + { + dev = &g_uart2port; + } + else +#endif +#ifdef CONFIG_SAMA5_UART3 + if (g_uart3priv.irq == irq) + { + dev = &g_uart3port; + } + else +#endif +#ifdef CONFIG_SAMA5_UART4 + if (g_uart4priv.irq == irq) + { + dev = &g_uart4port; + } + else +#endif #ifdef CONFIG_SAMA5_USART0 if (g_usart0priv.irq == irq) { @@ -1474,6 +1808,15 @@ void sam_earlyserialinit(void) #ifdef TTYS6_DEV up_disableallints(TTYS6_DEV.priv, NULL); #endif +#ifdef TTYS7_DEV + up_disableallints(TTYS7_DEV.priv, NULL); +#endif +#ifdef TTYS8_DEV + up_disableallints(TTYS8_DEV.priv, NULL); +#endif +#ifdef TTYS9_DEV + up_disableallints(TTYS9_DEV.priv, NULL); +#endif /* Configuration whichever one is the console */ @@ -1523,6 +1866,15 @@ void up_serialinit(void) #ifdef TTYS6_DEV (void)uart_register("/dev/ttyS6", &TTYS6_DEV); #endif +#ifdef TTYS7_DEV + (void)uart_register("/dev/ttyS7", &TTYS7_DEV); +#endif +#ifdef TTYS8_DEV + (void)uart_register("/dev/ttyS8", &TTYS8_DEV); +#endif +#ifdef TTYS9_DEV + (void)uart_register("/dev/ttyS9", &TTYS9_DEV); +#endif /* Register the DBGU as well */