mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 00:14:22 +08:00
Add EtherCAT support on xmc4800-relax.
This commit is contained in:
Rdk-T
Xiang Xiao
@@ -47,3 +47,7 @@ endif
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ifeq ($(CONFIG_XMC4_USCI_SPI),y)
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CHIP_CSRCS += xmc4_spi.c
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endif
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ifeq ($(CONFIG_ECAT),y)
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CHIP_CSRCS += xmc4_ecat.c
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endif
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@@ -373,6 +373,60 @@
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#define GPIO_EBU_SDCLKO_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN8)
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#define GPIO_EBU_SDCLKO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN4)
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#define GPIO_EBU_WAIT (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN3)
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#define GPIO_ECAT_CONF_OUTPUT GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | GPIO_PINCTRL_SOFTWARE | GPIO_OUTPUT_CLEAR
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#define GPIO_ECAT_CLK_25_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN0 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_CLK_25_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN13 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_LED_RUN (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN8 | GPIO_OUTPUT_ALT3)
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#define GPIO_ECAT_LED_ERR (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN7 | GPIO_OUTPUT_ALT3)
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#define GPIO_ECAT_MCLK (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN3 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_MDO (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN12)
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#define GPIO_ECAT_P0_LED_LINK_ACT_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN3 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_LED_LINK_ACT_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN12 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_LINK_STATUS (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN15)
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#define GPIO_ECAT_P0_RXD0_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0)
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#define GPIO_ECAT_P0_RXD0_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4)
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#define GPIO_ECAT_P0_RXD1_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN1)
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#define GPIO_ECAT_P0_RXD1_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5)
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#define GPIO_ECAT_P0_RXD2_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2)
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#define GPIO_ECAT_P0_RXD2_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN10)
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#define GPIO_ECAT_P0_RXD3_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN7)
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#define GPIO_ECAT_P0_RXD3_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN11)
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#define GPIO_ECAT_P0_RX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN4)
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#define GPIO_ECAT_P0_RX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1)
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#define GPIO_ECAT_P0_RX_DV_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN6)
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#define GPIO_ECAT_P0_RX_DV_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN9)
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#define GPIO_ECAT_P0_RX_ERR (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6)
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#define GPIO_ECAT_P0_TX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN5)
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#define GPIO_ECAT_P0_TX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0)
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#define GPIO_ECAT_P0_TXD0_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN2 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_TXD0_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN6 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P0_TXD1_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN4 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_TXD1_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN7 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P0_TXD2_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN5 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_TXD2_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P0_TXD3_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_TXD3_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN2 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P0_TX_EN_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN1 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_P0_TX_EN_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN3 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P1_LED_LINK_ACT (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN12 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P1_LINK_STATUS_1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4)
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#define GPIO_ECAT_P1_LINK_STATUS_2 (GPIO_INPUT_PULLUP | GPIO_PORT15 | GPIO_PIN3)
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#define GPIO_ECAT_P1_RXD0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN11)
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#define GPIO_ECAT_P1_RXD1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_ECAT_P1_RXD2 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN5)
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#define GPIO_ECAT_P1_RXD3 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_ECAT_P1_RX_CLK (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1)
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#define GPIO_ECAT_P1_RX_DV (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_ECAT_P1_RX_ERR (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN2)
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#define GPIO_ECAT_P1_TX_CLK (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN10)
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#define GPIO_ECAT_P1_TXD0 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN1 | GPIO_OUTPUT_ALT3)
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#define GPIO_ECAT_P1_TXD1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN2 | GPIO_OUTPUT_ALT3)
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#define GPIO_ECAT_P1_TXD2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN2 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P1_TXD3 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN3 | GPIO_OUTPUT_ALT1)
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#define GPIO_ECAT_P1_TX_EN (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT_ALT4)
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#define GPIO_ECAT_PHY_RESET (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN0 | GPIO_OUTPUT_ALT1)
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#define GPIO_ERU0_0A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1)
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#define GPIO_ERU0_0A1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN2)
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#define GPIO_ERU0_0A2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5)
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@@ -74,6 +74,9 @@
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#define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */
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#define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */
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#define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */
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#define XMC4_SCU_ECAT0CON_OFFSET 0x01b0 /* EtherCAT 0 Common Port Control */
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#define XMC4_SCU_ECAT0CONP0_OFFSET 0x01b4 /* EtherCAT 0 Port 0 Control */
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#define XMC4_SCU_ECAT0CONP1_OFFSET 0x01b8 /* EtherCAT 0 Port 1 Control */
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#define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */
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#define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */
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#define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */
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@@ -164,6 +167,7 @@
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#define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */
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#define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */
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#define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */
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#define XMC4_SCU_ECATCLKCR_OFFSET 0x0038 /* EtherCat Control Register */
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#ifdef XMC4_SCU_GATING
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# define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */
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# define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */
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@@ -206,6 +210,9 @@
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#define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET)
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#define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET)
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#define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET)
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#define XMC4_SCU_ECAT0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CON_OFFSET)
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#define XMC4_SCU_ECAT0CONP0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CONP0_OFFSET)
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#define XMC4_SCU_ECAT0CONP1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CONP1_OFFSET)
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#define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET)
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#define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET)
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#define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET)
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@@ -296,6 +303,7 @@
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#define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET)
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#define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET)
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#define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET)
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#define XMC4_SCU_ECATCLKCR (XMC4_SCU_CLK_BASE+ XMC4_SCU_ECATCLKCR_OFFSET)
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#ifdef XMC4_SCU_GATING
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# define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET)
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# define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET)
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@@ -454,6 +462,122 @@
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# define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */
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# define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */
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/* EtherCAT 0 Port Control */
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/* Common */
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#define SCU_ECAT0CON_MDIO_SHIFT (22)
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#define SCU_ECAT0CON_MDIOA (0 << SCU_ECAT0CON_MDIO_SHIFT)
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#define SCU_ECAT0CON_MDIOB (1 << SCU_ECAT0CON_MDIO_SHIFT)
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#define SCU_ECAT0CON_MDIOC (2 << SCU_ECAT0CON_MDIO_SHIFT)
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#define SCU_ECAT0CON_MDIOD (3 << SCU_ECAT0CON_MDIO_SHIFT)
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#define SCU_ECAT0CON_PHY_OFFSET_SHIFT (16)
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#define SCU_ECAT0CON_PHY_OFFSET (1 << SCU_ECAT0CON_PHY_OFFSET_SHIFT)
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#define SCU_ECAT0CON_ECATRSTEN_SHIFT (0)
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#define SCU_ECAT0CON_ECATRSTEN (0 << SCU_ECAT0CON_ECATRSTEN_SHIFT)
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/* Port 0 */
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#define SCU_ECAT0CON_RXD0_SHIFT (0)
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#define SCU_ECAT0CON_PORT0_RXD0A (0 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD0B (1 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD0C (2 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD0D (3 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_RXD1_SHIFT (2)
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#define SCU_ECAT0CON_PORT0_RXD1A (0 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD1B (1 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD1C (2 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD1D (3 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_RXD2_SHIFT (4)
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#define SCU_ECAT0CON_PORT0_RXD2A (0 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD2B (1 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD2C (2 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD2D (3 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_RXD3_SHIFT (6)
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#define SCU_ECAT0CON_PORT0_RXD3A (0 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD3B (1 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD3C (2 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT0_RXD3D (3 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_RX_ERR_SHIFT (8)
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#define SCU_ECAT0CON_PORT0_RX_ERRA (0 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_ERRB (1 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_ERRC (2 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_ERRD (3 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_RX_DV_SHIFT (10)
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#define SCU_ECAT0CON_PORT0_RX_DVA (0 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_DVB (1 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_DVC (2 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_DVD (3 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_RX_CLK_SHIFT (12)
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#define SCU_ECAT0CON_PORT0_RX_CLKA (0 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_CLKB (1 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_CLKC (2 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT0_RX_CLKD (3 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_LINK_SHIFT (16)
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#define SCU_ECAT0CON_PORT0_LINKA (0 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT0_LINKB (1 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT0_LINKC (2 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT0_LINKD (3 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_TX_CLK_SHIFT (28)
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#define SCU_ECAT0CON_PORT0_TX_CLKA (0 << SCU_ECAT0CON_TX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT0_TX_CLKB (1 << SCU_ECAT0CON_TX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT0_TX_CLKC (2 << SCU_ECAT0CON_TX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT0_TX_CLKD (3 << SCU_ECAT0CON_TX_CLK_SHIFT)
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/* Port 1 */
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#define SCU_ECAT0CON_PORT1_RXD0A (0 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD0B (1 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD0C (2 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD0D (3 << SCU_ECAT0CON_RXD0_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD1A (0 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD1B (1 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD1C (2 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD1D (3 << SCU_ECAT0CON_RXD1_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD2A (0 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD2B (1 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD2C (2 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD2D (3 << SCU_ECAT0CON_RXD2_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD3A (0 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD3B (1 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD3C (2 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT1_RXD3D (3 << SCU_ECAT0CON_RXD3_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_ERRA (0 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_ERRB (1 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_ERRC (2 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_ERRD (3 << SCU_ECAT0CON_RX_ERR_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_DVA (0 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_DVB (1 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_DVC (2 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_DVD (3 << SCU_ECAT0CON_RX_DV_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_CLKA (0 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_CLKB (1 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_CLKC (2 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT1_RX_CLKD (3 << SCU_ECAT0CON_RX_CLK_SHIFT)
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#define SCU_ECAT0CON_PORT1_LINKA (0 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT1_LINKB (1 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT1_LINKC (2 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT1_LINKD (3 << SCU_ECAT0CON_LINK_SHIFT)
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#define SCU_ECAT0CON_PORT1_TX_CLKA (0 << SCU_ECAT0CON_TX_CLK_SHIFT)
|
||||
#define SCU_ECAT0CON_PORT1_TX_CLKB (1 << SCU_ECAT0CON_TX_CLK_SHIFT)
|
||||
#define SCU_ECAT0CON_PORT1_TX_CLKC (2 << SCU_ECAT0CON_TX_CLK_SHIFT)
|
||||
#define SCU_ECAT0CON_PORT1_TX_CLKD (3 << SCU_ECAT0CON_TX_CLK_SHIFT)
|
||||
|
||||
/* CCUx Global Start Control Register */
|
||||
|
||||
#define SCU_CCUCON_GSC40 (1 << 0) /* Bit 0: Global Start Control CCU40 */
|
||||
@@ -871,6 +995,7 @@
|
||||
#define SCU_PR2_DMA1RS (1 << 5) /* Bit 5: DMA1 Reset */
|
||||
#define SCU_PR2_FCERS (1 << 6) /* Bit 6: FCE Reset */
|
||||
#define SCU_PR2_USBRS (1 << 7) /* Bit 7: USB Reset */
|
||||
#define SCU_PR2_ECAT0RS (1 << 10) /* Bit 10: ECAT0 Reset */
|
||||
|
||||
/* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3,
|
||||
* Peripheral Reset Clear Register 3
|
||||
|
||||
@@ -483,7 +483,7 @@ void xmc4_clock_configure(void)
|
||||
|
||||
regval = getreg32(XMC4_SCU_USBPLLCON);
|
||||
regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD);
|
||||
getreg32(regval, XMC4_SCU_USBPLLCON);
|
||||
putreg32(regval, XMC4_SCU_USBPLLCON);
|
||||
|
||||
/* USB PLL uses as clock input the OSC_HP */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,49 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/xmc4/xmc4_ecat.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: xmc4_ecat_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the EtherCAT module. Configure the pins, the PLL, the
|
||||
* physical ports and run the start up sequence.
|
||||
* See chapter "16.14 Initialization and System Dependencies" from
|
||||
* Infineon-ReferenceManual_XMC4700_XMC4800-UM-v01_03-EN.pdf for
|
||||
* references.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void xmc4_ecat_initialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: xmc4_ecat_initialize_port_control
|
||||
*
|
||||
* Description:
|
||||
* Apply the proper physical port configuration based on the pin properties
|
||||
* defined in board.h according to "26.10.1 Port I/O Function Table" from
|
||||
* Infineon-ReferenceManual_XMC4700_XMC4800-UM-v01_03-EN.pdf.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void xmc4_ecat_initialize_port_control(void);
|
||||
@@ -2,3 +2,12 @@
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_XMC4800RELAX
|
||||
|
||||
config ECAT
|
||||
bool "Enable EtherCAT interface"
|
||||
default y
|
||||
---help---
|
||||
Enable start up of the EtherCAT interface and configure ports.
|
||||
endif
|
||||
|
||||
@@ -228,9 +228,9 @@
|
||||
* fUSBPLLVCO <= 520 MHz
|
||||
*/
|
||||
|
||||
#undef BOARD_ENABLE_USBPLL
|
||||
#define BOARD_USB_PDIV 2
|
||||
#define BOARD_USB_NDIV 64
|
||||
#define BOARD_ENABLE_USBPLL
|
||||
#define BOARD_USB_PDIV 3
|
||||
#define BOARD_USB_NDIV 100
|
||||
|
||||
/* FLASH wait states */
|
||||
|
||||
@@ -323,6 +323,47 @@
|
||||
#define GPIO_SPI4_MISO (GPIO_U2C0_DX0C)
|
||||
#define GPIO_SPI4_SCLK (GPIO_U2C0_SCLKOUT_1 | GPIO_PADA2_STRONGMEDIUM)
|
||||
|
||||
/* ECAT0 configuration */
|
||||
|
||||
#define ECAT_CLK_25 GPIO_ECAT_CLK_25_1
|
||||
#define ECAT_LED_ERR GPIO_ECAT_LED_ERR
|
||||
#define ECAT_LED_RUN GPIO_ECAT_LED_RUN
|
||||
#define ECAT_MCLK GPIO_ECAT_MCLK
|
||||
#define ECAT_MDO GPIO_ECAT_MDO
|
||||
#define ECAT_PHY_RESET GPIO_ECAT_PHY_RESET
|
||||
|
||||
#define ECAT_P0_LED_LINK_ACT GPIO_ECAT_P0_LED_LINK_ACT_1
|
||||
#define ECAT_P0_LINK_STATUS GPIO_ECAT_P0_LINK_STATUS
|
||||
#define ECAT_P0_RXD0 GPIO_ECAT_P0_RXD0_1
|
||||
#define ECAT_P0_RXD1 GPIO_ECAT_P0_RXD1_1
|
||||
#define ECAT_P0_RXD2 GPIO_ECAT_P0_RXD2_1
|
||||
#define ECAT_P0_RXD3 GPIO_ECAT_P0_RXD3_1
|
||||
#define ECAT_P0_RX_CLK GPIO_ECAT_P0_RX_CLK_1
|
||||
#define ECAT_P0_RX_DV GPIO_ECAT_P0_RX_DV_1
|
||||
#define ECAT_P0_RX_ERR GPIO_ECAT_P0_RX_ERR
|
||||
#define ECAT_P0_TX_CLK GPIO_ECAT_P0_TX_CLK_1
|
||||
#define ECAT_P0_TXD0 GPIO_ECAT_P0_TXD0_1
|
||||
#define ECAT_P0_TXD1 GPIO_ECAT_P0_TXD1_1
|
||||
#define ECAT_P0_TXD2 GPIO_ECAT_P0_TXD2_1
|
||||
#define ECAT_P0_TXD3 GPIO_ECAT_P0_TXD3_1
|
||||
#define ECAT_P0_TX_EN GPIO_ECAT_P0_TX_EN_1
|
||||
|
||||
#define ECAT_P1_LED_LINK_ACT GPIO_ECAT_P1_LED_LINK_ACT
|
||||
#define ECAT_P1_LINK_STATUS GPIO_ECAT_P1_LINK_STATUS_1
|
||||
#define ECAT_P1_RXD0 GPIO_ECAT_P1_RXD0
|
||||
#define ECAT_P1_RXD1 GPIO_ECAT_P1_RXD1
|
||||
#define ECAT_P1_RXD2 GPIO_ECAT_P1_RXD2
|
||||
#define ECAT_P1_RXD3 GPIO_ECAT_P1_RXD3
|
||||
#define ECAT_P1_RX_CLK GPIO_ECAT_P1_RX_CLK
|
||||
#define ECAT_P1_RX_DV GPIO_ECAT_P1_RX_DV
|
||||
#define ECAT_P1_RX_ERR GPIO_ECAT_P1_RX_ERR
|
||||
#define ECAT_P1_TX_CLK GPIO_ECAT_P1_TX_CLK
|
||||
#define ECAT_P1_TXD0 GPIO_ECAT_P1_TXD0
|
||||
#define ECAT_P1_TXD1 GPIO_ECAT_P1_TXD1
|
||||
#define ECAT_P1_TXD2 GPIO_ECAT_P1_TXD2
|
||||
#define ECAT_P1_TXD3 GPIO_ECAT_P1_TXD3
|
||||
#define ECAT_P1_TX_EN GPIO_ECAT_P1_TX_EN
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
@@ -29,6 +29,8 @@
|
||||
|
||||
#include "xmc4800-relax.h"
|
||||
|
||||
#include "xmc4_ecat.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@@ -55,6 +57,10 @@ void xmc4_board_initialize(void)
|
||||
#ifdef CONFIG_XMC4_USCI_SPI
|
||||
xmc4_spidev_initialize();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ECAT
|
||||
xmc4_ecat_initialize();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
Reference in New Issue
Block a user