diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 20604841612..9d96fb2c21a 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -47,3 +47,7 @@ endif ifeq ($(CONFIG_XMC4_USCI_SPI),y) CHIP_CSRCS += xmc4_spi.c endif + +ifeq ($(CONFIG_ECAT),y) +CHIP_CSRCS += xmc4_ecat.c +endif diff --git a/arch/arm/src/xmc4/hardware/xmc4_pinmux.h b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h index 6d00ebd2a8f..a7194eb746e 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_pinmux.h +++ b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h @@ -373,6 +373,60 @@ #define GPIO_EBU_SDCLKO_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN8) #define GPIO_EBU_SDCLKO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN4) #define GPIO_EBU_WAIT (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN3) + +#define GPIO_ECAT_CONF_OUTPUT GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | GPIO_PINCTRL_SOFTWARE | GPIO_OUTPUT_CLEAR +#define GPIO_ECAT_CLK_25_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN0 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_CLK_25_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN13 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_LED_RUN (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN8 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_LED_ERR (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN7 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_MCLK (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN3 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_MDO (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_ECAT_P0_LED_LINK_ACT_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN3 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_LED_LINK_ACT_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN12 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_LINK_STATUS (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_ECAT_P0_RXD0_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_ECAT_P0_RXD0_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_ECAT_P0_RXD1_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_ECAT_P0_RXD1_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_ECAT_P0_RXD2_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_ECAT_P0_RXD2_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_ECAT_P0_RXD3_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_ECAT_P0_RXD3_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_ECAT_P0_RX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_ECAT_P0_RX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_ECAT_P0_RX_DV_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_ECAT_P0_RX_DV_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_ECAT_P0_RX_ERR (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_ECAT_P0_TX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_ECAT_P0_TX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_ECAT_P0_TXD0_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN2 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD0_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN6 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TXD1_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN4 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD1_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN7 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TXD2_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN5 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD2_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TXD3_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD3_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN2 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TX_EN_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN1 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TX_EN_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN3 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_LED_LINK_ACT (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN12 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_LINK_STATUS_1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_ECAT_P1_LINK_STATUS_2 (GPIO_INPUT_PULLUP | GPIO_PORT15 | GPIO_PIN3) +#define GPIO_ECAT_P1_RXD0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_ECAT_P1_RXD1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_ECAT_P1_RXD2 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_ECAT_P1_RXD3 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_ECAT_P1_RX_CLK (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_ECAT_P1_RX_DV (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_ECAT_P1_RX_ERR (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN2) +#define GPIO_ECAT_P1_TX_CLK (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_ECAT_P1_TXD0 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN1 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_P1_TXD1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN2 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_P1_TXD2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN2 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_TXD3 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN3 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_TX_EN (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_PHY_RESET (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN0 | GPIO_OUTPUT_ALT1) + #define GPIO_ERU0_0A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) #define GPIO_ERU0_0A1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN2) #define GPIO_ERU0_0A2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) diff --git a/arch/arm/src/xmc4/hardware/xmc4_scu.h b/arch/arm/src/xmc4/hardware/xmc4_scu.h index 0c0c44cae29..0f9d6c6a478 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_scu.h +++ b/arch/arm/src/xmc4/hardware/xmc4_scu.h @@ -74,6 +74,9 @@ #define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ #define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ #define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_SCU_ECAT0CON_OFFSET 0x01b0 /* EtherCAT 0 Common Port Control */ +#define XMC4_SCU_ECAT0CONP0_OFFSET 0x01b4 /* EtherCAT 0 Port 0 Control */ +#define XMC4_SCU_ECAT0CONP1_OFFSET 0x01b8 /* EtherCAT 0 Port 1 Control */ #define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ #define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */ #define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ @@ -164,6 +167,7 @@ #define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ #define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ #define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_SCU_ECATCLKCR_OFFSET 0x0038 /* EtherCat Control Register */ #ifdef XMC4_SCU_GATING # define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ # define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ @@ -206,6 +210,9 @@ #define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET) #define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET) #define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET) +#define XMC4_SCU_ECAT0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CON_OFFSET) +#define XMC4_SCU_ECAT0CONP0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CONP0_OFFSET) +#define XMC4_SCU_ECAT0CONP1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CONP1_OFFSET) #define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET) #define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET) #define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET) @@ -296,6 +303,7 @@ #define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET) #define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET) #define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET) +#define XMC4_SCU_ECATCLKCR (XMC4_SCU_CLK_BASE+ XMC4_SCU_ECATCLKCR_OFFSET) #ifdef XMC4_SCU_GATING # define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) # define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) @@ -454,6 +462,122 @@ # define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */ # define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */ +/* EtherCAT 0 Port Control */ + +/* Common */ +#define SCU_ECAT0CON_MDIO_SHIFT (22) +#define SCU_ECAT0CON_MDIOA (0 << SCU_ECAT0CON_MDIO_SHIFT) +#define SCU_ECAT0CON_MDIOB (1 << SCU_ECAT0CON_MDIO_SHIFT) +#define SCU_ECAT0CON_MDIOC (2 << SCU_ECAT0CON_MDIO_SHIFT) +#define SCU_ECAT0CON_MDIOD (3 << SCU_ECAT0CON_MDIO_SHIFT) + +#define SCU_ECAT0CON_PHY_OFFSET_SHIFT (16) +#define SCU_ECAT0CON_PHY_OFFSET (1 << SCU_ECAT0CON_PHY_OFFSET_SHIFT) + +#define SCU_ECAT0CON_ECATRSTEN_SHIFT (0) +#define SCU_ECAT0CON_ECATRSTEN (0 << SCU_ECAT0CON_ECATRSTEN_SHIFT) + +/* Port 0 */ +#define SCU_ECAT0CON_RXD0_SHIFT (0) +#define SCU_ECAT0CON_PORT0_RXD0A (0 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD0B (1 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD0C (2 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD0D (3 << SCU_ECAT0CON_RXD0_SHIFT) + +#define SCU_ECAT0CON_RXD1_SHIFT (2) +#define SCU_ECAT0CON_PORT0_RXD1A (0 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD1B (1 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD1C (2 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD1D (3 << SCU_ECAT0CON_RXD1_SHIFT) + +#define SCU_ECAT0CON_RXD2_SHIFT (4) +#define SCU_ECAT0CON_PORT0_RXD2A (0 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD2B (1 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD2C (2 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD2D (3 << SCU_ECAT0CON_RXD2_SHIFT) + +#define SCU_ECAT0CON_RXD3_SHIFT (6) +#define SCU_ECAT0CON_PORT0_RXD3A (0 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD3B (1 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD3C (2 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD3D (3 << SCU_ECAT0CON_RXD3_SHIFT) + +#define SCU_ECAT0CON_RX_ERR_SHIFT (8) +#define SCU_ECAT0CON_PORT0_RX_ERRA (0 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_ERRB (1 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_ERRC (2 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_ERRD (3 << SCU_ECAT0CON_RX_ERR_SHIFT) + +#define SCU_ECAT0CON_RX_DV_SHIFT (10) +#define SCU_ECAT0CON_PORT0_RX_DVA (0 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_DVB (1 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_DVC (2 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_DVD (3 << SCU_ECAT0CON_RX_DV_SHIFT) + +#define SCU_ECAT0CON_RX_CLK_SHIFT (12) +#define SCU_ECAT0CON_PORT0_RX_CLKA (0 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_CLKB (1 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_CLKC (2 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_CLKD (3 << SCU_ECAT0CON_RX_CLK_SHIFT) + +#define SCU_ECAT0CON_LINK_SHIFT (16) +#define SCU_ECAT0CON_PORT0_LINKA (0 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT0_LINKB (1 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT0_LINKC (2 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT0_LINKD (3 << SCU_ECAT0CON_LINK_SHIFT) + +#define SCU_ECAT0CON_TX_CLK_SHIFT (28) +#define SCU_ECAT0CON_PORT0_TX_CLKA (0 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_TX_CLKB (1 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_TX_CLKC (2 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_TX_CLKD (3 << SCU_ECAT0CON_TX_CLK_SHIFT) + +/* Port 1 */ +#define SCU_ECAT0CON_PORT1_RXD0A (0 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD0B (1 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD0C (2 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD0D (3 << SCU_ECAT0CON_RXD0_SHIFT) + +#define SCU_ECAT0CON_PORT1_RXD1A (0 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD1B (1 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD1C (2 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD1D (3 << SCU_ECAT0CON_RXD1_SHIFT) + +#define SCU_ECAT0CON_PORT1_RXD2A (0 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD2B (1 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD2C (2 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD2D (3 << SCU_ECAT0CON_RXD2_SHIFT) + +#define SCU_ECAT0CON_PORT1_RXD3A (0 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD3B (1 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD3C (2 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD3D (3 << SCU_ECAT0CON_RXD3_SHIFT) + +#define SCU_ECAT0CON_PORT1_RX_ERRA (0 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_ERRB (1 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_ERRC (2 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_ERRD (3 << SCU_ECAT0CON_RX_ERR_SHIFT) + +#define SCU_ECAT0CON_PORT1_RX_DVA (0 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_DVB (1 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_DVC (2 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_DVD (3 << SCU_ECAT0CON_RX_DV_SHIFT) + +#define SCU_ECAT0CON_PORT1_RX_CLKA (0 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_CLKB (1 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_CLKC (2 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_CLKD (3 << SCU_ECAT0CON_RX_CLK_SHIFT) + +#define SCU_ECAT0CON_PORT1_LINKA (0 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT1_LINKB (1 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT1_LINKC (2 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT1_LINKD (3 << SCU_ECAT0CON_LINK_SHIFT) + +#define SCU_ECAT0CON_PORT1_TX_CLKA (0 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_TX_CLKB (1 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_TX_CLKC (2 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_TX_CLKD (3 << SCU_ECAT0CON_TX_CLK_SHIFT) + /* CCUx Global Start Control Register */ #define SCU_CCUCON_GSC40 (1 << 0) /* Bit 0: Global Start Control CCU40 */ @@ -871,6 +995,7 @@ #define SCU_PR2_DMA1RS (1 << 5) /* Bit 5: DMA1 Reset */ #define SCU_PR2_FCERS (1 << 6) /* Bit 6: FCE Reset */ #define SCU_PR2_USBRS (1 << 7) /* Bit 7: USB Reset */ +#define SCU_PR2_ECAT0RS (1 << 10) /* Bit 10: ECAT0 Reset */ /* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3, * Peripheral Reset Clear Register 3 diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 1f95fa44e5e..78924a619af 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -483,7 +483,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_USBPLLCON); regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD); - getreg32(regval, XMC4_SCU_USBPLLCON); + putreg32(regval, XMC4_SCU_USBPLLCON); /* USB PLL uses as clock input the OSC_HP */ diff --git a/arch/arm/src/xmc4/xmc4_ecat.c b/arch/arm/src/xmc4/xmc4_ecat.c new file mode 100644 index 00000000000..e8b15310187 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_ecat.c @@ -0,0 +1,682 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_ecat.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "xmc4_ecat.h" + +#include +#include + +#include "arm_internal.h" +#include "hardware/xmc4_pinmux.h" +#include "hardware/xmc4_scu.h" +#include "debug.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void xmc4_ecat_initialize() +{ + /* Init inputs */ + + xmc4_gpio_config(ECAT_P0_LINK_STATUS); + xmc4_gpio_config(ECAT_P0_RXD3); + xmc4_gpio_config(ECAT_P0_RXD2); + xmc4_gpio_config(ECAT_P0_RXD1); + xmc4_gpio_config(ECAT_P0_RXD0); + xmc4_gpio_config(ECAT_P0_RX_DV); + xmc4_gpio_config(ECAT_P0_RX_CLK); + xmc4_gpio_config(ECAT_P0_RX_ERR); + xmc4_gpio_config(ECAT_P0_TX_CLK); + xmc4_gpio_config(ECAT_P1_LINK_STATUS); + xmc4_gpio_config(ECAT_P1_RXD3); + xmc4_gpio_config(ECAT_P1_RXD2); + xmc4_gpio_config(ECAT_P1_RXD1); + xmc4_gpio_config(ECAT_P1_RXD0); + xmc4_gpio_config(ECAT_P1_RX_DV); + xmc4_gpio_config(ECAT_P1_RX_CLK); + xmc4_gpio_config(ECAT_P1_RX_ERR); + xmc4_gpio_config(ECAT_P1_TX_CLK); + xmc4_gpio_config(ECAT_MDO); + + /* Init outputs */ + + xmc4_gpio_config(ECAT_P0_LED_LINK_ACT); + xmc4_gpio_config(ECAT_P0_TXD3); + xmc4_gpio_config(ECAT_P0_TXD2); + xmc4_gpio_config(ECAT_P0_TXD1); + xmc4_gpio_config(ECAT_P0_TXD0); + xmc4_gpio_config(ECAT_P0_TX_EN); + xmc4_gpio_config(ECAT_P1_LED_LINK_ACT); + xmc4_gpio_config(ECAT_P1_TXD3); + xmc4_gpio_config(ECAT_P1_TXD2); + xmc4_gpio_config(ECAT_P1_TXD1); + xmc4_gpio_config(ECAT_P1_TXD0); + xmc4_gpio_config(ECAT_P1_TX_EN); + xmc4_gpio_config(ECAT_CLK_25); + xmc4_gpio_config(ECAT_LED_ERR); + xmc4_gpio_config(ECAT_LED_RUN); + xmc4_gpio_config(ECAT_MCLK); + xmc4_gpio_config(ECAT_PHY_RESET); + + /* configure PLL */ + + #define SCU_ECATCLKCR_PLL ((0 << 16) | (1 << 0)) + putreg32(SCU_ECATCLKCR_PLL, XMC4_SCU_ECATCLKCR); + + /* ECAT reset */ + + putreg32(SCU_PR2_ECAT0RS, XMC4_SCU_PRSET2); + while (!(getreg32(XMC4_SCU_PRSTAT2) & SCU_PR2_ECAT0RS)) /* is ecat reset */ + { + }; + + /* Gate peripheral clock */ + + putreg32(SCU_CGAT2_ECAT, XMC4_SCU_CGATSET2); + + /* init port control MII */ + + xmc4_ecat_initialize_port_control(); + + /* ECAT init, Ungate peripheral */ + + putreg32(SCU_CGAT2_ECAT, XMC4_SCU_CGATCLR2); + + /* Deassert reset */ + + putreg32(SCU_PR2_ECAT0RS, XMC4_SCU_PRCLR2); + while ((getreg32(XMC4_SCU_PRSTAT2) & SCU_PR2_ECAT0RS)) /* is ecat reset */ + { + }; +} + +void xmc4_ecat_initialize_port_control() +{ + /* common */ + + uint32_t mdio_conf = 0; + switch (ECAT_MDO & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN12: + { + mdio_conf = SCU_ECAT0CON_MDIOA; + break; + } + + case GPIO_PORT4 | GPIO_PIN2: + { + mdio_conf = SCU_ECAT0CON_MDIOB; + break; + } + + case GPIO_PORT9 | GPIO_PIN7: + { + mdio_conf = SCU_ECAT0CON_MDIOC; + break; + } + + default: + { + nerr("Unknown mdio config \n"); + } + } + + uint32_t ecat0_con_conf = 0; + ecat0_con_conf |= SCU_ECAT0CON_PHY_OFFSET; + ecat0_con_conf |= SCU_ECAT0CON_ECATRSTEN; + ecat0_con_conf |= mdio_conf; + + /* port0 */ + + uint32_t port0_rxd0_conf = 0; + switch (ECAT_P0_RXD0 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN4: + { + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0A; + break; + } + + case GPIO_PORT5 | GPIO_PIN0: + { + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0B; + break; + } + + case GPIO_PORT7 | GPIO_PIN4: + { + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0C; + break; + } + + default: + { + nerr("Unknown port0_rxd0 config \n"); + } + } + + uint32_t port0_rxd1_conf = 0; + switch (ECAT_P0_RXD1 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN5: + { + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1A; + break; + } + + case GPIO_PORT5 | GPIO_PIN1: + { + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1B; + break; + } + + case GPIO_PORT7 | GPIO_PIN5: + { + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1C; + break; + } + + default: + { + nerr("Unknown port0_rxd1 config \n"); + } + } + + uint32_t port0_rxd2_conf = 0; + switch (ECAT_P0_RXD2 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN10: + { + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2A; + break; + } + + case GPIO_PORT5 | GPIO_PIN2: + { + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2B; + break; + } + + case GPIO_PORT7 | GPIO_PIN6: + { + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2C; + break; + } + + default: + { + nerr("Unknown port0_rxd2 config \n"); + } + } + + uint32_t port0_rxd3_conf = 0; + switch (ECAT_P0_RXD3 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN11: + { + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3A; + break; + } + + case GPIO_PORT5 | GPIO_PIN7: + { + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3B; + break; + } + + case GPIO_PORT7 | GPIO_PIN7: + { + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3C; + break; + } + + default: + { + nerr("Unknown port0_rxd2 config \n"); + } + } + + uint32_t port0_rx_clk_conf = 0; + switch (ECAT_P0_RX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN1: + { + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKA; + break; + } + + case GPIO_PORT5 | GPIO_PIN4: + { + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKB; + break; + } + + case GPIO_PORT7 | GPIO_PIN10: + { + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKC; + break; + } + + default: + { + nerr("Unknown port0_rx_clk config \n"); + } + } + + uint32_t port0_rx_dv_conf = 0; + switch (ECAT_P0_RX_DV & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN9: + { + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVA; + break; + } + + case GPIO_PORT5 | GPIO_PIN6: + { + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVB; + break; + } + + case GPIO_PORT7 | GPIO_PIN11: + { + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVC; + break; + } + + default: + { + nerr("Unknown port0_rx_dv config \n"); + } + } + + uint32_t port0_rx_err_conf = 0; + switch (ECAT_P0_RX_ERR & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT4 | GPIO_PIN0: + { + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRA; + break; + } + + case GPIO_PORT2 | GPIO_PIN6: + { + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRB; + break; + } + + case GPIO_PORT7 | GPIO_PIN9: + { + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRC; + break; + } + + default: + { + nerr("Unknown port0_rx_err config \n"); + } + } + + uint32_t port0_link_conf = 0; + switch (ECAT_P0_LINK_STATUS & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT4 | GPIO_PIN1: + { + port0_link_conf = SCU_ECAT0CON_PORT0_LINKA; + break; + } + + case GPIO_PORT1 | GPIO_PIN15: + { + port0_link_conf = SCU_ECAT0CON_PORT0_LINKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN10: + { + port0_link_conf = SCU_ECAT0CON_PORT0_LINKC; + break; + } + + default: + { + nerr("Unknown port0_link config \n"); + } + } + + uint32_t port0_tx_clk_conf = 0; + switch (ECAT_P0_TX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN0: + { + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKA; + break; + } + + case GPIO_PORT5 | GPIO_PIN5: + { + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN1: + { + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKC; + break; + } + + default: + { + nerr("Unknown port0_tx_clk config \n"); + } + } + + uint32_t ecat0_port0_conf = 0; + ecat0_port0_conf |= port0_rxd0_conf; + ecat0_port0_conf |= port0_rxd1_conf; + ecat0_port0_conf |= port0_rxd2_conf; + ecat0_port0_conf |= port0_rxd3_conf; + ecat0_port0_conf |= port0_rx_clk_conf; + ecat0_port0_conf |= port0_rx_dv_conf; + ecat0_port0_conf |= port0_rx_err_conf; + ecat0_port0_conf |= port0_link_conf; + ecat0_port0_conf |= port0_tx_clk_conf; + + putreg32(ecat0_port0_conf, XMC4_SCU_ECAT0CONP0); + + /* port 1 */ + + uint32_t port1_rxd0_conf = 0; + switch (ECAT_P1_RXD0 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN11: + { + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0A; + break; + } + + case GPIO_PORT14 | GPIO_PIN7: + { + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0B; + break; + } + + case GPIO_PORT8 | GPIO_PIN4: + { + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0C; + break; + } + + default: + { + nerr("Unknown port1_rxd0 config \n"); + } + } + + uint32_t port1_rxd1_conf = 0; + switch (ECAT_P1_RXD1 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN6: + { + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1A; + break; + } + + case GPIO_PORT14 | GPIO_PIN12: + { + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1B; + break; + } + + case GPIO_PORT8 | GPIO_PIN5: + { + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1C; + break; + } + + default: + { + nerr("Unknown port1_rxd1 config \n"); + } + } + + uint32_t port1_rxd2_conf = 0; + switch (ECAT_P1_RXD2 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN5: + { + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2A; + break; + } + + case GPIO_PORT14 | GPIO_PIN13: + { + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2B; + break; + } + + case GPIO_PORT8 | GPIO_PIN6: + { + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2C; + break; + } + + default: + { + nerr("Unknown port1_rxd2 config \n"); + } + } + + uint32_t port1_rxd3_conf = 0; + switch (ECAT_P1_RXD3 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN4: + { + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3A; + break; + } + + case GPIO_PORT14 | GPIO_PIN14: + { + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3B; + break; + } + + case GPIO_PORT8 | GPIO_PIN7: + { + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3C; + break; + } + + default: + { + nerr("Unknown port1_rxd3 config \n"); + } + } + + uint32_t port1_rx_clk_conf = 0; + switch (ECAT_P1_RX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN1: + { + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKA; + break; + } + + case GPIO_PORT14 | GPIO_PIN6: + { + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKB; + break; + } + + case GPIO_PORT8 | GPIO_PIN10: + { + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKC; + break; + } + + default: + { + nerr("Unknown port1_rx_clk config \n"); + } + } + + uint32_t port1_rx_dv_conf = 0; + switch (ECAT_P1_RX_DV & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN9: + { + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVA; + break; + } + + case GPIO_PORT14 | GPIO_PIN15: + { + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVB; + break; + } + + case GPIO_PORT8 | GPIO_PIN11: + { + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVC; + break; + } + + default: + { + nerr("Unknown port1_rx_dv config \n"); + } + } + + uint32_t port1_link_conf = 0; + switch (ECAT_P1_LINK_STATUS & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT3 | GPIO_PIN4: + { + port1_link_conf = SCU_ECAT0CON_PORT1_LINKA; + break; + } + + case GPIO_PORT15 | GPIO_PIN3: + { + port1_link_conf = SCU_ECAT0CON_PORT1_LINKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN11: + { + port1_link_conf = SCU_ECAT0CON_PORT1_LINKC; + break; + } + + default: + { + nerr("Unknown port1_link config \n"); + } + } + + uint32_t port1_tx_clk_conf = 0; + switch (ECAT_P1_TX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN10: + { + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKA; + break; + } + + case GPIO_PORT5 | GPIO_PIN9: + { + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN0: + { + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKC; + break; + } + + default: + { + nerr("Unknown port1_tx_clk config \n"); + } + } + + uint32_t port1_rx_err_conf = 0; + switch (ECAT_P1_RX_ERR & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT3 | GPIO_PIN5: + { + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRA; + break; + } + + case GPIO_PORT15 | GPIO_PIN2: + { + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRB; + break; + } + + case GPIO_PORT8 | GPIO_PIN9: + { + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRC; + break; + } + + default: + { + nerr("Unknown port1_rx_err config \n"); + } + } + + /* When port 1 is not available, the unused MII need to be tied + * to not connected pins. + */ + +#ifndef CONFIG_ECAT_P1_ENABLE + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0D; + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1D; + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2D; + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3D; + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKD; + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVD; + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRD; + port1_link_conf = SCU_ECAT0CON_PORT1_LINKB; + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKD; +#endif + + uint32_t ecat0_port1_conf = 0; + ecat0_port1_conf |= port1_rxd0_conf; + ecat0_port1_conf |= port1_rxd1_conf; + ecat0_port1_conf |= port1_rxd2_conf; + ecat0_port1_conf |= port1_rxd3_conf; + ecat0_port1_conf |= port1_rx_clk_conf; + ecat0_port1_conf |= port1_rx_dv_conf; + ecat0_port1_conf |= port1_rx_err_conf; + ecat0_port1_conf |= port1_link_conf; + ecat0_port1_conf |= port1_tx_clk_conf; + + putreg32(ecat0_port1_conf, XMC4_SCU_ECAT0CONP1); +} diff --git a/arch/arm/src/xmc4/xmc4_ecat.h b/arch/arm/src/xmc4/xmc4_ecat.h new file mode 100644 index 00000000000..27e0600e4fc --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_ecat.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_ecat.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_ecat_initialize + * + * Description: + * Initialize the EtherCAT module. Configure the pins, the PLL, the + * physical ports and run the start up sequence. + * See chapter "16.14 Initialization and System Dependencies" from + * Infineon-ReferenceManual_XMC4700_XMC4800-UM-v01_03-EN.pdf for + * references. + * + ****************************************************************************/ + +void xmc4_ecat_initialize(void); + +/**************************************************************************** + * Name: xmc4_ecat_initialize_port_control + * + * Description: + * Apply the proper physical port configuration based on the pin properties + * defined in board.h according to "26.10.1 Port I/O Function Table" from + * Infineon-ReferenceManual_XMC4700_XMC4800-UM-v01_03-EN.pdf. + * + ****************************************************************************/ + +void xmc4_ecat_initialize_port_control(void); diff --git a/boards/arm/xmc4/xmc4800-relax/Kconfig b/boards/arm/xmc4/xmc4800-relax/Kconfig index f72f3c094ce..4509e31a85a 100644 --- a/boards/arm/xmc4/xmc4800-relax/Kconfig +++ b/boards/arm/xmc4/xmc4800-relax/Kconfig @@ -2,3 +2,12 @@ # For a description of the syntax of this configuration file, # see the file kconfig-language.txt in the NuttX tools repository. # + +if ARCH_BOARD_XMC4800RELAX + +config ECAT + bool "Enable EtherCAT interface" + default y + ---help--- + Enable start up of the EtherCAT interface and configure ports. +endif diff --git a/boards/arm/xmc4/xmc4800-relax/include/board.h b/boards/arm/xmc4/xmc4800-relax/include/board.h index f999325df94..d5f07055479 100644 --- a/boards/arm/xmc4/xmc4800-relax/include/board.h +++ b/boards/arm/xmc4/xmc4800-relax/include/board.h @@ -228,9 +228,9 @@ * fUSBPLLVCO <= 520 MHz */ -#undef BOARD_ENABLE_USBPLL -#define BOARD_USB_PDIV 2 -#define BOARD_USB_NDIV 64 +#define BOARD_ENABLE_USBPLL +#define BOARD_USB_PDIV 3 +#define BOARD_USB_NDIV 100 /* FLASH wait states */ @@ -323,6 +323,47 @@ #define GPIO_SPI4_MISO (GPIO_U2C0_DX0C) #define GPIO_SPI4_SCLK (GPIO_U2C0_SCLKOUT_1 | GPIO_PADA2_STRONGMEDIUM) +/* ECAT0 configuration */ + +#define ECAT_CLK_25 GPIO_ECAT_CLK_25_1 +#define ECAT_LED_ERR GPIO_ECAT_LED_ERR +#define ECAT_LED_RUN GPIO_ECAT_LED_RUN +#define ECAT_MCLK GPIO_ECAT_MCLK +#define ECAT_MDO GPIO_ECAT_MDO +#define ECAT_PHY_RESET GPIO_ECAT_PHY_RESET + +#define ECAT_P0_LED_LINK_ACT GPIO_ECAT_P0_LED_LINK_ACT_1 +#define ECAT_P0_LINK_STATUS GPIO_ECAT_P0_LINK_STATUS +#define ECAT_P0_RXD0 GPIO_ECAT_P0_RXD0_1 +#define ECAT_P0_RXD1 GPIO_ECAT_P0_RXD1_1 +#define ECAT_P0_RXD2 GPIO_ECAT_P0_RXD2_1 +#define ECAT_P0_RXD3 GPIO_ECAT_P0_RXD3_1 +#define ECAT_P0_RX_CLK GPIO_ECAT_P0_RX_CLK_1 +#define ECAT_P0_RX_DV GPIO_ECAT_P0_RX_DV_1 +#define ECAT_P0_RX_ERR GPIO_ECAT_P0_RX_ERR +#define ECAT_P0_TX_CLK GPIO_ECAT_P0_TX_CLK_1 +#define ECAT_P0_TXD0 GPIO_ECAT_P0_TXD0_1 +#define ECAT_P0_TXD1 GPIO_ECAT_P0_TXD1_1 +#define ECAT_P0_TXD2 GPIO_ECAT_P0_TXD2_1 +#define ECAT_P0_TXD3 GPIO_ECAT_P0_TXD3_1 +#define ECAT_P0_TX_EN GPIO_ECAT_P0_TX_EN_1 + +#define ECAT_P1_LED_LINK_ACT GPIO_ECAT_P1_LED_LINK_ACT +#define ECAT_P1_LINK_STATUS GPIO_ECAT_P1_LINK_STATUS_1 +#define ECAT_P1_RXD0 GPIO_ECAT_P1_RXD0 +#define ECAT_P1_RXD1 GPIO_ECAT_P1_RXD1 +#define ECAT_P1_RXD2 GPIO_ECAT_P1_RXD2 +#define ECAT_P1_RXD3 GPIO_ECAT_P1_RXD3 +#define ECAT_P1_RX_CLK GPIO_ECAT_P1_RX_CLK +#define ECAT_P1_RX_DV GPIO_ECAT_P1_RX_DV +#define ECAT_P1_RX_ERR GPIO_ECAT_P1_RX_ERR +#define ECAT_P1_TX_CLK GPIO_ECAT_P1_TX_CLK +#define ECAT_P1_TXD0 GPIO_ECAT_P1_TXD0 +#define ECAT_P1_TXD1 GPIO_ECAT_P1_TXD1 +#define ECAT_P1_TXD2 GPIO_ECAT_P1_TXD2 +#define ECAT_P1_TXD3 GPIO_ECAT_P1_TXD3 +#define ECAT_P1_TX_EN GPIO_ECAT_P1_TX_EN + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c index 2a41dde74c1..08a7658588b 100644 --- a/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c @@ -29,6 +29,8 @@ #include "xmc4800-relax.h" +#include "xmc4_ecat.h" + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -55,6 +57,10 @@ void xmc4_board_initialize(void) #ifdef CONFIG_XMC4_USCI_SPI xmc4_spidev_initialize(); #endif + +#ifdef CONFIG_ECAT + xmc4_ecat_initialize(); +#endif } /****************************************************************************