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arch/arm/am67: Mark the DDR MPU region Non-shareable.

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LDREX/STREX to Shareable memory needs an external exclusive monitor, and this
Cortex-R5F has none on the path to DDR; Non-shareable uses the core-local
monitor instead.  Every atomic compiles to inline LDREX here, since the chip
selects no LIBC_ATOMIC_* backend and falls back to LIBC_ATOMIC_TOOLCHAIN.

Verified on t3-gem-o1: without this the core runs but the console never
appears; with it the same image boots and ostest exits with status 0.

Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
This commit is contained in:
Ulaş Sertan Kemeç
2026-09-11 02:59:59 +08:00
committed by Xiang Xiao
parent 5866c4e3af
commit 7d0b46b1f5
1 changed files with 5 additions and 2 deletions
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arch/arm/src/am67/am67_mpuinit.h
+5 -2
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@@ -101,14 +101,17 @@
MPU_RACR_AP_RWRW)
/* DDR REGION
* Shareable
* Non-shareable (do not add MPU_RACR_S)
* Cacheable
* Bufferable
* P:RW U:RW
*
* NOTE: if DDR is marked Shareable, LDREX/STREX to it take an external data
* abort on this R5F; Non-shareable uses the core-local monitor instead.
* Observed with ldrex-based code (e.g. C++ std::atomic).
*/
#define am67_ddr_region(base,size) \
mpu_configure_region(base, size, MPU_RACR_TEX(1) | \
MPU_RACR_S | \
MPU_RACR_C | \
MPU_RACR_B | \
MPU_RACR_AP_RWRW)