From 7d0b46b1f55945f9c719433f06bafb35ceb616bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ula=C5=9F=20Sertan=20Keme=C3=A7?= Date: Thu, 30 Jul 2026 12:05:07 +0300 Subject: [PATCH] arch/arm/am67: Mark the DDR MPU region Non-shareable. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LDREX/STREX to Shareable memory needs an external exclusive monitor, and this Cortex-R5F has none on the path to DDR; Non-shareable uses the core-local monitor instead. Every atomic compiles to inline LDREX here, since the chip selects no LIBC_ATOMIC_* backend and falls back to LIBC_ATOMIC_TOOLCHAIN. Verified on t3-gem-o1: without this the core runs but the console never appears; with it the same image boots and ostest exits with status 0. Assisted-by: Claude Code:claude-opus-4-8 Signed-off-by: Ulaş Sertan Kemeç --- arch/arm/src/am67/am67_mpuinit.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/am67/am67_mpuinit.h b/arch/arm/src/am67/am67_mpuinit.h index 1e8b3c1427d..9cf64c7ace4 100644 --- a/arch/arm/src/am67/am67_mpuinit.h +++ b/arch/arm/src/am67/am67_mpuinit.h @@ -101,14 +101,17 @@ MPU_RACR_AP_RWRW) /* DDR REGION - * Shareable + * Non-shareable (do not add MPU_RACR_S) * Cacheable * Bufferable * P:RW U:RW + * + * NOTE: if DDR is marked Shareable, LDREX/STREX to it take an external data + * abort on this R5F; Non-shareable uses the core-local monitor instead. + * Observed with ldrex-based code (e.g. C++ std::atomic). */ #define am67_ddr_region(base,size) \ mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ - MPU_RACR_S | \ MPU_RACR_C | \ MPU_RACR_B | \ MPU_RACR_AP_RWRW)