diff --git a/Documentation/platforms/tricore/index.rst b/Documentation/platforms/tricore/index.rst index d0cf6d644df..ad2ea204337 100644 --- a/Documentation/platforms/tricore/index.rst +++ b/Documentation/platforms/tricore/index.rst @@ -31,8 +31,8 @@ The core Chip implementation is based on Infineon Low Level Drivers (iLLDs). The unified API is more friendly to developers familiar with Infineon SDK/HAL. We can get more code examples on Infineon's official Github: `AURIX_code_examples `__ -``TC3xx`` - This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx microcontroller family. +``TC3xx/TC4xx`` + This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx/TC4xx microcontroller family. .. toctree:: :maxdepth: 1 diff --git a/Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst b/Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst new file mode 100644 index 00000000000..c3b391fc564 --- /dev/null +++ b/Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst @@ -0,0 +1,55 @@ +================== +TRIBOARD_TC4X9_COM +================== + +This port should work on TRIBOARD_TC4X9_COM with a proper CPU. +The mandatory CPU features are: + +* System Timer (STM) +* Asynchronous Serial Interface(ASCLIN) UART +* IRQs are managed by Interrupt Router(INT), IR Service Request Control Registers(SRC). + +Toolchains +========== + +Currently, only the Infineon’s AURIX™ GCC toolchain is tested. + +Configurations +============== + +Common Configuration Notes +-------------------------- + +1. Each TRIBOARD_TC4X9_COM configuration is maintained in a sub-directory + and can be selected as follow:: + + tools/configure.sh triboard_tc4x9_com: + + Where ```` is one of the configuration sub-directories described in + the following paragraph. + + NuttX Shell:: + + tools/configure.sh triboard_tc4x9_com:nsh + +2. These configurations use the mconf-based configuration tool. To + change a configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute ``make menuconfig`` in nuttx/ in order to start the + reconfiguration process. + +3. By default, all configurations assume the Linux. This is easily + reconfigured:: + + CONFIG_HOST_LINUX=y + +Configuration Sub-Directories +----------------------------- + +ostest +------ + +The "standard" NuttX examples/ostest configuration. diff --git a/Documentation/platforms/tricore/tc4d9/index.rst b/Documentation/platforms/tricore/tc4d9/index.rst new file mode 100644 index 00000000000..a5a70d757b3 --- /dev/null +++ b/Documentation/platforms/tricore/tc4d9/index.rst @@ -0,0 +1,23 @@ +============= +TriCore/TC4DA +============= + +**TriCore/TC4DA** An TriCore flat address port was ported in NuttX-12.0. It +consists of the following features: + +- Runs in Supervisor Mode. +- IRQs are managed by Interrupt Router (INT), IR Service Request Control Registers (SRC). +- Used System timer (STM) for systick. + +This kernel with ostest have been tested with + +- Infineon's AURIX™ TC4DA Evaluation Board: TRIBOARD_TC4X9_COM + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/arch/tricore/Kconfig b/arch/tricore/Kconfig index b505b6bce24..5edbc4ce3ed 100644 --- a/arch/tricore/Kconfig +++ b/arch/tricore/Kconfig @@ -54,7 +54,7 @@ config ARCH_FAMILY default "tc1v8" if ARCH_TC1V8 config ARCH_CHIP_TC3XX - bool "infineon aurix tc3xx" + bool select ARCH_TC1V6 select ARCH_HAVE_ADDRENV select ARCH_HAVE_I2CRESET @@ -67,7 +67,7 @@ config ARCH_CHIP_TC3XX Infineon aurix tc3xx (six cores) config ARCH_CHIP_TC4XX - bool "infineon aurix tc4xx" + bool select ARCH_TC1V8 select ARCH_HAVE_ADDRENV select ARCH_HAVE_I2CRESET @@ -123,10 +123,21 @@ config HAVE_SECURITY_CORE --help-- In addition to the 6 cores, tc4xx also has one more security core. +config CPU_COREID + int "TRICORE CPU CORE ID" + default 0 + range 0 6 + if ARCH_CHIP_TC3XX source "arch/tricore/src/tc3xx/Kconfig" endif +if ARCH_CHIP_TC4XX +source "arch/tricore/src/tc4xx/Kconfig" +endif if ARCH_CHIP_TC397 source "arch/tricore/src/tc397/Kconfig" endif +if ARCH_CHIP_TC4DA +source "arch/tricore/src/tc4da/Kconfig" +endif endif # ARCH_TRICORE diff --git a/arch/tricore/include/irq.h b/arch/tricore/include/irq.h index c26ac64ba7e..90f7d15ece3 100644 --- a/arch/tricore/include/irq.h +++ b/arch/tricore/include/irq.h @@ -157,6 +157,7 @@ extern "C" /**************************************************************************** * Public Types ****************************************************************************/ + struct xcptcontext { #ifdef CONFIG_ENABLE_ALL_SIGNALS diff --git a/arch/tricore/include/tc4da/chip.h b/arch/tricore/include/tc4da/chip.h new file mode 100644 index 00000000000..f063fabbe5d --- /dev/null +++ b/arch/tricore/include/tc4da/chip.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/tricore/include/tc4da/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H +#define __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H */ diff --git a/arch/tricore/include/tc4da/irq.h b/arch/tricore/include/tc4da/irq.h new file mode 100644 index 00000000000..afa681aac9f --- /dev/null +++ b/arch/tricore/include/tc4da/irq.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/tricore/include/tc4da/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H +#define __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define TRICORE_UART_RX_IRQ 173 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H */ diff --git a/arch/tricore/src/CMakeLists.txt b/arch/tricore/src/CMakeLists.txt index 78415e4af9a..9f2686a11ce 100644 --- a/arch/tricore/src/CMakeLists.txt +++ b/arch/tricore/src/CMakeLists.txt @@ -19,6 +19,7 @@ # the License. # # ############################################################################## + add_subdirectory(${ARCH_SUBDIR}) add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) add_subdirectory(common) diff --git a/arch/tricore/src/Makefile b/arch/tricore/src/Makefile index a9f1080a7c9..e86d95bfa1f 100644 --- a/arch/tricore/src/Makefile +++ b/arch/tricore/src/Makefile @@ -22,6 +22,7 @@ include $(TOPDIR)/Make.defs include chip/Make.defs +include common/Make.defs ifeq ($(CONFIG_ARCH_CHIP_TC3XX),y) ARCH_SUBDIR = tc3xx diff --git a/arch/tricore/src/cmake/ToolchainGnuc.cmake b/arch/tricore/src/cmake/ToolchainGnuc.cmake index 9118f36e937..627d9ba6e5c 100644 --- a/arch/tricore/src/cmake/ToolchainGnuc.cmake +++ b/arch/tricore/src/cmake/ToolchainGnuc.cmake @@ -31,7 +31,7 @@ elseif(CONFIG_ARCH_CHIP_TC4XX) set(ARCH_SUBDIR tc4xx) endif() -include(chip.cmake) +include(${CMAKE_CURRENT_LIST_DIR}/chip.cmake) set(TOOLCHAIN_PREFIX tricore-elf) set(CMAKE_LIBRARY_ARCHITECTURE ${TOOLCHAIN_PREFIX}) diff --git a/arch/tricore/src/common/tricore_cache.c b/arch/tricore/src/common/tricore_cache.c index f713960d07f..d86924b024b 100644 --- a/arch/tricore/src/common/tricore_cache.c +++ b/arch/tricore/src/common/tricore_cache.c @@ -27,6 +27,7 @@ #include #include "tricore_internal.h" +#include "IfxCpu_cfg.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/tricore/src/common/tricore_internal.h b/arch/tricore/src/common/tricore_internal.h index d176b3478d8..71218d6c2fe 100644 --- a/arch/tricore/src/common/tricore_internal.h +++ b/arch/tricore/src/common/tricore_internal.h @@ -38,7 +38,7 @@ # include # include -# include +# include # include #endif diff --git a/arch/tricore/src/common/tricore_irq.c b/arch/tricore/src/common/tricore_irq.c index edd536a0dff..b90423c28a6 100644 --- a/arch/tricore/src/common/tricore_irq.c +++ b/arch/tricore/src/common/tricore_irq.c @@ -216,7 +216,12 @@ void up_affinity_irq(int irq, cpu_set_t cpuset) * so routing to the first cpu in cpuset. */ +#ifdef CONFIG_ARCH_CHIP_TC3XX IfxSrc_init(src, ffs(cpuset) - 1, irq_prio); +#else + IfxSrc_init(src, ffs(cpuset) - 1, irq_prio, IfxSrc_VmId_none); +#endif + IfxSrc_enable(src); } diff --git a/arch/tricore/src/common/tricore_main.c b/arch/tricore/src/common/tricore_main.c index 9422380efcf..ed0d1d1bcc6 100644 --- a/arch/tricore/src/common/tricore_main.c +++ b/arch/tricore/src/common/tricore_main.c @@ -29,7 +29,12 @@ #include "Ifx_Types.h" #include "IfxCpu.h" -#include "IfxScuWdt.h" + +#ifdef CONFIG_ARCH_CHIP_TC4XX +# include "IfxWtu.h" +#else +# include "IfxScuWdt.h" +#endif /**************************************************************************** * Private Functions @@ -46,7 +51,12 @@ static void core_main(void) /* Wait for CPU sync event */ IfxCpu_emitEvent(&g_sync_event); + +#if defined(CONFIG_ARCH_CHIP_TC3XX) IfxCpu_waitEvent(&g_sync_event, 1); +#else + IfxCpu_waitEvent(&g_sync_event, UINT32_MAX, 1); +#endif if (IfxCpu_getCoreIndex() == 0) { diff --git a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h new file mode 100644 index 00000000000..ed353ea3ad4 --- /dev/null +++ b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H +#define __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DEVICE_TC39XB 1 +#define IFX_PIN_PACKAGE_LFBGA292 1 + +#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) +#define IFX_CFG_SCU_PLL_FREQUENCY (300000000) +#define IFX_CFG_SCU_PLL1_FREQUENCY (320000000) +#define IFX_CFG_SCU_PLL2_FREQUENCY (200000000) + +#define IFX_CFG_CPU_CLOCK_FREQUENCY IFX_CFG_SCU_PLL_FREQUENCY + +#define ISR_PRIORITY_STM_TICK 1 +#define ISR_PRIORITY_GETH_DMA0_TX 2 +#define ISR_PRIORITY_GETH_DMA0_RX 3 + +#ifdef CONFIG_TRICORE_BL +# define IFX_CFG_SSW_ENABLE_TRICORE0 1 +# define IFX_CFG_SSW_ENABLE_TRICORE1 0 +# define IFX_CFG_SSW_ENABLE_TRICORE2 0 +# define IFX_CFG_SSW_ENABLE_TRICORE3 0 +# define IFX_CFG_SSW_ENABLE_TRICORE4 0 +# define IFX_CFG_SSW_ENABLE_TRICORE5 0 +#else +# define IFX_CFG_SSW_ENABLE_TRICORE0 1 +# define IFX_CFG_SSW_ENABLE_TRICORE1 1 +# define IFX_CFG_SSW_ENABLE_TRICORE2 1 +# define IFX_CFG_SSW_ENABLE_TRICORE3 1 +# define IFX_CFG_SSW_ENABLE_TRICORE4 1 +# define IFX_CFG_SSW_ENABLE_TRICORE5 1 +#endif + +#define IFX_CFG_SSW_ENABLE_INDIVIDUAL_C_INIT (1U) + +#endif /* __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H */ diff --git a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c new file mode 100644 index 00000000000..d52c6a9c382 --- /dev/null +++ b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "Ifx_Cfg_Ssw.h" +#include "Ifx_Ssw_Infra.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(__TASKING__) +#pragma optimize RL +#elif defined(__GNUC__) +#pragma GCC optimize ("O1") +#endif + +#if (IFX_CFG_SSW_ENABLE_LBIST == 1) +void Ifx_Ssw_Lbist(void) +{ + if (!IfxScuLbist_isDone()) + { + if(Ifx_Ssw_isColdPoweronReset()) + { + IfxScuLbist_triggerInline(&IfxScuLbist_defaultConfig); + } + } + + if (!IfxScuLbist_evaluateResult(IfxScuLbist_defaultConfig.signature)) + { + __debug(); + while(1); + } + + Ifx_Ssw_jumpBackToLink(); +} +#endif + +#if defined(__TASKING__) +#pragma endoptimize +#elif defined(__GNUC__) +#pragma GCC reset_options +#endif diff --git a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h new file mode 100644 index 00000000000..2b6c5909713 --- /dev/null +++ b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h @@ -0,0 +1,111 @@ +/**************************************************************************** + * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H +#define __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "Ifx_Cfg.h" +#include "Ifx_Ssw.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef IFX_CFG_SSW_ENABLE_LBIST +#define IFX_CFG_SSW_ENABLE_LBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_MONBIST +#define IFX_CFG_SSW_ENABLE_MONBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT +#define IFX_CFG_SSW_ENABLE_PLL_INIT (1U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_MBIST +#define IFX_CFG_SSW_ENABLE_MBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_SMU +#define IFX_CFG_SSW_ENABLE_SMU (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_EMEM_INIT +#define IFX_CFG_SSW_ENABLE_EMEM_INIT (0U) +#endif + +#ifndef IFX_SCU_FLASHWAITSTATECHECK +#define IFX_SCU_FLASHWAITSTATECHECK (0U) +#endif + +#if IFX_CFG_SSW_ENABLE_LBIST == 1U +#include "IfxScuLbist.h" + +extern void Ifx_Ssw_Lbist(void); +#define IFX_CFG_SSW_CALLOUT_LBIST() \ +{ \ + Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Lbist); \ +} +#endif + +#if IFX_CFG_SSW_ENABLE_MONBIST == 1U +#include "IfxSmuStdby.h" + +extern void Ifx_Ssw_Monbist(void); +#define IFX_CFG_SSW_CALLOUT_MONBIST() \ +{ \ + Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Monbist); \ +} +#endif + +#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U +#include "IfxScuCcu.h" + +#define IFX_CFG_SSW_CALLOUT_PLL_INIT() \ +{ \ + if (IfxScuCcu_init(&IfxScuCcu_defaultClockConfig) == 1) \ + { \ + __debug(); \ + } \ +} + +#endif + +#if IFX_CFG_SSW_ENABLE_MBIST == 1U +#include "IfxMtu.h" + +#define IFX_CFG_SSW_CALLOUT_MBIST() \ +{ \ + IFX_EXTERN const IfxMtu_MbistConfig *const mbistGangConfig[]; \ + if (IfxMtu_runMbistAll(mbistGangConfig) == 1U) \ + { \ + __debug(); \ + } \ +} + +#endif +#endif /* __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H */ diff --git a/arch/tricore/src/illd/tc3xx/patches/change_illd.patch b/arch/tricore/src/illd/tc3xx/patches/change_illd.patch new file mode 100644 index 00000000000..ee7ec37bf39 --- /dev/null +++ b/arch/tricore/src/illd/tc3xx/patches/change_illd.patch @@ -0,0 +1,60 @@ +diff --git a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c +index f893b3e7e4b..e86811079d2 100644 +--- a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c ++++ b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c +@@ -45,6 +45,12 @@ + /*-------------------------Infrastructure Functions---------------------------*/ + /******************************************************************************/ + ++IFX_SSW_WEAK void hardware_init_hook(void) ++{} ++ ++IFX_SSW_WEAK void software_init_hook(void) ++{} ++ + unsigned short Ifx_Ssw_getCpuWatchdogPassword(Ifx_SCU_WDTCPU *watchdog) + { + return Ifx_Ssw_getCpuWatchdogPasswordInline(watchdog); +@@ -200,6 +206,7 @@ void Ifx_Ssw_doCppInit(void) + { + Ifx_Ssw_C_InitInline(); + ++#ifndef __NuttX__ + #ifdef __TASKING__ + extern void _main(void); /* cpp initialization */ + _main(); +@@ -219,10 +226,12 @@ void Ifx_Ssw_doCppInit(void) + extern void _main(void); /* cpp initialization */ + _main(); + #endif ++#endif /* __NuttX__ */ + } + + void Ifx_Ssw_doCppExit(int status) + { ++#ifndef __NuttX__ + #ifdef __TASKING__ + extern void _doexit(void); /* cpp deinitialization */ + _doexit(); +@@ -239,7 +248,7 @@ void Ifx_Ssw_doCppExit(int status) + extern void exit(int); /* cpp deinitialization */ + exit(0); + #endif +- ++#endif /* __NuttX__ */ + } + + +diff --git a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c +index 0c6b0771bf0..4b68b8b4121 100644 +--- a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c ++++ b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c +@@ -344,7 +344,7 @@ void IfxCpu_Trap_vectorTable0(void) + /* Map Instruction Error trap to its handler for CPU0 */ + IfxCpu_Tsr_CallTSR(IfxCpu_Trap_instructionError); + /* Map Context Management Error trap to its handler for CPU0 */ +- IfxCpu_Tsr_CallCSATSR(IfxCpu_Trap_contextManagementError); ++ IfxCpu_Tsr_CallTSR(IfxCpu_Trap_contextManagementError); + /* Map Bus Error trap to its handler for CPU0 */ + IfxCpu_Tsr_CallTSR(IfxCpu_Trap_busError); + /* Map Assertion trap to its handler for CPU0 */ diff --git a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h new file mode 100644 index 00000000000..8ba0031e141 --- /dev/null +++ b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H +#define __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define DEVICE_TC4DX 1 + +#define IFX_CFG_CLOCK_XTAL_FREQUENCY (25000000) +#define IFX_CFG_CLOCK_SYSPLL_FREQUENCY (500000000) +#define IFX_CFG_CLOCK_PPUPLL_FREQUENCY (450000000) +#define IFX_CFG_CLOCK_PERPLL1_FREQUENCY (160000000) +#define IFX_CFG_CLOCK_PERPLL2_FREQUENCY (200000000) +#define IFX_CFG_CLOCK_PERPLL3_FREQUENCY (200000000) + +#define IFX_CFG_CPU_CLOCK_FREQUENCY IFX_CFG_CLOCK_SYSPLL_FREQUENCY + +#define IFX_PROT_ENABLED 0 +#define IFX_CFG_VIRTUALIZATION_DISABLED 1 +#define IFX_CFG_STM_MORPHING_ENABLE 1 +#define IFX_CLOCK_BYPASS_FOSC_F 0 + +#define IFX_STM_RESOULTION IFX_CFG_CLOCK_SYSPLL_FREQUENCY + +#define IFX_CFG_INTERRUPT_INTERVAL (0.003) + +#define IFX_CFG_CPU0_PRIO 10 +#define IFX_CFG_CPU1_PRIO 10 +#define IFX_CFG_CPU2_PRIO 10 +#define IFX_CFG_CPU3_PRIO 10 +#define IFX_CFG_CPU4_PRIO 10 +#define IFX_CFG_CPU5_PRIO 10 + +#define ISR_PRIORITY_STM0_TICK 1 +#define ISR_PRIORITY_GETH0_DMA0_TX 2 +#define ISR_PRIORITY_GETH0_DMA0_RX 3 + +#ifdef CONFIG_TRICORE_BL +# define IFX_CFG_SSW_ENABLE_TRICORE0 1 +# define IFX_CFG_SSW_ENABLE_TRICORE1 0 +# define IFX_CFG_SSW_ENABLE_TRICORE2 0 +# define IFX_CFG_SSW_ENABLE_TRICORE3 0 +# define IFX_CFG_SSW_ENABLE_TRICORE4 0 +# define IFX_CFG_SSW_ENABLE_TRICORE5 0 +#else +# define IFX_CFG_SSW_ENABLE_TRICORE0 1 +# define IFX_CFG_SSW_ENABLE_TRICORE1 1 +# define IFX_CFG_SSW_ENABLE_TRICORE2 1 +# define IFX_CFG_SSW_ENABLE_TRICORE3 1 +# define IFX_CFG_SSW_ENABLE_TRICORE4 1 +# define IFX_CFG_SSW_ENABLE_TRICORE5 1 +#endif + +#endif /* __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H */ diff --git a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c new file mode 100644 index 00000000000..42f8cff1384 --- /dev/null +++ b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c @@ -0,0 +1,211 @@ +/**************************************************************************** + * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "Ifx_Cfg_Ssw.h" +#include "Ifx_Ssw_Infra.h" + +#if (IFX_CFG_SSW_ENABLE_LBIST == 1) +#include "IfxApProt.h" +#include "IfxTriLbist.h" +#endif + +#include "IfxVmt.h" +#include "IfxPmsPm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(__TASKING__) +#pragma optimize RL +#elif defined(__GNUC__) +#pragma GCC optimize ("O1") +#endif + +#if (IFX_CFG_SSW_ENABLE_LBIST == 1) +void Ifx_Ssw_Lbist(void) +{ + uint16 result; + + IfxApProt_setState((Ifx_PROT_PROT *)&TRI_PROTSE, IfxApProt_State_config); + TRI_ACCEN_WRA.U = 0xFFFFFFFFU; + TRI_ACCEN_WRB.U = 0xFFFFFFFFU; + IfxApProt_setState((Ifx_PROT_PROT *)&TRI_PROTSE, IfxApProt_State_run); + + result = IfxTriLbist_evaluateResult(&IfxTriLbist_keyOnDefaultConfig.signature[0]); + + if (result) + { + if (IfxTriLbist_getFailCount() >= 2) + { + Ifx_Ssw_debug(); + } + else + { + IfxTriLbist_incrementFailCount(); + } + + IfxTriLbist_resetLbist(); + IfxTriLbist_triggerInline(&IfxTriLbist_keyOnDefaultConfig); + } +} +#endif + +#if (IFX_CFG_SSW_ENABLE_MONBIST == 1) +void Ifx_Ssw_Monbist(void) +{ +} +#endif + +#if (IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM == 1) +void Ifx_Ssw_MbistDsprsDmaRam(void) +{ +} +#endif + +#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U +#include "IfxClock.h" + +void Ifx_Ssw_PowerOnCrystalOsc(void) +{ + Ifx_CLOCK_OSCCON scuOsccon; + unsigned int initError = 0U; + unsigned int timeoutCycleCount = IFX_CFG_SSW_CCUCON_LCK_BIT_TIMEOUT_COUNT; + scuOsccon.U = CLOCK_OSCCON.U; + +#if (IFX_CFG_SSW_CLOCK_EXT_CLOCK == 1) + scuOsccon.B.MODE = 2U; +#else + scuOsccon.B.MODE = 0U; +#endif + + while (CLOCK_CCUSTAT.B.LCK != 0U) + { + IFX_CFG_SSW_LOOP_TIMEOUT_CHECK(timeoutCycleCount, initError); + } + + CLOCK_OSCCON.U = scuOsccon.U; + + if (initError) + { + Ifx_Ssw_debug(); + } +} + +void Ifx_Ssw_PllInit(void) +{ + if (IfxClock_init(&IfxClock_defaultClockConfig) != 0U) + { + __debug(); + } +} +#endif + +#if IFX_CFG_SSW_ENABLE_MBIST == 1U +void Ifx_Ssw_Mbist(void) +{ + IfxVmt_clearSram(IfxVmt_MbistSel_lmu0); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu1); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu2); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu3); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu4); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu5); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu6); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu7); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu8); + IfxVmt_clearSram(IfxVmt_MbistSel_lmu9); + + /* clear CAN Message RAM */ + + IfxVmt_clearSram(IfxVmt_MbistSel_mcan0); + IfxVmt_clearSram(IfxVmt_MbistSel_mcan1); + IfxVmt_clearSram(IfxVmt_MbistSel_mcan2); + IfxVmt_clearSram(IfxVmt_MbistSel_mcan3); + IfxVmt_clearSram(IfxVmt_MbistSel_mcan4); +} +#endif + +#if IFX_CFG_SSW_ENABLE_SMU == 1U +void Ifx_Ssw_Smu(void) +{ +} +#endif + +#if (IFX_CFG_SSW_ENABLE_KEYOFF_LBIST == 1) +void Ifx_Ssw_Keyoff_Lbist(void) +{ +} +#endif + +#if IFX_CFG_SSW_ENABLE_KEYOFF_MBIST == 1U +void Ifx_Ssw_Keyoff_Mbist(void) +{ +} +#endif + +#if (IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM == 1) +void Ifx_Ssw_Keyoff_MbistDsprsDmaRam(void) +{ +} +#endif + +#if IFX_CFG_SSW_ENABLE_AP_INIT == 1U +void weak_function Ifx_Ssw_AP_Init(void) +{ +} +#endif + +void Ifx_Ssw_MultiCore_Sync_Cpu0(void) +{ +} + +void Ifx_Ssw_MultiCore_Sync_Cpu1(void) +{ +} + +void Ifx_Ssw_MultiCore_Sync_Cpu2(void) +{ +} + +void Ifx_Ssw_MultiCore_Sync_Cpu3(void) +{ +} + +void Ifx_Ssw_MultiCore_Sync_Cpu4(void) +{ +} + +void Ifx_Ssw_MultiCore_Sync_Cpu5(void) +{ +} + +#if defined(__TASKING__) +#pragma endoptimize +#elif defined(__GNUC__) +#pragma GCC reset_options +#endif diff --git a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h new file mode 100644 index 00000000000..e26e3f85b88 --- /dev/null +++ b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H +#define __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "Ifx_Cfg.h" +#include "Ifx_Ssw.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef IFX_CFG_SSW_ENABLE_LBIST +#define IFX_CFG_SSW_ENABLE_LBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_MONBIST +#define IFX_CFG_SSW_ENABLE_MONBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM +#define IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_XTALSRC_CHECK +#define IFX_CFG_SSW_ENABLE_XTALSRC_CHECK (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT +#define IFX_CFG_SSW_ENABLE_PLL_INIT (1U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_MBIST +#define IFX_CFG_SSW_ENABLE_MBIST (1U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_SMU +#define IFX_CFG_SSW_ENABLE_SMU (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_AP_INIT +#define IFX_CFG_SSW_ENABLE_AP_INIT (1U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_LBIST +#define IFX_CFG_SSW_ENABLE_KEYOFF_LBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_MBIST +#define IFX_CFG_SSW_ENABLE_KEYOFF_MBIST (0U) +#endif + +#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM +#define IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM (0U) +#endif + +#endif /* __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H */ diff --git a/arch/tricore/src/illd/tc4xx/patches/change_illd.patch b/arch/tricore/src/illd/tc4xx/patches/change_illd.patch new file mode 100644 index 00000000000..946e38af313 --- /dev/null +++ b/arch/tricore/src/illd/tc4xx/patches/change_illd.patch @@ -0,0 +1,33 @@ +diff --git a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c +index cf3c6c74010..f386599481e 100644 +--- a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c ++++ b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c +@@ -429,6 +429,7 @@ void Ifx_Ssw_doCppInit(void) + { + Ifx_Ssw_C_InitInline(); + ++#ifndef __NuttX__ + #ifdef __TASKING__ + extern void _main(void); /* cpp initialization */ + _main(); +@@ -451,10 +452,12 @@ void Ifx_Ssw_doCppInit(void) + #elif defined(__DCC__) + /* Cpp Init part of the init_main called in C Init Inline */ + #endif ++#endif + } + + void Ifx_Ssw_doCppExit(int status) + { ++#ifndef __NuttX__ + #ifdef __TASKING__ + extern void _doexit(void); /* cpp deinitialization */ + _doexit(); +@@ -474,6 +477,7 @@ void Ifx_Ssw_doCppExit(int status) + extern void exit(int); /* cpp deinitialization */ + exit(0); + #endif ++#endif + } + + diff --git a/arch/tricore/src/tc397/CMakeLists.txt b/arch/tricore/src/tc397/CMakeLists.txt index 4f2be510058..90bed2ddc60 100644 --- a/arch/tricore/src/tc397/CMakeLists.txt +++ b/arch/tricore/src/tc397/CMakeLists.txt @@ -19,19 +19,3 @@ # the License. # # ############################################################################## - -if(CONFIG_ARCH_CHIP_TC397) - if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/tc397) - FetchContent_Declare( - tc397 - URL https://github.com/wangchdo/tc397_sdk/archive/refs/heads/master.tar.gz - SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/tc397 BINARY_DIR - ${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/${CONFIG_ARCH_CHIP}/tc397) - FetchContent_GetProperties(tc397) - if(NOT tc397_POPULATED) - FetchContent_Populate(tc397) - endif() - endif() - - add_subdirectory(tc397) -endif() diff --git a/arch/tricore/src/tc397/Make.defs b/arch/tricore/src/tc397/Make.defs index 29f19305040..79e00f2bc27 100644 --- a/arch/tricore/src/tc397/Make.defs +++ b/arch/tricore/src/tc397/Make.defs @@ -19,31 +19,3 @@ # under the License. # ############################################################################ -ifeq ($(CONFIG_ARCH_CHIP_TC397),y) - -include tc397/tc397/Make.defs -endif - -TC397_UNPACK = tc397 -TC397_COMMIT = master -TC397_URL = https://github.com/wangchdo/tc397_sdk/archive/refs/heads -TC397_TARBALL = tc397/$(TC397_UNPACK).tar.gz -TC397_DIR = tc397_sdk-master - -$(TC397_TARBALL): - $(call DOWNLOAD,$(TC397_URL),$(TC397_COMMIT).tar.gz,$(TC397_TARBALL)) - -tc397/.tc397_unpack: $(TC397_TARBALL) - $(Q) echo "Unpacking: TC397" - $(Q) tar xzf $(TC397_TARBALL) -C tc397 - $(Q) mv tc397/$(TC397_DIR) tc397/$(TC397_UNPACK) - $(Q) touch tc397/.tc397_unpack - - -ifeq ($(wildcard tc397/$(TC397_UNPACK)/.git),) -context:: tc397/.tc397_unpack - -distclean:: - $(call DELFILE, tc397/.tc397_unpack) - $(call DELFILE, $(TC397_TARBALL)) - $(call DELDIR, tc397/$(TC397_UNPACK)) -endif diff --git a/arch/tricore/src/tc3xx/CMakeLists.txt b/arch/tricore/src/tc3xx/CMakeLists.txt index 6860f9f0861..ebb9ee5edb0 100644 --- a/arch/tricore/src/tc3xx/CMakeLists.txt +++ b/arch/tricore/src/tc3xx/CMakeLists.txt @@ -31,3 +31,131 @@ if(CONFIG_TRICORE_TOOLCHAIN_TASKING) nuttx PRIVATE --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip) endif() + +set(ILLD_UNPACK "${CMAKE_CURRENT_SOURCE_DIR}/../illd/tc3xx") +set(ILLD_TARBALL "${ILLD_UNPACK}/illd.tar.gz") +set(ILLD_UNPACK_NAME "illd_release_tc3x-main") +set(ILLD_SRC "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}/src/BaseSw") +set(ILLD_URL + "https://github.com/Infineon/illd_release_tc3x/archive/refs/heads/main.tar.gz" +) + +set(CONFIG_DIR "${ILLD_UNPACK}/Configurations") +set(ILLD_DIR "${ILLD_UNPACK}/Libraries/src") +set(PATCHES_DIR "${ILLD_UNPACK}/patches") + +if(NOT EXISTS "${ILLD_DIR}/Libraries") + file(MAKE_DIRECTORY "${ILLD_UNPACK}") + file(DOWNLOAD "${ILLD_URL}" "${ILLD_TARBALL}" SHOW_PROGRESS) + + message(STATUS "Unpacking: ILLD for tc3xx") + execute_process( + COMMAND ${CMAKE_COMMAND} -E tar xzf "${ILLD_TARBALL}" + WORKING_DIRECTORY "${ILLD_UNPACK}" + RESULT_VARIABLE tar_result) + if(NOT tar_result EQUAL 0) + message(FATAL_ERROR "Failed to unpack ${ILLD_TARBALL}") + endif() + + file(MAKE_DIRECTORY "${ILLD_DIR}/Libraries") + + execute_process(COMMAND ${CMAKE_COMMAND} -E copy_directory "${ILLD_SRC}/" + "${ILLD_DIR}/Libraries/" RESULT_VARIABLE copy_result) + if(NOT copy_result EQUAL 0) + message( + FATAL_ERROR + "Failed to stage ILLD from ${ILLD_SRC} to ${ILLD_DIR}/Libraries") + endif() + + file(REMOVE_RECURSE "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}") +endif() + +file(GLOB PATCH_FILES "${PATCHES_DIR}/*.patch") + +foreach(PATCH ${PATCH_FILES}) + execute_process( + COMMAND git apply --reverse --check ${PATCH} + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo + # root + RESULT_VARIABLE PATCH_NEEDED + OUTPUT_QUIET ERROR_QUIET) + + if(PATCH_NEEDED EQUAL 0) + message(STATUS "Patch ${PATCH} already applied, skipping.") + else() + execute_process( + COMMAND git apply --whitespace=nowarn ${PATCH} + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo + # root + RESULT_VARIABLE APPLY_RESULT) + if(NOT APPLY_RESULT EQUAL 0) + message(FATAL_ERROR "Failed to apply patch ${PATCH}!") + else() + message(STATUS "Successfully applied patch ${PATCH}.") + endif() + endif() +endforeach() + +set(SDK_INCDIR + "${CONFIG_DIR}" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Std" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Src/Std" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Timer" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x" + "${ILLD_DIR}/Libraries/Infra/Platform" + "${ILLD_DIR}/Libraries/Infra/Platform/Tricore" + "${ILLD_DIR}/Libraries/Infra/Sfr/TC39xB" + "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore" + "${ILLD_DIR}/Libraries/Service/CpuGeneric") + +target_include_directories(arch PRIVATE ${SDK_INCDIR}) +target_include_directories(nuttx PRIVATE ${SDK_INCDIR}) + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_INCLUDE_DIRECTORIES ${SDK_INCDIR}) + +set(SDK_CSRCS + "${CONFIG_DIR}/Ifx_Cfg_Ssw.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x/IfxAsclin_PinMap_TC39xB_LFBGA292.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsEvr.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsPm.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Port/Std/IfxPort.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuCcu.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuEru.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuLbist.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuRcu.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuWdt.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Src/Std/IfxSrc.c" + "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Std/IfxStm.c" + "${ILLD_DIR}/Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c" + "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c" + "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Tc0.c") + +target_sources(nuttx PRIVATE ${SDK_CSRCS}) + +if(NOT CONFIG_TRICORE_TOOLCHAIN_TASKING) + target_compile_options(nuttx PRIVATE -Wno-undef -Wno-strict-prototypes + -Wno-shadow) + target_compile_options(nuttx PRIVATE -fstrict-volatile-bitfields) + target_compile_options(nuttx PRIVATE -Wno-unused-parameter + -Wno-unused-but-set-parameter) + target_compile_options(nuttx PRIVATE -Wno-implicit-fallthrough) +else() + nuttx_add_extra_library( + "${CMAKE_CURRENT_LIST_DIR}/illd/prebuilts/tc162/cinit.o") +endif() diff --git a/arch/tricore/src/tc3xx/Make.defs b/arch/tricore/src/tc3xx/Make.defs index 79365c51f13..124d8cf6447 100644 --- a/arch/tricore/src/tc3xx/Make.defs +++ b/arch/tricore/src/tc3xx/Make.defs @@ -47,4 +47,99 @@ EXTRA_LIBS += libos$(LIBEXT) endif -LIBPATHS += $(CURDIR) +ILLD_UNPACK = illd/tc3xx +ILLD_TARBALL = $(ILLD_UNPACK)/illd.tar.gz +ILLD_UNPACK_NAME = illd_release_tc3x-main +ILLD_SRC = $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)/src/BaseSw +ILLD_URL = https://github.com/Infineon/illd_release_tc3x/archive/refs/heads + +$(ILLD_TARBALL): + $(call DOWNLOAD,$(ILLD_URL),main.tar.gz,$(ILLD_TARBALL)) + +$(ILLD_UNPACK)/.illd_unpack: $(ILLD_TARBALL) + $(Q) echo "Unpacking: ILLD" + $(Q) tar xzf $(ILLD_TARBALL) -C $(ILLD_UNPACK) + $(Q) mkdir -p $(ILLD_UNPACK)/Libraries/src/Libraries + $(Q) mv $(ILLD_SRC)/* $(ILLD_UNPACK)/Libraries/src/Libraries/ + $(Q) rm -rf $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME) + $(Q) touch $(ILLD_UNPACK)/.illd_unpack + +ifeq ($(wildcard $(ILLD_UNPACK)/.git),) +context:: $(ILLD_UNPACK)/.illd_unpack + +distclean:: + $(call DELFILE, $(ILLD_UNPACK)/.illd_unpack) + $(call DELFILE, $(ILLD_TARBALL)) + $(call DELDIR, $(ILLD_UNPACK)/Libraries/src/Libraries) +endif + +CONFIG_DIR = $(ILLD_UNPACK)/Configurations +ILLD_DIR = $(ILLD_UNPACK)/Libraries/src +PATCHES_DIR = $(ILLD_UNPACK)/patches +PATCH_FILES = $(wildcard $(CURDIR)/$(PATCHES_DIR)/*.patch) + +apply_change_patches: + @if [ -n "$(PATCH_FILES)" ]; then \ + for p in $(PATCH_FILES); do \ + if git -C "$(CURDIR)" apply --reverse --check "$$p" >/dev/null 2>&1; then \ + echo "-- Patch $$p already applied, skipping."; \ + else \ + if git -C "$(CURDIR)" apply --whitespace=nowarn "$$p" >/dev/null 2>&1; then \ + echo "-- Successfully applied patch $$p."; \ + else \ + echo "-- Failed to apply patch $$p!"; \ + exit 1; \ + fi; \ + fi; \ + done; \ + fi + +context:: apply_change_patches + +SDK_INCDIR += ${CONFIG_DIR} +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Src/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Timer +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform/Tricore +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Sfr/TC39xB +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore +SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric + +SDK_CSRCS += ${CONFIG_DIR}/Ifx_Cfg_Ssw.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x/IfxAsclin_PinMap_TC39xB_LFBGA292.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsEvr.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsPm.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Port/Std/IfxPort.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuCcu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuEru.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuLbist.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuRcu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuWdt.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Src/Std/IfxSrc.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Std/IfxStm.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Tc0.c + +CFLAGS += $(addprefix ${INCDIR_PREFIX},$(SDK_INCDIR)) + +VPATH += $(dir $(SDK_CSRCS)) + +HEAD_CSRC += $(notdir $(SDK_CSRCS)) + +LIBPATHS += $(CURDIR) diff --git a/arch/tricore/src/tc3xx/Toolchain.defs b/arch/tricore/src/tc3xx/Toolchain.defs index bcfc9cadcad..ee16fc33bdf 100644 --- a/arch/tricore/src/tc3xx/Toolchain.defs +++ b/arch/tricore/src/tc3xx/Toolchain.defs @@ -29,9 +29,9 @@ ifeq ($(CONFIG_ARCH_CHIP_TC397),y) ARCHCPUFLAGS += -mtc162 endif - ARCHINCLUDES += ${INCDIR_PREFIX}$(CHIP_DIR)/tc397/Libraries/iLLD/TC39B/Tricore/Cpu/Std - ARCHINCLUDES += ${INCDIR_PREFIX}$(CHIP_DIR)/tc397/Libraries/Infra/Platform - ARCHINCLUDES += ${INCDIR_PREFIX}$(CHIP_DIR)/tc397/Configurations + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Std + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Platform + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Configurations endif include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs diff --git a/arch/tricore/src/tc4da/CMakeLists.txt b/arch/tricore/src/tc4da/CMakeLists.txt new file mode 100644 index 00000000000..869adb877b1 --- /dev/null +++ b/arch/tricore/src/tc4da/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# arch/tricore/src/tc4da/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## diff --git a/arch/tricore/src/tc4da/Kconfig b/arch/tricore/src/tc4da/Kconfig new file mode 100644 index 00000000000..18c7905aed7 --- /dev/null +++ b/arch/tricore/src/tc4da/Kconfig @@ -0,0 +1,5 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + diff --git a/arch/tricore/src/tc4da/Make.defs b/arch/tricore/src/tc4da/Make.defs new file mode 100644 index 00000000000..fd041dcf882 --- /dev/null +++ b/arch/tricore/src/tc4da/Make.defs @@ -0,0 +1,21 @@ +############################################################################ +# arch/tricore/src/tc4da/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ diff --git a/arch/tricore/src/tc4da/chip.h b/arch/tricore/src/tc4da/chip.h new file mode 100644 index 00000000000..89f26c2d667 --- /dev/null +++ b/arch/tricore/src/tc4da/chip.h @@ -0,0 +1,33 @@ +/**************************************************************************** + * arch/tricore/src/tc4da/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC4DA_CHIP_H +#define __ARCH_TRICORE_SRC_TC4DA_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define UART_PIN_RX IfxAsclin0_RXA_F_P14_1_IN /* UART receive port pin */ +#define UART_PIN_TX IfxAsclin0_TX_F_P14_0_OUT /* UART transmit port pin */ + +#endif /* __ARCH_TRICORE_SRC_TC4DA_CHIP_H */ diff --git a/arch/tricore/src/tc4xx/CMakeLists.txt b/arch/tricore/src/tc4xx/CMakeLists.txt new file mode 100644 index 00000000000..0735c9b48dc --- /dev/null +++ b/arch/tricore/src/tc4xx/CMakeLists.txt @@ -0,0 +1,192 @@ +# ############################################################################## +# arch/tricore/src/tc4xx/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS tc4xx_timerisr.c tc4xx_serial.c) + +target_sources(arch PRIVATE ${SRCS}) + +if(CONFIG_TRICORE_TOOLCHAIN_TASKING) + nuttx_add_kernel_library(c_fpu) + target_sources(c_fpu PRIVATE tc4xx_libc.c) + target_link_options( + nuttx PRIVATE + --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip) +endif() + +set(ILLD_UNPACK "${CMAKE_CURRENT_SOURCE_DIR}/../illd/tc4xx") +set(ILLD_TARBALL "${ILLD_UNPACK}/illd.tar.gz") +set(ILLD_UNPACK_NAME "illd_release_tc4x-main") +set(ILLD_SRC "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}/src/Libraries") +set(ILLD_URL + "https://github.com/Infineon/illd_release_tc4x/archive/refs/heads/main.tar.gz" +) + +set(CONFIG_DIR "${ILLD_UNPACK}/Configurations") +set(ILLD_DIR "${ILLD_UNPACK}/Libraries/src") +set(PATCHES_DIR "${ILLD_UNPACK}/patches") + +if(NOT EXISTS "${ILLD_DIR}/Libraries") + file(MAKE_DIRECTORY "${ILLD_UNPACK}") + file(DOWNLOAD "${ILLD_URL}" "${ILLD_TARBALL}") + + message(STATUS "Unpacking: ILLD for tc4xx") + execute_process( + COMMAND ${CMAKE_COMMAND} -E tar xzf "${ILLD_TARBALL}" + WORKING_DIRECTORY "${ILLD_UNPACK}" + RESULT_VARIABLE tar_result) + if(NOT tar_result EQUAL 0) + message(FATAL_ERROR "Failed to unpack ${ILLD_TARBALL}") + endif() + + file(MAKE_DIRECTORY "${ILLD_DIR}/Libraries") + + execute_process(COMMAND ${CMAKE_COMMAND} -E copy_directory "${ILLD_SRC}/" + "${ILLD_DIR}/Libraries/" RESULT_VARIABLE copy_result) + if(NOT copy_result EQUAL 0) + message( + FATAL_ERROR + "Failed to stage ILLD from ${ILLD_SRC} to ${ILLD_DIR}/Libraries") + endif() + + file(REMOVE_RECURSE "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}") +endif() + +file(GLOB PATCH_FILES "${PATCHES_DIR}/*.patch") + +foreach(PATCH ${PATCH_FILES}) + execute_process( + COMMAND git apply --reverse --check ${PATCH} + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo + # root + RESULT_VARIABLE PATCH_NEEDED + OUTPUT_QUIET ERROR_QUIET) + + if(PATCH_NEEDED EQUAL 0) + message(STATUS "Patch ${PATCH} already applied, skipping.") + else() + execute_process( + COMMAND git apply --whitespace=nowarn ${PATCH} + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo + # root + RESULT_VARIABLE APPLY_RESULT) + if(NOT APPLY_RESULT EQUAL 0) + message(FATAL_ERROR "Failed to apply patch ${PATCH}!") + else() + message(STATUS "Successfully applied patch ${PATCH}.") + endif() + endif() +endforeach() + +set(SDK_INCDIR + "${CONFIG_DIR}" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/ArcEV" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Asc" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Lin" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Atom" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Tom" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Crc" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Scr" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_PinMap" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_PinMap/TC4Dx" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Can/Can" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Can/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Flash/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/I2c/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Pms/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smu/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Src/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Timer" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Vmt/Std" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Wtu/Std" + "${ILLD_DIR}/Libraries/Infra/Platform" + "${ILLD_DIR}/Libraries/Infra/Sfr/TC4Dx" + "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore" + "${ILLD_DIR}/Libraries/Service/CpuGeneric" + "${ILLD_DIR}/Libraries/Infra/Platform/Compilers") + +target_include_directories(arch PRIVATE ${SDK_INCDIR}) +target_include_directories(nuttx PRIVATE ${SDK_INCDIR}) + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_INCLUDE_DIRECTORIES ${SDK_INCDIR}) + +set(SDK_CSRCS + "${CONFIG_DIR}/Ifx_Cfg_Ssw.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxAp_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxDma_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx/IfxAsclin_PinMap_TC4Dx_BGA436_COM.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Std/IfxAsclin.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApApu.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApProt.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std/IfxClock.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Dma/IfxDma_Dma.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Std/IfxDma.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std/IfxPort.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmmRst.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smu/Std/IfxSmu.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Vmt/Std/IfxVmt.c" + "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Wtu/Std/IfxWtu.c" + "${ILLD_DIR}/Libraries/Infra/Platform/Compilers/CompilerTasking.c" + "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c" + "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Tc0.c") + +target_sources(nuttx PRIVATE ${SDK_CSRCS}) + +if(NOT CONFIG_TRICORE_TOOLCHAIN_TASKING) + target_compile_options(nuttx PRIVATE -Wno-undef -Wno-strict-prototypes + -Wno-shadow) + target_compile_options(nuttx PRIVATE -fstrict-volatile-bitfields) + target_compile_options(nuttx PRIVATE -Wno-unused-parameter + -Wno-unused-but-set-parameter) + target_compile_options(nuttx PRIVATE -Wno-implicit-fallthrough) +endif() + +target_compile_definitions( + arch PRIVATE -DSRC_GPSR00=SRC_GPSR0SR0 -DSRC_CPU_CPU0_SB=SRC_CPU0SB + -DMODULE_STM0=MODULE_CPU0 -DSRC_STM0SR0=SRC_STMCPU0_SR2) diff --git a/arch/tricore/src/tc4xx/Kconfig b/arch/tricore/src/tc4xx/Kconfig new file mode 100644 index 00000000000..dfe17717c53 --- /dev/null +++ b/arch/tricore/src/tc4xx/Kconfig @@ -0,0 +1,18 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "TC4XX Configuration Options" + +menu "TC4XX Peripheral Support" + +# These are the peripheral selections proper + +config TC4XX_UART0 + bool "TC4XX UART0" + default y + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +endmenu diff --git a/arch/tricore/src/tc4xx/Make.defs b/arch/tricore/src/tc4xx/Make.defs new file mode 100644 index 00000000000..7df4ec01e92 --- /dev/null +++ b/arch/tricore/src/tc4xx/Make.defs @@ -0,0 +1,180 @@ +############################################################################ +# arch/tricore/src/tc4xx/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +CHIP_CSRCS += tc4xx_timerisr.c +CHIP_CSRCS += tc4xx_serial.c + +VPATH += tc4xx + +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) + +tc4xx_libc$(OBJEXT): tc4xx_libc.c + $(call COMPILE, $<, $@) + +libc_fpu$(LIBEXT): tc4xx_libc$(OBJEXT) + $(call ARCHIVE, $@, $<) + +EXTRA_LIBS += libc_fpu$(LIBEXT) + +else + +tc4xx_dummy$(OBJEXT): tc4xx_dummy.c + $(call COMPILE, $<, $@) + +libos$(LIBEXT): tc4xx_dummy$(OBJEXT) + $(call ARCHIVE, $@, $<) + +EXTRA_LIBS += libos$(LIBEXT) + +endif + +ILLD_UNPACK = illd/tc4xx +ILLD_TARBALL = $(ILLD_UNPACK)/illd.tar.gz +ILLD_UNPACK_NAME = illd_release_tc4x-main +ILLD_SRC = $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)/src/Libraries +ILLD_URL = https://github.com/Infineon/illd_release_tc4x/archive/refs/heads + +$(ILLD_TARBALL): + $(call DOWNLOAD,$(ILLD_URL),main.tar.gz,$(ILLD_TARBALL)) + +$(ILLD_UNPACK)/.illd_unpack: $(ILLD_TARBALL) + $(Q) echo "Unpacking: ILLD" + $(Q) tar xzf $(ILLD_TARBALL) -C $(ILLD_UNPACK) + $(Q) mkdir -p $(ILLD_UNPACK)/Libraries/src/Libraries + $(Q) mv $(ILLD_SRC)/* $(ILLD_UNPACK)/Libraries/src/Libraries/ + $(Q) rm -rf $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME) + $(Q) touch $(ILLD_UNPACK)/.illd_unpack + +ifeq ($(wildcard $(ILLD_UNPACK)/.git),) +context:: $(ILLD_UNPACK)/.illd_unpack + +distclean:: + $(call DELFILE, $(ILLD_UNPACK)/.illd_unpack) + $(call DELFILE, $(ILLD_TARBALL)) + $(call DELDIR, $(ILLD_UNPACK)/Libraries/src/Libraries) +endif + +CONFIG_DIR = $(ILLD_UNPACK)/Configurations +ILLD_DIR = $(ILLD_UNPACK)/Libraries/src +PATCHES_DIR = $(ILLD_UNPACK)/patches + +PATCH_FILES = $(wildcard $(CURDIR)/$(PATCHES_DIR)/*.patch) + +apply_change_patches: + @if [ -n "$(PATCH_FILES)" ]; then \ + for p in $(PATCH_FILES); do \ + if git -C "$(CURDIR)" apply --reverse --check "$$p" >/dev/null 2>&1; then \ + echo "-- Patch $$p already applied, skipping."; \ + else \ + if git -C "$(CURDIR)" apply --whitespace=nowarn "$$p" >/dev/null 2>&1; then \ + echo "-- Successfully applied patch $$p."; \ + else \ + echo "-- Failed to apply patch $$p!"; \ + exit 1; \ + fi; \ + fi; \ + done; \ + fi + +context:: apply_change_patches + +SDK_INCDIR += ${CONFIG_DIR} +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/ArcEV +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Asc +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Lin +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Atom +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Tom +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Crc +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Scr +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_PinMap +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_PinMap/TC4Dx +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Can/Can +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Can/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Flash/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/I2c/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Pms/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smu/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Src/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Timer +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Vmt/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Wtu/Std +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Sfr/TC4Dx +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore +SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric +SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform/Compilers + +SDK_CSRCS += $(CONFIG_DIR)/Ifx_Cfg_Ssw.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxAp_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxDma_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx/IfxAsclin_PinMap_TC4Dx_BGA436_COM.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Std/IfxAsclin.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApApu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApProt.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std/IfxClock.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Dma/IfxDma_Dma.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Std/IfxDma.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std/IfxPort.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmmRst.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smu/Std/IfxSmu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Vmt/Std/IfxVmt.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Wtu/Std/IfxWtu.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Platform/Compilers/CompilerTasking.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c +SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Tc0.c + +CFLAGS += $(addprefix ${INCDIR_PREFIX},$(SDK_INCDIR)) +CFLAGS += -DSRC_CPU_CPU0_SB=SRC_CPU0SB +CFLAGS += -DSRC_GPSR00=SRC_GPSR0SR0 +CFLAGS += -DMODULE_STM0=MODULE_CPU0 +CFLAGS += -DSRC_STM0SR0=SRC_STMCPU0_SR2 + +VPATH += $(dir $(SDK_CSRCS)) + +HEAD_CSRC += $(notdir $(SDK_CSRCS)) + +LIBPATHS += $(CURDIR) diff --git a/arch/tricore/src/tc4xx/Toolchain.defs b/arch/tricore/src/tc4xx/Toolchain.defs new file mode 100644 index 00000000000..9eff515a243 --- /dev/null +++ b/arch/tricore/src/tc4xx/Toolchain.defs @@ -0,0 +1,39 @@ +############################################################################ +# arch/tricore/src/tc4xx/Toolchain.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ARCH_CHIP_TC4XX),y) + ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) + ARCHCPUFLAGS += --misrac-version=2004 --user-mode=hypervisor + ARCHCPUFLAGS += --default-near-size=0 + LDFLAGS += -Ctc4dx + else + ARCHCPUFLAGS += -mcpu=tc4DAx + ARCHCPUFLAGS += -mtc18 +endif + + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Std + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Platform + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Platform/Compilers + ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Configurations +endif + +include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs diff --git a/arch/tricore/src/tc4xx/tc4xx_dummy.c b/arch/tricore/src/tc4xx/tc4xx_dummy.c new file mode 100644 index 00000000000..720c66095fe --- /dev/null +++ b/arch/tricore/src/tc4xx/tc4xx_dummy.c @@ -0,0 +1,29 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_dummy.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/tricore/src/tc4xx/tc4xx_libc.c b/arch/tricore/src/tc4xx/tc4xx_libc.c new file mode 100644 index 00000000000..ba1138e7f84 --- /dev/null +++ b/arch/tricore/src/tc4xx/tc4xx_libc.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_libc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* TODO: + * The data copy from flash to ram reuses the implementation in tricore sdk. + * The next update will reimplement _c_init() to abandon the copy code. + * + * Usage: ltc [options] files + * -i --user-provided-initialization-code + * + * the user provides his own initialization + * routine, do not emit the copytable + * + * void _c_init(void) + * { + * } + */ + +/* The implementation of libc is introduced by default in the Tricore + * toolchain, in nuttx we made a fake libc_fpu.a library to bypass + * this issue, but the linker will still generate markup code, + * add a few definitions to fool the linker. + */ + +void __printf_float(void) +{ +} + +void __printf_int(void) +{ +} + +void __printf_llong(void) +{ +} + +void _main(void) +{ +} + +void _doexit(void) +{ +} + +/* BUG, Workaround for tasking compiler: + * + * ltc E106: unresolved external: regulator_gpio_init - + * (drivers_initialize.o) + * ltc F019: unrecoverable error: fatal link error + * + */ + +int regulator_gpio_init(void *iodev, void *desc) +{ + return 0; +} diff --git a/arch/tricore/src/tc4xx/tc4xx_serial.c b/arch/tricore/src/tc4xx/tc4xx_serial.c new file mode 100644 index 00000000000..705ef0a6041 --- /dev/null +++ b/arch/tricore/src/tc4xx/tc4xx_serial.c @@ -0,0 +1,732 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_serial.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "tricore_internal.h" + +#include "Asclin/Asc/IfxAsclin_Asc.h" +#include "IfxAsclin_PinMap.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TC4XX_UART0) +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define SERIAL_CONSOLE 1 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART0_SERIAL_CONSOLE +# if defined(CONFIG_TC4XX_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define SERIAL_CONSOLE 1 +# else +# undef TTYS0_DEV +# endif +#endif + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_TC4XX_UART0) +# define HAVE_UART_DEVICE 1 +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of tricore_earlyserialinit(), + * tricore_serialinit(), and up_putc(). + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + volatile void *uartbase; /* Base address of UART registers */ + const void *pins; /* Pin configuration */ + uint32_t baud; /* Configured baud */ + uint8_t irq; /* IRQ associated with this UART */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Serial driver methods */ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_TC4XX_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +#ifdef CONFIG_TC4XX_UART0 + +/* Pin configuration */ + +static const IfxAsclin_Asc_Pins g_uart0_pins = +{ + NULL, IfxPort_InputMode_pullUp, /* CTS pin not used */ + &UART_PIN_RX, IfxPort_InputMode_pullUp, /* RX pin */ + NULL, IfxPort_OutputMode_pushPull, /* RTS pin not used */ + &UART_PIN_TX, IfxPort_OutputMode_pushPull, /* TX pin */ + IfxPort_PadDriver_cmosAutomotiveSpeed1 +}; + +static struct up_dev_s g_uart0priv = +{ + .uartbase = &MODULE_ASCLIN0, + .pins = &g_uart0_pins, + .baud = CONFIG_UART0_BAUD, + .irq = TRICORE_UART_RX_IRQ, +}; + +static uart_dev_t g_uart0port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: asclin_init + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static void asclin_init(struct up_dev_s *priv) +{ + Ifx_ASCLIN *asclin = priv->uartbase; + const IfxAsclin_Asc_Pins *pins = priv->pins; + + /* enabling the module */ + + IfxAsclin_enableModule(asclin); + + /* disabling the clock */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); + + /* setting the module in Initialise mode */ + + IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_initialise); + + /* sets the prescaler */ + + IfxAsclin_setPrescaler(asclin, 1); + + /* temporary set the clock source for baudrate configuration */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); + + /* setting the baudrate bit fields to generate the required baudrate */ + + IfxAsclin_setBitTiming(asclin, priv->baud, + IfxAsclin_OversamplingFactor_16, + IfxAsclin_SamplePointPosition_8, + IfxAsclin_SamplesPerBit_three); + + /* disabling the clock again */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); + + /* selecting the loopback mode */ + + IfxAsclin_enableLoopBackMode(asclin, false); + + /* setting parity enable */ + + IfxAsclin_enableParity(asclin, false); + + /* setting parity type (odd/even) */ + + IfxAsclin_setParityType(asclin, IfxAsclin_ParityType_even); + + /* setting the stop bit */ + + IfxAsclin_setStopBit(asclin, IfxAsclin_StopBit_1); + + /* setting the shift direction */ + + IfxAsclin_setShiftDirection(asclin, + IfxAsclin_ShiftDirection_lsbFirst); + + /* setting the data length */ + + IfxAsclin_setDataLength(asclin, IfxAsclin_DataLength_8); + + /* setting Tx FIFO inlet width */ + + IfxAsclin_setTxFifoInletWidth(asclin, + IfxAsclin_TxFifoInletWidth_1); + + /* setting Rx FIFO outlet width */ + + IfxAsclin_setRxFifoOutletWidth(asclin, + IfxAsclin_RxFifoOutletWidth_1); + + /* setting idle delay */ + + IfxAsclin_setIdleDelay(asclin, IfxAsclin_IdleDelay_0); + + /* setting Tx FIFO level at which a Tx interrupt will be triggered */ + + IfxAsclin_setTxFifoInterruptLevel(asclin, + IfxAsclin_TxFifoInterruptLevel_0); + + /* setting Rx FIFO interrupt level at which a Rx + * interrupt will be triggered + */ + + IfxAsclin_setRxFifoInterruptLevel(asclin, + IfxAsclin_RxFifoInterruptLevel_1); + + /* setting Tx FIFO interrupt generation mode */ + + IfxAsclin_setTxFifoInterruptMode(asclin, + IfxAsclin_FifoInterruptMode_combined); + + /* setting Rx FIFO interrupt generation mode */ + + IfxAsclin_setRxFifoInterruptMode(asclin, + IfxAsclin_FifoInterruptMode_combined); + + /* selecting the frame mode */ + + IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_asc); + + /* Pin mapping */ + + if (pins != NULL) + { + IfxAsclin_Cts_In *cts = pins->cts; + + if (cts != NULL) + { + IfxAsclin_initCtsPin(cts, pins->ctsMode, pins->pinDriver); + } + + IfxAsclin_Rx_In *rx = pins->rx; + + if (rx != NULL) + { + IfxAsclin_initRxPin(rx, pins->rxMode, pins->pinDriver); + } + + IfxAsclin_Rts_Out *rts = pins->rts; + + if (rts != NULL) + { + IfxAsclin_initRtsPin(rts, pins->rtsMode, pins->pinDriver); + } + + IfxAsclin_Tx_Out *tx = pins->tx; + + if (tx != NULL) + { + IfxAsclin_initTxPin(tx, pins->txMode, pins->pinDriver); + } + } + + /* select the clock source */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); + + /* disable all flags */ + + IfxAsclin_disableAllFlags(asclin); + + /* clear all flags */ + + IfxAsclin_clearAllFlags(asclin); + + /* HW error flags */ + + IfxAsclin_enableParityErrorFlag(asclin, true); + IfxAsclin_enableFrameErrorFlag(asclin, true); + IfxAsclin_enableRxFifoOverflowFlag(asclin, true); + IfxAsclin_enableRxFifoUnderflowFlag(asclin, true); + IfxAsclin_enableTxFifoOverflowFlag(asclin, true); + + /* enable transfers */ + + IfxAsclin_enableRxFifoInlet(asclin, true); + IfxAsclin_enableTxFifoOutlet(asclin, true); + + IfxAsclin_flushRxFifo(asclin); + IfxAsclin_flushTxFifo(asclin); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + asclin_init(dev->priv); + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + int ret; + + /* Initialize interrupt generation on the peripheral */ + + ret = irq_attach(priv->irq, up_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = arg; + + if (up_rxavailable(dev)) + { + uart_recvchars(dev); + } + + if (up_txready(dev)) + { + uart_xmitchars(dev); + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = dev->priv; + + return IfxAsclin_readRxData(priv->uartbase); +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = dev->priv; + irqstate_t flags = enter_critical_section(); + + IfxAsclin_enableRxFifoFillLevelFlag(priv->uartbase, enable); + IfxAsclin_enableRxFifoInlet(priv->uartbase, enable); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + return IfxAsclin_getRxFifoFillLevel(priv->uartbase) > 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = dev->priv; + + /* Wait for FIFO */ + + if (dev == &CONSOLE_DEV) + { + up_putc(ch); + return; + } + + while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); + + IfxAsclin_clearAllFlags(priv->uartbase); + IfxAsclin_writeTxData(priv->uartbase, ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (enable) + { + /* Enable the TX interrupt */ + + uart_xmitchars(dev); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + return true; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + /* Return true if the TX wartermak is pending */ + + return IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0; +} + +/**************************************************************************** + * Name: tricore_lowputc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void tricore_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct up_dev_s *priv = CONSOLE_DEV.priv; + + /* Wait for FIFO */ + + while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); + + IfxAsclin_clearAllFlags(priv->uartbase); + IfxAsclin_writeTxData(priv->uartbase, ch); +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: tricore_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during boot up. This must be called + * before tricore_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock + * initialization performed in up_clkinitialize(). + * + ****************************************************************************/ + +void tricore_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: tricore_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that tricore_earlyserialinit was called previously. + * + ****************************************************************************/ + +void tricore_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + uart_register("/dev/ttyS0", &TTYS0_DEV); +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + tricore_lowputc(ch); +#endif +} +#endif /* USE_SERIALDRIVER */ diff --git a/arch/tricore/src/tc4xx/tc4xx_timerisr.c b/arch/tricore/src/tc4xx/tc4xx_timerisr.c new file mode 100644 index 00000000000..85625685a36 --- /dev/null +++ b/arch/tricore/src/tc4xx/tc4xx_timerisr.c @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_timerisr.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "tricore_internal.h" + +#include "IfxStm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + struct oneshot_lowerhalf_s *lower; + + lower = tricore_systimer_initialize(&MODULE_CPU0, + TRICORE_SRC2IRQ(&SRC_STMCPU0_SR2), + SCU_FREQUENCY); + + DEBUGASSERT(lower != NULL); + + up_alarm_set_lowerhalf(lower); +} diff --git a/boards/Kconfig b/boards/Kconfig index b8c82fd2072..0ae1906040d 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2409,6 +2409,13 @@ config ARCH_BOARD_A2G_TC397_5V_TFT This options selects support for NuttX on the Infineon's AURIX board board featuring the TC397 6Quad CPU. +config ARCH_BOARD_TRIBOARD_TC4X9_COM + bool "Infineon's AURIX TC4DA board: TRIBOARD_TC4X9_COM" + depends on ARCH_CHIP_TC4DA + ---help--- + This options selects support for NuttX on the Infineon's AURIX board + board featuring the TC4DA 6Quad CPU. + config ARCH_BOARD_QEMU_ARMV7A bool "Qemu ARMv7a CPUs board" depends on ARCH_CHIP_QEMU_ARM @@ -3802,6 +3809,7 @@ config ARCH_BOARD default "starpro64" if ARCH_BOARD_EIC7700X_STARPRO64 default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD default "a2g-tc397-5v-tft" if ARCH_BOARD_A2G_TC397_5V_TFT + default "triboard_tc4x9_com" if ARCH_BOARD_TRIBOARD_TC4X9_COM default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A default "qemu-armv7r" if ARCH_BOARD_QEMU_ARMV7R default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h b/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h index 12fb901b624..681acca15b7 100644 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h @@ -33,6 +33,310 @@ * Pre-processor Definitions ****************************************************************************/ +#define BANKA_CORE0_PFLASH_KERNEL_START 0x80000000 +#define BANKA_CORE0_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE0_PFLASH_USER_START 0x80180000 +#define BANKA_CORE0_PFLASH_USER_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE1_PFLASH_KERNEL_START 0x80300000 +#define BANKA_CORE1_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE1_PFLASH_USER_START 0x80480000 +#define BANKA_CORE1_PFLASH_USER_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE2_PFLASH_KERNEL_START 0x80600000 +#define BANKA_CORE2_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE2_PFLASH_USER_START 0x80780000 +#define BANKA_CORE2_PFLASH_USER_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE3_PFLASH_KERNEL_START 0x80900000 +#define BANKA_CORE3_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE3_PFLASH_USER_START 0x80A80000 +#define BANKA_CORE3_PFLASH_USER_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE4_PFLASH_KERNEL_START 0x80C00000 +#define BANKA_CORE4_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE4_PFLASH_USER_START 0x80D80000 +#define BANKA_CORE4_PFLASH_USER_SIZE 0x180000 /* 1536KB */ +#define BANKA_CORE5_PFLASH_KERNEL_START 0x80F00000 +#define BANKA_CORE5_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ +#define BANKA_CORE5_PFLASH_USER_START 0x80F80000 +#define BANKA_CORE5_PFLASH_USER_SIZE 0x80000 /* 512KB */ +#define CORE0_STACK_KERNEL_START 0x70000000 +#define CORE0_STACK_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE0_STACK_USER_START 0x70008000 +#define CORE0_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE0_DSPR_KERNEL_START 0x70010000 +#define CORE0_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ +#define CORE0_DSPR_USER_START 0x7003C000 +#define CORE0_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE0_PSPR_KERNEL_START 0x70100000 +#define CORE0_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE0_PSPR_USER_START 0x70108000 +#define CORE0_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE0_DLMU_KERNEL_START 0x90000000 +#define CORE0_DLMU_KERNEL_SIZE 0x0 /* 0KB */ +#define CORE0_DLMU_USER_START 0x90000000 +#define CORE0_DLMU_USER_SIZE 0x10000 /* 64KB */ +#define CORE1_STACK_KERNEL_START 0x60000000 +#define CORE1_STACK_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE1_STACK_USER_START 0x60008000 +#define CORE1_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE1_DSPR_KERNEL_START 0x60010000 +#define CORE1_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ +#define CORE1_DSPR_USER_START 0x6003C000 +#define CORE1_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE1_PSPR_KERNEL_START 0x60100000 +#define CORE1_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE1_PSPR_USER_START 0x60108000 +#define CORE1_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE1_DLMU_KERNEL_START 0x90010000 +#define CORE1_DLMU_KERNEL_SIZE 0x0 /* 0KB */ +#define CORE1_DLMU_USER_START 0x90010000 +#define CORE1_DLMU_USER_SIZE 0x10000 /* 64KB */ +#define CORE2_STACK_KERNEL_START 0x50000000 +#define CORE2_STACK_KERNEL_SIZE 0x6000 /* 24KB */ +#define CORE2_STACK_USER_START 0x50006000 +#define CORE2_STACK_USER_SIZE 0x5000 /* 20KB */ +#define CORE2_DSPR_KERNEL_START 0x5000B000 +#define CORE2_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ +#define CORE2_DSPR_USER_START 0x50018000 +#define CORE2_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE2_PSPR_KERNEL_START 0x50100000 +#define CORE2_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE2_PSPR_USER_START 0x50108000 +#define CORE2_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE2_DLMU_KERNEL_START 0x90020000 +#define CORE2_DLMU_KERNEL_SIZE 0x0 /* 0KB */ +#define CORE2_DLMU_USER_START 0x90020000 +#define CORE2_DLMU_USER_SIZE 0x10000 /* 64KB */ +#define CORE3_STACK_KERNEL_START 0x40000000 +#define CORE3_STACK_KERNEL_SIZE 0x6000 /* 24KB */ +#define CORE3_STACK_USER_START 0x40006000 +#define CORE3_STACK_USER_SIZE 0x5000 /* 20KB */ +#define CORE3_DSPR_KERNEL_START 0x4000B000 +#define CORE3_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ +#define CORE3_DSPR_USER_START 0x40018000 +#define CORE3_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE3_PSPR_KERNEL_START 0x40100000 +#define CORE3_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE3_PSPR_USER_START 0x40108000 +#define CORE3_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE3_DLMU_KERNEL_START 0x90030000 +#define CORE3_DLMU_KERNEL_SIZE 0x0 /* 0KB */ +#define CORE3_DLMU_USER_START 0x90030000 +#define CORE3_DLMU_USER_SIZE 0x10000 /* 64KB */ +#define CORE4_STACK_KERNEL_START 0x30000000 +#define CORE4_STACK_KERNEL_SIZE 0x6000 /* 24KB */ +#define CORE4_STACK_USER_START 0x30006000 +#define CORE4_STACK_USER_SIZE 0x5000 /* 20KB */ +#define CORE4_DSPR_KERNEL_START 0x3000B000 +#define CORE4_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ +#define CORE4_DSPR_USER_START 0x30018000 +#define CORE4_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE4_PSPR_KERNEL_START 0x30100000 +#define CORE4_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE4_PSPR_USER_START 0x30108000 +#define CORE4_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE4_DLMU_KERNEL_START 0x90100000 +#define CORE4_DLMU_KERNEL_SIZE 0x0 /* 0KB */ +#define CORE4_DLMU_USER_START 0x90100000 +#define CORE4_DLMU_USER_SIZE 0x10000 /* 64KB */ +#define CORE5_STACK_KERNEL_START 0x10000000 +#define CORE5_STACK_KERNEL_SIZE 0x6000 /* 24KB */ +#define CORE5_STACK_USER_START 0x10006000 +#define CORE5_STACK_USER_SIZE 0x5000 /* 20KB */ +#define CORE5_DSPR_KERNEL_START 0x1000B000 +#define CORE5_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ +#define CORE5_DSPR_USER_START 0x10018000 +#define CORE5_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE5_PSPR_KERNEL_START 0x10100000 +#define CORE5_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE5_PSPR_USER_START 0x10108000 +#define CORE5_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE5_DLMU_KERNEL_START 0x90110000 +#define CORE5_DLMU_KERNEL_SIZE 0x0 /* 0KB */ +#define CORE5_DLMU_USER_START 0x90110000 +#define CORE5_DLMU_USER_SIZE 0x10000 /* 64KB */ +#define LMU0_UNUSED_START 0xB0040000 +#define LMU0_UNUSED_SIZE 0x40000 /* 256KB */ +#define LMU1_UNUSED_START 0xB0080000 +#define LMU1_UNUSED_SIZE 0x40000 /* 256KB */ +#define LMU2_UNUSED_START 0xB00C0000 +#define LMU2_UNUSED_SIZE 0x40000 /* 256KB */ +#define DFLASH0_NVM_START 0xAF000000 +#define DFLASH0_NVM_SIZE 0x40000 /* 256KB */ +#define DFLASH0_MANUFACTURY_START 0xAF040000 +#define DFLASH0_MANUFACTURY_SIZE 0x2800 /* 10K */ +#define DFLASH0_BSWLOG_START 0xAF042800 +#define DFLASH0_BSWLOG_SIZE 0x10000 /* 64K */ +#define DFLASH0_TRAPINFO_START 0xAF052800 +#define DFLASH0_TRAPINFO_SIZE 0x4000 /* 16K */ +#define DFLASH0_DFXLOG_START 0xAF056800 +#define DFLASH0_DFXLOG_SIZE 0x4000 /* 16K */ +#define DFLASH0_UNUSED_START 0xAF05A800 +#define DFLASH0_UNUSED_SIZE 0xA5800 /* 662K */ +#define UCB0_START 0xAF400000 +#define UCB0_SIZE 0x6000 /* 24K */ +#define PERIPHERALS_START 0xF0000000 +#define PERIPHERALS_SIZE 0xB720000 /* 187520K */ +#define CORE0_DCACHE_START 0x7003C000 +#define CORE0_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE1_DCACHE_START 0x6003C000 +#define CORE1_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE2_DCACHE_START 0x50018000 +#define CORE2_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE3_DCACHE_START 0x40018000 +#define CORE3_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE4_DCACHE_START 0x30018000 +#define CORE4_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE5_DCACHE_START 0x10018000 +#define CORE5_DCACHE_SIZE 0x4000 /* 16K */ + +/**************************************************************************** + * Common macros + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_FLAT + +# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START +# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE +# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START +# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE +# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START +# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE +# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START +# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE +# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START +# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE +# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START +# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE + +#else + +# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START +# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE +# define CORE0_PFLASH_USER_START BANKA_CORE0_PFLASH_USER_START +# define CORE0_PFLASH_USER_SIZE BANKA_CORE0_PFLASH_USER_SIZE + +# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START +# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE +# define CORE1_PFLASH_USER_START BANKA_CORE1_PFLASH_USER_START +# define CORE1_PFLASH_USER_SIZE BANKA_CORE1_PFLASH_USER_SIZE + +# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START +# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE +# define CORE2_PFLASH_USER_START BANKA_CORE2_PFLASH_USER_START +# define CORE2_PFLASH_USER_SIZE BANKA_CORE2_PFLASH_USER_SIZE + +# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START +# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE +# define CORE3_PFLASH_USER_START BANKA_CORE3_PFLASH_USER_START +# define CORE3_PFLASH_USER_SIZE BANKA_CORE3_PFLASH_USER_SIZE + +# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START +# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE +# define CORE4_PFLASH_USER_START BANKA_CORE4_PFLASH_USER_START +# define CORE4_PFLASH_USER_SIZE BANKA_CORE4_PFLASH_USER_SIZE + +# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START +# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE +# define CORE5_PFLASH_USER_START BANKA_CORE5_PFLASH_USER_START +# define CORE5_PFLASH_USER_SIZE BANKA_CORE5_PFLASH_USER_SIZE + +#endif + +#define BL_PFLASH_START BANKA_BL_PFLASH_START +#define BL_PFLASH_SIZE BANKA_BL_PFLASH_SIZE +#define BL_DLMU_START CORE0_DLMU_KERNEL_START +#define BL_DLMU_SIZE CORE0_DLMU_KERNEL_SIZE +#define BL_DSPR_START CORE0_DSPR_KERNEL_START +#define BL_DSPR_SIZE CORE0_DSPR_KERNEL_SIZE +#define BL_PSPR_START CORE0_PSPR_KERNEL_START +#define BL_PSPR_SIZE CORE0_PSPR_KERNEL_SIZE +#define MBF_HASH_START BANKA_MBF_HASH_START +#define MBF_HASH_SIZE BANKA_MBF_HASH_SIZE + +#define NC_START(addr) \ + ((addr) >= 0x80000000 && (addr) <= 0x9FFFFFFF ? (addr) + 0x20000000 : (addr)) + +#define AURIX_PERIPHERAL_BASE_ADDR 0xF0000000 +#define AURIX_PERIPHERAL_SIZE 0x0B720000 + +#define DSPR_LOCAL_START 0xD0000000 +#define PSPR_LOCAL_START 0xC0000000 + +#define BACKGROUND_START 0x0 +#define BACKGROUND_SIZE 0xFFFFFFFF + +#define CORE0_DCACHE_KERNEL_START 0x7003C000 +#define CORE0_DCACHE_KERNEL_SIZE 0x4000 +#define CORE1_DCACHE_KERNEL_START 0x6003C000 +#define CORE1_DCACHE_KERNEL_SIZE 0x4000 +#define CORE2_DCACHE_KERNEL_START 0x50018000 +#define CORE2_DCACHE_KERNEL_SIZE 0x4000 +#define CORE3_DCACHE_KERNEL_START 0x40018000 +#define CORE3_DCACHE_KERNEL_SIZE 0x4000 +#define CORE4_DCACHE_KERNEL_START 0x30018000 +#define CORE4_DCACHE_KERNEL_SIZE 0x4000 +#define CORE5_DCACHE_KERNEL_START 0x10018000 +#define CORE5_DCACHE_KERNEL_SIZE 0x4000 + +#define CORE_PFLASH_KERNEL_START(COREID) CORE##COREID##_PFLASH_KERNEL_START +#define CORE_PFLASH_KERNEL_SIZE(COREID) CORE##COREID##_PFLASH_KERNEL_SIZE +#define GENERATE_CORE_PFLASH_KERNEL_START(COREID) CORE_PFLASH_KERNEL_START(COREID) +#define GENERATE_CORE_PFLASH_KERNEL_SIZE(COREID) CORE_PFLASH_KERNEL_SIZE(COREID) + +#define CORE_STACK_KERNEL_START(COREID) CORE##COREID##_STACK_KERNEL_START +#define CORE_STACK_KERNEL_SIZE(COREID) CORE##COREID##_STACK_KERNEL_SIZE +#define GENERATE_CORE_STACK_KERNEL_START(COREID) CORE_STACK_KERNEL_START(COREID) +#define GENERATE_CORE_STACK_KERNEL_SIZE(COREID) CORE_STACK_KERNEL_SIZE(COREID) + +#define CORE_DSPR_KERNEL_START(COREID) CORE##COREID##_DSPR_KERNEL_START +#define CORE_DSPR_KERNEL_SIZE(COREID) CORE##COREID##_DSPR_KERNEL_SIZE +#define GENERATE_CORE_DSPR_KERNEL_START(COREID) CORE_DSPR_KERNEL_START(COREID) +#define GENERATE_CORE_DSPR_KERNEL_SIZE(COREID) CORE_DSPR_KERNEL_SIZE(COREID) + +#define CORE_PSPR_KERNEL_START(COREID) CORE##COREID##_PSPR_KERNEL_START +#define CORE_PSPR_KERNEL_SIZE(COREID) CORE##COREID##_PSPR_KERNEL_SIZE +#define GENERATE_CORE_PSPR_KERNEL_START(COREID) CORE_PSPR_KERNEL_START(COREID) +#define GENERATE_CORE_PSPR_KERNEL_SIZE(COREID) CORE_PSPR_KERNEL_SIZE(COREID) + +#define CORE_DLMU_KERNEL_START(COREID) CORE##COREID##_DLMU_KERNEL_START +#define CORE_DLMU_KERNEL_SIZE(COREID) CORE##COREID##_DLMU_KERNEL_SIZE +#define GENERATE_CORE_DLMU_KERNEL_START(COREID) CORE_DLMU_KERNEL_START(COREID) +#define GENERATE_CORE_DLMU_KERNEL_SIZE(COREID) CORE_DLMU_KERNEL_SIZE(COREID) + +#define CORE_DCACHE_KERNEL_START(COREID) CORE##COREID##_DCACHE_KERNEL_START +#define CORE_DCACHE_KERNEL_SIZE(COREID) CORE##COREID##_DCACHE_KERNEL_SIZE +#define GENERATE_CORE_DCACHE_KERNEL_START(COREID) CORE_DCACHE_KERNEL_START(COREID) +#define GENERATE_CORE_DCACHE_KERNEL_SIZE(COREID) CORE_DCACHE_KERNEL_SIZE(COREID) + +#ifndef CONFIG_BUILD_FLAT + +#define CORE_PFLASH_USER_START(COREID) CORE##COREID##_PFLASH_USER_START +#define CORE_PFLASH_USER_SIZE(COREID) CORE##COREID##_PFLASH_USER_SIZE +#define GENERATE_CORE_PFLASH_USER_START(COREID) CORE_PFLASH_USER_START(COREID) +#define GENERATE_CORE_PFLASH_USER_SIZE(COREID) CORE_PFLASH_USER_SIZE(COREID) + +#define CORE_STACK_USER_START(COREID) CORE##COREID##_STACK_USER_START +#define CORE_STACK_USER_SIZE(COREID) CORE##COREID##_STACK_USER_SIZE +#define GENERATE_CORE_STACK_USER_START(COREID) CORE_STACK_USER_START(COREID) +#define GENERATE_CORE_STACK_USER_SIZE(COREID) CORE_STACK_USER_SIZE(COREID) + +#define CORE_DSPR_USER_START(COREID) CORE##COREID##_DSPR_USER_START +#define CORE_DSPR_USER_SIZE(COREID) CORE##COREID##_DSPR_USER_SIZE +#define GENERATE_CORE_DSPR_USER_START(COREID) CORE_DSPR_USER_START(COREID) +#define GENERATE_CORE_DSPR_USER_SIZE(COREID) CORE_DSPR_USER_SIZE(COREID) + +#define CORE_PSPR_USER_START(COREID) CORE##COREID##_PSPR_USER_START +#define CORE_PSPR_USER_SIZE(COREID) CORE##COREID##_PSPR_USER_SIZE +#define GENERATE_CORE_PSPR_USER_START(COREID) CORE_PSPR_USER_START(COREID) +#define GENERATE_CORE_PSPR_USER_SIZE(COREID) CORE_PSPR_USER_SIZE(COREID) + +#define CORE_DLMU_USER_START(COREID) CORE##COREID##_DLMU_USER_START +#define CORE_DLMU_USER_SIZE(COREID) CORE##COREID##_DLMU_USER_SIZE +#define GENERATE_CORE_DLMU_USER_START(COREID) CORE_DLMU_USER_START(COREID) +#define GENERATE_CORE_DLMU_USER_SIZE(COREID) CORE_DLMU_USER_SIZE(COREID) + +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -58,4 +362,5 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ + #endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl deleted file mode 100644 index 126640d8f93..00000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl +++ /dev/null @@ -1,2983 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include - -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf32-tricore") -OUTPUT_ARCH("tricore") -ENTRY(_START) - -__TRICORE_DERIVATE_MEMORY_MAP__ = 0x390; - -LCF_CSA0_SIZE = 40k; -LCF_USTACK0_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK0_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA1_SIZE = 40k; -LCF_USTACK1_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK1_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA2_SIZE = 40k; -LCF_USTACK2_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK2_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA3_SIZE = 40k; -LCF_USTACK3_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK3_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA4_SIZE = 40k; -LCF_USTACK4_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK4_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA5_SIZE = 40k; -LCF_USTACK5_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK5_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_HEAP_SIZE = 4k; - -LCF_DSPR5_START = 0x10000000; -LCF_DSPR5_SIZE = 96k; - -LCF_DSPR4_START = 0x30000000; -LCF_DSPR4_SIZE = 96k; - -LCF_DSPR3_START = 0x40000000; -LCF_DSPR3_SIZE = 96k; - -LCF_DSPR2_START = 0x50000000; -LCF_DSPR2_SIZE = 96k; - -LCF_DSPR1_START = 0x60000000; -LCF_DSPR1_SIZE = 240k; - -LCF_DSPR0_START = 0x70000000; -LCF_DSPR0_SIZE = 240k; - -LCF_CSA5_OFFSET = (LCF_DSPR5_SIZE - 1k - LCF_CSA5_SIZE); -LCF_ISTACK5_OFFSET = (LCF_CSA5_OFFSET - 256 - LCF_ISTACK5_SIZE); -LCF_USTACK5_OFFSET = (LCF_ISTACK5_OFFSET - 256 - LCF_USTACK5_SIZE); - -LCF_CSA4_OFFSET = (LCF_DSPR4_SIZE - 1k - LCF_CSA4_SIZE); -LCF_ISTACK4_OFFSET = (LCF_CSA4_OFFSET - 256 - LCF_ISTACK4_SIZE); -LCF_USTACK4_OFFSET = (LCF_ISTACK4_OFFSET - 256 - LCF_USTACK4_SIZE); - -LCF_CSA3_OFFSET = (LCF_DSPR3_SIZE - 1k - LCF_CSA3_SIZE); -LCF_ISTACK3_OFFSET = (LCF_CSA3_OFFSET - 256 - LCF_ISTACK3_SIZE); -LCF_USTACK3_OFFSET = (LCF_ISTACK3_OFFSET - 256 - LCF_USTACK3_SIZE); - -LCF_CSA2_OFFSET = (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE); -LCF_ISTACK2_OFFSET = (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE); -LCF_USTACK2_OFFSET = (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE); - -LCF_CSA1_OFFSET = (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE); -LCF_ISTACK1_OFFSET = (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE); -LCF_USTACK1_OFFSET = (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE); - -LCF_CSA0_OFFSET = (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE); -LCF_ISTACK0_OFFSET = (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE); -LCF_USTACK0_OFFSET = (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE); - -LCF_HEAP0_OFFSET = (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE); -LCF_HEAP1_OFFSET = (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE); -LCF_HEAP2_OFFSET = (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE); -LCF_HEAP3_OFFSET = (LCF_USTACK3_OFFSET - LCF_HEAP_SIZE); -LCF_HEAP4_OFFSET = (LCF_USTACK4_OFFSET - LCF_HEAP_SIZE); -LCF_HEAP5_OFFSET = (LCF_USTACK5_OFFSET - LCF_HEAP_SIZE); - -LCF_INTVEC0_START = 0x802FE000; -LCF_INTVEC1_START = 0x805FE000; -LCF_INTVEC2_START = 0x808FE000; -LCF_INTVEC3_START = 0x80BFE000; -LCF_INTVEC4_START = 0x80EFE000; -LCF_INTVEC5_START = 0x80FFE000; - -__INTTAB_CPU0 = LCF_INTVEC0_START; -__INTTAB_CPU1 = LCF_INTVEC1_START; -__INTTAB_CPU2 = LCF_INTVEC2_START; -__INTTAB_CPU3 = LCF_INTVEC3_START; -__INTTAB_CPU4 = LCF_INTVEC4_START; -__INTTAB_CPU5 = LCF_INTVEC5_START; - -LCF_TRAPVEC0_START = 0x80000100; -LCF_TRAPVEC1_START = 0x80300000; -LCF_TRAPVEC2_START = 0x80600000; -LCF_TRAPVEC3_START = 0x80900000; -LCF_TRAPVEC4_START = 0x80C00000; -LCF_TRAPVEC5_START = 0x80F00000; - -LCF_STARTPTR_CPU0 = 0x80000000; -LCF_STARTPTR_CPU1 = 0x80300100; -LCF_STARTPTR_CPU2 = 0x80600100; -LCF_STARTPTR_CPU3 = 0x80900100; -LCF_STARTPTR_CPU4 = 0x80C00100; -LCF_STARTPTR_CPU5 = 0x80F00100; - -LCF_STARTPTR_NC_CPU0 = 0xA0000000; -LCF_STARTPTR_NC_CPU1 = 0xA0300100; -LCF_STARTPTR_NC_CPU2 = 0xA0600100; -LCF_STARTPTR_NC_CPU3 = 0xA0900100; -LCF_STARTPTR_NC_CPU4 = 0xA0C00100; -LCF_STARTPTR_NC_CPU5 = 0xA0F00100; - -RESET = LCF_STARTPTR_NC_CPU0; - -MEMORY -{ - dsram5_local (w!xp): org = 0xd0000000, len = 96K - dsram5 (w!xp): org = 0x10000000, len = 96K - psram5 (w!xp): org = 0x10100000, len = 64K - - dsram4_local (w!xp): org = 0xd0000000, len = 96K - dsram4 (w!xp): org = 0x30000000, len = 96K - psram4 (w!xp): org = 0x30100000, len = 64K - - dsram3_local (w!xp): org = 0xd0000000, len = 96K - dsram3 (w!xp): org = 0x40000000, len = 96K - psram3 (w!xp): org = 0x40100000, len = 64K - - dsram2_local (w!xp): org = 0xd0000000, len = 96K - dsram2 (w!xp): org = 0x50000000, len = 96K - psram2 (w!xp): org = 0x50100000, len = 64K - - dsram1_local (w!xp): org = 0xd0000000, len = 240K - dsram1 (w!xp): org = 0x60000000, len = 240K - psram1 (w!xp): org = 0x60100000, len = 64K - - dsram0_local (w!xp): org = 0xd0000000, len = 240K - dsram0 (w!xp): org = 0x70000000, len = 240K - psram0 (w!xp): org = 0x70100000, len = 64K - - psram_local (w!xp): org = 0xc0000000, len = 64K - - pfls0 (rx!p): org = 0x80000000, len = 3M - pfls0_nc (rx!p): org = 0xa0000000, len = 3M - - pfls1 (rx!p): org = 0x80300000, len = 3M - pfls1_nc (rx!p): org = 0xa0300000, len = 3M - - pfls2 (rx!p): org = 0x80600000, len = 3M - pfls2_nc (rx!p): org = 0xa0600000, len = 3M - - pfls3 (rx!p): org = 0x80900000, len = 3M - pfls3_nc (rx!p): org = 0xa0900000, len = 3M - - pfls4 (rx!p): org = 0x80c00000, len = 3M - pfls4_nc (rx!p): org = 0xa0c00000, len = 3M - - pfls5 (rx!p): org = 0x80f00000, len = 1M - pfls5_nc (rx!p): org = 0xa0f00000, len = 1M - - dfls0 (rx!p): org = 0xaf000000, len = 1M - - ucb (rx!p): org = 0xaf400000, len = 24K - - cpu0_dlmu (w!xp): org = 0x90000000, len = 64K - cpu0_dlmu_nc (w!xp): org = 0xb0000000, len = 64K - - cpu1_dlmu (w!xp): org = 0x90010000, len = 64K - cpu1_dlmu_nc (w!xp): org = 0xb0010000, len = 64K - - cpu2_dlmu (w!xp): org = 0x90020000, len = 64K - cpu2_dlmu_nc (w!xp): org = 0xb0020000, len = 64K - - cpu3_dlmu (w!xp): org = 0x90030000, len = 64K - cpu3_dlmu_nc (w!xp): org = 0xb0030000, len = 64K - - lmuram (w!xp): org = 0x90040000, len = 768K - lmuram_nc (w!xp): org = 0xb0040000, len = 768K - - cpu4_dlmu (w!xp): org = 0x90100000, len = 64K - cpu4_dlmu_nc (w!xp): org = 0xb0100000, len = 64K - - cpu5_dlmu (w!xp): org = 0x90110000, len = 64K - cpu5_dlmu_nc (w!xp): org = 0xb0110000, len = 64K - - edmem (w!xp): org = 0x99000000, len = 4M - edmem_nc (w!xp): org = 0xb9000000, len = 4M -} - -/* map local memory address to a global address */ -REGION_MAP( CPU0 , ORIGIN(dsram0_local), LENGTH(dsram0_local), ORIGIN(dsram0)) -REGION_MAP( CPU1 , ORIGIN(dsram1_local), LENGTH(dsram1_local), ORIGIN(dsram1)) -REGION_MAP( CPU2 , ORIGIN(dsram2_local), LENGTH(dsram2_local), ORIGIN(dsram2)) -REGION_MAP( CPU3 , ORIGIN(dsram3_local), LENGTH(dsram3_local), ORIGIN(dsram3)) -REGION_MAP( CPU4 , ORIGIN(dsram4_local), LENGTH(dsram4_local), ORIGIN(dsram4)) -REGION_MAP( CPU5 , ORIGIN(dsram5_local), LENGTH(dsram5_local), ORIGIN(dsram5)) - -/* map cached and non cached addresses */ -REGION_MIRROR("pfls0", "pfls0_nc") -REGION_MIRROR("pfls1", "pfls1_nc") -REGION_MIRROR("pfls2", "pfls2_nc") -REGION_MIRROR("pfls3", "pfls3_nc") -REGION_MIRROR("pfls4", "pfls4_nc") -REGION_MIRROR("pfls5", "pfls5_nc") -REGION_MIRROR("cpu0_dlmu", "cpu0_dlmu_nc") -REGION_MIRROR("cpu1_dlmu", "cpu1_dlmu_nc") -REGION_MIRROR("cpu2_dlmu", "cpu2_dlmu_nc") -REGION_MIRROR("cpu3_dlmu", "cpu3_dlmu_nc") -REGION_MIRROR("cpu4_dlmu", "cpu4_dlmu_nc") -REGION_MIRROR("cpu5_dlmu", "cpu5_dlmu_nc") -REGION_MIRROR("lmuram", "lmuram_nc") - -/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ - -REGION_ALIAS( default_ram , dsram0) -REGION_ALIAS( default_rom , pfls0) - -/* -REGION_ALIAS( default_ram , dsram1) -REGION_ALIAS( default_rom , pfls1) -*/ -/* -REGION_ALIAS( default_ram , dsram2) -REGION_ALIAS( default_rom , pfls2) -*/ -/* -REGION_ALIAS( default_ram , dsram3) -REGION_ALIAS( default_rom , pfls3) -*/ -/* -REGION_ALIAS( default_ram , dsram4) -REGION_ALIAS( default_rom , pfls4) -*/ -/* -REGION_ALIAS( default_ram , dsram5) -REGION_ALIAS( default_rom , pfls5) -*/ - -/*Sections located at absolute fixed address*/ - /*Fixed memory Allocations for stack memory and CSA*/ - CORE_ID = CPU5; - SECTIONS - { - CORE_SEC(.ustack) (LCF_DSPR5_START + LCF_USTACK5_OFFSET): - { PROVIDE(__USTACK5_END = .); . = . + LCF_USTACK5_SIZE; PROVIDE(__USTACK5 = .); } - - CORE_SEC(.istack) (LCF_DSPR5_START + LCF_ISTACK5_OFFSET): - { PROVIDE(__ISTACK5_END = .); . = . + LCF_ISTACK5_SIZE; PROVIDE(__ISTACK5 = .); } - - CORE_SEC(.csa) (LCF_DSPR5_START + LCF_CSA5_OFFSET): - { PROVIDE(__CSA5 = .); . = . + LCF_CSA5_SIZE; PROVIDE(__CSA5_END = .); } - } - - CORE_ID = CPU4; - SECTIONS - { - CORE_SEC(.ustack) (LCF_DSPR4_START + LCF_USTACK4_OFFSET): - { PROVIDE(__USTACK4_END = .); . = . + LCF_USTACK4_SIZE; PROVIDE(__USTACK4 = .); } - - CORE_SEC(.istack) (LCF_DSPR4_START + LCF_ISTACK4_OFFSET): - { PROVIDE(__ISTACK4_END = .); . = . + LCF_ISTACK4_SIZE; PROVIDE(__ISTACK4 = .); } - - CORE_SEC(.csa) (LCF_DSPR4_START + LCF_CSA4_OFFSET): - { PROVIDE(__CSA4 = .); . = . + LCF_CSA4_SIZE; PROVIDE(__CSA4_END = .); } - } - - CORE_ID = CPU3; - SECTIONS - { - CORE_SEC(.ustack) (LCF_DSPR3_START + LCF_USTACK3_OFFSET): - { PROVIDE(__USTACK3_END = .); . = . + LCF_USTACK3_SIZE; PROVIDE(__USTACK3 = .); } - - CORE_SEC(.istack) (LCF_DSPR3_START + LCF_ISTACK3_OFFSET): - { PROVIDE(__ISTACK3_END = .); . = . + LCF_ISTACK3_SIZE; PROVIDE(__ISTACK3 = .); } - - CORE_SEC(.csa) (LCF_DSPR3_START + LCF_CSA3_OFFSET): - { PROVIDE(__CSA3 = .); . = . + LCF_CSA3_SIZE; PROVIDE(__CSA3_END = .); } - } - - CORE_ID = CPU2; - SECTIONS - { - CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET): - { PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); } - - CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET): - { PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); } - - CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET): - { PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); } - } - - CORE_ID = CPU1; - SECTIONS - { - CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET): - { PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); } - - CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET): - { PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); } - - CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET): - { PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); } - } - - CORE_ID = CPU0; - SECTIONS - { - CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET): - { PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); } - - CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET): - { PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); } - - CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET): - { PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); } - } - - /*Fixed memory Allocations for _START*/ - CORE_ID = GLOBAL ; - SECTIONS - { - .start_tc0 (LCF_STARTPTR_NC_CPU0) : FLAGS(rxl) { KEEP (*(.start)); } > pfls0_nc - .interface_const (0x80000020) : { __IF_CONST = .; KEEP (*(.interface_const)); } > pfls0 - PROVIDE(__START0 = LCF_STARTPTR_NC_CPU0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); /* Not used */ - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU3 = 0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 0); - } - - /*Fixed memory Allocations for Trap Vector Table*/ - CORE_ID = GLOBAL; - SECTIONS - { - .traptab_tc0 (LCF_TRAPVEC0_START) : { PROVIDE(__TRAPTAB_CPU0 = .); KEEP (*(.traptab_cpu0)); } > pfls0 - .traptab_tc1 (LCF_TRAPVEC1_START) : { PROVIDE(__TRAPTAB_CPU1 = .); KEEP (*(.traptab_cpu1)); } > pfls1 - .traptab_tc2 (LCF_TRAPVEC2_START) : { PROVIDE(__TRAPTAB_CPU2 = .); KEEP (*(.traptab_cpu2)); } > pfls2 - .traptab_tc3 (LCF_TRAPVEC3_START) : { PROVIDE(__TRAPTAB_CPU3 = .); KEEP (*(.traptab_cpu3)); } > pfls3 - .traptab_tc4 (LCF_TRAPVEC4_START) : { PROVIDE(__TRAPTAB_CPU4 = .); KEEP (*(.traptab_cpu4)); } > pfls4 - .traptab_tc5 (LCF_TRAPVEC5_START) : { PROVIDE(__TRAPTAB_CPU5 = .); KEEP (*(.traptab_cpu5)); } > pfls5 - } - - /*Fixed memory Allocations for _START1 to 5*/ - CORE_ID = GLOBAL ; - SECTIONS - { - .start_tc1 (LCF_STARTPTR_NC_CPU1) : FLAGS(rxl) { KEEP (*(.start_cpu1)); } > pfls1_nc - .start_tc2 (LCF_STARTPTR_NC_CPU2) : FLAGS(rxl) { KEEP (*(.start_cpu2)); } > pfls2_nc - .start_tc3 (LCF_STARTPTR_NC_CPU3) : FLAGS(rxl) { KEEP (*(.start_cpu3)); } > pfls3_nc - .start_tc4 (LCF_STARTPTR_NC_CPU4) : FLAGS(rxl) { KEEP (*(.start_cpu4)); } > pfls4_nc - .start_tc5 (LCF_STARTPTR_NC_CPU5) : FLAGS(rxl) { KEEP (*(.start_cpu5)); } > pfls5_nc - PROVIDE(__START1 = LCF_STARTPTR_NC_CPU1); - PROVIDE(__START2 = LCF_STARTPTR_NC_CPU2); - PROVIDE(__START3 = LCF_STARTPTR_NC_CPU3); - PROVIDE(__START4 = LCF_STARTPTR_NC_CPU4); - PROVIDE(__START5 = LCF_STARTPTR_NC_CPU5); - } - - /*Fixed memory Allocations for Interrupt Vector Table*/ - SECTIONS - { - /*CPU0 Interrupt Vector Table*/ - .inttab_tc0_000 (__INTTAB_CPU0 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_0 )); } - .inttab_tc0_001 (__INTTAB_CPU0 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_1 )); } - .inttab_tc0_002 (__INTTAB_CPU0 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_2 )); } - .inttab_tc0_003 (__INTTAB_CPU0 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_3 )); } - .inttab_tc0_004 (__INTTAB_CPU0 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_4 )); } - .inttab_tc0_005 (__INTTAB_CPU0 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_5 )); } - .inttab_tc0_006 (__INTTAB_CPU0 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_6 )); } - .inttab_tc0_007 (__INTTAB_CPU0 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_7 )); } - .inttab_tc0_008 (__INTTAB_CPU0 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_8 )); } - .inttab_tc0_009 (__INTTAB_CPU0 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_9 )); } - .inttab_tc0_00A (__INTTAB_CPU0 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_10 )); } - .inttab_tc0_00B (__INTTAB_CPU0 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_11 )); } - .inttab_tc0_00C (__INTTAB_CPU0 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_12 )); } - .inttab_tc0_00D (__INTTAB_CPU0 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_13 )); } - .inttab_tc0_00E (__INTTAB_CPU0 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_14 )); } - .inttab_tc0_00F (__INTTAB_CPU0 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_15 )); } - .inttab_tc0_010 (__INTTAB_CPU0 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_16 )); } - .inttab_tc0_011 (__INTTAB_CPU0 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_17 )); } - .inttab_tc0_012 (__INTTAB_CPU0 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_18 )); } - .inttab_tc0_013 (__INTTAB_CPU0 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_19 )); } - .inttab_tc0_014 (__INTTAB_CPU0 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_20 )); } - .inttab_tc0_015 (__INTTAB_CPU0 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_21 )); } - .inttab_tc0_016 (__INTTAB_CPU0 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_22 )); } - .inttab_tc0_017 (__INTTAB_CPU0 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_23 )); } - .inttab_tc0_018 (__INTTAB_CPU0 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_24 )); } - .inttab_tc0_019 (__INTTAB_CPU0 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_25 )); } - .inttab_tc0_01A (__INTTAB_CPU0 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_26 )); } - .inttab_tc0_01B (__INTTAB_CPU0 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_27 )); } - .inttab_tc0_01C (__INTTAB_CPU0 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_28 )); } - .inttab_tc0_01D (__INTTAB_CPU0 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_29 )); } - .inttab_tc0_01E (__INTTAB_CPU0 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_30 )); } - .inttab_tc0_01F (__INTTAB_CPU0 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_31 )); } - .inttab_tc0_020 (__INTTAB_CPU0 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_32 )); } - .inttab_tc0_021 (__INTTAB_CPU0 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_33 )); } - .inttab_tc0_022 (__INTTAB_CPU0 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_34 )); } - .inttab_tc0_023 (__INTTAB_CPU0 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_35 )); } - .inttab_tc0_024 (__INTTAB_CPU0 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_36 )); } - .inttab_tc0_025 (__INTTAB_CPU0 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_37 )); } - .inttab_tc0_026 (__INTTAB_CPU0 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_38 )); } - .inttab_tc0_027 (__INTTAB_CPU0 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_39 )); } - .inttab_tc0_028 (__INTTAB_CPU0 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_40 )); } - .inttab_tc0_029 (__INTTAB_CPU0 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_41 )); } - .inttab_tc0_02A (__INTTAB_CPU0 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_42 )); } - .inttab_tc0_02B (__INTTAB_CPU0 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_43 )); } - .inttab_tc0_02C (__INTTAB_CPU0 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_44 )); } - .inttab_tc0_02D (__INTTAB_CPU0 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_45 )); } - .inttab_tc0_02E (__INTTAB_CPU0 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_46 )); } - .inttab_tc0_02F (__INTTAB_CPU0 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_47 )); } - .inttab_tc0_030 (__INTTAB_CPU0 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_48 )); } - .inttab_tc0_031 (__INTTAB_CPU0 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_49 )); } - .inttab_tc0_032 (__INTTAB_CPU0 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_50 )); } - .inttab_tc0_033 (__INTTAB_CPU0 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_51 )); } - .inttab_tc0_034 (__INTTAB_CPU0 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_52 )); } - .inttab_tc0_035 (__INTTAB_CPU0 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_53 )); } - .inttab_tc0_036 (__INTTAB_CPU0 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_54 )); } - .inttab_tc0_037 (__INTTAB_CPU0 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_55 )); } - .inttab_tc0_038 (__INTTAB_CPU0 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_56 )); } - .inttab_tc0_039 (__INTTAB_CPU0 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_57 )); } - .inttab_tc0_03A (__INTTAB_CPU0 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_58 )); } - .inttab_tc0_03B (__INTTAB_CPU0 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_59 )); } - .inttab_tc0_03C (__INTTAB_CPU0 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_60 )); } - .inttab_tc0_03D (__INTTAB_CPU0 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_61 )); } - .inttab_tc0_03E (__INTTAB_CPU0 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_62 )); } - .inttab_tc0_03F (__INTTAB_CPU0 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_63 )); } - .inttab_tc0_040 (__INTTAB_CPU0 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_64 )); } - .inttab_tc0_041 (__INTTAB_CPU0 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_65 )); } - .inttab_tc0_042 (__INTTAB_CPU0 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_66 )); } - .inttab_tc0_043 (__INTTAB_CPU0 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_67 )); } - .inttab_tc0_044 (__INTTAB_CPU0 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_68 )); } - .inttab_tc0_045 (__INTTAB_CPU0 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_69 )); } - .inttab_tc0_046 (__INTTAB_CPU0 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_70 )); } - .inttab_tc0_047 (__INTTAB_CPU0 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_71 )); } - .inttab_tc0_048 (__INTTAB_CPU0 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_72 )); } - .inttab_tc0_049 (__INTTAB_CPU0 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_73 )); } - .inttab_tc0_04A (__INTTAB_CPU0 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_74 )); } - .inttab_tc0_04B (__INTTAB_CPU0 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_75 )); } - .inttab_tc0_04C (__INTTAB_CPU0 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_76 )); } - .inttab_tc0_04D (__INTTAB_CPU0 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_77 )); } - .inttab_tc0_04E (__INTTAB_CPU0 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_78 )); } - .inttab_tc0_04F (__INTTAB_CPU0 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_79 )); } - .inttab_tc0_050 (__INTTAB_CPU0 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_80 )); } - .inttab_tc0_051 (__INTTAB_CPU0 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_81 )); } - .inttab_tc0_052 (__INTTAB_CPU0 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_82 )); } - .inttab_tc0_053 (__INTTAB_CPU0 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_83 )); } - .inttab_tc0_054 (__INTTAB_CPU0 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_84 )); } - .inttab_tc0_055 (__INTTAB_CPU0 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_85 )); } - .inttab_tc0_056 (__INTTAB_CPU0 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_86 )); } - .inttab_tc0_057 (__INTTAB_CPU0 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_87 )); } - .inttab_tc0_058 (__INTTAB_CPU0 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_88 )); } - .inttab_tc0_059 (__INTTAB_CPU0 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_89 )); } - .inttab_tc0_05A (__INTTAB_CPU0 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_90 )); } - .inttab_tc0_05B (__INTTAB_CPU0 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_91 )); } - .inttab_tc0_05C (__INTTAB_CPU0 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_92 )); } - .inttab_tc0_05D (__INTTAB_CPU0 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_93 )); } - .inttab_tc0_05E (__INTTAB_CPU0 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_94 )); } - .inttab_tc0_05F (__INTTAB_CPU0 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_95 )); } - .inttab_tc0_060 (__INTTAB_CPU0 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_96 )); } - .inttab_tc0_061 (__INTTAB_CPU0 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_97 )); } - .inttab_tc0_062 (__INTTAB_CPU0 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_98 )); } - .inttab_tc0_063 (__INTTAB_CPU0 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_99 )); } - .inttab_tc0_064 (__INTTAB_CPU0 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_100)); } - .inttab_tc0_065 (__INTTAB_CPU0 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_101)); } - .inttab_tc0_066 (__INTTAB_CPU0 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_102)); } - .inttab_tc0_067 (__INTTAB_CPU0 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_103)); } - .inttab_tc0_068 (__INTTAB_CPU0 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_104)); } - .inttab_tc0_069 (__INTTAB_CPU0 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_105)); } - .inttab_tc0_06A (__INTTAB_CPU0 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_106)); } - .inttab_tc0_06B (__INTTAB_CPU0 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_107)); } - .inttab_tc0_06C (__INTTAB_CPU0 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_108)); } - .inttab_tc0_06D (__INTTAB_CPU0 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_109)); } - .inttab_tc0_06E (__INTTAB_CPU0 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_110)); } - .inttab_tc0_06F (__INTTAB_CPU0 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_111)); } - .inttab_tc0_070 (__INTTAB_CPU0 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_112)); } - .inttab_tc0_071 (__INTTAB_CPU0 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_113)); } - .inttab_tc0_072 (__INTTAB_CPU0 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_114)); } - .inttab_tc0_073 (__INTTAB_CPU0 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_115)); } - .inttab_tc0_074 (__INTTAB_CPU0 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_116)); } - .inttab_tc0_075 (__INTTAB_CPU0 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_117)); } - .inttab_tc0_076 (__INTTAB_CPU0 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_118)); } - .inttab_tc0_077 (__INTTAB_CPU0 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_119)); } - .inttab_tc0_078 (__INTTAB_CPU0 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_120)); } - .inttab_tc0_079 (__INTTAB_CPU0 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_121)); } - .inttab_tc0_07A (__INTTAB_CPU0 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_122)); } - .inttab_tc0_07B (__INTTAB_CPU0 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_123)); } - .inttab_tc0_07C (__INTTAB_CPU0 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_124)); } - .inttab_tc0_07D (__INTTAB_CPU0 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_125)); } - .inttab_tc0_07E (__INTTAB_CPU0 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_126)); } - .inttab_tc0_07F (__INTTAB_CPU0 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_127)); } - .inttab_tc0_080 (__INTTAB_CPU0 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_128)); } - .inttab_tc0_081 (__INTTAB_CPU0 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_129)); } - .inttab_tc0_082 (__INTTAB_CPU0 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_130)); } - .inttab_tc0_083 (__INTTAB_CPU0 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_131)); } - .inttab_tc0_084 (__INTTAB_CPU0 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_132)); } - .inttab_tc0_085 (__INTTAB_CPU0 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_133)); } - .inttab_tc0_086 (__INTTAB_CPU0 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_134)); } - .inttab_tc0_087 (__INTTAB_CPU0 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_135)); } - .inttab_tc0_088 (__INTTAB_CPU0 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_136)); } - .inttab_tc0_089 (__INTTAB_CPU0 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_137)); } - .inttab_tc0_08A (__INTTAB_CPU0 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_138)); } - .inttab_tc0_08B (__INTTAB_CPU0 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_139)); } - .inttab_tc0_08C (__INTTAB_CPU0 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_140)); } - .inttab_tc0_08D (__INTTAB_CPU0 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_141)); } - .inttab_tc0_08E (__INTTAB_CPU0 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_142)); } - .inttab_tc0_08F (__INTTAB_CPU0 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_143)); } - .inttab_tc0_090 (__INTTAB_CPU0 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_144)); } - .inttab_tc0_091 (__INTTAB_CPU0 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_145)); } - .inttab_tc0_092 (__INTTAB_CPU0 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_146)); } - .inttab_tc0_093 (__INTTAB_CPU0 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_147)); } - .inttab_tc0_094 (__INTTAB_CPU0 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_148)); } - .inttab_tc0_095 (__INTTAB_CPU0 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_149)); } - .inttab_tc0_096 (__INTTAB_CPU0 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_150)); } - .inttab_tc0_097 (__INTTAB_CPU0 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_151)); } - .inttab_tc0_098 (__INTTAB_CPU0 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_152)); } - .inttab_tc0_099 (__INTTAB_CPU0 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_153)); } - .inttab_tc0_09A (__INTTAB_CPU0 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_154)); } - .inttab_tc0_09B (__INTTAB_CPU0 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_155)); } - .inttab_tc0_09C (__INTTAB_CPU0 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_156)); } - .inttab_tc0_09D (__INTTAB_CPU0 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_157)); } - .inttab_tc0_09E (__INTTAB_CPU0 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_158)); } - .inttab_tc0_09F (__INTTAB_CPU0 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_159)); } - .inttab_tc0_0A0 (__INTTAB_CPU0 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_160)); } - .inttab_tc0_0A1 (__INTTAB_CPU0 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_161)); } - .inttab_tc0_0A2 (__INTTAB_CPU0 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_162)); } - .inttab_tc0_0A3 (__INTTAB_CPU0 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_163)); } - .inttab_tc0_0A4 (__INTTAB_CPU0 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_164)); } - .inttab_tc0_0A5 (__INTTAB_CPU0 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_165)); } - .inttab_tc0_0A6 (__INTTAB_CPU0 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_166)); } - .inttab_tc0_0A7 (__INTTAB_CPU0 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_167)); } - .inttab_tc0_0A8 (__INTTAB_CPU0 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_168)); } - .inttab_tc0_0A9 (__INTTAB_CPU0 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_169)); } - .inttab_tc0_0AA (__INTTAB_CPU0 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_170)); } - .inttab_tc0_0AB (__INTTAB_CPU0 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_171)); } - .inttab_tc0_0AC (__INTTAB_CPU0 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_172)); } - .inttab_tc0_0AD (__INTTAB_CPU0 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_173)); } - .inttab_tc0_0AE (__INTTAB_CPU0 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_174)); } - .inttab_tc0_0AF (__INTTAB_CPU0 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_175)); } - .inttab_tc0_0B0 (__INTTAB_CPU0 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_176)); } - .inttab_tc0_0B1 (__INTTAB_CPU0 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_177)); } - .inttab_tc0_0B2 (__INTTAB_CPU0 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_178)); } - .inttab_tc0_0B3 (__INTTAB_CPU0 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_179)); } - .inttab_tc0_0B4 (__INTTAB_CPU0 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_180)); } - .inttab_tc0_0B5 (__INTTAB_CPU0 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_181)); } - .inttab_tc0_0B6 (__INTTAB_CPU0 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_182)); } - .inttab_tc0_0B7 (__INTTAB_CPU0 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_183)); } - .inttab_tc0_0B8 (__INTTAB_CPU0 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_184)); } - .inttab_tc0_0B9 (__INTTAB_CPU0 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_185)); } - .inttab_tc0_0BA (__INTTAB_CPU0 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_186)); } - .inttab_tc0_0BB (__INTTAB_CPU0 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_187)); } - .inttab_tc0_0BC (__INTTAB_CPU0 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_188)); } - .inttab_tc0_0BD (__INTTAB_CPU0 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_189)); } - .inttab_tc0_0BE (__INTTAB_CPU0 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_190)); } - .inttab_tc0_0BF (__INTTAB_CPU0 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_191)); } - .inttab_tc0_0C0 (__INTTAB_CPU0 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_192)); } - .inttab_tc0_0C1 (__INTTAB_CPU0 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_193)); } - .inttab_tc0_0C2 (__INTTAB_CPU0 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_194)); } - .inttab_tc0_0C3 (__INTTAB_CPU0 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_195)); } - .inttab_tc0_0C4 (__INTTAB_CPU0 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_196)); } - .inttab_tc0_0C5 (__INTTAB_CPU0 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_197)); } - .inttab_tc0_0C6 (__INTTAB_CPU0 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_198)); } - .inttab_tc0_0C7 (__INTTAB_CPU0 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_199)); } - .inttab_tc0_0C8 (__INTTAB_CPU0 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_200)); } - .inttab_tc0_0C9 (__INTTAB_CPU0 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_201)); } - .inttab_tc0_0CA (__INTTAB_CPU0 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_202)); } - .inttab_tc0_0CB (__INTTAB_CPU0 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_203)); } - .inttab_tc0_0CC (__INTTAB_CPU0 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_204)); } - .inttab_tc0_0CD (__INTTAB_CPU0 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_205)); } - .inttab_tc0_0CE (__INTTAB_CPU0 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_206)); } - .inttab_tc0_0CF (__INTTAB_CPU0 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_207)); } - .inttab_tc0_0D0 (__INTTAB_CPU0 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_208)); } - .inttab_tc0_0D1 (__INTTAB_CPU0 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_209)); } - .inttab_tc0_0D2 (__INTTAB_CPU0 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_210)); } - .inttab_tc0_0D3 (__INTTAB_CPU0 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_211)); } - .inttab_tc0_0D4 (__INTTAB_CPU0 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_212)); } - .inttab_tc0_0D5 (__INTTAB_CPU0 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_213)); } - .inttab_tc0_0D6 (__INTTAB_CPU0 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_214)); } - .inttab_tc0_0D7 (__INTTAB_CPU0 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_215)); } - .inttab_tc0_0D8 (__INTTAB_CPU0 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_216)); } - .inttab_tc0_0D9 (__INTTAB_CPU0 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_217)); } - .inttab_tc0_0DA (__INTTAB_CPU0 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_218)); } - .inttab_tc0_0DB (__INTTAB_CPU0 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_219)); } - .inttab_tc0_0DC (__INTTAB_CPU0 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_220)); } - .inttab_tc0_0DD (__INTTAB_CPU0 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_221)); } - .inttab_tc0_0DE (__INTTAB_CPU0 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_222)); } - .inttab_tc0_0DF (__INTTAB_CPU0 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_223)); } - .inttab_tc0_0E0 (__INTTAB_CPU0 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_224)); } - .inttab_tc0_0E1 (__INTTAB_CPU0 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_225)); } - .inttab_tc0_0E2 (__INTTAB_CPU0 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_226)); } - .inttab_tc0_0E3 (__INTTAB_CPU0 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_227)); } - .inttab_tc0_0E4 (__INTTAB_CPU0 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_228)); } - .inttab_tc0_0E5 (__INTTAB_CPU0 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_229)); } - .inttab_tc0_0E6 (__INTTAB_CPU0 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_230)); } - .inttab_tc0_0E7 (__INTTAB_CPU0 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_231)); } - .inttab_tc0_0E8 (__INTTAB_CPU0 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_232)); } - .inttab_tc0_0E9 (__INTTAB_CPU0 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_233)); } - .inttab_tc0_0EA (__INTTAB_CPU0 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_234)); } - .inttab_tc0_0EB (__INTTAB_CPU0 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_235)); } - .inttab_tc0_0EC (__INTTAB_CPU0 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_236)); } - .inttab_tc0_0ED (__INTTAB_CPU0 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_237)); } - .inttab_tc0_0EE (__INTTAB_CPU0 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_238)); } - .inttab_tc0_0EF (__INTTAB_CPU0 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_239)); } - .inttab_tc0_0F0 (__INTTAB_CPU0 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_240)); } - .inttab_tc0_0F1 (__INTTAB_CPU0 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_241)); } - .inttab_tc0_0F2 (__INTTAB_CPU0 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_242)); } - .inttab_tc0_0F3 (__INTTAB_CPU0 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_243)); } - .inttab_tc0_0F4 (__INTTAB_CPU0 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_244)); } - .inttab_tc0_0F5 (__INTTAB_CPU0 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_245)); } - .inttab_tc0_0F6 (__INTTAB_CPU0 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_246)); } - .inttab_tc0_0F7 (__INTTAB_CPU0 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_247)); } - .inttab_tc0_0F8 (__INTTAB_CPU0 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_248)); } - .inttab_tc0_0F9 (__INTTAB_CPU0 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_249)); } - .inttab_tc0_0FA (__INTTAB_CPU0 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_250)); } - .inttab_tc0_0FB (__INTTAB_CPU0 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_251)); } - .inttab_tc0_0FC (__INTTAB_CPU0 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_252)); } - .inttab_tc0_0FD (__INTTAB_CPU0 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_253)); } - .inttab_tc0_0FE (__INTTAB_CPU0 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_254)); } - .inttab_tc0_0FF (__INTTAB_CPU0 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_255)); } - } - SECTIONS - { - /*CPU1 Interrupt Vector Table*/ - .inttab_tc1_000 (__INTTAB_CPU1 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_0 )); } - .inttab_tc1_001 (__INTTAB_CPU1 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_1 )); } - .inttab_tc1_002 (__INTTAB_CPU1 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_2 )); } - .inttab_tc1_003 (__INTTAB_CPU1 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_3 )); } - .inttab_tc1_004 (__INTTAB_CPU1 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_4 )); } - .inttab_tc1_005 (__INTTAB_CPU1 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_5 )); } - .inttab_tc1_006 (__INTTAB_CPU1 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_6 )); } - .inttab_tc1_007 (__INTTAB_CPU1 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_7 )); } - .inttab_tc1_008 (__INTTAB_CPU1 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_8 )); } - .inttab_tc1_009 (__INTTAB_CPU1 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_9 )); } - .inttab_tc1_00A (__INTTAB_CPU1 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_10 )); } - .inttab_tc1_00B (__INTTAB_CPU1 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_11 )); } - .inttab_tc1_00C (__INTTAB_CPU1 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_12 )); } - .inttab_tc1_00D (__INTTAB_CPU1 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_13 )); } - .inttab_tc1_00E (__INTTAB_CPU1 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_14 )); } - .inttab_tc1_00F (__INTTAB_CPU1 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_15 )); } - .inttab_tc1_010 (__INTTAB_CPU1 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_16 )); } - .inttab_tc1_011 (__INTTAB_CPU1 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_17 )); } - .inttab_tc1_012 (__INTTAB_CPU1 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_18 )); } - .inttab_tc1_013 (__INTTAB_CPU1 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_19 )); } - .inttab_tc1_014 (__INTTAB_CPU1 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_20 )); } - .inttab_tc1_015 (__INTTAB_CPU1 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_21 )); } - .inttab_tc1_016 (__INTTAB_CPU1 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_22 )); } - .inttab_tc1_017 (__INTTAB_CPU1 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_23 )); } - .inttab_tc1_018 (__INTTAB_CPU1 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_24 )); } - .inttab_tc1_019 (__INTTAB_CPU1 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_25 )); } - .inttab_tc1_01A (__INTTAB_CPU1 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_26 )); } - .inttab_tc1_01B (__INTTAB_CPU1 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_27 )); } - .inttab_tc1_01C (__INTTAB_CPU1 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_28 )); } - .inttab_tc1_01D (__INTTAB_CPU1 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_29 )); } - .inttab_tc1_01E (__INTTAB_CPU1 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_30 )); } - .inttab_tc1_01F (__INTTAB_CPU1 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_31 )); } - .inttab_tc1_020 (__INTTAB_CPU1 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_32 )); } - .inttab_tc1_021 (__INTTAB_CPU1 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_33 )); } - .inttab_tc1_022 (__INTTAB_CPU1 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_34 )); } - .inttab_tc1_023 (__INTTAB_CPU1 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_35 )); } - .inttab_tc1_024 (__INTTAB_CPU1 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_36 )); } - .inttab_tc1_025 (__INTTAB_CPU1 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_37 )); } - .inttab_tc1_026 (__INTTAB_CPU1 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_38 )); } - .inttab_tc1_027 (__INTTAB_CPU1 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_39 )); } - .inttab_tc1_028 (__INTTAB_CPU1 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_40 )); } - .inttab_tc1_029 (__INTTAB_CPU1 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_41 )); } - .inttab_tc1_02A (__INTTAB_CPU1 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_42 )); } - .inttab_tc1_02B (__INTTAB_CPU1 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_43 )); } - .inttab_tc1_02C (__INTTAB_CPU1 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_44 )); } - .inttab_tc1_02D (__INTTAB_CPU1 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_45 )); } - .inttab_tc1_02E (__INTTAB_CPU1 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_46 )); } - .inttab_tc1_02F (__INTTAB_CPU1 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_47 )); } - .inttab_tc1_030 (__INTTAB_CPU1 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_48 )); } - .inttab_tc1_031 (__INTTAB_CPU1 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_49 )); } - .inttab_tc1_032 (__INTTAB_CPU1 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_50 )); } - .inttab_tc1_033 (__INTTAB_CPU1 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_51 )); } - .inttab_tc1_034 (__INTTAB_CPU1 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_52 )); } - .inttab_tc1_035 (__INTTAB_CPU1 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_53 )); } - .inttab_tc1_036 (__INTTAB_CPU1 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_54 )); } - .inttab_tc1_037 (__INTTAB_CPU1 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_55 )); } - .inttab_tc1_038 (__INTTAB_CPU1 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_56 )); } - .inttab_tc1_039 (__INTTAB_CPU1 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_57 )); } - .inttab_tc1_03A (__INTTAB_CPU1 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_58 )); } - .inttab_tc1_03B (__INTTAB_CPU1 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_59 )); } - .inttab_tc1_03C (__INTTAB_CPU1 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_60 )); } - .inttab_tc1_03D (__INTTAB_CPU1 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_61 )); } - .inttab_tc1_03E (__INTTAB_CPU1 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_62 )); } - .inttab_tc1_03F (__INTTAB_CPU1 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_63 )); } - .inttab_tc1_040 (__INTTAB_CPU1 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_64 )); } - .inttab_tc1_041 (__INTTAB_CPU1 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_65 )); } - .inttab_tc1_042 (__INTTAB_CPU1 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_66 )); } - .inttab_tc1_043 (__INTTAB_CPU1 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_67 )); } - .inttab_tc1_044 (__INTTAB_CPU1 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_68 )); } - .inttab_tc1_045 (__INTTAB_CPU1 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_69 )); } - .inttab_tc1_046 (__INTTAB_CPU1 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_70 )); } - .inttab_tc1_047 (__INTTAB_CPU1 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_71 )); } - .inttab_tc1_048 (__INTTAB_CPU1 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_72 )); } - .inttab_tc1_049 (__INTTAB_CPU1 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_73 )); } - .inttab_tc1_04A (__INTTAB_CPU1 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_74 )); } - .inttab_tc1_04B (__INTTAB_CPU1 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_75 )); } - .inttab_tc1_04C (__INTTAB_CPU1 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_76 )); } - .inttab_tc1_04D (__INTTAB_CPU1 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_77 )); } - .inttab_tc1_04E (__INTTAB_CPU1 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_78 )); } - .inttab_tc1_04F (__INTTAB_CPU1 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_79 )); } - .inttab_tc1_050 (__INTTAB_CPU1 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_80 )); } - .inttab_tc1_051 (__INTTAB_CPU1 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_81 )); } - .inttab_tc1_052 (__INTTAB_CPU1 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_82 )); } - .inttab_tc1_053 (__INTTAB_CPU1 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_83 )); } - .inttab_tc1_054 (__INTTAB_CPU1 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_84 )); } - .inttab_tc1_055 (__INTTAB_CPU1 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_85 )); } - .inttab_tc1_056 (__INTTAB_CPU1 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_86 )); } - .inttab_tc1_057 (__INTTAB_CPU1 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_87 )); } - .inttab_tc1_058 (__INTTAB_CPU1 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_88 )); } - .inttab_tc1_059 (__INTTAB_CPU1 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_89 )); } - .inttab_tc1_05A (__INTTAB_CPU1 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_90 )); } - .inttab_tc1_05B (__INTTAB_CPU1 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_91 )); } - .inttab_tc1_05C (__INTTAB_CPU1 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_92 )); } - .inttab_tc1_05D (__INTTAB_CPU1 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_93 )); } - .inttab_tc1_05E (__INTTAB_CPU1 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_94 )); } - .inttab_tc1_05F (__INTTAB_CPU1 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_95 )); } - .inttab_tc1_060 (__INTTAB_CPU1 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_96 )); } - .inttab_tc1_061 (__INTTAB_CPU1 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_97 )); } - .inttab_tc1_062 (__INTTAB_CPU1 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_98 )); } - .inttab_tc1_063 (__INTTAB_CPU1 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_99 )); } - .inttab_tc1_064 (__INTTAB_CPU1 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_100)); } - .inttab_tc1_065 (__INTTAB_CPU1 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_101)); } - .inttab_tc1_066 (__INTTAB_CPU1 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_102)); } - .inttab_tc1_067 (__INTTAB_CPU1 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_103)); } - .inttab_tc1_068 (__INTTAB_CPU1 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_104)); } - .inttab_tc1_069 (__INTTAB_CPU1 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_105)); } - .inttab_tc1_06A (__INTTAB_CPU1 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_106)); } - .inttab_tc1_06B (__INTTAB_CPU1 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_107)); } - .inttab_tc1_06C (__INTTAB_CPU1 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_108)); } - .inttab_tc1_06D (__INTTAB_CPU1 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_109)); } - .inttab_tc1_06E (__INTTAB_CPU1 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_110)); } - .inttab_tc1_06F (__INTTAB_CPU1 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_111)); } - .inttab_tc1_070 (__INTTAB_CPU1 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_112)); } - .inttab_tc1_071 (__INTTAB_CPU1 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_113)); } - .inttab_tc1_072 (__INTTAB_CPU1 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_114)); } - .inttab_tc1_073 (__INTTAB_CPU1 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_115)); } - .inttab_tc1_074 (__INTTAB_CPU1 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_116)); } - .inttab_tc1_075 (__INTTAB_CPU1 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_117)); } - .inttab_tc1_076 (__INTTAB_CPU1 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_118)); } - .inttab_tc1_077 (__INTTAB_CPU1 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_119)); } - .inttab_tc1_078 (__INTTAB_CPU1 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_120)); } - .inttab_tc1_079 (__INTTAB_CPU1 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_121)); } - .inttab_tc1_07A (__INTTAB_CPU1 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_122)); } - .inttab_tc1_07B (__INTTAB_CPU1 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_123)); } - .inttab_tc1_07C (__INTTAB_CPU1 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_124)); } - .inttab_tc1_07D (__INTTAB_CPU1 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_125)); } - .inttab_tc1_07E (__INTTAB_CPU1 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_126)); } - .inttab_tc1_07F (__INTTAB_CPU1 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_127)); } - .inttab_tc1_080 (__INTTAB_CPU1 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_128)); } - .inttab_tc1_081 (__INTTAB_CPU1 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_129)); } - .inttab_tc1_082 (__INTTAB_CPU1 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_130)); } - .inttab_tc1_083 (__INTTAB_CPU1 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_131)); } - .inttab_tc1_084 (__INTTAB_CPU1 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_132)); } - .inttab_tc1_085 (__INTTAB_CPU1 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_133)); } - .inttab_tc1_086 (__INTTAB_CPU1 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_134)); } - .inttab_tc1_087 (__INTTAB_CPU1 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_135)); } - .inttab_tc1_088 (__INTTAB_CPU1 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_136)); } - .inttab_tc1_089 (__INTTAB_CPU1 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_137)); } - .inttab_tc1_08A (__INTTAB_CPU1 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_138)); } - .inttab_tc1_08B (__INTTAB_CPU1 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_139)); } - .inttab_tc1_08C (__INTTAB_CPU1 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_140)); } - .inttab_tc1_08D (__INTTAB_CPU1 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_141)); } - .inttab_tc1_08E (__INTTAB_CPU1 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_142)); } - .inttab_tc1_08F (__INTTAB_CPU1 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_143)); } - .inttab_tc1_090 (__INTTAB_CPU1 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_144)); } - .inttab_tc1_091 (__INTTAB_CPU1 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_145)); } - .inttab_tc1_092 (__INTTAB_CPU1 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_146)); } - .inttab_tc1_093 (__INTTAB_CPU1 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_147)); } - .inttab_tc1_094 (__INTTAB_CPU1 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_148)); } - .inttab_tc1_095 (__INTTAB_CPU1 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_149)); } - .inttab_tc1_096 (__INTTAB_CPU1 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_150)); } - .inttab_tc1_097 (__INTTAB_CPU1 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_151)); } - .inttab_tc1_098 (__INTTAB_CPU1 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_152)); } - .inttab_tc1_099 (__INTTAB_CPU1 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_153)); } - .inttab_tc1_09A (__INTTAB_CPU1 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_154)); } - .inttab_tc1_09B (__INTTAB_CPU1 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_155)); } - .inttab_tc1_09C (__INTTAB_CPU1 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_156)); } - .inttab_tc1_09D (__INTTAB_CPU1 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_157)); } - .inttab_tc1_09E (__INTTAB_CPU1 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_158)); } - .inttab_tc1_09F (__INTTAB_CPU1 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_159)); } - .inttab_tc1_0A0 (__INTTAB_CPU1 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_160)); } - .inttab_tc1_0A1 (__INTTAB_CPU1 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_161)); } - .inttab_tc1_0A2 (__INTTAB_CPU1 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_162)); } - .inttab_tc1_0A3 (__INTTAB_CPU1 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_163)); } - .inttab_tc1_0A4 (__INTTAB_CPU1 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_164)); } - .inttab_tc1_0A5 (__INTTAB_CPU1 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_165)); } - .inttab_tc1_0A6 (__INTTAB_CPU1 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_166)); } - .inttab_tc1_0A7 (__INTTAB_CPU1 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_167)); } - .inttab_tc1_0A8 (__INTTAB_CPU1 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_168)); } - .inttab_tc1_0A9 (__INTTAB_CPU1 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_169)); } - .inttab_tc1_0AA (__INTTAB_CPU1 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_170)); } - .inttab_tc1_0AB (__INTTAB_CPU1 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_171)); } - .inttab_tc1_0AC (__INTTAB_CPU1 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_172)); } - .inttab_tc1_0AD (__INTTAB_CPU1 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_173)); } - .inttab_tc1_0AE (__INTTAB_CPU1 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_174)); } - .inttab_tc1_0AF (__INTTAB_CPU1 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_175)); } - .inttab_tc1_0B0 (__INTTAB_CPU1 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_176)); } - .inttab_tc1_0B1 (__INTTAB_CPU1 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_177)); } - .inttab_tc1_0B2 (__INTTAB_CPU1 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_178)); } - .inttab_tc1_0B3 (__INTTAB_CPU1 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_179)); } - .inttab_tc1_0B4 (__INTTAB_CPU1 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_180)); } - .inttab_tc1_0B5 (__INTTAB_CPU1 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_181)); } - .inttab_tc1_0B6 (__INTTAB_CPU1 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_182)); } - .inttab_tc1_0B7 (__INTTAB_CPU1 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_183)); } - .inttab_tc1_0B8 (__INTTAB_CPU1 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_184)); } - .inttab_tc1_0B9 (__INTTAB_CPU1 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_185)); } - .inttab_tc1_0BA (__INTTAB_CPU1 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_186)); } - .inttab_tc1_0BB (__INTTAB_CPU1 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_187)); } - .inttab_tc1_0BC (__INTTAB_CPU1 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_188)); } - .inttab_tc1_0BD (__INTTAB_CPU1 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_189)); } - .inttab_tc1_0BE (__INTTAB_CPU1 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_190)); } - .inttab_tc1_0BF (__INTTAB_CPU1 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_191)); } - .inttab_tc1_0C0 (__INTTAB_CPU1 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_192)); } - .inttab_tc1_0C1 (__INTTAB_CPU1 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_193)); } - .inttab_tc1_0C2 (__INTTAB_CPU1 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_194)); } - .inttab_tc1_0C3 (__INTTAB_CPU1 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_195)); } - .inttab_tc1_0C4 (__INTTAB_CPU1 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_196)); } - .inttab_tc1_0C5 (__INTTAB_CPU1 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_197)); } - .inttab_tc1_0C6 (__INTTAB_CPU1 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_198)); } - .inttab_tc1_0C7 (__INTTAB_CPU1 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_199)); } - .inttab_tc1_0C8 (__INTTAB_CPU1 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_200)); } - .inttab_tc1_0C9 (__INTTAB_CPU1 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_201)); } - .inttab_tc1_0CA (__INTTAB_CPU1 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_202)); } - .inttab_tc1_0CB (__INTTAB_CPU1 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_203)); } - .inttab_tc1_0CC (__INTTAB_CPU1 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_204)); } - .inttab_tc1_0CD (__INTTAB_CPU1 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_205)); } - .inttab_tc1_0CE (__INTTAB_CPU1 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_206)); } - .inttab_tc1_0CF (__INTTAB_CPU1 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_207)); } - .inttab_tc1_0D0 (__INTTAB_CPU1 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_208)); } - .inttab_tc1_0D1 (__INTTAB_CPU1 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_209)); } - .inttab_tc1_0D2 (__INTTAB_CPU1 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_210)); } - .inttab_tc1_0D3 (__INTTAB_CPU1 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_211)); } - .inttab_tc1_0D4 (__INTTAB_CPU1 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_212)); } - .inttab_tc1_0D5 (__INTTAB_CPU1 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_213)); } - .inttab_tc1_0D6 (__INTTAB_CPU1 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_214)); } - .inttab_tc1_0D7 (__INTTAB_CPU1 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_215)); } - .inttab_tc1_0D8 (__INTTAB_CPU1 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_216)); } - .inttab_tc1_0D9 (__INTTAB_CPU1 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_217)); } - .inttab_tc1_0DA (__INTTAB_CPU1 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_218)); } - .inttab_tc1_0DB (__INTTAB_CPU1 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_219)); } - .inttab_tc1_0DC (__INTTAB_CPU1 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_220)); } - .inttab_tc1_0DD (__INTTAB_CPU1 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_221)); } - .inttab_tc1_0DE (__INTTAB_CPU1 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_222)); } - .inttab_tc1_0DF (__INTTAB_CPU1 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_223)); } - .inttab_tc1_0E0 (__INTTAB_CPU1 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_224)); } - .inttab_tc1_0E1 (__INTTAB_CPU1 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_225)); } - .inttab_tc1_0E2 (__INTTAB_CPU1 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_226)); } - .inttab_tc1_0E3 (__INTTAB_CPU1 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_227)); } - .inttab_tc1_0E4 (__INTTAB_CPU1 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_228)); } - .inttab_tc1_0E5 (__INTTAB_CPU1 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_229)); } - .inttab_tc1_0E6 (__INTTAB_CPU1 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_230)); } - .inttab_tc1_0E7 (__INTTAB_CPU1 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_231)); } - .inttab_tc1_0E8 (__INTTAB_CPU1 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_232)); } - .inttab_tc1_0E9 (__INTTAB_CPU1 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_233)); } - .inttab_tc1_0EA (__INTTAB_CPU1 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_234)); } - .inttab_tc1_0EB (__INTTAB_CPU1 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_235)); } - .inttab_tc1_0EC (__INTTAB_CPU1 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_236)); } - .inttab_tc1_0ED (__INTTAB_CPU1 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_237)); } - .inttab_tc1_0EE (__INTTAB_CPU1 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_238)); } - .inttab_tc1_0EF (__INTTAB_CPU1 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_239)); } - .inttab_tc1_0F0 (__INTTAB_CPU1 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_240)); } - .inttab_tc1_0F1 (__INTTAB_CPU1 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_241)); } - .inttab_tc1_0F2 (__INTTAB_CPU1 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_242)); } - .inttab_tc1_0F3 (__INTTAB_CPU1 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_243)); } - .inttab_tc1_0F4 (__INTTAB_CPU1 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_244)); } - .inttab_tc1_0F5 (__INTTAB_CPU1 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_245)); } - .inttab_tc1_0F6 (__INTTAB_CPU1 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_246)); } - .inttab_tc1_0F7 (__INTTAB_CPU1 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_247)); } - .inttab_tc1_0F8 (__INTTAB_CPU1 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_248)); } - .inttab_tc1_0F9 (__INTTAB_CPU1 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_249)); } - .inttab_tc1_0FA (__INTTAB_CPU1 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_250)); } - .inttab_tc1_0FB (__INTTAB_CPU1 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_251)); } - .inttab_tc1_0FC (__INTTAB_CPU1 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_252)); } - .inttab_tc1_0FD (__INTTAB_CPU1 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_253)); } - .inttab_tc1_0FE (__INTTAB_CPU1 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_254)); } - .inttab_tc1_0FF (__INTTAB_CPU1 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_255)); } - } - SECTIONS - { - /*CPU2 Interrupt Vector Table*/ - .inttab_tc2_000 (__INTTAB_CPU2 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_0 )); } - .inttab_tc2_001 (__INTTAB_CPU2 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_1 )); } - .inttab_tc2_002 (__INTTAB_CPU2 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_2 )); } - .inttab_tc2_003 (__INTTAB_CPU2 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_3 )); } - .inttab_tc2_004 (__INTTAB_CPU2 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_4 )); } - .inttab_tc2_005 (__INTTAB_CPU2 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_5 )); } - .inttab_tc2_006 (__INTTAB_CPU2 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_6 )); } - .inttab_tc2_007 (__INTTAB_CPU2 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_7 )); } - .inttab_tc2_008 (__INTTAB_CPU2 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_8 )); } - .inttab_tc2_009 (__INTTAB_CPU2 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_9 )); } - .inttab_tc2_00A (__INTTAB_CPU2 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_10 )); } - .inttab_tc2_00B (__INTTAB_CPU2 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_11 )); } - .inttab_tc2_00C (__INTTAB_CPU2 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_12 )); } - .inttab_tc2_00D (__INTTAB_CPU2 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_13 )); } - .inttab_tc2_00E (__INTTAB_CPU2 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_14 )); } - .inttab_tc2_00F (__INTTAB_CPU2 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_15 )); } - .inttab_tc2_010 (__INTTAB_CPU2 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_16 )); } - .inttab_tc2_011 (__INTTAB_CPU2 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_17 )); } - .inttab_tc2_012 (__INTTAB_CPU2 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_18 )); } - .inttab_tc2_013 (__INTTAB_CPU2 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_19 )); } - .inttab_tc2_014 (__INTTAB_CPU2 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_20 )); } - .inttab_tc2_015 (__INTTAB_CPU2 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_21 )); } - .inttab_tc2_016 (__INTTAB_CPU2 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_22 )); } - .inttab_tc2_017 (__INTTAB_CPU2 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_23 )); } - .inttab_tc2_018 (__INTTAB_CPU2 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_24 )); } - .inttab_tc2_019 (__INTTAB_CPU2 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_25 )); } - .inttab_tc2_01A (__INTTAB_CPU2 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_26 )); } - .inttab_tc2_01B (__INTTAB_CPU2 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_27 )); } - .inttab_tc2_01C (__INTTAB_CPU2 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_28 )); } - .inttab_tc2_01D (__INTTAB_CPU2 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_29 )); } - .inttab_tc2_01E (__INTTAB_CPU2 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_30 )); } - .inttab_tc2_01F (__INTTAB_CPU2 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_31 )); } - .inttab_tc2_020 (__INTTAB_CPU2 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_32 )); } - .inttab_tc2_021 (__INTTAB_CPU2 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_33 )); } - .inttab_tc2_022 (__INTTAB_CPU2 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_34 )); } - .inttab_tc2_023 (__INTTAB_CPU2 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_35 )); } - .inttab_tc2_024 (__INTTAB_CPU2 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_36 )); } - .inttab_tc2_025 (__INTTAB_CPU2 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_37 )); } - .inttab_tc2_026 (__INTTAB_CPU2 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_38 )); } - .inttab_tc2_027 (__INTTAB_CPU2 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_39 )); } - .inttab_tc2_028 (__INTTAB_CPU2 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_40 )); } - .inttab_tc2_029 (__INTTAB_CPU2 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_41 )); } - .inttab_tc2_02A (__INTTAB_CPU2 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_42 )); } - .inttab_tc2_02B (__INTTAB_CPU2 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_43 )); } - .inttab_tc2_02C (__INTTAB_CPU2 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_44 )); } - .inttab_tc2_02D (__INTTAB_CPU2 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_45 )); } - .inttab_tc2_02E (__INTTAB_CPU2 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_46 )); } - .inttab_tc2_02F (__INTTAB_CPU2 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_47 )); } - .inttab_tc2_030 (__INTTAB_CPU2 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_48 )); } - .inttab_tc2_031 (__INTTAB_CPU2 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_49 )); } - .inttab_tc2_032 (__INTTAB_CPU2 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_50 )); } - .inttab_tc2_033 (__INTTAB_CPU2 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_51 )); } - .inttab_tc2_034 (__INTTAB_CPU2 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_52 )); } - .inttab_tc2_035 (__INTTAB_CPU2 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_53 )); } - .inttab_tc2_036 (__INTTAB_CPU2 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_54 )); } - .inttab_tc2_037 (__INTTAB_CPU2 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_55 )); } - .inttab_tc2_038 (__INTTAB_CPU2 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_56 )); } - .inttab_tc2_039 (__INTTAB_CPU2 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_57 )); } - .inttab_tc2_03A (__INTTAB_CPU2 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_58 )); } - .inttab_tc2_03B (__INTTAB_CPU2 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_59 )); } - .inttab_tc2_03C (__INTTAB_CPU2 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_60 )); } - .inttab_tc2_03D (__INTTAB_CPU2 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_61 )); } - .inttab_tc2_03E (__INTTAB_CPU2 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_62 )); } - .inttab_tc2_03F (__INTTAB_CPU2 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_63 )); } - .inttab_tc2_040 (__INTTAB_CPU2 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_64 )); } - .inttab_tc2_041 (__INTTAB_CPU2 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_65 )); } - .inttab_tc2_042 (__INTTAB_CPU2 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_66 )); } - .inttab_tc2_043 (__INTTAB_CPU2 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_67 )); } - .inttab_tc2_044 (__INTTAB_CPU2 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_68 )); } - .inttab_tc2_045 (__INTTAB_CPU2 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_69 )); } - .inttab_tc2_046 (__INTTAB_CPU2 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_70 )); } - .inttab_tc2_047 (__INTTAB_CPU2 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_71 )); } - .inttab_tc2_048 (__INTTAB_CPU2 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_72 )); } - .inttab_tc2_049 (__INTTAB_CPU2 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_73 )); } - .inttab_tc2_04A (__INTTAB_CPU2 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_74 )); } - .inttab_tc2_04B (__INTTAB_CPU2 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_75 )); } - .inttab_tc2_04C (__INTTAB_CPU2 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_76 )); } - .inttab_tc2_04D (__INTTAB_CPU2 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_77 )); } - .inttab_tc2_04E (__INTTAB_CPU2 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_78 )); } - .inttab_tc2_04F (__INTTAB_CPU2 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_79 )); } - .inttab_tc2_050 (__INTTAB_CPU2 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_80 )); } - .inttab_tc2_051 (__INTTAB_CPU2 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_81 )); } - .inttab_tc2_052 (__INTTAB_CPU2 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_82 )); } - .inttab_tc2_053 (__INTTAB_CPU2 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_83 )); } - .inttab_tc2_054 (__INTTAB_CPU2 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_84 )); } - .inttab_tc2_055 (__INTTAB_CPU2 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_85 )); } - .inttab_tc2_056 (__INTTAB_CPU2 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_86 )); } - .inttab_tc2_057 (__INTTAB_CPU2 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_87 )); } - .inttab_tc2_058 (__INTTAB_CPU2 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_88 )); } - .inttab_tc2_059 (__INTTAB_CPU2 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_89 )); } - .inttab_tc2_05A (__INTTAB_CPU2 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_90 )); } - .inttab_tc2_05B (__INTTAB_CPU2 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_91 )); } - .inttab_tc2_05C (__INTTAB_CPU2 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_92 )); } - .inttab_tc2_05D (__INTTAB_CPU2 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_93 )); } - .inttab_tc2_05E (__INTTAB_CPU2 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_94 )); } - .inttab_tc2_05F (__INTTAB_CPU2 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_95 )); } - .inttab_tc2_060 (__INTTAB_CPU2 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_96 )); } - .inttab_tc2_061 (__INTTAB_CPU2 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_97 )); } - .inttab_tc2_062 (__INTTAB_CPU2 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_98 )); } - .inttab_tc2_063 (__INTTAB_CPU2 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_99 )); } - .inttab_tc2_064 (__INTTAB_CPU2 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_100)); } - .inttab_tc2_065 (__INTTAB_CPU2 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_101)); } - .inttab_tc2_066 (__INTTAB_CPU2 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_102)); } - .inttab_tc2_067 (__INTTAB_CPU2 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_103)); } - .inttab_tc2_068 (__INTTAB_CPU2 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_104)); } - .inttab_tc2_069 (__INTTAB_CPU2 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_105)); } - .inttab_tc2_06A (__INTTAB_CPU2 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_106)); } - .inttab_tc2_06B (__INTTAB_CPU2 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_107)); } - .inttab_tc2_06C (__INTTAB_CPU2 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_108)); } - .inttab_tc2_06D (__INTTAB_CPU2 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_109)); } - .inttab_tc2_06E (__INTTAB_CPU2 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_110)); } - .inttab_tc2_06F (__INTTAB_CPU2 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_111)); } - .inttab_tc2_070 (__INTTAB_CPU2 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_112)); } - .inttab_tc2_071 (__INTTAB_CPU2 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_113)); } - .inttab_tc2_072 (__INTTAB_CPU2 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_114)); } - .inttab_tc2_073 (__INTTAB_CPU2 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_115)); } - .inttab_tc2_074 (__INTTAB_CPU2 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_116)); } - .inttab_tc2_075 (__INTTAB_CPU2 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_117)); } - .inttab_tc2_076 (__INTTAB_CPU2 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_118)); } - .inttab_tc2_077 (__INTTAB_CPU2 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_119)); } - .inttab_tc2_078 (__INTTAB_CPU2 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_120)); } - .inttab_tc2_079 (__INTTAB_CPU2 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_121)); } - .inttab_tc2_07A (__INTTAB_CPU2 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_122)); } - .inttab_tc2_07B (__INTTAB_CPU2 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_123)); } - .inttab_tc2_07C (__INTTAB_CPU2 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_124)); } - .inttab_tc2_07D (__INTTAB_CPU2 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_125)); } - .inttab_tc2_07E (__INTTAB_CPU2 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_126)); } - .inttab_tc2_07F (__INTTAB_CPU2 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_127)); } - .inttab_tc2_080 (__INTTAB_CPU2 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_128)); } - .inttab_tc2_081 (__INTTAB_CPU2 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_129)); } - .inttab_tc2_082 (__INTTAB_CPU2 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_130)); } - .inttab_tc2_083 (__INTTAB_CPU2 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_131)); } - .inttab_tc2_084 (__INTTAB_CPU2 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_132)); } - .inttab_tc2_085 (__INTTAB_CPU2 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_133)); } - .inttab_tc2_086 (__INTTAB_CPU2 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_134)); } - .inttab_tc2_087 (__INTTAB_CPU2 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_135)); } - .inttab_tc2_088 (__INTTAB_CPU2 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_136)); } - .inttab_tc2_089 (__INTTAB_CPU2 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_137)); } - .inttab_tc2_08A (__INTTAB_CPU2 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_138)); } - .inttab_tc2_08B (__INTTAB_CPU2 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_139)); } - .inttab_tc2_08C (__INTTAB_CPU2 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_140)); } - .inttab_tc2_08D (__INTTAB_CPU2 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_141)); } - .inttab_tc2_08E (__INTTAB_CPU2 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_142)); } - .inttab_tc2_08F (__INTTAB_CPU2 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_143)); } - .inttab_tc2_090 (__INTTAB_CPU2 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_144)); } - .inttab_tc2_091 (__INTTAB_CPU2 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_145)); } - .inttab_tc2_092 (__INTTAB_CPU2 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_146)); } - .inttab_tc2_093 (__INTTAB_CPU2 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_147)); } - .inttab_tc2_094 (__INTTAB_CPU2 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_148)); } - .inttab_tc2_095 (__INTTAB_CPU2 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_149)); } - .inttab_tc2_096 (__INTTAB_CPU2 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_150)); } - .inttab_tc2_097 (__INTTAB_CPU2 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_151)); } - .inttab_tc2_098 (__INTTAB_CPU2 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_152)); } - .inttab_tc2_099 (__INTTAB_CPU2 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_153)); } - .inttab_tc2_09A (__INTTAB_CPU2 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_154)); } - .inttab_tc2_09B (__INTTAB_CPU2 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_155)); } - .inttab_tc2_09C (__INTTAB_CPU2 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_156)); } - .inttab_tc2_09D (__INTTAB_CPU2 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_157)); } - .inttab_tc2_09E (__INTTAB_CPU2 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_158)); } - .inttab_tc2_09F (__INTTAB_CPU2 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_159)); } - .inttab_tc2_0A0 (__INTTAB_CPU2 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_160)); } - .inttab_tc2_0A1 (__INTTAB_CPU2 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_161)); } - .inttab_tc2_0A2 (__INTTAB_CPU2 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_162)); } - .inttab_tc2_0A3 (__INTTAB_CPU2 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_163)); } - .inttab_tc2_0A4 (__INTTAB_CPU2 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_164)); } - .inttab_tc2_0A5 (__INTTAB_CPU2 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_165)); } - .inttab_tc2_0A6 (__INTTAB_CPU2 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_166)); } - .inttab_tc2_0A7 (__INTTAB_CPU2 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_167)); } - .inttab_tc2_0A8 (__INTTAB_CPU2 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_168)); } - .inttab_tc2_0A9 (__INTTAB_CPU2 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_169)); } - .inttab_tc2_0AA (__INTTAB_CPU2 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_170)); } - .inttab_tc2_0AB (__INTTAB_CPU2 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_171)); } - .inttab_tc2_0AC (__INTTAB_CPU2 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_172)); } - .inttab_tc2_0AD (__INTTAB_CPU2 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_173)); } - .inttab_tc2_0AE (__INTTAB_CPU2 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_174)); } - .inttab_tc2_0AF (__INTTAB_CPU2 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_175)); } - .inttab_tc2_0B0 (__INTTAB_CPU2 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_176)); } - .inttab_tc2_0B1 (__INTTAB_CPU2 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_177)); } - .inttab_tc2_0B2 (__INTTAB_CPU2 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_178)); } - .inttab_tc2_0B3 (__INTTAB_CPU2 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_179)); } - .inttab_tc2_0B4 (__INTTAB_CPU2 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_180)); } - .inttab_tc2_0B5 (__INTTAB_CPU2 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_181)); } - .inttab_tc2_0B6 (__INTTAB_CPU2 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_182)); } - .inttab_tc2_0B7 (__INTTAB_CPU2 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_183)); } - .inttab_tc2_0B8 (__INTTAB_CPU2 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_184)); } - .inttab_tc2_0B9 (__INTTAB_CPU2 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_185)); } - .inttab_tc2_0BA (__INTTAB_CPU2 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_186)); } - .inttab_tc2_0BB (__INTTAB_CPU2 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_187)); } - .inttab_tc2_0BC (__INTTAB_CPU2 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_188)); } - .inttab_tc2_0BD (__INTTAB_CPU2 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_189)); } - .inttab_tc2_0BE (__INTTAB_CPU2 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_190)); } - .inttab_tc2_0BF (__INTTAB_CPU2 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_191)); } - .inttab_tc2_0C0 (__INTTAB_CPU2 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_192)); } - .inttab_tc2_0C1 (__INTTAB_CPU2 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_193)); } - .inttab_tc2_0C2 (__INTTAB_CPU2 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_194)); } - .inttab_tc2_0C3 (__INTTAB_CPU2 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_195)); } - .inttab_tc2_0C4 (__INTTAB_CPU2 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_196)); } - .inttab_tc2_0C5 (__INTTAB_CPU2 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_197)); } - .inttab_tc2_0C6 (__INTTAB_CPU2 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_198)); } - .inttab_tc2_0C7 (__INTTAB_CPU2 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_199)); } - .inttab_tc2_0C8 (__INTTAB_CPU2 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_200)); } - .inttab_tc2_0C9 (__INTTAB_CPU2 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_201)); } - .inttab_tc2_0CA (__INTTAB_CPU2 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_202)); } - .inttab_tc2_0CB (__INTTAB_CPU2 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_203)); } - .inttab_tc2_0CC (__INTTAB_CPU2 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_204)); } - .inttab_tc2_0CD (__INTTAB_CPU2 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_205)); } - .inttab_tc2_0CE (__INTTAB_CPU2 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_206)); } - .inttab_tc2_0CF (__INTTAB_CPU2 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_207)); } - .inttab_tc2_0D0 (__INTTAB_CPU2 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_208)); } - .inttab_tc2_0D1 (__INTTAB_CPU2 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_209)); } - .inttab_tc2_0D2 (__INTTAB_CPU2 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_210)); } - .inttab_tc2_0D3 (__INTTAB_CPU2 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_211)); } - .inttab_tc2_0D4 (__INTTAB_CPU2 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_212)); } - .inttab_tc2_0D5 (__INTTAB_CPU2 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_213)); } - .inttab_tc2_0D6 (__INTTAB_CPU2 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_214)); } - .inttab_tc2_0D7 (__INTTAB_CPU2 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_215)); } - .inttab_tc2_0D8 (__INTTAB_CPU2 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_216)); } - .inttab_tc2_0D9 (__INTTAB_CPU2 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_217)); } - .inttab_tc2_0DA (__INTTAB_CPU2 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_218)); } - .inttab_tc2_0DB (__INTTAB_CPU2 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_219)); } - .inttab_tc2_0DC (__INTTAB_CPU2 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_220)); } - .inttab_tc2_0DD (__INTTAB_CPU2 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_221)); } - .inttab_tc2_0DE (__INTTAB_CPU2 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_222)); } - .inttab_tc2_0DF (__INTTAB_CPU2 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_223)); } - .inttab_tc2_0E0 (__INTTAB_CPU2 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_224)); } - .inttab_tc2_0E1 (__INTTAB_CPU2 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_225)); } - .inttab_tc2_0E2 (__INTTAB_CPU2 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_226)); } - .inttab_tc2_0E3 (__INTTAB_CPU2 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_227)); } - .inttab_tc2_0E4 (__INTTAB_CPU2 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_228)); } - .inttab_tc2_0E5 (__INTTAB_CPU2 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_229)); } - .inttab_tc2_0E6 (__INTTAB_CPU2 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_230)); } - .inttab_tc2_0E7 (__INTTAB_CPU2 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_231)); } - .inttab_tc2_0E8 (__INTTAB_CPU2 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_232)); } - .inttab_tc2_0E9 (__INTTAB_CPU2 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_233)); } - .inttab_tc2_0EA (__INTTAB_CPU2 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_234)); } - .inttab_tc2_0EB (__INTTAB_CPU2 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_235)); } - .inttab_tc2_0EC (__INTTAB_CPU2 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_236)); } - .inttab_tc2_0ED (__INTTAB_CPU2 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_237)); } - .inttab_tc2_0EE (__INTTAB_CPU2 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_238)); } - .inttab_tc2_0EF (__INTTAB_CPU2 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_239)); } - .inttab_tc2_0F0 (__INTTAB_CPU2 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_240)); } - .inttab_tc2_0F1 (__INTTAB_CPU2 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_241)); } - .inttab_tc2_0F2 (__INTTAB_CPU2 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_242)); } - .inttab_tc2_0F3 (__INTTAB_CPU2 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_243)); } - .inttab_tc2_0F4 (__INTTAB_CPU2 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_244)); } - .inttab_tc2_0F5 (__INTTAB_CPU2 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_245)); } - .inttab_tc2_0F6 (__INTTAB_CPU2 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_246)); } - .inttab_tc2_0F7 (__INTTAB_CPU2 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_247)); } - .inttab_tc2_0F8 (__INTTAB_CPU2 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_248)); } - .inttab_tc2_0F9 (__INTTAB_CPU2 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_249)); } - .inttab_tc2_0FA (__INTTAB_CPU2 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_250)); } - .inttab_tc2_0FB (__INTTAB_CPU2 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_251)); } - .inttab_tc2_0FC (__INTTAB_CPU2 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_252)); } - .inttab_tc2_0FD (__INTTAB_CPU2 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_253)); } - .inttab_tc2_0FE (__INTTAB_CPU2 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_254)); } - .inttab_tc2_0FF (__INTTAB_CPU2 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_255)); } - } - SECTIONS - { - /*CPU3 Interrupt Vector Table*/ - .inttab_tc3_000 (__INTTAB_CPU3 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_0 )); } - .inttab_tc3_001 (__INTTAB_CPU3 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_1 )); } - .inttab_tc3_002 (__INTTAB_CPU3 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_2 )); } - .inttab_tc3_003 (__INTTAB_CPU3 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_3 )); } - .inttab_tc3_004 (__INTTAB_CPU3 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_4 )); } - .inttab_tc3_005 (__INTTAB_CPU3 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_5 )); } - .inttab_tc3_006 (__INTTAB_CPU3 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_6 )); } - .inttab_tc3_007 (__INTTAB_CPU3 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_7 )); } - .inttab_tc3_008 (__INTTAB_CPU3 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_8 )); } - .inttab_tc3_009 (__INTTAB_CPU3 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_9 )); } - .inttab_tc3_00A (__INTTAB_CPU3 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_10 )); } - .inttab_tc3_00B (__INTTAB_CPU3 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_11 )); } - .inttab_tc3_00C (__INTTAB_CPU3 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_12 )); } - .inttab_tc3_00D (__INTTAB_CPU3 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_13 )); } - .inttab_tc3_00E (__INTTAB_CPU3 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_14 )); } - .inttab_tc3_00F (__INTTAB_CPU3 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_15 )); } - .inttab_tc3_010 (__INTTAB_CPU3 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_16 )); } - .inttab_tc3_011 (__INTTAB_CPU3 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_17 )); } - .inttab_tc3_012 (__INTTAB_CPU3 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_18 )); } - .inttab_tc3_013 (__INTTAB_CPU3 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_19 )); } - .inttab_tc3_014 (__INTTAB_CPU3 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_20 )); } - .inttab_tc3_015 (__INTTAB_CPU3 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_21 )); } - .inttab_tc3_016 (__INTTAB_CPU3 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_22 )); } - .inttab_tc3_017 (__INTTAB_CPU3 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_23 )); } - .inttab_tc3_018 (__INTTAB_CPU3 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_24 )); } - .inttab_tc3_019 (__INTTAB_CPU3 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_25 )); } - .inttab_tc3_01A (__INTTAB_CPU3 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_26 )); } - .inttab_tc3_01B (__INTTAB_CPU3 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_27 )); } - .inttab_tc3_01C (__INTTAB_CPU3 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_28 )); } - .inttab_tc3_01D (__INTTAB_CPU3 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_29 )); } - .inttab_tc3_01E (__INTTAB_CPU3 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_30 )); } - .inttab_tc3_01F (__INTTAB_CPU3 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_31 )); } - .inttab_tc3_020 (__INTTAB_CPU3 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_32 )); } - .inttab_tc3_021 (__INTTAB_CPU3 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_33 )); } - .inttab_tc3_022 (__INTTAB_CPU3 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_34 )); } - .inttab_tc3_023 (__INTTAB_CPU3 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_35 )); } - .inttab_tc3_024 (__INTTAB_CPU3 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_36 )); } - .inttab_tc3_025 (__INTTAB_CPU3 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_37 )); } - .inttab_tc3_026 (__INTTAB_CPU3 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_38 )); } - .inttab_tc3_027 (__INTTAB_CPU3 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_39 )); } - .inttab_tc3_028 (__INTTAB_CPU3 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_40 )); } - .inttab_tc3_029 (__INTTAB_CPU3 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_41 )); } - .inttab_tc3_02A (__INTTAB_CPU3 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_42 )); } - .inttab_tc3_02B (__INTTAB_CPU3 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_43 )); } - .inttab_tc3_02C (__INTTAB_CPU3 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_44 )); } - .inttab_tc3_02D (__INTTAB_CPU3 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_45 )); } - .inttab_tc3_02E (__INTTAB_CPU3 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_46 )); } - .inttab_tc3_02F (__INTTAB_CPU3 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_47 )); } - .inttab_tc3_030 (__INTTAB_CPU3 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_48 )); } - .inttab_tc3_031 (__INTTAB_CPU3 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_49 )); } - .inttab_tc3_032 (__INTTAB_CPU3 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_50 )); } - .inttab_tc3_033 (__INTTAB_CPU3 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_51 )); } - .inttab_tc3_034 (__INTTAB_CPU3 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_52 )); } - .inttab_tc3_035 (__INTTAB_CPU3 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_53 )); } - .inttab_tc3_036 (__INTTAB_CPU3 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_54 )); } - .inttab_tc3_037 (__INTTAB_CPU3 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_55 )); } - .inttab_tc3_038 (__INTTAB_CPU3 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_56 )); } - .inttab_tc3_039 (__INTTAB_CPU3 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_57 )); } - .inttab_tc3_03A (__INTTAB_CPU3 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_58 )); } - .inttab_tc3_03B (__INTTAB_CPU3 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_59 )); } - .inttab_tc3_03C (__INTTAB_CPU3 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_60 )); } - .inttab_tc3_03D (__INTTAB_CPU3 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_61 )); } - .inttab_tc3_03E (__INTTAB_CPU3 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_62 )); } - .inttab_tc3_03F (__INTTAB_CPU3 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_63 )); } - .inttab_tc3_040 (__INTTAB_CPU3 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_64 )); } - .inttab_tc3_041 (__INTTAB_CPU3 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_65 )); } - .inttab_tc3_042 (__INTTAB_CPU3 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_66 )); } - .inttab_tc3_043 (__INTTAB_CPU3 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_67 )); } - .inttab_tc3_044 (__INTTAB_CPU3 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_68 )); } - .inttab_tc3_045 (__INTTAB_CPU3 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_69 )); } - .inttab_tc3_046 (__INTTAB_CPU3 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_70 )); } - .inttab_tc3_047 (__INTTAB_CPU3 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_71 )); } - .inttab_tc3_048 (__INTTAB_CPU3 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_72 )); } - .inttab_tc3_049 (__INTTAB_CPU3 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_73 )); } - .inttab_tc3_04A (__INTTAB_CPU3 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_74 )); } - .inttab_tc3_04B (__INTTAB_CPU3 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_75 )); } - .inttab_tc3_04C (__INTTAB_CPU3 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_76 )); } - .inttab_tc3_04D (__INTTAB_CPU3 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_77 )); } - .inttab_tc3_04E (__INTTAB_CPU3 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_78 )); } - .inttab_tc3_04F (__INTTAB_CPU3 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_79 )); } - .inttab_tc3_050 (__INTTAB_CPU3 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_80 )); } - .inttab_tc3_051 (__INTTAB_CPU3 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_81 )); } - .inttab_tc3_052 (__INTTAB_CPU3 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_82 )); } - .inttab_tc3_053 (__INTTAB_CPU3 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_83 )); } - .inttab_tc3_054 (__INTTAB_CPU3 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_84 )); } - .inttab_tc3_055 (__INTTAB_CPU3 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_85 )); } - .inttab_tc3_056 (__INTTAB_CPU3 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_86 )); } - .inttab_tc3_057 (__INTTAB_CPU3 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_87 )); } - .inttab_tc3_058 (__INTTAB_CPU3 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_88 )); } - .inttab_tc3_059 (__INTTAB_CPU3 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_89 )); } - .inttab_tc3_05A (__INTTAB_CPU3 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_90 )); } - .inttab_tc3_05B (__INTTAB_CPU3 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_91 )); } - .inttab_tc3_05C (__INTTAB_CPU3 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_92 )); } - .inttab_tc3_05D (__INTTAB_CPU3 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_93 )); } - .inttab_tc3_05E (__INTTAB_CPU3 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_94 )); } - .inttab_tc3_05F (__INTTAB_CPU3 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_95 )); } - .inttab_tc3_060 (__INTTAB_CPU3 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_96 )); } - .inttab_tc3_061 (__INTTAB_CPU3 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_97 )); } - .inttab_tc3_062 (__INTTAB_CPU3 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_98 )); } - .inttab_tc3_063 (__INTTAB_CPU3 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_99 )); } - .inttab_tc3_064 (__INTTAB_CPU3 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_100)); } - .inttab_tc3_065 (__INTTAB_CPU3 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_101)); } - .inttab_tc3_066 (__INTTAB_CPU3 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_102)); } - .inttab_tc3_067 (__INTTAB_CPU3 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_103)); } - .inttab_tc3_068 (__INTTAB_CPU3 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_104)); } - .inttab_tc3_069 (__INTTAB_CPU3 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_105)); } - .inttab_tc3_06A (__INTTAB_CPU3 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_106)); } - .inttab_tc3_06B (__INTTAB_CPU3 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_107)); } - .inttab_tc3_06C (__INTTAB_CPU3 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_108)); } - .inttab_tc3_06D (__INTTAB_CPU3 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_109)); } - .inttab_tc3_06E (__INTTAB_CPU3 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_110)); } - .inttab_tc3_06F (__INTTAB_CPU3 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_111)); } - .inttab_tc3_070 (__INTTAB_CPU3 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_112)); } - .inttab_tc3_071 (__INTTAB_CPU3 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_113)); } - .inttab_tc3_072 (__INTTAB_CPU3 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_114)); } - .inttab_tc3_073 (__INTTAB_CPU3 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_115)); } - .inttab_tc3_074 (__INTTAB_CPU3 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_116)); } - .inttab_tc3_075 (__INTTAB_CPU3 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_117)); } - .inttab_tc3_076 (__INTTAB_CPU3 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_118)); } - .inttab_tc3_077 (__INTTAB_CPU3 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_119)); } - .inttab_tc3_078 (__INTTAB_CPU3 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_120)); } - .inttab_tc3_079 (__INTTAB_CPU3 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_121)); } - .inttab_tc3_07A (__INTTAB_CPU3 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_122)); } - .inttab_tc3_07B (__INTTAB_CPU3 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_123)); } - .inttab_tc3_07C (__INTTAB_CPU3 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_124)); } - .inttab_tc3_07D (__INTTAB_CPU3 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_125)); } - .inttab_tc3_07E (__INTTAB_CPU3 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_126)); } - .inttab_tc3_07F (__INTTAB_CPU3 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_127)); } - .inttab_tc3_080 (__INTTAB_CPU3 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_128)); } - .inttab_tc3_081 (__INTTAB_CPU3 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_129)); } - .inttab_tc3_082 (__INTTAB_CPU3 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_130)); } - .inttab_tc3_083 (__INTTAB_CPU3 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_131)); } - .inttab_tc3_084 (__INTTAB_CPU3 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_132)); } - .inttab_tc3_085 (__INTTAB_CPU3 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_133)); } - .inttab_tc3_086 (__INTTAB_CPU3 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_134)); } - .inttab_tc3_087 (__INTTAB_CPU3 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_135)); } - .inttab_tc3_088 (__INTTAB_CPU3 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_136)); } - .inttab_tc3_089 (__INTTAB_CPU3 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_137)); } - .inttab_tc3_08A (__INTTAB_CPU3 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_138)); } - .inttab_tc3_08B (__INTTAB_CPU3 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_139)); } - .inttab_tc3_08C (__INTTAB_CPU3 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_140)); } - .inttab_tc3_08D (__INTTAB_CPU3 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_141)); } - .inttab_tc3_08E (__INTTAB_CPU3 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_142)); } - .inttab_tc3_08F (__INTTAB_CPU3 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_143)); } - .inttab_tc3_090 (__INTTAB_CPU3 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_144)); } - .inttab_tc3_091 (__INTTAB_CPU3 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_145)); } - .inttab_tc3_092 (__INTTAB_CPU3 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_146)); } - .inttab_tc3_093 (__INTTAB_CPU3 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_147)); } - .inttab_tc3_094 (__INTTAB_CPU3 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_148)); } - .inttab_tc3_095 (__INTTAB_CPU3 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_149)); } - .inttab_tc3_096 (__INTTAB_CPU3 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_150)); } - .inttab_tc3_097 (__INTTAB_CPU3 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_151)); } - .inttab_tc3_098 (__INTTAB_CPU3 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_152)); } - .inttab_tc3_099 (__INTTAB_CPU3 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_153)); } - .inttab_tc3_09A (__INTTAB_CPU3 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_154)); } - .inttab_tc3_09B (__INTTAB_CPU3 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_155)); } - .inttab_tc3_09C (__INTTAB_CPU3 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_156)); } - .inttab_tc3_09D (__INTTAB_CPU3 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_157)); } - .inttab_tc3_09E (__INTTAB_CPU3 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_158)); } - .inttab_tc3_09F (__INTTAB_CPU3 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_159)); } - .inttab_tc3_0A0 (__INTTAB_CPU3 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_160)); } - .inttab_tc3_0A1 (__INTTAB_CPU3 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_161)); } - .inttab_tc3_0A2 (__INTTAB_CPU3 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_162)); } - .inttab_tc3_0A3 (__INTTAB_CPU3 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_163)); } - .inttab_tc3_0A4 (__INTTAB_CPU3 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_164)); } - .inttab_tc3_0A5 (__INTTAB_CPU3 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_165)); } - .inttab_tc3_0A6 (__INTTAB_CPU3 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_166)); } - .inttab_tc3_0A7 (__INTTAB_CPU3 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_167)); } - .inttab_tc3_0A8 (__INTTAB_CPU3 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_168)); } - .inttab_tc3_0A9 (__INTTAB_CPU3 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_169)); } - .inttab_tc3_0AA (__INTTAB_CPU3 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_170)); } - .inttab_tc3_0AB (__INTTAB_CPU3 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_171)); } - .inttab_tc3_0AC (__INTTAB_CPU3 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_172)); } - .inttab_tc3_0AD (__INTTAB_CPU3 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_173)); } - .inttab_tc3_0AE (__INTTAB_CPU3 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_174)); } - .inttab_tc3_0AF (__INTTAB_CPU3 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_175)); } - .inttab_tc3_0B0 (__INTTAB_CPU3 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_176)); } - .inttab_tc3_0B1 (__INTTAB_CPU3 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_177)); } - .inttab_tc3_0B2 (__INTTAB_CPU3 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_178)); } - .inttab_tc3_0B3 (__INTTAB_CPU3 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_179)); } - .inttab_tc3_0B4 (__INTTAB_CPU3 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_180)); } - .inttab_tc3_0B5 (__INTTAB_CPU3 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_181)); } - .inttab_tc3_0B6 (__INTTAB_CPU3 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_182)); } - .inttab_tc3_0B7 (__INTTAB_CPU3 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_183)); } - .inttab_tc3_0B8 (__INTTAB_CPU3 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_184)); } - .inttab_tc3_0B9 (__INTTAB_CPU3 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_185)); } - .inttab_tc3_0BA (__INTTAB_CPU3 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_186)); } - .inttab_tc3_0BB (__INTTAB_CPU3 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_187)); } - .inttab_tc3_0BC (__INTTAB_CPU3 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_188)); } - .inttab_tc3_0BD (__INTTAB_CPU3 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_189)); } - .inttab_tc3_0BE (__INTTAB_CPU3 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_190)); } - .inttab_tc3_0BF (__INTTAB_CPU3 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_191)); } - .inttab_tc3_0C0 (__INTTAB_CPU3 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_192)); } - .inttab_tc3_0C1 (__INTTAB_CPU3 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_193)); } - .inttab_tc3_0C2 (__INTTAB_CPU3 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_194)); } - .inttab_tc3_0C3 (__INTTAB_CPU3 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_195)); } - .inttab_tc3_0C4 (__INTTAB_CPU3 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_196)); } - .inttab_tc3_0C5 (__INTTAB_CPU3 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_197)); } - .inttab_tc3_0C6 (__INTTAB_CPU3 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_198)); } - .inttab_tc3_0C7 (__INTTAB_CPU3 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_199)); } - .inttab_tc3_0C8 (__INTTAB_CPU3 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_200)); } - .inttab_tc3_0C9 (__INTTAB_CPU3 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_201)); } - .inttab_tc3_0CA (__INTTAB_CPU3 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_202)); } - .inttab_tc3_0CB (__INTTAB_CPU3 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_203)); } - .inttab_tc3_0CC (__INTTAB_CPU3 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_204)); } - .inttab_tc3_0CD (__INTTAB_CPU3 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_205)); } - .inttab_tc3_0CE (__INTTAB_CPU3 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_206)); } - .inttab_tc3_0CF (__INTTAB_CPU3 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_207)); } - .inttab_tc3_0D0 (__INTTAB_CPU3 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_208)); } - .inttab_tc3_0D1 (__INTTAB_CPU3 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_209)); } - .inttab_tc3_0D2 (__INTTAB_CPU3 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_210)); } - .inttab_tc3_0D3 (__INTTAB_CPU3 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_211)); } - .inttab_tc3_0D4 (__INTTAB_CPU3 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_212)); } - .inttab_tc3_0D5 (__INTTAB_CPU3 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_213)); } - .inttab_tc3_0D6 (__INTTAB_CPU3 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_214)); } - .inttab_tc3_0D7 (__INTTAB_CPU3 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_215)); } - .inttab_tc3_0D8 (__INTTAB_CPU3 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_216)); } - .inttab_tc3_0D9 (__INTTAB_CPU3 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_217)); } - .inttab_tc3_0DA (__INTTAB_CPU3 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_218)); } - .inttab_tc3_0DB (__INTTAB_CPU3 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_219)); } - .inttab_tc3_0DC (__INTTAB_CPU3 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_220)); } - .inttab_tc3_0DD (__INTTAB_CPU3 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_221)); } - .inttab_tc3_0DE (__INTTAB_CPU3 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_222)); } - .inttab_tc3_0DF (__INTTAB_CPU3 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_223)); } - .inttab_tc3_0E0 (__INTTAB_CPU3 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_224)); } - .inttab_tc3_0E1 (__INTTAB_CPU3 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_225)); } - .inttab_tc3_0E2 (__INTTAB_CPU3 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_226)); } - .inttab_tc3_0E3 (__INTTAB_CPU3 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_227)); } - .inttab_tc3_0E4 (__INTTAB_CPU3 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_228)); } - .inttab_tc3_0E5 (__INTTAB_CPU3 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_229)); } - .inttab_tc3_0E6 (__INTTAB_CPU3 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_230)); } - .inttab_tc3_0E7 (__INTTAB_CPU3 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_231)); } - .inttab_tc3_0E8 (__INTTAB_CPU3 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_232)); } - .inttab_tc3_0E9 (__INTTAB_CPU3 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_233)); } - .inttab_tc3_0EA (__INTTAB_CPU3 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_234)); } - .inttab_tc3_0EB (__INTTAB_CPU3 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_235)); } - .inttab_tc3_0EC (__INTTAB_CPU3 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_236)); } - .inttab_tc3_0ED (__INTTAB_CPU3 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_237)); } - .inttab_tc3_0EE (__INTTAB_CPU3 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_238)); } - .inttab_tc3_0EF (__INTTAB_CPU3 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_239)); } - .inttab_tc3_0F0 (__INTTAB_CPU3 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_240)); } - .inttab_tc3_0F1 (__INTTAB_CPU3 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_241)); } - .inttab_tc3_0F2 (__INTTAB_CPU3 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_242)); } - .inttab_tc3_0F3 (__INTTAB_CPU3 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_243)); } - .inttab_tc3_0F4 (__INTTAB_CPU3 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_244)); } - .inttab_tc3_0F5 (__INTTAB_CPU3 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_245)); } - .inttab_tc3_0F6 (__INTTAB_CPU3 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_246)); } - .inttab_tc3_0F7 (__INTTAB_CPU3 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_247)); } - .inttab_tc3_0F8 (__INTTAB_CPU3 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_248)); } - .inttab_tc3_0F9 (__INTTAB_CPU3 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_249)); } - .inttab_tc3_0FA (__INTTAB_CPU3 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_250)); } - .inttab_tc3_0FB (__INTTAB_CPU3 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_251)); } - .inttab_tc3_0FC (__INTTAB_CPU3 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_252)); } - .inttab_tc3_0FD (__INTTAB_CPU3 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_253)); } - .inttab_tc3_0FE (__INTTAB_CPU3 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_254)); } - .inttab_tc3_0FF (__INTTAB_CPU3 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc3_255)); } - } - SECTIONS - { - /*CPU4 Interrupt Vector Table*/ - .inttab_tc4_000 (__INTTAB_CPU4 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_0 )); } - .inttab_tc4_001 (__INTTAB_CPU4 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_1 )); } - .inttab_tc4_002 (__INTTAB_CPU4 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_2 )); } - .inttab_tc4_003 (__INTTAB_CPU4 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_3 )); } - .inttab_tc4_004 (__INTTAB_CPU4 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_4 )); } - .inttab_tc4_005 (__INTTAB_CPU4 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_5 )); } - .inttab_tc4_006 (__INTTAB_CPU4 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_6 )); } - .inttab_tc4_007 (__INTTAB_CPU4 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_7 )); } - .inttab_tc4_008 (__INTTAB_CPU4 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_8 )); } - .inttab_tc4_009 (__INTTAB_CPU4 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_9 )); } - .inttab_tc4_00A (__INTTAB_CPU4 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_10 )); } - .inttab_tc4_00B (__INTTAB_CPU4 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_11 )); } - .inttab_tc4_00C (__INTTAB_CPU4 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_12 )); } - .inttab_tc4_00D (__INTTAB_CPU4 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_13 )); } - .inttab_tc4_00E (__INTTAB_CPU4 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_14 )); } - .inttab_tc4_00F (__INTTAB_CPU4 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_15 )); } - .inttab_tc4_010 (__INTTAB_CPU4 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_16 )); } - .inttab_tc4_011 (__INTTAB_CPU4 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_17 )); } - .inttab_tc4_012 (__INTTAB_CPU4 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_18 )); } - .inttab_tc4_013 (__INTTAB_CPU4 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_19 )); } - .inttab_tc4_014 (__INTTAB_CPU4 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_20 )); } - .inttab_tc4_015 (__INTTAB_CPU4 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_21 )); } - .inttab_tc4_016 (__INTTAB_CPU4 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_22 )); } - .inttab_tc4_017 (__INTTAB_CPU4 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_23 )); } - .inttab_tc4_018 (__INTTAB_CPU4 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_24 )); } - .inttab_tc4_019 (__INTTAB_CPU4 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_25 )); } - .inttab_tc4_01A (__INTTAB_CPU4 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_26 )); } - .inttab_tc4_01B (__INTTAB_CPU4 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_27 )); } - .inttab_tc4_01C (__INTTAB_CPU4 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_28 )); } - .inttab_tc4_01D (__INTTAB_CPU4 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_29 )); } - .inttab_tc4_01E (__INTTAB_CPU4 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_30 )); } - .inttab_tc4_01F (__INTTAB_CPU4 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_31 )); } - .inttab_tc4_020 (__INTTAB_CPU4 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_32 )); } - .inttab_tc4_021 (__INTTAB_CPU4 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_33 )); } - .inttab_tc4_022 (__INTTAB_CPU4 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_34 )); } - .inttab_tc4_023 (__INTTAB_CPU4 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_35 )); } - .inttab_tc4_024 (__INTTAB_CPU4 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_36 )); } - .inttab_tc4_025 (__INTTAB_CPU4 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_37 )); } - .inttab_tc4_026 (__INTTAB_CPU4 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_38 )); } - .inttab_tc4_027 (__INTTAB_CPU4 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_39 )); } - .inttab_tc4_028 (__INTTAB_CPU4 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_40 )); } - .inttab_tc4_029 (__INTTAB_CPU4 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_41 )); } - .inttab_tc4_02A (__INTTAB_CPU4 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_42 )); } - .inttab_tc4_02B (__INTTAB_CPU4 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_43 )); } - .inttab_tc4_02C (__INTTAB_CPU4 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_44 )); } - .inttab_tc4_02D (__INTTAB_CPU4 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_45 )); } - .inttab_tc4_02E (__INTTAB_CPU4 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_46 )); } - .inttab_tc4_02F (__INTTAB_CPU4 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_47 )); } - .inttab_tc4_030 (__INTTAB_CPU4 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_48 )); } - .inttab_tc4_031 (__INTTAB_CPU4 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_49 )); } - .inttab_tc4_032 (__INTTAB_CPU4 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_50 )); } - .inttab_tc4_033 (__INTTAB_CPU4 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_51 )); } - .inttab_tc4_034 (__INTTAB_CPU4 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_52 )); } - .inttab_tc4_035 (__INTTAB_CPU4 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_53 )); } - .inttab_tc4_036 (__INTTAB_CPU4 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_54 )); } - .inttab_tc4_037 (__INTTAB_CPU4 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_55 )); } - .inttab_tc4_038 (__INTTAB_CPU4 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_56 )); } - .inttab_tc4_039 (__INTTAB_CPU4 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_57 )); } - .inttab_tc4_03A (__INTTAB_CPU4 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_58 )); } - .inttab_tc4_03B (__INTTAB_CPU4 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_59 )); } - .inttab_tc4_03C (__INTTAB_CPU4 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_60 )); } - .inttab_tc4_03D (__INTTAB_CPU4 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_61 )); } - .inttab_tc4_03E (__INTTAB_CPU4 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_62 )); } - .inttab_tc4_03F (__INTTAB_CPU4 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_63 )); } - .inttab_tc4_040 (__INTTAB_CPU4 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_64 )); } - .inttab_tc4_041 (__INTTAB_CPU4 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_65 )); } - .inttab_tc4_042 (__INTTAB_CPU4 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_66 )); } - .inttab_tc4_043 (__INTTAB_CPU4 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_67 )); } - .inttab_tc4_044 (__INTTAB_CPU4 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_68 )); } - .inttab_tc4_045 (__INTTAB_CPU4 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_69 )); } - .inttab_tc4_046 (__INTTAB_CPU4 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_70 )); } - .inttab_tc4_047 (__INTTAB_CPU4 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_71 )); } - .inttab_tc4_048 (__INTTAB_CPU4 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_72 )); } - .inttab_tc4_049 (__INTTAB_CPU4 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_73 )); } - .inttab_tc4_04A (__INTTAB_CPU4 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_74 )); } - .inttab_tc4_04B (__INTTAB_CPU4 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_75 )); } - .inttab_tc4_04C (__INTTAB_CPU4 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_76 )); } - .inttab_tc4_04D (__INTTAB_CPU4 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_77 )); } - .inttab_tc4_04E (__INTTAB_CPU4 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_78 )); } - .inttab_tc4_04F (__INTTAB_CPU4 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_79 )); } - .inttab_tc4_050 (__INTTAB_CPU4 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_80 )); } - .inttab_tc4_051 (__INTTAB_CPU4 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_81 )); } - .inttab_tc4_052 (__INTTAB_CPU4 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_82 )); } - .inttab_tc4_053 (__INTTAB_CPU4 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_83 )); } - .inttab_tc4_054 (__INTTAB_CPU4 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_84 )); } - .inttab_tc4_055 (__INTTAB_CPU4 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_85 )); } - .inttab_tc4_056 (__INTTAB_CPU4 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_86 )); } - .inttab_tc4_057 (__INTTAB_CPU4 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_87 )); } - .inttab_tc4_058 (__INTTAB_CPU4 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_88 )); } - .inttab_tc4_059 (__INTTAB_CPU4 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_89 )); } - .inttab_tc4_05A (__INTTAB_CPU4 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_90 )); } - .inttab_tc4_05B (__INTTAB_CPU4 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_91 )); } - .inttab_tc4_05C (__INTTAB_CPU4 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_92 )); } - .inttab_tc4_05D (__INTTAB_CPU4 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_93 )); } - .inttab_tc4_05E (__INTTAB_CPU4 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_94 )); } - .inttab_tc4_05F (__INTTAB_CPU4 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_95 )); } - .inttab_tc4_060 (__INTTAB_CPU4 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_96 )); } - .inttab_tc4_061 (__INTTAB_CPU4 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_97 )); } - .inttab_tc4_062 (__INTTAB_CPU4 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_98 )); } - .inttab_tc4_063 (__INTTAB_CPU4 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_99 )); } - .inttab_tc4_064 (__INTTAB_CPU4 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_100)); } - .inttab_tc4_065 (__INTTAB_CPU4 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_101)); } - .inttab_tc4_066 (__INTTAB_CPU4 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_102)); } - .inttab_tc4_067 (__INTTAB_CPU4 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_103)); } - .inttab_tc4_068 (__INTTAB_CPU4 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_104)); } - .inttab_tc4_069 (__INTTAB_CPU4 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_105)); } - .inttab_tc4_06A (__INTTAB_CPU4 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_106)); } - .inttab_tc4_06B (__INTTAB_CPU4 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_107)); } - .inttab_tc4_06C (__INTTAB_CPU4 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_108)); } - .inttab_tc4_06D (__INTTAB_CPU4 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_109)); } - .inttab_tc4_06E (__INTTAB_CPU4 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_110)); } - .inttab_tc4_06F (__INTTAB_CPU4 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_111)); } - .inttab_tc4_070 (__INTTAB_CPU4 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_112)); } - .inttab_tc4_071 (__INTTAB_CPU4 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_113)); } - .inttab_tc4_072 (__INTTAB_CPU4 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_114)); } - .inttab_tc4_073 (__INTTAB_CPU4 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_115)); } - .inttab_tc4_074 (__INTTAB_CPU4 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_116)); } - .inttab_tc4_075 (__INTTAB_CPU4 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_117)); } - .inttab_tc4_076 (__INTTAB_CPU4 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_118)); } - .inttab_tc4_077 (__INTTAB_CPU4 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_119)); } - .inttab_tc4_078 (__INTTAB_CPU4 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_120)); } - .inttab_tc4_079 (__INTTAB_CPU4 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_121)); } - .inttab_tc4_07A (__INTTAB_CPU4 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_122)); } - .inttab_tc4_07B (__INTTAB_CPU4 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_123)); } - .inttab_tc4_07C (__INTTAB_CPU4 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_124)); } - .inttab_tc4_07D (__INTTAB_CPU4 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_125)); } - .inttab_tc4_07E (__INTTAB_CPU4 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_126)); } - .inttab_tc4_07F (__INTTAB_CPU4 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_127)); } - .inttab_tc4_080 (__INTTAB_CPU4 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_128)); } - .inttab_tc4_081 (__INTTAB_CPU4 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_129)); } - .inttab_tc4_082 (__INTTAB_CPU4 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_130)); } - .inttab_tc4_083 (__INTTAB_CPU4 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_131)); } - .inttab_tc4_084 (__INTTAB_CPU4 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_132)); } - .inttab_tc4_085 (__INTTAB_CPU4 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_133)); } - .inttab_tc4_086 (__INTTAB_CPU4 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_134)); } - .inttab_tc4_087 (__INTTAB_CPU4 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_135)); } - .inttab_tc4_088 (__INTTAB_CPU4 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_136)); } - .inttab_tc4_089 (__INTTAB_CPU4 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_137)); } - .inttab_tc4_08A (__INTTAB_CPU4 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_138)); } - .inttab_tc4_08B (__INTTAB_CPU4 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_139)); } - .inttab_tc4_08C (__INTTAB_CPU4 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_140)); } - .inttab_tc4_08D (__INTTAB_CPU4 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_141)); } - .inttab_tc4_08E (__INTTAB_CPU4 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_142)); } - .inttab_tc4_08F (__INTTAB_CPU4 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_143)); } - .inttab_tc4_090 (__INTTAB_CPU4 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_144)); } - .inttab_tc4_091 (__INTTAB_CPU4 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_145)); } - .inttab_tc4_092 (__INTTAB_CPU4 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_146)); } - .inttab_tc4_093 (__INTTAB_CPU4 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_147)); } - .inttab_tc4_094 (__INTTAB_CPU4 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_148)); } - .inttab_tc4_095 (__INTTAB_CPU4 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_149)); } - .inttab_tc4_096 (__INTTAB_CPU4 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_150)); } - .inttab_tc4_097 (__INTTAB_CPU4 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_151)); } - .inttab_tc4_098 (__INTTAB_CPU4 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_152)); } - .inttab_tc4_099 (__INTTAB_CPU4 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_153)); } - .inttab_tc4_09A (__INTTAB_CPU4 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_154)); } - .inttab_tc4_09B (__INTTAB_CPU4 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_155)); } - .inttab_tc4_09C (__INTTAB_CPU4 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_156)); } - .inttab_tc4_09D (__INTTAB_CPU4 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_157)); } - .inttab_tc4_09E (__INTTAB_CPU4 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_158)); } - .inttab_tc4_09F (__INTTAB_CPU4 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_159)); } - .inttab_tc4_0A0 (__INTTAB_CPU4 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_160)); } - .inttab_tc4_0A1 (__INTTAB_CPU4 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_161)); } - .inttab_tc4_0A2 (__INTTAB_CPU4 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_162)); } - .inttab_tc4_0A3 (__INTTAB_CPU4 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_163)); } - .inttab_tc4_0A4 (__INTTAB_CPU4 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_164)); } - .inttab_tc4_0A5 (__INTTAB_CPU4 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_165)); } - .inttab_tc4_0A6 (__INTTAB_CPU4 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_166)); } - .inttab_tc4_0A7 (__INTTAB_CPU4 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_167)); } - .inttab_tc4_0A8 (__INTTAB_CPU4 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_168)); } - .inttab_tc4_0A9 (__INTTAB_CPU4 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_169)); } - .inttab_tc4_0AA (__INTTAB_CPU4 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_170)); } - .inttab_tc4_0AB (__INTTAB_CPU4 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_171)); } - .inttab_tc4_0AC (__INTTAB_CPU4 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_172)); } - .inttab_tc4_0AD (__INTTAB_CPU4 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_173)); } - .inttab_tc4_0AE (__INTTAB_CPU4 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_174)); } - .inttab_tc4_0AF (__INTTAB_CPU4 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_175)); } - .inttab_tc4_0B0 (__INTTAB_CPU4 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_176)); } - .inttab_tc4_0B1 (__INTTAB_CPU4 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_177)); } - .inttab_tc4_0B2 (__INTTAB_CPU4 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_178)); } - .inttab_tc4_0B3 (__INTTAB_CPU4 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_179)); } - .inttab_tc4_0B4 (__INTTAB_CPU4 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_180)); } - .inttab_tc4_0B5 (__INTTAB_CPU4 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_181)); } - .inttab_tc4_0B6 (__INTTAB_CPU4 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_182)); } - .inttab_tc4_0B7 (__INTTAB_CPU4 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_183)); } - .inttab_tc4_0B8 (__INTTAB_CPU4 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_184)); } - .inttab_tc4_0B9 (__INTTAB_CPU4 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_185)); } - .inttab_tc4_0BA (__INTTAB_CPU4 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_186)); } - .inttab_tc4_0BB (__INTTAB_CPU4 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_187)); } - .inttab_tc4_0BC (__INTTAB_CPU4 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_188)); } - .inttab_tc4_0BD (__INTTAB_CPU4 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_189)); } - .inttab_tc4_0BE (__INTTAB_CPU4 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_190)); } - .inttab_tc4_0BF (__INTTAB_CPU4 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_191)); } - .inttab_tc4_0C0 (__INTTAB_CPU4 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_192)); } - .inttab_tc4_0C1 (__INTTAB_CPU4 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_193)); } - .inttab_tc4_0C2 (__INTTAB_CPU4 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_194)); } - .inttab_tc4_0C3 (__INTTAB_CPU4 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_195)); } - .inttab_tc4_0C4 (__INTTAB_CPU4 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_196)); } - .inttab_tc4_0C5 (__INTTAB_CPU4 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_197)); } - .inttab_tc4_0C6 (__INTTAB_CPU4 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_198)); } - .inttab_tc4_0C7 (__INTTAB_CPU4 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_199)); } - .inttab_tc4_0C8 (__INTTAB_CPU4 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_200)); } - .inttab_tc4_0C9 (__INTTAB_CPU4 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_201)); } - .inttab_tc4_0CA (__INTTAB_CPU4 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_202)); } - .inttab_tc4_0CB (__INTTAB_CPU4 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_203)); } - .inttab_tc4_0CC (__INTTAB_CPU4 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_204)); } - .inttab_tc4_0CD (__INTTAB_CPU4 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_205)); } - .inttab_tc4_0CE (__INTTAB_CPU4 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_206)); } - .inttab_tc4_0CF (__INTTAB_CPU4 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_207)); } - .inttab_tc4_0D0 (__INTTAB_CPU4 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_208)); } - .inttab_tc4_0D1 (__INTTAB_CPU4 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_209)); } - .inttab_tc4_0D2 (__INTTAB_CPU4 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_210)); } - .inttab_tc4_0D3 (__INTTAB_CPU4 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_211)); } - .inttab_tc4_0D4 (__INTTAB_CPU4 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_212)); } - .inttab_tc4_0D5 (__INTTAB_CPU4 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_213)); } - .inttab_tc4_0D6 (__INTTAB_CPU4 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_214)); } - .inttab_tc4_0D7 (__INTTAB_CPU4 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_215)); } - .inttab_tc4_0D8 (__INTTAB_CPU4 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_216)); } - .inttab_tc4_0D9 (__INTTAB_CPU4 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_217)); } - .inttab_tc4_0DA (__INTTAB_CPU4 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_218)); } - .inttab_tc4_0DB (__INTTAB_CPU4 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_219)); } - .inttab_tc4_0DC (__INTTAB_CPU4 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_220)); } - .inttab_tc4_0DD (__INTTAB_CPU4 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_221)); } - .inttab_tc4_0DE (__INTTAB_CPU4 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_222)); } - .inttab_tc4_0DF (__INTTAB_CPU4 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_223)); } - .inttab_tc4_0E0 (__INTTAB_CPU4 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_224)); } - .inttab_tc4_0E1 (__INTTAB_CPU4 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_225)); } - .inttab_tc4_0E2 (__INTTAB_CPU4 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_226)); } - .inttab_tc4_0E3 (__INTTAB_CPU4 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_227)); } - .inttab_tc4_0E4 (__INTTAB_CPU4 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_228)); } - .inttab_tc4_0E5 (__INTTAB_CPU4 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_229)); } - .inttab_tc4_0E6 (__INTTAB_CPU4 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_230)); } - .inttab_tc4_0E7 (__INTTAB_CPU4 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_231)); } - .inttab_tc4_0E8 (__INTTAB_CPU4 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_232)); } - .inttab_tc4_0E9 (__INTTAB_CPU4 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_233)); } - .inttab_tc4_0EA (__INTTAB_CPU4 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_234)); } - .inttab_tc4_0EB (__INTTAB_CPU4 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_235)); } - .inttab_tc4_0EC (__INTTAB_CPU4 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_236)); } - .inttab_tc4_0ED (__INTTAB_CPU4 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_237)); } - .inttab_tc4_0EE (__INTTAB_CPU4 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_238)); } - .inttab_tc4_0EF (__INTTAB_CPU4 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_239)); } - .inttab_tc4_0F0 (__INTTAB_CPU4 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_240)); } - .inttab_tc4_0F1 (__INTTAB_CPU4 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_241)); } - .inttab_tc4_0F2 (__INTTAB_CPU4 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_242)); } - .inttab_tc4_0F3 (__INTTAB_CPU4 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_243)); } - .inttab_tc4_0F4 (__INTTAB_CPU4 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_244)); } - .inttab_tc4_0F5 (__INTTAB_CPU4 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_245)); } - .inttab_tc4_0F6 (__INTTAB_CPU4 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_246)); } - .inttab_tc4_0F7 (__INTTAB_CPU4 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_247)); } - .inttab_tc4_0F8 (__INTTAB_CPU4 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_248)); } - .inttab_tc4_0F9 (__INTTAB_CPU4 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_249)); } - .inttab_tc4_0FA (__INTTAB_CPU4 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_250)); } - .inttab_tc4_0FB (__INTTAB_CPU4 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_251)); } - .inttab_tc4_0FC (__INTTAB_CPU4 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_252)); } - .inttab_tc4_0FD (__INTTAB_CPU4 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_253)); } - .inttab_tc4_0FE (__INTTAB_CPU4 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_254)); } - .inttab_tc4_0FF (__INTTAB_CPU4 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc4_255)); } - } - SECTIONS - { - /*CPU5 Interrupt Vector Table*/ - .inttab_tc5_000 (__INTTAB_CPU5 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_0 )); } - .inttab_tc5_001 (__INTTAB_CPU5 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_1 )); } - .inttab_tc5_002 (__INTTAB_CPU5 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_2 )); } - .inttab_tc5_003 (__INTTAB_CPU5 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_3 )); } - .inttab_tc5_004 (__INTTAB_CPU5 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_4 )); } - .inttab_tc5_005 (__INTTAB_CPU5 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_5 )); } - .inttab_tc5_006 (__INTTAB_CPU5 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_6 )); } - .inttab_tc5_007 (__INTTAB_CPU5 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_7 )); } - .inttab_tc5_008 (__INTTAB_CPU5 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_8 )); } - .inttab_tc5_009 (__INTTAB_CPU5 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_9 )); } - .inttab_tc5_00A (__INTTAB_CPU5 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_10 )); } - .inttab_tc5_00B (__INTTAB_CPU5 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_11 )); } - .inttab_tc5_00C (__INTTAB_CPU5 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_12 )); } - .inttab_tc5_00D (__INTTAB_CPU5 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_13 )); } - .inttab_tc5_00E (__INTTAB_CPU5 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_14 )); } - .inttab_tc5_00F (__INTTAB_CPU5 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_15 )); } - .inttab_tc5_010 (__INTTAB_CPU5 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_16 )); } - .inttab_tc5_011 (__INTTAB_CPU5 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_17 )); } - .inttab_tc5_012 (__INTTAB_CPU5 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_18 )); } - .inttab_tc5_013 (__INTTAB_CPU5 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_19 )); } - .inttab_tc5_014 (__INTTAB_CPU5 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_20 )); } - .inttab_tc5_015 (__INTTAB_CPU5 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_21 )); } - .inttab_tc5_016 (__INTTAB_CPU5 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_22 )); } - .inttab_tc5_017 (__INTTAB_CPU5 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_23 )); } - .inttab_tc5_018 (__INTTAB_CPU5 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_24 )); } - .inttab_tc5_019 (__INTTAB_CPU5 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_25 )); } - .inttab_tc5_01A (__INTTAB_CPU5 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_26 )); } - .inttab_tc5_01B (__INTTAB_CPU5 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_27 )); } - .inttab_tc5_01C (__INTTAB_CPU5 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_28 )); } - .inttab_tc5_01D (__INTTAB_CPU5 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_29 )); } - .inttab_tc5_01E (__INTTAB_CPU5 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_30 )); } - .inttab_tc5_01F (__INTTAB_CPU5 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_31 )); } - .inttab_tc5_020 (__INTTAB_CPU5 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_32 )); } - .inttab_tc5_021 (__INTTAB_CPU5 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_33 )); } - .inttab_tc5_022 (__INTTAB_CPU5 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_34 )); } - .inttab_tc5_023 (__INTTAB_CPU5 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_35 )); } - .inttab_tc5_024 (__INTTAB_CPU5 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_36 )); } - .inttab_tc5_025 (__INTTAB_CPU5 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_37 )); } - .inttab_tc5_026 (__INTTAB_CPU5 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_38 )); } - .inttab_tc5_027 (__INTTAB_CPU5 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_39 )); } - .inttab_tc5_028 (__INTTAB_CPU5 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_40 )); } - .inttab_tc5_029 (__INTTAB_CPU5 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_41 )); } - .inttab_tc5_02A (__INTTAB_CPU5 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_42 )); } - .inttab_tc5_02B (__INTTAB_CPU5 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_43 )); } - .inttab_tc5_02C (__INTTAB_CPU5 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_44 )); } - .inttab_tc5_02D (__INTTAB_CPU5 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_45 )); } - .inttab_tc5_02E (__INTTAB_CPU5 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_46 )); } - .inttab_tc5_02F (__INTTAB_CPU5 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_47 )); } - .inttab_tc5_030 (__INTTAB_CPU5 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_48 )); } - .inttab_tc5_031 (__INTTAB_CPU5 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_49 )); } - .inttab_tc5_032 (__INTTAB_CPU5 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_50 )); } - .inttab_tc5_033 (__INTTAB_CPU5 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_51 )); } - .inttab_tc5_034 (__INTTAB_CPU5 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_52 )); } - .inttab_tc5_035 (__INTTAB_CPU5 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_53 )); } - .inttab_tc5_036 (__INTTAB_CPU5 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_54 )); } - .inttab_tc5_037 (__INTTAB_CPU5 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_55 )); } - .inttab_tc5_038 (__INTTAB_CPU5 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_56 )); } - .inttab_tc5_039 (__INTTAB_CPU5 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_57 )); } - .inttab_tc5_03A (__INTTAB_CPU5 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_58 )); } - .inttab_tc5_03B (__INTTAB_CPU5 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_59 )); } - .inttab_tc5_03C (__INTTAB_CPU5 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_60 )); } - .inttab_tc5_03D (__INTTAB_CPU5 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_61 )); } - .inttab_tc5_03E (__INTTAB_CPU5 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_62 )); } - .inttab_tc5_03F (__INTTAB_CPU5 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_63 )); } - .inttab_tc5_040 (__INTTAB_CPU5 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_64 )); } - .inttab_tc5_041 (__INTTAB_CPU5 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_65 )); } - .inttab_tc5_042 (__INTTAB_CPU5 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_66 )); } - .inttab_tc5_043 (__INTTAB_CPU5 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_67 )); } - .inttab_tc5_044 (__INTTAB_CPU5 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_68 )); } - .inttab_tc5_045 (__INTTAB_CPU5 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_69 )); } - .inttab_tc5_046 (__INTTAB_CPU5 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_70 )); } - .inttab_tc5_047 (__INTTAB_CPU5 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_71 )); } - .inttab_tc5_048 (__INTTAB_CPU5 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_72 )); } - .inttab_tc5_049 (__INTTAB_CPU5 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_73 )); } - .inttab_tc5_04A (__INTTAB_CPU5 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_74 )); } - .inttab_tc5_04B (__INTTAB_CPU5 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_75 )); } - .inttab_tc5_04C (__INTTAB_CPU5 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_76 )); } - .inttab_tc5_04D (__INTTAB_CPU5 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_77 )); } - .inttab_tc5_04E (__INTTAB_CPU5 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_78 )); } - .inttab_tc5_04F (__INTTAB_CPU5 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_79 )); } - .inttab_tc5_050 (__INTTAB_CPU5 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_80 )); } - .inttab_tc5_051 (__INTTAB_CPU5 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_81 )); } - .inttab_tc5_052 (__INTTAB_CPU5 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_82 )); } - .inttab_tc5_053 (__INTTAB_CPU5 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_83 )); } - .inttab_tc5_054 (__INTTAB_CPU5 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_84 )); } - .inttab_tc5_055 (__INTTAB_CPU5 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_85 )); } - .inttab_tc5_056 (__INTTAB_CPU5 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_86 )); } - .inttab_tc5_057 (__INTTAB_CPU5 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_87 )); } - .inttab_tc5_058 (__INTTAB_CPU5 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_88 )); } - .inttab_tc5_059 (__INTTAB_CPU5 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_89 )); } - .inttab_tc5_05A (__INTTAB_CPU5 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_90 )); } - .inttab_tc5_05B (__INTTAB_CPU5 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_91 )); } - .inttab_tc5_05C (__INTTAB_CPU5 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_92 )); } - .inttab_tc5_05D (__INTTAB_CPU5 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_93 )); } - .inttab_tc5_05E (__INTTAB_CPU5 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_94 )); } - .inttab_tc5_05F (__INTTAB_CPU5 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_95 )); } - .inttab_tc5_060 (__INTTAB_CPU5 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_96 )); } - .inttab_tc5_061 (__INTTAB_CPU5 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_97 )); } - .inttab_tc5_062 (__INTTAB_CPU5 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_98 )); } - .inttab_tc5_063 (__INTTAB_CPU5 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_99 )); } - .inttab_tc5_064 (__INTTAB_CPU5 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_100)); } - .inttab_tc5_065 (__INTTAB_CPU5 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_101)); } - .inttab_tc5_066 (__INTTAB_CPU5 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_102)); } - .inttab_tc5_067 (__INTTAB_CPU5 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_103)); } - .inttab_tc5_068 (__INTTAB_CPU5 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_104)); } - .inttab_tc5_069 (__INTTAB_CPU5 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_105)); } - .inttab_tc5_06A (__INTTAB_CPU5 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_106)); } - .inttab_tc5_06B (__INTTAB_CPU5 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_107)); } - .inttab_tc5_06C (__INTTAB_CPU5 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_108)); } - .inttab_tc5_06D (__INTTAB_CPU5 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_109)); } - .inttab_tc5_06E (__INTTAB_CPU5 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_110)); } - .inttab_tc5_06F (__INTTAB_CPU5 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_111)); } - .inttab_tc5_070 (__INTTAB_CPU5 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_112)); } - .inttab_tc5_071 (__INTTAB_CPU5 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_113)); } - .inttab_tc5_072 (__INTTAB_CPU5 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_114)); } - .inttab_tc5_073 (__INTTAB_CPU5 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_115)); } - .inttab_tc5_074 (__INTTAB_CPU5 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_116)); } - .inttab_tc5_075 (__INTTAB_CPU5 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_117)); } - .inttab_tc5_076 (__INTTAB_CPU5 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_118)); } - .inttab_tc5_077 (__INTTAB_CPU5 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_119)); } - .inttab_tc5_078 (__INTTAB_CPU5 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_120)); } - .inttab_tc5_079 (__INTTAB_CPU5 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_121)); } - .inttab_tc5_07A (__INTTAB_CPU5 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_122)); } - .inttab_tc5_07B (__INTTAB_CPU5 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_123)); } - .inttab_tc5_07C (__INTTAB_CPU5 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_124)); } - .inttab_tc5_07D (__INTTAB_CPU5 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_125)); } - .inttab_tc5_07E (__INTTAB_CPU5 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_126)); } - .inttab_tc5_07F (__INTTAB_CPU5 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_127)); } - .inttab_tc5_080 (__INTTAB_CPU5 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_128)); } - .inttab_tc5_081 (__INTTAB_CPU5 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_129)); } - .inttab_tc5_082 (__INTTAB_CPU5 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_130)); } - .inttab_tc5_083 (__INTTAB_CPU5 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_131)); } - .inttab_tc5_084 (__INTTAB_CPU5 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_132)); } - .inttab_tc5_085 (__INTTAB_CPU5 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_133)); } - .inttab_tc5_086 (__INTTAB_CPU5 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_134)); } - .inttab_tc5_087 (__INTTAB_CPU5 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_135)); } - .inttab_tc5_088 (__INTTAB_CPU5 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_136)); } - .inttab_tc5_089 (__INTTAB_CPU5 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_137)); } - .inttab_tc5_08A (__INTTAB_CPU5 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_138)); } - .inttab_tc5_08B (__INTTAB_CPU5 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_139)); } - .inttab_tc5_08C (__INTTAB_CPU5 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_140)); } - .inttab_tc5_08D (__INTTAB_CPU5 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_141)); } - .inttab_tc5_08E (__INTTAB_CPU5 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_142)); } - .inttab_tc5_08F (__INTTAB_CPU5 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_143)); } - .inttab_tc5_090 (__INTTAB_CPU5 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_144)); } - .inttab_tc5_091 (__INTTAB_CPU5 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_145)); } - .inttab_tc5_092 (__INTTAB_CPU5 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_146)); } - .inttab_tc5_093 (__INTTAB_CPU5 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_147)); } - .inttab_tc5_094 (__INTTAB_CPU5 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_148)); } - .inttab_tc5_095 (__INTTAB_CPU5 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_149)); } - .inttab_tc5_096 (__INTTAB_CPU5 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_150)); } - .inttab_tc5_097 (__INTTAB_CPU5 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_151)); } - .inttab_tc5_098 (__INTTAB_CPU5 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_152)); } - .inttab_tc5_099 (__INTTAB_CPU5 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_153)); } - .inttab_tc5_09A (__INTTAB_CPU5 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_154)); } - .inttab_tc5_09B (__INTTAB_CPU5 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_155)); } - .inttab_tc5_09C (__INTTAB_CPU5 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_156)); } - .inttab_tc5_09D (__INTTAB_CPU5 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_157)); } - .inttab_tc5_09E (__INTTAB_CPU5 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_158)); } - .inttab_tc5_09F (__INTTAB_CPU5 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_159)); } - .inttab_tc5_0A0 (__INTTAB_CPU5 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_160)); } - .inttab_tc5_0A1 (__INTTAB_CPU5 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_161)); } - .inttab_tc5_0A2 (__INTTAB_CPU5 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_162)); } - .inttab_tc5_0A3 (__INTTAB_CPU5 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_163)); } - .inttab_tc5_0A4 (__INTTAB_CPU5 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_164)); } - .inttab_tc5_0A5 (__INTTAB_CPU5 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_165)); } - .inttab_tc5_0A6 (__INTTAB_CPU5 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_166)); } - .inttab_tc5_0A7 (__INTTAB_CPU5 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_167)); } - .inttab_tc5_0A8 (__INTTAB_CPU5 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_168)); } - .inttab_tc5_0A9 (__INTTAB_CPU5 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_169)); } - .inttab_tc5_0AA (__INTTAB_CPU5 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_170)); } - .inttab_tc5_0AB (__INTTAB_CPU5 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_171)); } - .inttab_tc5_0AC (__INTTAB_CPU5 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_172)); } - .inttab_tc5_0AD (__INTTAB_CPU5 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_173)); } - .inttab_tc5_0AE (__INTTAB_CPU5 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_174)); } - .inttab_tc5_0AF (__INTTAB_CPU5 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_175)); } - .inttab_tc5_0B0 (__INTTAB_CPU5 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_176)); } - .inttab_tc5_0B1 (__INTTAB_CPU5 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_177)); } - .inttab_tc5_0B2 (__INTTAB_CPU5 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_178)); } - .inttab_tc5_0B3 (__INTTAB_CPU5 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_179)); } - .inttab_tc5_0B4 (__INTTAB_CPU5 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_180)); } - .inttab_tc5_0B5 (__INTTAB_CPU5 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_181)); } - .inttab_tc5_0B6 (__INTTAB_CPU5 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_182)); } - .inttab_tc5_0B7 (__INTTAB_CPU5 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_183)); } - .inttab_tc5_0B8 (__INTTAB_CPU5 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_184)); } - .inttab_tc5_0B9 (__INTTAB_CPU5 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_185)); } - .inttab_tc5_0BA (__INTTAB_CPU5 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_186)); } - .inttab_tc5_0BB (__INTTAB_CPU5 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_187)); } - .inttab_tc5_0BC (__INTTAB_CPU5 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_188)); } - .inttab_tc5_0BD (__INTTAB_CPU5 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_189)); } - .inttab_tc5_0BE (__INTTAB_CPU5 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_190)); } - .inttab_tc5_0BF (__INTTAB_CPU5 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_191)); } - .inttab_tc5_0C0 (__INTTAB_CPU5 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_192)); } - .inttab_tc5_0C1 (__INTTAB_CPU5 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_193)); } - .inttab_tc5_0C2 (__INTTAB_CPU5 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_194)); } - .inttab_tc5_0C3 (__INTTAB_CPU5 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_195)); } - .inttab_tc5_0C4 (__INTTAB_CPU5 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_196)); } - .inttab_tc5_0C5 (__INTTAB_CPU5 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_197)); } - .inttab_tc5_0C6 (__INTTAB_CPU5 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_198)); } - .inttab_tc5_0C7 (__INTTAB_CPU5 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_199)); } - .inttab_tc5_0C8 (__INTTAB_CPU5 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_200)); } - .inttab_tc5_0C9 (__INTTAB_CPU5 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_201)); } - .inttab_tc5_0CA (__INTTAB_CPU5 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_202)); } - .inttab_tc5_0CB (__INTTAB_CPU5 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_203)); } - .inttab_tc5_0CC (__INTTAB_CPU5 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_204)); } - .inttab_tc5_0CD (__INTTAB_CPU5 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_205)); } - .inttab_tc5_0CE (__INTTAB_CPU5 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_206)); } - .inttab_tc5_0CF (__INTTAB_CPU5 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_207)); } - .inttab_tc5_0D0 (__INTTAB_CPU5 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_208)); } - .inttab_tc5_0D1 (__INTTAB_CPU5 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_209)); } - .inttab_tc5_0D2 (__INTTAB_CPU5 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_210)); } - .inttab_tc5_0D3 (__INTTAB_CPU5 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_211)); } - .inttab_tc5_0D4 (__INTTAB_CPU5 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_212)); } - .inttab_tc5_0D5 (__INTTAB_CPU5 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_213)); } - .inttab_tc5_0D6 (__INTTAB_CPU5 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_214)); } - .inttab_tc5_0D7 (__INTTAB_CPU5 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_215)); } - .inttab_tc5_0D8 (__INTTAB_CPU5 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_216)); } - .inttab_tc5_0D9 (__INTTAB_CPU5 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_217)); } - .inttab_tc5_0DA (__INTTAB_CPU5 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_218)); } - .inttab_tc5_0DB (__INTTAB_CPU5 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_219)); } - .inttab_tc5_0DC (__INTTAB_CPU5 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_220)); } - .inttab_tc5_0DD (__INTTAB_CPU5 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_221)); } - .inttab_tc5_0DE (__INTTAB_CPU5 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_222)); } - .inttab_tc5_0DF (__INTTAB_CPU5 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_223)); } - .inttab_tc5_0E0 (__INTTAB_CPU5 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_224)); } - .inttab_tc5_0E1 (__INTTAB_CPU5 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_225)); } - .inttab_tc5_0E2 (__INTTAB_CPU5 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_226)); } - .inttab_tc5_0E3 (__INTTAB_CPU5 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_227)); } - .inttab_tc5_0E4 (__INTTAB_CPU5 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_228)); } - .inttab_tc5_0E5 (__INTTAB_CPU5 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_229)); } - .inttab_tc5_0E6 (__INTTAB_CPU5 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_230)); } - .inttab_tc5_0E7 (__INTTAB_CPU5 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_231)); } - .inttab_tc5_0E8 (__INTTAB_CPU5 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_232)); } - .inttab_tc5_0E9 (__INTTAB_CPU5 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_233)); } - .inttab_tc5_0EA (__INTTAB_CPU5 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_234)); } - .inttab_tc5_0EB (__INTTAB_CPU5 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_235)); } - .inttab_tc5_0EC (__INTTAB_CPU5 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_236)); } - .inttab_tc5_0ED (__INTTAB_CPU5 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_237)); } - .inttab_tc5_0EE (__INTTAB_CPU5 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_238)); } - .inttab_tc5_0EF (__INTTAB_CPU5 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_239)); } - .inttab_tc5_0F0 (__INTTAB_CPU5 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_240)); } - .inttab_tc5_0F1 (__INTTAB_CPU5 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_241)); } - .inttab_tc5_0F2 (__INTTAB_CPU5 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_242)); } - .inttab_tc5_0F3 (__INTTAB_CPU5 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_243)); } - .inttab_tc5_0F4 (__INTTAB_CPU5 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_244)); } - .inttab_tc5_0F5 (__INTTAB_CPU5 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_245)); } - .inttab_tc5_0F6 (__INTTAB_CPU5 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_246)); } - .inttab_tc5_0F7 (__INTTAB_CPU5 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_247)); } - .inttab_tc5_0F8 (__INTTAB_CPU5 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_248)); } - .inttab_tc5_0F9 (__INTTAB_CPU5 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_249)); } - .inttab_tc5_0FA (__INTTAB_CPU5 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_250)); } - .inttab_tc5_0FB (__INTTAB_CPU5 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_251)); } - .inttab_tc5_0FC (__INTTAB_CPU5 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_252)); } - .inttab_tc5_0FD (__INTTAB_CPU5 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_253)); } - .inttab_tc5_0FE (__INTTAB_CPU5 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_254)); } - .inttab_tc5_0FF (__INTTAB_CPU5 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_255)); } - } - - /*Fixed memory Allocations for BMHD*/ - CORE_ID = GLOBAL; - SECTIONS - { - .bmhd_0_org (0xaf400000) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb - .bmhd_1_org (0xaf400200) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb - .bmhd_2_org (0xaf400400) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb - .bmhd_3_org (0xaf400600) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb - .ucb_reserved (0xaf400800) : FLAGS(arl) { } > ucb - .bmhd_0_copy (0xaf401000) : FLAGS(arl) { KEEP (*(.bmhd_0_copy)); } > ucb - .bmhd_1_copy (0xaf401200) : FLAGS(arl) { KEEP (*(.bmhd_1_copy)); } > ucb - .bmhd_2_copy (0xaf401400) : FLAGS(arl) { KEEP (*(.bmhd_2_copy)); } > ucb - .bmhd_3_copy (0xaf401600) : FLAGS(arl) { KEEP (*(.bmhd_3_copy)); } > ucb - } - - /*Near Abbsolute Addressable Data Sections*/ - /*Near Absolute Data, selectable with patterns and user defined sections*/ - CORE_ID = CPU5; - SECTIONS - { - CORE_SEC(.zdata) (LCF_DSPR5_START): FLAGS(awzl) - { - *Ifx_Ssw_Tc5.* (.zdata) - *Cpu5_Main.* (.zdata) - *(.zdata_cpu5) - *(.zdata_cpu5.*) - . = ALIGN(2); - } > dsram5 AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) - { - *Ifx_Ssw_Tc5.* (.zbss) - *Cpu5_Main.* (.zbss) - *(.zbss_cpu5) - *(.zbss_cpu5.*) - } > dsram5 - } - CORE_ID = CPU4; - SECTIONS - { - CORE_SEC(.zdata) (LCF_DSPR4_START): FLAGS(awzl) - { - *Ifx_Ssw_Tc4.* (.zdata) - *Cpu4_Main.* (.zdata) - *(.zdata_cpu4) - *(.zdata_cpu4.*) - . = ALIGN(2); - } > dsram4 AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) - { - *Ifx_Ssw_Tc4.* (.zbss) - *Cpu4_Main.* (.zbss) - *(.zbss_cpu4) - *(.zbss_cpu4.*) - } > dsram4 - } - CORE_ID = CPU3; - SECTIONS - { - CORE_SEC(.zdata) (LCF_DSPR3_START): FLAGS(awzl) - { - *Ifx_Ssw_Tc3.* (.zdata) - *Cpu3_Main.* (.zdata) - *(.zdata_cpu3) - *(.zdata_cpu3.*) - . = ALIGN(2); - } > dsram3 AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) - { - *Ifx_Ssw_Tc3.* (.zbss) - *Cpu3_Main.* (.zbss) - *(.zbss_cpu3) - *(.zbss_cpu3.*) - } > dsram3 - } - CORE_ID = CPU2; - SECTIONS - { - CORE_SEC(.zdata) (LCF_DSPR2_START): FLAGS(awzl) - { - *Ifx_Ssw_Tc2.* (.zdata) - *Cpu2_Main.* (.zdata) - *(.zdata_cpu2) - *(.zdata_cpu2.*) - . = ALIGN(2); - } > dsram2 AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) - { - *Ifx_Ssw_Tc2.* (.zbss) - *Cpu2_Main.* (.zbss) - *(.zbss_cpu2) - *(.zbss_cpu2.*) - } > dsram2 - } - CORE_ID = CPU1; - SECTIONS - { - CORE_SEC(.zdata) (LCF_DSPR1_START): FLAGS(awzl) - { - *Ifx_Ssw_Tc1.* (.zdata) - *Cpu1_Main.* (.zdata) - *(.zdata_cpu1) - *(.zdata_cpu1.*) - . = ALIGN(2); - } > dsram1 AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) - { - *Ifx_Ssw_Tc1.* (.zbss) - *Cpu1_Main.* (.zbss) - *(.zbss_cpu1) - *(.zbss_cpu1.*) - } > dsram1 - } - CORE_ID = CPU0; - SECTIONS - { - CORE_SEC(.zdata) (LCF_DSPR0_START): FLAGS(awzl) - { - *Ifx_Ssw_Tc0.* (.zdata) - *Cpu0_Main.* (.zdata) - *(.zdata_cpu0) - *(.zdata_cpu0.*) - . = ALIGN(2); - } > dsram0 AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) - { - *Ifx_Ssw_Tc0.* (.zbss) - *Cpu0_Main.* (.zbss) - *(.zbss_cpu0) - *(.zbss_cpu0.*) - } > dsram0 - } - - /*Near Absolute Data, selectable by toolchain*/ - CORE_ID = GLOBAL; - SECTIONS - { - CORE_SEC(.zdata_powerOn) : FLAGS(awzl) - { - *(.zdata.dsprPowerOnInit.cpu0.32bit) - *(.zdata.dsprPowerOnInit.cpu0.16bit) - *(.zdata.dsprPowerOnInit.cpu0.8bit) - . = ALIGN(2); - } > default_ram AT> pfls0 - - CORE_SEC(.zdata) : FLAGS(awzl) - { - *(.zdata.dsprInit.cpu0.32bit) - *(.zdata.dsprInit.cpu0.16bit) - *(.zdata.dsprInit.cpu0.8bit) - *(.zdata) - *(.zdata.*) - *(.gnu.linkonce.z.*) - . = ALIGN(2); - } > default_ram AT> pfls0 - - CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz) - { - *(.zbss.dsprPowerOnClear.cpu0.32bit) - *(.zbss.dsprPowerOnClear.cpu0.16bit) - *(.zbss.dsprPowerOnClear.cpu0.8bit) - } > default_ram - - CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz) - { - *(.zbss.dsprNoInit.cpu0.32bit) - *(.zbss.dsprNoInit.cpu0.16bit) - *(.zbss.dsprNoInit.cpu0.8bit) - } > default_ram - - CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) - { - *(.zbss.dsprClearOnInit.cpu0.32bit) - *(.zbss.dsprClearOnInit.cpu0.16bit) - *(.zbss.dsprClearOnInit.cpu0.8bit) - *(.zbss) - *(.zbss.*) - *(.bbss) - *(.bbss.*) - *(.gnu.linkonce.zb.*) - } > default_ram - } - - CORE_ID = GLOBAL; - SECTIONS - { - /*Cpu0_dlmu also is the segment start, all the near lmu data shll be located here*/ - CORE_SEC(.lmuzdata) : FLAGS(awzl) - { - *(.zlmudata) - *(.zlmudata.*) - . = ALIGN(2); - } > cpu0_dlmu AT> pfls0 - - CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) - { - *(.zlmubss) - *(.zlmubss.*) - } > cpu0_dlmu - } - - /*Near Absolute Const, selectable with patterns and user defined sections*/ - CORE_ID = GLOBAL; - SECTIONS - { - CORE_SEC(.zrodata) : FLAGS(arzl) - { - *Ifx_Ssw_Tc?.* (.zrodata) - *Cpu?_Main.* (.zrodata) - *(.zrodata_cpu?) - } > pfls0 - } - - /*Near Absolute Const, selectable by toolchain*/ - CORE_ID = GLOBAL; - SECTIONS - { - CORE_SEC(.zrodata) : FLAGS(arzl) - { - *(.zrodata.const.cpu0.32bit) - *(.zrodata.const.cpu0.16bit) - *(.zrodata.const.cpu0.8bit) - *(.zrodata.config.cpu0.32bit) - *(.zrodata.config.cpu0.16bit) - *(.zrodata.config.cpu0.8bit) - *(.zrodata) - *(.zrodata.*) - } > pfls0 - } - -/*Relative A0/A1/A8/A9 Addressable Sections*/ -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ - /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ - /*Relative A0 Addressable Data, selectable by toolchain*/ - CORE_SEC(.sdata) : FLAGS(awsl) - { - *(.sdata) - *(.sdata.*) - . = ALIGN(2); - } > default_ram AT> pfls0 - CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) - { - *(.sbss) - *(.sbss.*) - } > default_ram - _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; - __A0_MEM = _SMALL_DATA_; -} - -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ - /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ - /*Relative A1 Addressable Const, selectable by toolchain*/ - CORE_SEC(.sdata2) : FLAGS(arsl) - { - *(.srodata) - *(.srodata.*) - } > default_rom - _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; - __A1_MEM = _SMALL_DATA2_; -} - -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - CORE_SEC(.sdata4) : - { - *(.a9sdata) - *(.a9sdata.*) - . = ALIGN(2); - } > lmuram AT> pfls0 - - CORE_SEC(.sbss4) : - { - *(.a9sbss) - *(.a9sbss.*) - } > lmuram - - _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; - __A9_MEM = _SMALL_DATA4_; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ - CORE_SEC(.sdata3) : FLAGS(arsl) - { - *(.rodata_a8) - *(.rodata_a8.*) - } > default_rom - - _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; - __A8_MEM = _SMALL_DATA3_; -} - -/*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ -/*Far Data Sections, selectable with patterns and user defined sections*/ -CORE_ID = CPU5 ; -SECTIONS -{ - /*DSRAM5 Sections*/ - CORE_SEC(.data) : FLAGS(awl) - { - *Ifx_Ssw_Tc5.* (.data) - *Cpu5_Main.* (.data) - *(.data_cpu5) - *(.data_cpu5.*) - . = ALIGN(2); - } > dsram5 AT> pfls0 - - CORE_SEC(.bss) (NOLOAD): FLAGS(aw) - { - *Ifx_Ssw_Tc5.* (.bss) - *Cpu5_Main.* (.bss) - *(.bss_cpu5) - *(.bss_cpu5.*) - } > dsram5 - - /*DLMU5 Sections*/ - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata_cpu5) - *(.lmudata_cpu5.*) - . = ALIGN(2); - } > cpu5_dlmu AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss_cpu5) - *(.lmubss_cpu5.*) - } > cpu5_dlmu -} -CORE_ID = CPU4 ; -SECTIONS -{ - /*DSRAM4 Sections*/ - CORE_SEC(.data) : FLAGS(awl) - { - *Ifx_Ssw_Tc4.* (.data) - *Cpu4_Main.* (.data) - *(.data_cpu4) - *(.data_cpu4.*) - . = ALIGN(2); - } > dsram4 AT> pfls0 - - CORE_SEC(.bss) (NOLOAD): FLAGS(aw) - { - *Ifx_Ssw_Tc4.* (.bss) - *Cpu4_Main.* (.bss) - *(.bss_cpu4) - *(.bss_cpu4.*) - } > dsram4 - - /*DLMU4 Sections*/ - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata_cpu4) - *(.lmudata_cpu4.*) - . = ALIGN(2); - } > cpu4_dlmu AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss_cpu4) - *(.lmubss_cpu4.*) - } > cpu4_dlmu -} -CORE_ID = CPU3 ; -SECTIONS -{ - /*DSRAM3 Sections*/ - CORE_SEC(.data) : FLAGS(awl) - { - *Ifx_Ssw_Tc3.* (.data) - *Cpu3_Main.* (.data) - *(.data_cpu3) - *(.data_cpu3.*) - . = ALIGN(2); - } > dsram3 AT> pfls0 - - CORE_SEC(.bss) (NOLOAD): FLAGS(aw) - { - *Ifx_Ssw_Tc3.* (.bss) - *Cpu3_Main.* (.bss) - *(.bss_cpu3) - *(.bss_cpu3.*) - } > dsram3 - - /*DLMU3 Sections*/ - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata_cpu3) - *(.lmudata_cpu3.*) - . = ALIGN(2); - } > cpu3_dlmu AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss_cpu3) - *(.lmubss_cpu3.*) - } > cpu3_dlmu -} -CORE_ID = CPU2 ; -SECTIONS -{ - /*DSRAM2 Sections*/ - CORE_SEC(.data) : FLAGS(awl) - { - *Ifx_Ssw_Tc2.* (.data) - *Cpu2_Main.* (.data) - *(.data_cpu2) - *(.data_cpu2.*) - . = ALIGN(2); - } > dsram2 AT> pfls0 - - CORE_SEC(.bss) (NOLOAD): FLAGS(aw) - { - *Ifx_Ssw_Tc2.* (.bss) - *Cpu2_Main.* (.bss) - *(.bss_cpu2) - *(.bss_cpu2.*) - } > dsram2 - - /*DLMU2 Sections*/ - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata_cpu2) - *(.lmudata_cpu2.*) - . = ALIGN(2); - } > cpu2_dlmu AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss_cpu2) - *(.lmubss_cpu2.*) - } > cpu2_dlmu -} -CORE_ID = CPU1 ; -SECTIONS -{ - /*DSRAM1 Sections*/ - CORE_SEC(.data) : FLAGS(awl) - { - *Ifx_Ssw_Tc1.* (.data) - *Cpu1_Main.* (.data) - *(.data_cpu1) - *(.data_cpu1.*) - . = ALIGN(2); - } > dsram1 AT> pfls0 - - CORE_SEC(.bss) (NOLOAD): FLAGS(aw) - { - *Ifx_Ssw_Tc1.* (.bss) - *Cpu1_Main.* (.bss) - *(.bss_cpu1) - *(.bss_cpu1.*) - } > dsram1 - - /*DLMU1 Sections*/ - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata_cpu1) - *(.lmudata_cpu1.*) - . = ALIGN(2); - } > cpu1_dlmu AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss_cpu1) - *(.lmubss_cpu1.*) - } > cpu1_dlmu -} -CORE_ID = CPU0 ; -SECTIONS -{ - /*DSRAM0 Sections*/ - CORE_SEC(.data) : FLAGS(awl) - { - *Ifx_Ssw_Tc0.* (.data) - *Cpu0_Main.* (.data) - *(.data_cpu0) - *(.data_cpu0.*) - . = ALIGN(2); - } > dsram0 AT> pfls0 - - CORE_SEC(.bss) (NOLOAD): FLAGS(aw) - { - *Ifx_Ssw_Tc0.* (.bss) - *Cpu0_Main.* (.bss) - *(.bss_cpu0) - *(.bss_cpu0.*) - } > dsram0 - - /*DLMU0 Sections*/ - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata_cpu0) - *(.lmudata_cpu0.*) - . = ALIGN(2); - } > cpu0_dlmu AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss_cpu0) - *(.lmubss_cpu0.*) - } > cpu0_dlmu -} - -/*Far Data Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.bss_noClear) (NOLOAD) : FLAGS(aw) - { - *(.bss.farDsprNoInit.cpu0.32bit) - *(.bss.farDsprNoInit.cpu0.16bit) - *(.bss.farDsprNoInit.cpu0.8bit) - } > default_ram - - CORE_SEC(.data) : FLAGS(awl) - { - *(.data.farDsprInit.cpu0.32bit) - *(.data.farDsprInit.cpu0.16bit) - *(.data.farDsprInit.cpu0.8bit) - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(2); - } > default_ram AT> pfls0 - - CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) - { - *(.bss.farDsprClearOnInit.cpu0.32bit) - *(.bss.farDsprClearOnInit.cpu0.16bit) - *(.bss.farDsprClearOnInit.cpu0.8bit) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - } > default_ram - - .heap : FLAGS(aw) - { - . = ALIGN(4); - __HEAP = .; - . += LCF_HEAP_SIZE; - __HEAP_END = .; - } > default_ram - - CORE_SEC(.lmudata) : FLAGS(awl) - { - *(.lmudata) - *(.lmudata.*) - . = ALIGN(2); - } > lmuram AT> pfls0 - - CORE_SEC(.lmubss) : FLAGS(aw) - { - *(.lmubss) - *(.lmubss.*) - } > lmuram -} -/*Far Const Sections, selectable with patterns and user defined sections*/ -CORE_ID = CPU0; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *Ifx_Ssw_Tc0.* (.rodata) - *Cpu0_Main.* (.rodata) - *(.rodata_cpu0) - *(.rodata_cpu0.*) - } > pfls0 -} - -CORE_ID = CPU1; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *Ifx_Ssw_Tc1.* (.rodata) - *Cpu1_Main.* (.rodata) - *(.rodata_cpu1) - *(.rodata_cpu1.*) - } > pfls1 -} - -CORE_ID = CPU2; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *Ifx_Ssw_Tc2.* (.rodata) - *Cpu2_Main.* (.rodata) - *(.rodata_cpu2) - *(.rodata_cpu2.*) - } > pfls2 -} - -CORE_ID = CPU3; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *Ifx_Ssw_Tc3.* (.rodata) - *Cpu3_Main.* (.rodata) - *(.rodata_cpu3) - *(.rodata_cpu3.*) - } > pfls3 -} - -CORE_ID = CPU4; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *Ifx_Ssw_Tc4.* (.rodata) - *Cpu4_Main.* (.rodata) - *(.rodata_cpu4) - *(.rodata_cpu4.*) - } > pfls4 -} - -CORE_ID = CPU5; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *Ifx_Ssw_Tc5.* (.rodata) - *Cpu5_Main.* (.rodata) - *(.rodata_cpu5) - *(.rodata_cpu5.*) - } > pfls5 -} - -/*Far Const Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *(.rodata.farConst.cpu0.32bit) - *(.rodata.farConst.cpu0.16bit) - *(.rodata.farConst.cpu0.8bit) - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - /* - * Create the clear and copy tables that tell the startup code - * which memory areas to clear and to copy, respectively. - */ - . = ALIGN(4) ; - PROVIDE(__clear_table = .); - LONG(0 + ADDR(.CPU5.zbss)); LONG(SIZEOF(.CPU5.zbss)); - LONG(0 + ADDR(.CPU5.bss)); LONG(SIZEOF(.CPU5.bss)); - LONG(0 + ADDR(.CPU5.lmubss)); LONG(SIZEOF(.CPU5.lmubss)); - LONG(0 + ADDR(.CPU4.zbss)); LONG(SIZEOF(.CPU4.zbss)); - LONG(0 + ADDR(.CPU4.bss)); LONG(SIZEOF(.CPU4.bss)); - LONG(0 + ADDR(.CPU4.lmubss)); LONG(SIZEOF(.CPU4.lmubss)); - LONG(0 + ADDR(.CPU3.zbss)); LONG(SIZEOF(.CPU3.zbss)); - LONG(0 + ADDR(.CPU3.bss)); LONG(SIZEOF(.CPU3.bss)); - LONG(0 + ADDR(.CPU3.lmubss)); LONG(SIZEOF(.CPU3.lmubss)); - LONG(0 + ADDR(.CPU2.zbss)); LONG(SIZEOF(.CPU2.zbss)); - LONG(0 + ADDR(.CPU2.bss)); LONG(SIZEOF(.CPU2.bss)); - LONG(0 + ADDR(.CPU2.lmubss)); LONG(SIZEOF(.CPU2.lmubss)); - LONG(0 + ADDR(.CPU1.zbss)); LONG(SIZEOF(.CPU1.zbss)); - LONG(0 + ADDR(.CPU1.bss)); LONG(SIZEOF(.CPU1.bss)); - LONG(0 + ADDR(.CPU1.lmubss)); LONG(SIZEOF(.CPU1.lmubss)); - LONG(0 + ADDR(.CPU0.zbss)); LONG(SIZEOF(.CPU0.zbss)); - LONG(0 + ADDR(.CPU0.bss)); LONG(SIZEOF(.CPU0.bss)); - LONG(0 + ADDR(.CPU0.lmubss)); LONG(SIZEOF(.CPU0.lmubss)); - LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); - LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); - LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); - LONG(0 + ADDR(.lmubss)); LONG(SIZEOF(.lmubss)); - LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); - LONG(-1); LONG(-1); - PROVIDE(__clear_table_powerOn = .); - LONG(0 + ADDR(.zbss_powerOn)); LONG(SIZEOF(.zbss_powerOn)); - LONG(-1); LONG(-1); - PROVIDE(__copy_table = .); - LONG(LOADADDR(.CPU5.zdata)); LONG(0 + ADDR(.CPU5.zdata)); LONG(SIZEOF(.CPU5.zdata)); - LONG(LOADADDR(.CPU5.data)); LONG(0 + ADDR(.CPU5.data)); LONG(SIZEOF(.CPU5.data)); - LONG(LOADADDR(.CPU5.lmudata)); LONG(0 + ADDR(.CPU5.lmudata)); LONG(SIZEOF(.CPU5.lmudata)); - LONG(LOADADDR(.CPU4.zdata)); LONG(0 + ADDR(.CPU4.zdata)); LONG(SIZEOF(.CPU4.zdata)); - LONG(LOADADDR(.CPU4.data)); LONG(0 + ADDR(.CPU4.data)); LONG(SIZEOF(.CPU4.data)); - LONG(LOADADDR(.CPU4.lmudata)); LONG(0 + ADDR(.CPU4.lmudata)); LONG(SIZEOF(.CPU4.lmudata)); - LONG(LOADADDR(.CPU3.zdata)); LONG(0 + ADDR(.CPU3.zdata)); LONG(SIZEOF(.CPU3.zdata)); - LONG(LOADADDR(.CPU3.data)); LONG(0 + ADDR(.CPU3.data)); LONG(SIZEOF(.CPU3.data)); - LONG(LOADADDR(.CPU3.lmudata)); LONG(0 + ADDR(.CPU3.lmudata)); LONG(SIZEOF(.CPU3.lmudata)); - LONG(LOADADDR(.CPU2.zdata)); LONG(0 + ADDR(.CPU2.zdata)); LONG(SIZEOF(.CPU2.zdata)); - LONG(LOADADDR(.CPU2.data)); LONG(0 + ADDR(.CPU2.data)); LONG(SIZEOF(.CPU2.data)); - LONG(LOADADDR(.CPU2.lmudata)); LONG(0 + ADDR(.CPU2.lmudata)); LONG(SIZEOF(.CPU2.lmudata)); - LONG(LOADADDR(.CPU1.zdata)); LONG(0 + ADDR(.CPU1.zdata)); LONG(SIZEOF(.CPU1.zdata)); - LONG(LOADADDR(.CPU1.data)); LONG(0 + ADDR(.CPU1.data)); LONG(SIZEOF(.CPU1.data)); - LONG(LOADADDR(.CPU1.lmudata)); LONG(0 + ADDR(.CPU1.lmudata)); LONG(SIZEOF(.CPU1.lmudata)); - LONG(LOADADDR(.CPU0.zdata)); LONG(0 + ADDR(.CPU0.zdata)); LONG(SIZEOF(.CPU0.zdata)); - LONG(LOADADDR(.CPU0.data)); LONG(0 + ADDR(.CPU0.data)); LONG(SIZEOF(.CPU0.data)); - LONG(LOADADDR(.CPU0.lmudata)); LONG(0 + ADDR(.CPU0.lmudata)); LONG(SIZEOF(.CPU0.lmudata)); - LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); - LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); - LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); - LONG(LOADADDR(.lmudata)); LONG(0 + ADDR(.lmudata)); LONG(SIZEOF(.lmudata)); - LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); - LONG(LOADADDR(.CPU0.psram_text)); LONG(0 + ADDR(.CPU0.psram_text)); LONG(SIZEOF(.CPU0.psram_text)); - LONG(LOADADDR(.CPU1.psram_text)); LONG(0 + ADDR(.CPU1.psram_text)); LONG(SIZEOF(.CPU1.psram_text)); - LONG(LOADADDR(.CPU2.psram_text)); LONG(0 + ADDR(.CPU2.psram_text)); LONG(SIZEOF(.CPU2.psram_text)); - LONG(LOADADDR(.CPU3.psram_text)); LONG(0 + ADDR(.CPU3.psram_text)); LONG(SIZEOF(.CPU3.psram_text)); - LONG(LOADADDR(.CPU4.psram_text)); LONG(0 + ADDR(.CPU4.psram_text)); LONG(SIZEOF(.CPU4.psram_text)); - LONG(LOADADDR(.CPU5.psram_text)); LONG(0 + ADDR(.CPU5.psram_text)); LONG(SIZEOF(.CPU5.psram_text)); - LONG(-1); LONG(-1); LONG(-1); - PROVIDE(__copy_table_powerOn = .) ; - LONG(LOADADDR(.zdata_powerOn)); LONG(0 + ADDR(.zdata_powerOn)); LONG(SIZEOF(.zdata_powerOn)); - LONG(-1); LONG(-1); LONG(-1); - . = ALIGN(8); - } > default_rom -} - -/*Code selections*/ -/*Code Sections, selectable with patterns and user defined sections*/ -CORE_ID = CPU0; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(2); - *Ifx_Ssw_Tc0.*(.text) - *Cpu0_Main.*(.text) - *Ifx_Ssw_Tc0.*(.text.*) - *Cpu0_Main.*(.text.*) - *(.text_cpu0) - *(.text_cpu0.*) - } > pfls0 - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - .init : - { - PROVIDE(__init_start = .); - KEEP(*(.init)) - KEEP(*(.init*)) - PROVIDE(__init_end = .); - . = ALIGN(8); - - } > pfls0 - - .fini : - { - PROVIDE(__fini_start = .); - KEEP(*(.fini)) - KEEP(*(.fini*)) - PROVIDE(__fini_end = .); - . = ALIGN(8); - } > pfls0 - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - CORE_SEC(.psram_text) : FLAGS(awx) - { - . = ALIGN(2); - *(.psram_text_cpu0) - *(.psram_text_cpu0.*) - *(.cpu0_psram) - *(.cpu0_psram.*) - . = ALIGN(2); - } > psram0 AT> pfls0 -} - -CORE_ID = CPU1; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(2); - *Ifx_Ssw_Tc1.*(.text) - *Cpu1_Main.*(.text) - *Ifx_Ssw_Tc1.*(.text.*) - *Cpu1_Main.*(.text.*) - *(.text_cpu1) - *(.text_cpu1.*) - } > pfls1 - - CORE_SEC(.psram_text) : FLAGS(awx) - { - . = ALIGN(2); - *(.psram_text_cpu1) - *(.psram_text_cpu1.*) - *(.cpu1_psram) - *(.cpu1_psram.*) - . = ALIGN(2); - } > psram1 AT> pfls1 -} - -CORE_ID = CPU2; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(2); - *Ifx_Ssw_Tc2.*(.text) - *Cpu2_Main.*(.text) - *Ifx_Ssw_Tc2.*(.text.*) - *Cpu2_Main.*(.text.*) - *(.text_cpu2) - *(.text_cpu2.*) - } > pfls2 - - CORE_SEC(.psram_text) : FLAGS(awx) - { - . = ALIGN(2); - *(.psram_text_cpu2) - *(.psram_text_cpu2.*) - *(.cpu2_psram) - *(.cpu2_psram.*) - . = ALIGN(2); - } > psram2 AT> pfls2 -} - -CORE_ID = CPU3; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(2); - *Ifx_Ssw_Tc3.*(.text) - *Cpu3_Main.*(.text) - *Ifx_Ssw_Tc3.*(.text.*) - *Cpu3_Main.*(.text.*) - *(.text_cpu3) - *(.text_cpu3.*) - } > pfls3 - - CORE_SEC(.psram_text) : FLAGS(awx) - { - . = ALIGN(2); - *(.psram_text_cpu3) - *(.psram_text_cpu3.*) - *(.cpu3_psram) - *(.cpu3_psram.*) - . = ALIGN(2); - } > psram3 AT> pfls3 -} - -CORE_ID = CPU4; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(2); - *Ifx_Ssw_Tc4.*(.text) - *Cpu4_Main.*(.text) - *Ifx_Ssw_Tc4.*(.text.*) - *Cpu4_Main.*(.text.*) - *(.text_cpu4) - *(.text_cpu4.*) - } > pfls4 - - CORE_SEC(.psram_text) : FLAGS(awx) - { - . = ALIGN(2); - *(.psram_text_cpu4) - *(.psram_text_cpu4.*) - *(.cpu4_psram) - *(.cpu4_psram.*) - . = ALIGN(2); - } > psram4 AT> pfls4 -} - -CORE_ID = CPU5; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(2); - *Ifx_Ssw_Tc5.*(.text) - *Cpu5_Main.*(.text) - *Ifx_Ssw_Tc5.*(.text.*) - *Cpu5_Main.*(.text.*) - *(.text_cpu5) - *(.text_cpu5.*) - } > pfls5 - - CORE_SEC(.psram_text) : FLAGS(awx) - { - . = ALIGN(2); - *(.psram_text_cpu5) - *(.psram_text_cpu5.*) - *(.cpu5_psram) - *(.cpu5_psram.*) - . = ALIGN(2); - } > psram5 AT> pfls5 -} - -/*Code Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.text) : FLAGS(axl) - { - *(.text.fast.pfls.cpu0) - *(.text.slow.pfls.cpu0) - *(.text.5ms.pfls.cpu0) - *(.text.10ms.pfls.cpu0) - *(.text.callout.pfls.cpu0) - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ - . = ALIGN(4); - } > default_rom - - /* - * C++ exception handling tables. NOTE: gcc emits .eh_frame - * sections when compiling C sources with debugging enabled (-g). - * If you can be sure that your final application consists - * exclusively of C objects (i.e., no C++ objects), you may use - * the -R option of the "strip" and "objcopy" utilities to remove - * the .eh_frame section from the executable. - */ - .eh_frame : - { - *(.gcc_except_table) - __EH_FRAME_BEGIN__ = . ; - KEEP (*(.eh_frame)) - __EH_FRAME_END__ = . ; - . = ALIGN(8); - } > default_rom - - /* - * Constructors and destructors. - */ - .ctors : FLAGS(ar) - { - __CTOR_LIST__ = . ; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2); - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - LONG(0) ; - __CTOR_END__ = . ; - . = ALIGN(8); - } > default_rom - .dtors : FLAGS(ar) - { - __DTOR_LIST__ = . ; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------Start----------------------------------------- - */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------End----------------------------------------- - */ - LONG(0) ; - __DTOR_END__ = . ; - . = ALIGN(8); - } > default_rom - /* - * DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the - * beginning of the section, so we begin them at 0. - */ - /* - * DWARF 1 - */ - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* - * GNU DWARF 1 extensions - */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* - * DWARF 1.1 and DWARF 2 - */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* - * DWARF 2 - */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_ranges 0 : { *(.debug_ranges) } - /* - * SGI/MIPS DWARF 2 extensions - */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* - * Optional sections that may only appear when relocating. - */ - /* - * Optional sections that may appear regardless of relocating. - */ - .version_info 0 : { *(.version_info) } - .boffs 0 : { KEEP (*(.boffs)) } -} - diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel new file mode 100644 index 00000000000..23a9c438f71 --- /dev/null +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel @@ -0,0 +1,554 @@ +/**************************************************************************** + * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +#define __JOIN2(x,y) x##y +#define JOIN2(x,y) __JOIN2(x,y) +#define __JOIN3(x,y,z) x##y##z +#define JOIN3(x,y,z) __JOIN3(x,y,z) +#define __JOIN4(x,y,z,w) x##y##z##w +#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) + +#define COREID_LST(x) JOIN2(x, CONFIG_CPU_COREID) +#define COREID_MID(x,y) JOIN3(x, CONFIG_CPU_COREID, y) + +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") +#if CONFIG_CPU_COREID == 0 +ENTRY(_START) +#endif + +__TRICORE_DERIVATE_MEMORY_MAP__ = 0x390; + +LCF_PFLASH_KERNEL_START = GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID); +LCF_PFLASH_KERNEL_SIZE = GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_DSPR_KERNEL_START = GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID); +LCF_DSPR_KERNEL_SIZE = GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_PSPR_KERNEL_START = GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID); +LCF_PSPR_KERNEL_SIZE = GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_DLMU_KERNEL_START = GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID); +LCF_DLMU_KERNEL_SIZE = GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_KSTACK_START = GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID); +LCF_KSTACK_SIZE = GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID); + +LCF_CSA_SIZE = 40k; +LCF_USTACK_SIZE = CONFIG_IDLETHREAD_STACKSIZE; +LCF_ISTACK_SIZE = CONFIG_ARCH_INTERRUPTSTACK; + +LCF_CSA_OFFSET = (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE); +LCF_ISTACK_OFFSET = (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE); +LCF_USTACK_OFFSET = (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE); + +LCF_STARTPTR = LCF_PFLASH_KERNEL_START; +LCF_STARTPTR_NC = NC_START(LCF_STARTPTR); +LCF_TRAPVEC_START = LCF_STARTPTR + 0x100; + +COREID_LST(__INTTAB_CPU) = LCF_PFLASH_KERNEL_START; + +LCF_STARTPTR_NC_CPU0 = NC_START(CORE0_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU1 = NC_START(CORE1_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU2 = NC_START(CORE2_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU3 = NC_START(CORE3_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU4 = NC_START(CORE4_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU5 = NC_START(CORE5_PFLASH_KERNEL_START); +RESET = CORE0_PFLASH_KERNEL_START; + +MEMORY +{ + kstack (w!xp): org = LCF_KSTACK_START, len = LCF_KSTACK_SIZE + + dspr (w!xp): org = LCF_DSPR_KERNEL_START, len = LCF_DSPR_KERNEL_SIZE + pspr (w!xp): org = LCF_PSPR_KERNEL_START, len = LCF_PSPR_KERNEL_SIZE + + psram_local (w!xp): org = PSPR_LOCAL_START, len = LCF_PSPR_KERNEL_SIZE + + pfls (rx!p): org = LCF_PFLASH_KERNEL_START, len = LCF_PFLASH_KERNEL_SIZE + pfls_nc (rx!p): org = NC_START(LCF_PFLASH_KERNEL_START), len = LCF_PFLASH_KERNEL_SIZE + + ucb (rx!p): org = 0xAF400000, len = 24K + + cpu_dlmu (w!xp): org = LCF_DLMU_KERNEL_START, len = LCF_DLMU_KERNEL_SIZE + cpu_dlmu_nc (w!xp): org = NC_START(LCF_DLMU_KERNEL_START), len = LCF_DLMU_KERNEL_SIZE +} + +/* map cached and non cached addresses */ +REGION_MIRROR("pfls", "pfls_nc") +REGION_MIRROR("cpu_dlmu", "cpu_dlmu_nc") + +/*Sections located at absolute fixed address*/ +/*Fixed memory Allocations for stack memory*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.ustack) (LCF_DSPR_KERNEL_START + LCF_USTACK_OFFSET): + { + PROVIDE(__USTACK_END = .); + PROVIDE(COREID_MID(__USTACK, _END) = .); + . = . + LCF_USTACK_SIZE; + PROVIDE(__USTACK = .); + PROVIDE(COREID_LST(__USTACK) = .); + } + + CORE_SEC(.istack) (LCF_DSPR_KERNEL_START + LCF_ISTACK_OFFSET): + { + PROVIDE(__ISTACK_END = .); + PROVIDE(COREID_MID(__ISTACK, _END) = .); + . = . + LCF_ISTACK_SIZE; + PROVIDE(__ISTACK = .); + PROVIDE(COREID_LST(__ISTACK) = .); + } + CORE_SEC(.csa) (LCF_DSPR_KERNEL_START + LCF_CSA_OFFSET): + { + PROVIDE(COREID_LST(__CSA) = .); + . = . + LCF_CSA_SIZE; + PROVIDE(COREID_MID(__CSA, _END) = .); + } +} + +/*Fixed memory Allocations for _START*/ +CORE_ID = GLOBAL ; +SECTIONS +{ + .start_tc (LCF_STARTPTR) : FLAGS(rxl) + { + KEEP (*(.start)); + KEEP (*(.start_cpu?)); + } > pfls + + .interface_const (LCF_STARTPTR + 0x20) : + { + __IF_CONST = .; + KEEP (*(.interface_const)); + } > pfls + + PROVIDE(__START = LCF_STARTPTR); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU3 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 1); +} + +/*Fixed memory Allocations for Trap Vector Table*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .traptab_tc (LCF_TRAPVEC_START) : + { + PROVIDE(COREID_LST(__TRAPTAB_CPU) = .); + KEEP (*(.COREID_LST(traptab_cpu))); + } > pfls +} + +/*Fixed memory Allocations for _START1 to 5 */ +CORE_ID = GLOBAL ; +SECTIONS +{ + PROVIDE(__START1 = CORE1_PFLASH_KERNEL_START); + PROVIDE(__START2 = CORE2_PFLASH_KERNEL_START); + PROVIDE(__START3 = CORE3_PFLASH_KERNEL_START); + PROVIDE(__START4 = CORE4_PFLASH_KERNEL_START); + PROVIDE(__START5 = CORE5_PFLASH_KERNEL_START); +} + +/*Fixed memory Allocations for Interrupt Vector Table*/ +SECTIONS +{ + /*Interrupt Vector Table*/ + .COREID_MID(inttab_tc, _0FF) (COREID_LST(__INTTAB_CPU) + 0x1FE0) : + { + . = ALIGN(8); + KEEP (*(.COREID_MID(intvec_tc, _255))); + . = ALIGN(0x2000); + } > pfls +} + +/* Fixed memory Allocations for BMHD*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .bmhd_0_org (0xaf400000) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb + .bmhd_1_org (0xaf400200) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb + .bmhd_2_org (0xaf400400) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb + .bmhd_3_org (0xaf400600) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb +} + +/*Relative A0/A1/A8/A9 Addressable Sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ + /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A0 Addressable Data, selectable by toolchain*/ + CORE_SEC(.sdata) : FLAGS(awsl) + { + *(.sdata) + *(.sdata.*) + . = ALIGN(4); + } > dspr AT> pfls + + CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) + { + *(.sbss) + *(.sbss.*) + } > dspr + _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; + __A0_MEM = _SMALL_DATA_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ + /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A1 Addressable Const, selectable by toolchain*/ + CORE_SEC(.sdata2) : FLAGS(arsl) + { + *(.srodata) + *(.srodata.*) + } > pfls + _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; + __A1_MEM = _SMALL_DATA2_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata4) : + { + *(.a9sdata) + *(.a9sdata.*) + . = ALIGN(4); + } > dspr AT> pfls + + CORE_SEC(.sbss4) (NOLOAD) : + { + *(.a9sbss) + *(.a9sbss.*) + } > dspr + + _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; + __A9_MEM = _SMALL_DATA4_; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata3) : FLAGS(arsl) + { + *(.rodata_a8) + *(.rodata_a8.*) + } > pfls + + _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; + __A8_MEM = _SMALL_DATA3_; +} + +/*kstack*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) + { + *(.dtcm_stack) + *(.dtcm_stack.*) + } > kstack +} + +/*data&bss*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.dspr_data) : FLAGS(awzl) + { + *Ifx_Ssw_Tc?.* (.data) + *Cpu?_Main.* (.data.*) + . = ALIGN(4); + } > dspr AT> pfls + + CORE_SEC(.dspr_bss) (NOLOAD) : FLAGS(awz) + { + *Ifx_Ssw_Tc?.* (.bss) + *Cpu?_Main.* (.bss.*) + . = ALIGN(4); + } > dspr + + CORE_SEC(.zdata) : FLAGS(awzl) + { + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.z.*) + . = ALIGN(4); + } > dspr AT> pfls + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + } > dspr + + CORE_SEC(.data) : FLAGS(awl) + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(4); + } > dspr AT> pfls + + CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) + { + *(.bss) + *(.bss.*) + *(.lmubss_cpu?) + *(.lmubss_cpu?.*) + *(.gnu.linkonce.b.*) + } > dspr +} + +/*Heap*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .heap (NOLOAD) : FLAGS(aw) + { + . = ALIGN(4); + _sheap = ABSOLUTE(.); + _eheap = ABSOLUTE(__USTACK_END); + } > dspr +} + +/*rodata*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + /* + * Create the clear and copy tables that tell the startup code + * which memory areas to clear and to copy, respectively. + */ + . = ALIGN(4) ; + PROVIDE(__clear_table = .); + LONG(0 + ADDR(.dspr_bss)); LONG(SIZEOF(.dspr_bss)); + LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); + LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); + LONG(-1); LONG(-1); + PROVIDE(__clear_table_powerOn = .); + LONG(-1); LONG(-1); + PROVIDE(__copy_table = .); + LONG(LOADADDR(.dspr_data)); LONG(0 + ADDR(.dspr_data)); LONG(SIZEOF(.dspr_data)); + LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); + LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); + LONG(LOADADDR(.psram_text)); LONG(0 + ADDR(.psram_text)); LONG(SIZEOF(.psram_text)); + LONG(-1); LONG(-1); LONG(-1); + PROVIDE(__copy_table_powerOn = .) ; + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(8); + } > pfls +} + +/*Code selections*/ +/*Code Sections, selectable with patterns and user defined sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *Ifx_Ssw_Tc?.* (.zrodata) + *Cpu?_Main.* (.zrodata) + *(.zrodata_cpu?) + *(.zrodata) + *(.zrodata.*) + } > pfls + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + .init : + { + PROVIDE(__init_start = .); + KEEP(*(.init)) + KEEP(*(.init*)) + PROVIDE(__init_end = .); + . = ALIGN(8); + + } > pfls + + .fini : + { + PROVIDE(__fini_start = .); + KEEP(*(.fini)) + KEEP(*(.fini*)) + PROVIDE(__fini_end = .); + . = ALIGN(8); + } > pfls + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + CORE_SEC(.psram_text) : FLAGS(awxl) + { + . = ALIGN(4); + *aurix_mtd_flash.*(.text) + *aurix_mtd_flash.*(.text.*) + *aurix_mtd_partition.*(.text) + *aurix_mtd_partition.*(.text.*) + . = ALIGN(4); + } > pspr AT> pfls + + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(4); + *Ifx_Ssw_Tc?.*(.text) + *Cpu?_Main.*(.text) + *Ifx_Ssw_Tc?.*(.text.*) + *Cpu?_Main.*(.text.*) + *(.text) + *(.text.*) + *(.gcc_except_table) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(8); + } > pfls + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : ALIGN(8) + { + KEEP (*(.eh_frame_hdr)) + . = ALIGN(8); + } > pfls + + .eh_frame : ALIGN(8) + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > pfls + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + _sinit = ABSOLUTE(.); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + _einit = ABSOLUTE(.); + . = ALIGN(8); + } > pfls + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > pfls + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user new file mode 100644 index 00000000000..42ddc47b3ff --- /dev/null +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user @@ -0,0 +1,264 @@ +/**************************************************************************** + * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") + +LCF_PFLASH_USER_START = GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID); +LCF_PFLASH_USER_SIZE = GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID); +LCF_DLMU_USER_START = GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID); +LCF_DLMU_USER_SIZE = GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID); +LCF_USTACK_START = GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID); +LCF_USTACK_SIZE = GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID); + +MEMORY +{ + upfls (rx!p): org = LCF_PFLASH_USER_START, len = LCF_PFLASH_USER_SIZE + upfls_nc (rx!p): org = NC_START(LCF_PFLASH_USER_START), len = LCF_PFLASH_USER_SIZE + + cpu_udlmu (w!xp): org = LCF_DLMU_USER_START, len = LCF_DLMU_USER_SIZE + cpu_udlmu_nc (w!xp): org = NC_START(LCF_DLMU_USER_START), len = LCF_DLMU_USER_SIZE + + ustack (w!xp): org = LCF_USTACK_START, len = LCF_USTACK_SIZE +} + +/* map cached and non cached addresses */ +REGION_MIRROR("upfls", "upfls_nc") +REGION_MIRROR("cpu_udlmu", "cpu_udlmu_nc") + +/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ + +/*Code Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .userspace : ALIGN(64) + { + _suserspace = ABSOLUTE(.); + KEEP(*(.userspace)) + . = ALIGN(64); /* userspace align to 64 to keep the address continuous for MBF */ + _euserspace = ABSOLUTE(.); + } > upfls + + CORE_SEC(.text) : FLAGS(axl) + { + _stext = ABSOLUTE(.); + *(.text) + *(.text.*) + *(.zrodata) + *(.zrodata.*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.gcc_except_table) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(4); + _etext = ABSOLUTE(.); + } > upfls + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : ALIGN(8) + { + KEEP (*(.eh_frame_hdr)) + . = ALIGN(8); + } > upfls + + .eh_frame : ALIGN(8) + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > upfls + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + _sinit = ABSOLUTE(.); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + _einit = ABSOLUTE(.); + . = ALIGN(8); + } > upfls + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > upfls + + _eronly = ABSOLUTE(.); + + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} + +/*Far Data Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) + { + *(.dtcm_stack) + *(.dtcm_stack.*) + } > ustack + + CORE_SEC(.data) : FLAGS(awzl) + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.z.*) + . = ALIGN(2); + _edata = ABSOLUTE(.); + } > cpu_udlmu AT> upfls + + CORE_SEC(.bss) (NOLOAD): FLAGS(awz) + { + _sbss = ABSOLUTE(.); + *(.bss) + *(.bss.*) + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > cpu_udlmu + + .heap (NOLOAD) : FLAGS(aw) + { + _sheap = ABSOLUTE(.); + _eheap = ABSOLUTE(LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE); + } > cpu_udlmu + + _sdata_pflash = LOADADDR(.data); +} + +#if CONFIG_CPU_COREID == 5 +/* This sections is added to reserve last 4 bytes of flash in core5's user + * space. This is because the car's diagnostic service will query this area, + * and if the area has been erased but not written to, the query will cause + * an exception. Since the page size of pflash is 32 bytes, we reserve 32 + * bytes instead of 4 bytes. + */ + +CORE_ID = GLOBAL; +SECTIONS +{ + .flash_reserve (LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) : { + . = ALIGN(32); + FILL(0x55); + . = . + 28; + LONG(0x55555555); + } > upfls +} +#endif diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl deleted file mode 100644 index 0cb345caf48..00000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl +++ /dev/null @@ -1,1478 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include - -#define LCF_CSA0_SIZE 40k -#define LCF_USTACK0_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK0_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_CSA1_SIZE 40k -#define LCF_USTACK1_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK1_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_CSA2_SIZE 40k -#define LCF_USTACK2_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK2_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_CSA3_SIZE 40k -#define LCF_USTACK3_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK3_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_CSA4_SIZE 40k -#define LCF_USTACK4_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK4_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_CSA5_SIZE 40k -#define LCF_USTACK5_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK5_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_HEAP_SIZE 4k - -#define LCF_CPU0 0 -#define LCF_CPU1 1 -#define LCF_CPU2 2 -#define LCF_CPU3 3 -#define LCF_CPU4 4 -#define LCF_CPU5 5 - - -/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ -#define LCF_DEFAULT_HOST LCF_CPU0 -/*#define LCF_DEFAULT_HOST LCF_CPU1*/ -/*#define LCF_DEFAULT_HOST LCF_CPU2*/ -/*#define LCF_DEFAULT_HOST LCF_CPU3*/ -/*#define LCF_DEFAULT_HOST LCF_CPU4*/ -/*#define LCF_DEFAULT_HOST LCF_CPU5*/ - -#define LCF_DSPR5_START 0x10000000 -#define LCF_DSPR5_SIZE 96k - -#define LCF_DSPR4_START 0x30000000 -#define LCF_DSPR4_SIZE 96k - -#define LCF_DSPR3_START 0x40000000 -#define LCF_DSPR3_SIZE 96k - -#define LCF_DSPR2_START 0x50000000 -#define LCF_DSPR2_SIZE 96k - -#define LCF_DSPR1_START 0x60000000 -#define LCF_DSPR1_SIZE 240k - -#define LCF_DSPR0_START 0x70000000 -#define LCF_DSPR0_SIZE 240k - -#define LCF_CSA5_OFFSET (LCF_DSPR5_SIZE - 1k - LCF_CSA5_SIZE) -#define LCF_ISTACK5_OFFSET (LCF_CSA5_OFFSET - 256 - LCF_ISTACK5_SIZE) -#define LCF_USTACK5_OFFSET (LCF_ISTACK5_OFFSET - 256 - LCF_USTACK5_SIZE) - -#define LCF_CSA4_OFFSET (LCF_DSPR4_SIZE - 1k - LCF_CSA4_SIZE) -#define LCF_ISTACK4_OFFSET (LCF_CSA4_OFFSET - 256 - LCF_ISTACK4_SIZE) -#define LCF_USTACK4_OFFSET (LCF_ISTACK4_OFFSET - 256 - LCF_USTACK4_SIZE) - -#define LCF_CSA3_OFFSET (LCF_DSPR3_SIZE - 1k - LCF_CSA3_SIZE) -#define LCF_ISTACK3_OFFSET (LCF_CSA3_OFFSET - 256 - LCF_ISTACK3_SIZE) -#define LCF_USTACK3_OFFSET (LCF_ISTACK3_OFFSET - 256 - LCF_USTACK3_SIZE) - -#define LCF_CSA2_OFFSET (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE) -#define LCF_ISTACK2_OFFSET (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE) -#define LCF_USTACK2_OFFSET (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE) - -#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE) -#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE) -#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE) - -#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE) -#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE) -#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE) - -#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP2_OFFSET (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP3_OFFSET (LCF_USTACK3_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP4_OFFSET (LCF_USTACK4_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP5_OFFSET (LCF_USTACK5_OFFSET - LCF_HEAP_SIZE) - -#define LCF_INTVEC0_START 0x802FE000 -#define LCF_INTVEC1_START 0x805FE000 -#define LCF_INTVEC2_START 0x808FE000 -#define LCF_INTVEC3_START 0x80BFE000 -#define LCF_INTVEC4_START 0x80EFE000 -#define LCF_INTVEC5_START 0x80FFE000 - -#define LCF_TRAPVEC0_START 0x80000100 -#define LCF_TRAPVEC1_START 0x80300000 -#define LCF_TRAPVEC2_START 0x80600000 -#define LCF_TRAPVEC3_START 0x80900000 -#define LCF_TRAPVEC4_START 0x80C00000 -#define LCF_TRAPVEC5_START 0x80F00000 - -#define LCF_STARTPTR_CPU0 0x80000000 -#define LCF_STARTPTR_CPU1 0x80300100 -#define LCF_STARTPTR_CPU2 0x80600100 -#define LCF_STARTPTR_CPU3 0x80900100 -#define LCF_STARTPTR_CPU4 0x80C00100 -#define LCF_STARTPTR_CPU5 0x80F00100 - -#define LCF_STARTPTR_NC_CPU0 0xA0000000 -#define LCF_STARTPTR_NC_CPU1 0xA0300100 -#define LCF_STARTPTR_NC_CPU2 0xA0600100 -#define LCF_STARTPTR_NC_CPU3 0xA0900100 -#define LCF_STARTPTR_NC_CPU4 0xA0C00100 -#define LCF_STARTPTR_NC_CPU5 0xA0F00100 - -#define INTTAB0 (LCF_INTVEC0_START) -#define INTTAB1 (LCF_INTVEC1_START) -#define INTTAB2 (LCF_INTVEC2_START) -#define INTTAB3 (LCF_INTVEC3_START) -#define INTTAB4 (LCF_INTVEC4_START) -#define INTTAB5 (LCF_INTVEC5_START) -#define TRAPTAB0 (LCF_TRAPVEC0_START) -#define TRAPTAB1 (LCF_TRAPVEC1_START) -#define TRAPTAB2 (LCF_TRAPVEC2_START) -#define TRAPTAB3 (LCF_TRAPVEC3_START) -#define TRAPTAB4 (LCF_TRAPVEC4_START) -#define TRAPTAB5 (LCF_TRAPVEC5_START) - -#define RESET LCF_STARTPTR_NC_CPU0 - -#include "tc1v1_6_2.lsl" - -// Specify a multi-core processor environment (mpe) - -processor mpe -{ - derivative = tc39; -} - -derivative tc39 -{ - core tc0 - { - architecture = TC1V1.6.2; - space_id_offset = 100; // add 100 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc1 // core 1 TC16E - { - architecture = TC1V1.6.2; - space_id_offset = 200; // add 200 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc2 // core 2 TC16P - { - architecture = TC1V1.6.2; - space_id_offset = 300; // add 300 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc3 // core 3 TC16P - { - architecture = TC1V1.6.2; - space_id_offset = 400; // add 300 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc4 // core 4 TC16P - { - architecture = TC1V1.6.2; - space_id_offset = 500; // add 300 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc5 // core 5 TC16P - { - architecture = TC1V1.6.2; - space_id_offset = 600; // add 300 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core vtc - { - architecture = TC1V1.6.2; - import tc0; // add all address spaces of core tc0 to core vtc for linking and locating - import tc1; // tc1 - import tc2; // tc2 - import tc3; // tc3 - import tc4; // tc4 - import tc5; // tc5 - } - - bus sri - { - mau = 8; - width = 32; - - // map shared addresses one-to-one to real cores and virtual cores - map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc2:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc3:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc4:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc5:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - } - - memory dsram5 // Data Scratch Pad Ram - { - mau = 8; - size = 96k; - type = ram; - map (dest=bus:tc5:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); - map (dest=bus:sri, dest_offset=0x10000000, size=96k); - } - - memory psram5 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc5:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x10100000, size=64k); - } - - memory dsram4 // Data Scratch Pad Ram - { - mau = 8; - size = 96k; - type = ram; - map (dest=bus:tc4:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); - map (dest=bus:sri, dest_offset=0x30000000, size=96k); - } - - memory psram4 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc4:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x30100000, size=64k); - } - - memory dsram3 // Data Scratch Pad Ram - { - mau = 8; - size = 96k; - type = ram; - map (dest=bus:tc3:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); - map (dest=bus:sri, dest_offset=0x40000000, size=96k); - } - - memory psram3 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc3:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x40100000, size=64k); - } - - memory dsram2 // Data Scratch Pad Ram - { - mau = 8; - size = 96k; - type = ram; - map (dest=bus:tc2:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); - map (dest=bus:sri, dest_offset=0x50000000, size=96k); - } - - memory psram2 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc2:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x50100000, size=64k); - } - - memory dsram1 // Data Scratch Pad Ram - { - mau = 8; - size = 240k; - type = ram; - map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); - map (dest=bus:sri, dest_offset=0x60000000, size=240k); - } - - memory psram1 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x60100000, size=64k); - } - - memory dsram0 // Data Scratch Pad Ram - { - mau = 8; - size = 240k; - type = ram; - map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); - map (dest=bus:sri, dest_offset=0x70000000, size=240k); - } - - memory psram0 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x70100000, size=64k); - } - - memory pfls0 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80000000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=3M); - } - - memory pfls1 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80300000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0300000, reserved, size=3M); - } - - memory pfls2 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80600000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0600000, reserved, size=3M); - } - - memory pfls3 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80900000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0900000, reserved, size=3M); - } - - memory pfls4 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80c00000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0c00000, reserved, size=3M); - } - - memory pfls5 - { - mau = 8; - size = 1M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80f00000, size=1M); - map not_cached (dest=bus:sri, dest_offset=0xa0f00000, reserved, size=1M); - } - - memory dfls0 - { - mau = 8; - size = 1M; - type = reserved nvram; - map (dest=bus:sri, dest_offset=0xaf000000, size=1M ); - } - - memory ucb - { - mau = 8; - size = 24k; - type = rom; - map (dest=bus:sri, dest_offset=0xaf400000, reserved, size=24k); - } - - memory cpu0_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90000000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=64k); - } - - memory cpu1_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90010000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0010000, reserved, size=64k); - } - - memory cpu2_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90020000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0020000, reserved, size=64k); - } - - memory cpu3_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90030000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0030000, reserved, size=64k); - } - - memory lmuram - { - mau = 8; - size = 768K; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90040000, size=768K); - map not_cached (dest=bus:sri, dest_offset=0xb0040000, reserved, size=768K); - } - - memory cpu4_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90100000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0100000, reserved, size=64k); - } - - memory cpu5_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90110000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0110000, reserved, size=64k); - } - - memory edmem - { - mau = 8; - size = 4M; - type = ram; - map (dest=bus:sri, dest_offset=0x99000000, size=4M); - map (dest=bus:sri, dest_offset=0xb9000000, reserved, size=4M); - } - -#if (__VERSION__ >= 6003) - section_setup :vtc:linear - { - heap "heap" (min_size = (1k), fixed, align = 8); - } -#endif - - section_setup :vtc:linear - { - start_address - ( - symbol = "_START" - ); - } - - section_setup :vtc:linear - { - stack "ustack_tc0" (min_size = 1k, fixed, align = 8); - stack "istack_tc0" (min_size = 1k, fixed, align = 8); - stack "ustack_tc1" (min_size = 1k, fixed, align = 8); - stack "istack_tc1" (min_size = 1k, fixed, align = 8); - stack "ustack_tc2" (min_size = 1k, fixed, align = 8); - stack "istack_tc2" (min_size = 1k, fixed, align = 8); - stack "ustack_tc3" (min_size = 1k, fixed, align = 8); - stack "istack_tc3" (min_size = 1k, fixed, align = 8); - stack "ustack_tc4" (min_size = 1k, fixed, align = 8); - stack "istack_tc4" (min_size = 1k, fixed, align = 8); - stack "ustack_tc5" (min_size = 1k, fixed, align = 8); - stack "istack_tc5" (min_size = 1k, fixed, align = 8); - } - - /*Section setup for the copy table*/ - section_setup :vtc:linear - { - copytable - ( - align = 4, - dest = linear, - table - { - symbol = "_lc_ub_table_tc0"; - space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa; - }, - table - { - symbol = "_lc_ub_table_tc1"; - space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa; - }, - table - { - symbol = "_lc_ub_table_tc2"; - space = :tc2:linear, :tc2:abs24, :tc2:abs18, :tc2:csa; - }, - table - { - symbol = "_lc_ub_table_tc3"; - space = :tc3:linear, :tc3:abs24, :tc3:abs18, :tc3:csa; - }, - table - { - symbol = "_lc_ub_table_tc4"; - space = :tc4:linear, :tc4:abs24, :tc4:abs18, :tc4:csa; - }, - table - { - symbol = "_lc_ub_table_tc5"; - space = :tc5:linear, :tc5:abs24, :tc5:abs18, :tc5:csa; - } - ); - } - - /*Sections located at absolute fixed address*/ - - section_layout :vtc:linear - { - /*Fixed memory Allocations for stack memory and CSA*/ - group (ordered) - { - group ustack5(align = 8, run_addr = mem:dsram5[LCF_USTACK5_OFFSET]) - { - stack "ustack_tc5" (size = LCF_USTACK5_SIZE); - } - "__USTACK5":= sizeof(group:ustack5) > 0 ? "_lc_ue_ustack_tc5" : 0; - "__USTACK5_END"="_lc_gb_ustack5"; - - group istack5(align = 8, run_addr = mem:dsram5[LCF_ISTACK5_OFFSET]) - { - stack "istack_tc5" (size = LCF_ISTACK5_SIZE); - } - "__ISTACK5":= sizeof(group:istack5) > 0 ? "_lc_ue_istack_tc5" : 0; - "__ISTACK5_END"="_lc_gb_istack5"; - - group (align = 64, attributes=rw, run_addr=mem:dsram5[LCF_CSA5_OFFSET]) - reserved "csa_tc5" (size = LCF_CSA5_SIZE); - "__CSA5":= "_lc_ub_csa_tc5"; - "__CSA5_END":= "_lc_ue_csa_tc5"; - } - group (ordered) - { - group ustack4(align = 8, run_addr = mem:dsram4[LCF_USTACK4_OFFSET]) - { - stack "ustack_tc4" (size = LCF_USTACK4_SIZE); - } - "__USTACK4":= sizeof(group:ustack4) > 0 ? "_lc_ue_ustack_tc4" : 0; - "__USTACK4_END"="_lc_gb_ustack4"; - - group istack4(align = 8, run_addr = mem:dsram4[LCF_ISTACK4_OFFSET]) - { - stack "istack_tc4" (size = LCF_ISTACK4_SIZE); - } - "__ISTACK4":= sizeof(group:istack4) > 0 ? "_lc_ue_istack_tc4" : 0; - "__ISTACK4_END"="_lc_gb_istack4"; - - group (align = 64, attributes=rw, run_addr=mem:dsram4[LCF_CSA4_OFFSET]) - reserved "csa_tc4" (size = LCF_CSA4_SIZE); - "__CSA4":= "_lc_ub_csa_tc4"; - "__CSA4_END":= "_lc_ue_csa_tc4"; - } - group (ordered) - { - group ustack3(align = 8, run_addr = mem:dsram3[LCF_USTACK3_OFFSET]) - { - stack "ustack_tc3" (size = LCF_USTACK3_SIZE); - } - "__USTACK3":= sizeof(group:ustack3) > 0 ? "_lc_ue_ustack_tc3" : 0; - "__USTACK3_END"="_lc_gb_ustack3"; - - group istack3(align = 8, run_addr = mem:dsram3[LCF_ISTACK3_OFFSET]) - { - stack "istack_tc3" (size = LCF_ISTACK3_SIZE); - } - "__ISTACK3":= sizeof(group:istack3) > 0 ? "_lc_ue_istack_tc3" : 0; - "__ISTACK3_END"="_lc_gb_istack3"; - - group (align = 64, attributes=rw, run_addr=mem:dsram3[LCF_CSA3_OFFSET]) - reserved "csa_tc3" (size = LCF_CSA3_SIZE); - "__CSA3":= "_lc_ub_csa_tc3"; - "__CSA3_END":= "_lc_ue_csa_tc3"; - } - group (ordered) - { - group ustack2(align = 8, run_addr = mem:dsram2[LCF_USTACK2_OFFSET]) - { - stack "ustack_tc2" (size = LCF_USTACK2_SIZE); - } - "__USTACK2":= sizeof(group:ustack2) > 0 ? "_lc_ue_ustack_tc2" : 0; - "__USTACK2_END"="_lc_gb_ustack2"; - - group istack2(align = 8, run_addr = mem:dsram2[LCF_ISTACK2_OFFSET]) - { - stack "istack_tc2" (size = LCF_ISTACK2_SIZE); - } - "__ISTACK2":= sizeof(group:istack2) > 0 ? "_lc_ue_istack_tc2" : 0; - "__ISTACK2_END"="_lc_gb_istack2"; - - group (align = 64, attributes=rw, run_addr=mem:dsram2[LCF_CSA2_OFFSET]) - reserved "csa_tc2" (size = LCF_CSA2_SIZE); - "__CSA2":= "_lc_ub_csa_tc2"; - "__CSA2_END":= "_lc_ue_csa_tc2"; - } - group (ordered) - { - group ustack1(align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET]) - { - stack "ustack_tc1" (size = LCF_USTACK1_SIZE); - } - "__USTACK1":= sizeof(group:ustack1) > 0 ? "_lc_ue_ustack_tc1" : 0; - "__USTACK1_END"="_lc_gb_ustack1"; - - group istack1(align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET]) - { - stack "istack_tc1" (size = LCF_ISTACK1_SIZE); - } - "__ISTACK1":= sizeof(group:istack1) > 0 ? "_lc_ue_istack_tc1" : 0; - "__ISTACK1_END"="_lc_gb_istack1"; - - group (align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET]) - reserved "csa_tc1" (size = LCF_CSA1_SIZE); - "__CSA1":= "_lc_ub_csa_tc1"; - "__CSA1_END":= "_lc_ue_csa_tc1"; - } - group (ordered) - { - group ustack0(align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET]) - { - stack "ustack_tc0" (size = LCF_USTACK0_SIZE); - } - "__USTACK0":= sizeof(group:ustack0) > 0 ? "_lc_ue_ustack_tc0" : 0; - "__USTACK0_END"="_lc_gb_ustack0"; - - group istack0(align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET]) - { - stack "istack_tc0" (size = LCF_ISTACK0_SIZE); - } - "__ISTACK0":= sizeof(group:istack0) > 0 ? "_lc_ue_istack_tc0" : 0; - "__ISTACK0_END"="_lc_gb_istack0"; - - group (align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) - reserved "csa_tc0" (size = LCF_CSA0_SIZE); - "__CSA0":= "_lc_ub_csa_tc0"; - "__CSA0_END":= "_lc_ue_csa_tc0"; - } - - /*Fixed memory Allocations for _START*/ - group (ordered) - { - group reset (run_addr=RESET) - { - section "reset" ( size = 0x20, fill = 0x0800, attributes = r ) - { - select ".text.start"; - } - } - group interface_const (run_addr=mem:pfls0[0x0020]) - { - select "*.interface_const"; - } - "__IF_CONST" := addressof(group:interface_const); - "__START0" := LCF_STARTPTR_NC_CPU0; - "__START1" := LCF_STARTPTR_NC_CPU1; - "__START2" := LCF_STARTPTR_NC_CPU2; - "__START3" := LCF_STARTPTR_NC_CPU3; - "__START4" := LCF_STARTPTR_NC_CPU4; - "__START5" := LCF_STARTPTR_NC_CPU5; - } - - /*Fixed memory Allocations for Trap Vector Table*/ - group (ordered) - { - group trapvec_tc0 (align = 8, run_addr=LCF_TRAPVEC0_START) - { - section "trapvec_tc0" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu0*)"; - } - } - group trapvec_tc1 (align = 8, run_addr=LCF_TRAPVEC1_START) - { - section "trapvec_tc1" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu1*)"; - } - } - group trapvec_tc2 (align = 8, run_addr=LCF_TRAPVEC2_START) - { - section "trapvec_tc2" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu2*)"; - } - } - group trapvec_tc3 (align = 8, run_addr=LCF_TRAPVEC3_START) - { - section "trapvec_tc3" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu3*)"; - } - } - group trapvec_tc4 (align = 8, run_addr=LCF_TRAPVEC4_START) - { - section "trapvec_tc4" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu4*)"; - } - } - group trapvec_tc5 (align = 8, run_addr=LCF_TRAPVEC5_START) - { - section "trapvec_tc5" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu5*)"; - } - } - "__TRAPTAB_CPU0" := TRAPTAB0; - "__TRAPTAB_CPU1" := TRAPTAB1; - "__TRAPTAB_CPU2" := TRAPTAB2; - "__TRAPTAB_CPU3" := TRAPTAB3; - "__TRAPTAB_CPU4" := TRAPTAB4; - "__TRAPTAB_CPU5" := TRAPTAB5; - } - - /*Fixed memory Allocations for Start up code*/ - group (ordered) - { - group start_tc0 (run_addr=LCF_STARTPTR_NC_CPU0) - { - select "(.text.start_cpu0*)"; - } - group start_tc1 (run_addr=LCF_STARTPTR_NC_CPU1) - { - select "(.text.start_cpu1*)"; - } - group start_tc2 (run_addr=LCF_STARTPTR_NC_CPU2) - { - select "(.text.start_cpu2*)"; - } - group start_tc3 (run_addr=LCF_STARTPTR_NC_CPU3) - { - select "(.text.start_cpu3*)"; - } - group start_tc4 (run_addr=LCF_STARTPTR_NC_CPU4) - { - select "(.text.start_cpu4*)"; - } - group start_tc5 (run_addr=LCF_STARTPTR_NC_CPU5) - { - select "(.text.start_cpu5*)"; - } - "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 0; - "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 0; - "__ENABLE_INDIVIDUAL_C_INIT_CPU3" := 0; - "__ENABLE_INDIVIDUAL_C_INIT_CPU4" := 0; - "__ENABLE_INDIVIDUAL_C_INIT_CPU5" := 0; - } - - /*Fixed memory Allocations for Interrupt Vector Table*/ - group (ordered) - { - group int_tab_tc0 (ordered) - { -# include "inttab0.lsl" - } - group int_tab_tc1 (ordered) - { -# include "inttab1.lsl" - } - group int_tab_tc2 (ordered) - { -# include "inttab2.lsl" - } - group int_tab_tc3 (ordered) - { -# include "inttab3.lsl" - } - group int_tab_tc4 (ordered) - { -# include "inttab4.lsl" - } - group int_tab_tc5 (ordered) - { -# include "inttab5.lsl" - } - "_lc_u_int_tab" = (LCF_INTVEC0_START); - "__INTTAB_CPU0" = (LCF_INTVEC0_START); - "__INTTAB_CPU1" = (LCF_INTVEC1_START); - "__INTTAB_CPU2" = (LCF_INTVEC2_START); - "__INTTAB_CPU3" = (LCF_INTVEC3_START); - "__INTTAB_CPU4" = (LCF_INTVEC4_START); - "__INTTAB_CPU5" = (LCF_INTVEC5_START); - } - - /*Fixed memory Allocations for BMHD*/ - group (ordered) - { - group bmh_0_orig (run_addr=mem:ucb[0x0000]) - { - select ".rodata.bmhd_0_orig"; - } - group bmh_1_orig (run_addr=mem:ucb[0x0200]) - { - select ".rodata.bmhd_1_orig"; - } - group bmh_2_orig (run_addr=mem:ucb[0x0400]) - { - select ".rodata.bmhd_2_orig"; - } - group bmh_3_orig (run_addr=mem:ucb[0x0600]) - { - select ".rodata.bmhd_3_orig"; - } - group bmh_blank (run_addr=mem:ucb[0x0800]) - { - } - group bmh_0_copy (run_addr=mem:ucb[0x1000]) - { - select ".rodata.bmhd_0_copy"; - } - group bmh_1_copy (run_addr=mem:ucb[0x1200]) - { - select ".rodata.bmhd_1_copy"; - } - group bmh_2_copy (run_addr=mem:ucb[0x1400]) - { - select ".rodata.bmhd_2_copy"; - } - group bmh_3_copy (run_addr=mem:ucb[0x1600]) - { - select ".rodata.bmhd_3_copy"; - } - } - } - - /*Near Abbsolute Addressable Data Sections*/ - section_layout :vtc:abs18 - { - /*Near Absolute Data, selectable with patterns and user defined sections*/ - group - { - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) - { - select "(.zdata.zdata_cpu5|.zdata.zdata_cpu5.*)"; - select "(.zbss.zbss_cpu5|.zbss.zbss_cpu5.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) - { - select "(.zdata.zdata_cpu4|.zdata.zdata_cpu4.*)"; - select "(.zbss.zbss_cpu4|.zbss.zbss_cpu4.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) - { - select "(.zdata.zdata_cpu3|.zdata.zdata_cpu3.*)"; - select "(.zbss.zbss_cpu3|.zbss.zbss_cpu3.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) - { - select "(.zdata.zdata_cpu2|.zdata.zdata_cpu2.*)"; - select "(.zbss.zbss_cpu2|.zbss.zbss_cpu2.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) - { - select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1.*)"; - select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) - { - select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0.*)"; - select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0.*)"; - } - - group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) - { - select "(.zdata.zlmudata|.zdata.zlmudata.*)"; - select "(.zbss.zlmubss|.zbss.zlmubss.*)"; - } - } - - /*Near Absolute Data, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) -# endif - { - group zdata_mcal(attributes=rw) - { - select ".zdata.dsprInit.cpu0.32bit"; - select ".zdata.dsprInit.cpu0.16bit"; - select ".zdata.dsprInit.cpu0.8bit"; - } - - group zdata_powerOn(attributes=rw) - { - select ".zdata.dsprPowerOnInit.cpu0.32bit"; - select ".zdata.dsprPowerOnInit.cpu0.16bit"; - select ".zdata.dsprPowerOnInit.cpu0.8bit"; - } - - group zbss_mcal(attributes=rw) - { - select ".zbss.dsprClearOnInit.cpu0.32bit"; - select ".zbss.dsprClearOnInit.cpu0.16bit"; - select ".zbss.dsprClearOnInit.cpu0.8bit"; - } - - group zbss_noClear(attributes=rw) - { - select ".zbss.dsprNoInit.cpu0.32bit"; - select ".zbss.dsprNoInit.cpu0.16bit"; - select ".zbss.dsprNoInit.cpu0.8bit"; - } - - group zbss_powerOn(attributes=rw) - { - select ".zbss.dsprPowerOnClear.cpu0.32bit"; - select ".zbss.dsprPowerOnClear.cpu0.16bit"; - select ".zbss.dsprPowerOnClear.cpu0.8bit"; - } - - group zdata(attributes=rw) - { - select "(.zdata|.zdata.*)"; - select "(.zbss|.zbss.*)"; - } - } - - /*Near Absolute Const, selectable with patterns and user defined sections*/ - group - { - group (ordered, align = 4, contiguous, run_addr=mem:pfls0) - { - select ".zrodata.Ifx_Ssw_Tc0.*"; - select ".zrodata.Ifx_Ssw_Tc1.*"; - select ".zrodata.Ifx_Ssw_Tc2.*"; - select ".zrodata.Ifx_Ssw_Tc3.*"; - select ".zrodata.Ifx_Ssw_Tc4.*"; - select ".zrodata.Ifx_Ssw_Tc5.*"; - select ".zrodata.Cpu0_Main.*"; - select ".zrodata.Cpu1_Main.*"; - select ".zrodata.Cpu2_Main.*"; - select ".zrodata.Cpu3_Main.*"; - select ".zrodata.Cpu4_Main.*"; - select ".zrodata.Cpu5_Main.*"; - - /*Near Absolute Const, selectable by toolchain*/ - select ".zrodata.const.cpu0.32bit"; - select ".zrodata.const.cpu0.16bit"; - select ".zrodata.const.cpu0.8bit"; - select ".zrodata.config.cpu0.32bit"; - select ".zrodata.config.cpu0.16bit"; - select ".zrodata.config.cpu0.8bit"; - select "(.zrodata|.zrodata.*)"; - } - } - } - - /*Relative A0/A1/A8/A9 Addressable Sections*/ - section_layout :vtc:linear - { - /*Relative A0 Addressable Data, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) -# endif - { - select "(.data_a0.sdata|.data_a0.sdata.*)"; - select "(.bss_a0.sbss|.bss_a0.sbss.*)"; - } - "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; - "__A0_MEM" = "_SMALL_DATA_"; - - /*Relative A1 Addressable Const, selectable by toolchain*/ - /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group a1 (ordered, align = 4, run_addr=mem:pfls5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group a1 (ordered, align = 4, run_addr=mem:pfls4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group a1 (ordered, align = 4, run_addr=mem:pfls3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group a1 (ordered, align = 4, run_addr=mem:pfls2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group a1 (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group a1 (ordered, align = 4, run_addr=mem:pfls0) -# endif - { - select "(.rodata_a1.srodata|.rodata_a1.srodata.*)"; - select "(.ldata|.ldata.*)"; - } - "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; - "__A1_MEM" = "_LITERAL_DATA_"; - - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - group a9 (ordered, align = 4, run_addr=mem:lmuram) - { - select "(.data_a9.a9sdata|.data_a9.a9sdata.*)"; - select "(.bss_a9.a9sbss|.bss_a9.a9sbss.*)"; - } - "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; - "__A9_MEM" = "_A9_DATA_"; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group a8 (ordered, align = 4, run_addr=mem:pfls5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group a8 (ordered, align = 4, run_addr=mem:pfls4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group a8 (ordered, align = 4, run_addr=mem:pfls3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group a8 (ordered, align = 4, run_addr=mem:pfls2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group a8 (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group a8 (ordered, align = 4, run_addr=mem:pfls0) -# endif - { - select "(.rodata_a8.a8srodata|.rodata_a8.a8srodata.*)"; - } - "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; - "__A8_MEM" = "_A8_DATA_"; - } - - /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ - section_layout :vtc:linear - { - /*Far Data Sections, selectable with patterns and user defined sections*/ - group - { - /*DSRAM sections*/ - group - { - group (ordered, attributes=rw, run_addr=mem:dsram5) - { - select ".data.Ifx_Ssw_Tc5.*"; - select ".data.Cpu5_Main.*"; - select "(.data.data_cpu5|.data.data_cpu5.*)"; - select ".bss.Ifx_Ssw_Tc5.*"; - select ".bss.Cpu5_Main.*"; - select "(.bss.bss_cpu5|.bss.bss_cpu5.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram4) - { - select ".data.Ifx_Ssw_Tc4.*"; - select ".data.Cpu4_Main.*"; - select "(.data.data_cpu4|.data.data_cpu4.*)"; - select ".bss.Ifx_Ssw_Tc4.*"; - select ".bss.Cpu4_Main.*"; - select "(.bss.bss_cpu4|.bss.bss_cpu4.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram3) - { - select ".data.Ifx_Ssw_Tc3.*"; - select ".data.Cpu3_Main.*"; - select "(.data.data_cpu3|.data.data_cpu3.*)"; - select ".bss.Ifx_Ssw_Tc3.*"; - select ".bss.Cpu3_Main.*"; - select "(.bss.bss_cpu3|.bss.bss_cpu3.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram2) - { - select ".data.Ifx_Ssw_Tc2.*"; - select ".data.Cpu2_Main.*"; - select "(.data.data_cpu2|.data.data_cpu2.*)"; - select ".bss.Ifx_Ssw_Tc2.*"; - select ".bss.Cpu2_Main.*"; - select "(.bss.bss_cpu2|.bss.bss_cpu2.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram1) - { - select ".data.Ifx_Ssw_Tc1.*"; - select ".data.Cpu1_Main.*"; - select "(.data.data_cpu1|.data.data_cpu1.*)"; - select ".bss.Ifx_Ssw_Tc1.*"; - select ".bss.Cpu1_Main.*"; - select "(.bss.bss_cpu1|.bss.bss_cpu1.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram0) - { - select ".data.Ifx_Ssw_Tc0.*"; - select ".data.Cpu0_Main.*"; - select "(.data.data_cpu0|.data.data_cpu0.*)"; - select ".bss.Ifx_Ssw_Tc0.*"; - select ".bss.Cpu0_Main.*"; - select "(.bss.bss_cpu0|.bss.bss_cpu0.*)"; - } - } - - /*LMU Data sections*/ - group - { - group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) - { - select "(.data.lmudata_cpu0|.data.lmudata_cpu0.*)"; - select "(.bss.lmubss_cpu0|.bss.lmubss_cpu0.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu1_dlmu) - { - select "(.data.lmudata_cpu1|.data.lmudata_cpu1.*)"; - select "(.bss.lmubss_cpu1|.bss.lmubss_cpu1.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu2_dlmu) - { - select "(.data.lmudata_cpu2|.data.lmudata_cpu2.*)"; - select "(.bss.lmubss_cpu2|.bss.lmubss_cpu2.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu3_dlmu) - { - select "(.data.lmudata_cpu3|.data.lmudata_cpu3.*)"; - select "(.bss.lmubss_cpu3|.bss.lmubss_cpu3.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu4_dlmu) - { - select "(.data.lmudata_cpu4|.data.lmudata_cpu4.*)"; - select "(.bss.lmubss_cpu4|.bss.lmubss_cpu4.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu5_dlmu) - { - select "(.data.lmudata_cpu5|.data.lmudata_cpu5.*)"; - select "(.bss.lmubss_cpu5|.bss.lmubss_cpu5.*)"; - } - group (ordered, attributes=rw, run_addr=mem:lmuram) - { - select "(.data.lmudata|.data.lmudata.*)"; - select "(.bss.lmubss|.bss.lmubss.*)"; - } - } - } - - /*Far Data Sections, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) -# endif - { - group data_mcal(attributes=rw) - { - select ".data.farDsprInit.cpu0.32bit"; - select ".data.farDsprInit.cpu0.16bit"; - select ".data.farDsprInit.cpu0.8bit"; - } - - group bss_mcal(attributes=rw) - { - select ".bss.farDsprClearOnInit.cpu0.32bit"; - select ".bss.farDsprClearOnInit.cpu0.16bit"; - select ".bss.farDsprClearOnInit.cpu0.8bit"; - } - - group bss_noInit(attributes=rw) - { - select ".bss.farDsprNoInit.cpu0.32bit"; - select ".bss.farDsprNoInit.cpu0.16bit"; - select ".bss.farDsprNoInit.cpu0.8bit"; - } - - group data(attributes=rw) - { - select "(.data|.data.*)"; - select "(.bss|.bss.*)"; - } - } - - /*Heap allocation*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group (ordered, align = 4, run_addr = mem:dsram5[LCF_HEAP5_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group (ordered, align = 4, run_addr = mem:dsram4[LCF_HEAP4_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group (ordered, align = 4, run_addr = mem:dsram3[LCF_HEAP3_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, align = 4, run_addr = mem:dsram2[LCF_HEAP2_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET]) -# endif - { - heap "heap" (size = LCF_HEAP_SIZE); - } - - /*Far Const Sections, selectable with patterns and user defined sections*/ - group - { - group (ordered, align = 4, run_addr=mem:pfls0) - { - select ".rodata.Ifx_Ssw_Tc0.*"; - select ".rodata.Cpu0_Main.*"; - select "(.rodata.rodata_cpu0|.rodata.rodata_cpu0.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls1) - { - select ".rodata.Cpu1_Main.*"; - select ".rodata.Ifx_Ssw_Tc1.*"; - select "(.rodata.rodata_cpu1|.rodata.rodata_cpu1.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls2) - { - select ".rodata.Ifx_Ssw_Tc2.*"; - select ".rodata.Cpu2_Main.*"; - select "(.rodata.rodata_cpu2|.rodata.rodata_cpu2.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls3) - { - select ".rodata.Ifx_Ssw_Tc3.*"; - select ".rodata.Cpu3_Main.*"; - select "(.rodata.rodata_cpu3|.rodata.rodata_cpu3.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls4) - { - select ".rodata.Ifx_Ssw_Tc4.*"; - select ".rodata.Cpu4_Main.*"; - select "(.rodata.rodata_cpu4|.rodata.rodata_cpu4.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls5) - { - select ".rodata.Ifx_Ssw_Tc5.*"; - select ".rodata.Cpu5_Main.*"; - select "(.rodata.rodata_cpu5|.rodata.rodata_cpu5.*)"; - } - } - - /*Far Const Sections, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group (ordered, align = 4, run_addr=mem:pfls5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group ordered, align = 4, run_addr=mem:pfls4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group (ordered, align = 4, run_addr=mem:pfls3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, align = 4, run_addr=mem:pfls2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, align = 4, run_addr=mem:pfls0) -# endif - { - select ".rodata.farConst.cpu0.32bit"; - select ".rodata.farConst.cpu0.16bit"; - select ".rodata.farConst.cpu0.8bit"; - select "(.rodata|.rodata.*)"; - } - } - - /* PSRAM Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Program Scratchpad Sections*/ - group - { - group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0) - { - select "(.text.cpu0_psram|.text.cpu0_psram.*)"; - select "(.text.psram_text_cpu0|.text.psram_text_cpu0.*)"; - } - group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1) - { - select "(.text.cpu1_psram|.text.cpu1_psram.*)"; - select "(.text.psram_text_cpu1|.text.psram_text_cpu1.*)"; - } - group code_psram2 (ordered, attributes=rwx, copy, run_addr=mem:psram2) - { - select "(.text.cpu2_psram|.text.cpu2_psram.*)"; - select "(.text.psram_text_cpu2|.text.psram_text_cpu2.*)"; - } - group code_psram3 (ordered, attributes=rwx, copy, run_addr=mem:psram3) - { - select "(.text.cpu3_psram|.text.cpu3_psram.*)"; - select "(.text.psram_text_cpu3|.text.psram_text_cpu3.*)"; - } - group code_psram4 (ordered, attributes=rwx, copy, run_addr=mem:psram4) - { - select "(.text.cpu4_psram|.text.cpu4_psram.*)"; - select "(.text.psram_text_cpu4|.text.psram_text_cpu4.*)"; - } - group code_psram5 (ordered, attributes=rwx, copy, run_addr=mem:psram5) - { - select "(.text.cpu5_psram|.text.cpu5_psram.*)"; - select "(.text.psram_text_cpu5|.text.psram_text_cpu5.*)"; - } - } - } - } - - /* FLS Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Cpu specific PFLASH Sections*/ - group - { - group (ordered, align = 4, run_addr=mem:pfls0) - { - select ".text.Ifx_Ssw_Tc0.*"; - select ".text.Cpu0_Main.*"; - select ".text.CompilerTasking.Ifx_C_Init"; - select "(.text.text_cpu0|.text.text_cpu0.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls1) - { - select ".text.Ifx_Ssw_Tc1.*"; - select ".text.Cpu1_Main.*"; - select "(.text.text_cpu1|.text.text_cpu1.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls2) - { - select ".text.Ifx_Ssw_Tc2.*"; - select ".text.Cpu2_Main.*"; - select "(.text.text_cpu2|.text.text_cpu2.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls3) - { - select ".text.Ifx_Ssw_Tc3.*"; - select ".text.Cpu3_Main.*"; - select "(.text.text_cpu3|.text.text_cpu3.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls4) - { - select ".text.Ifx_Ssw_Tc4.*"; - select ".text.Cpu4_Main.*"; - select ".text.text_cpu4*"; - select "(.text.text_cpu4|.text.text_cpu4.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls5) - { - select ".text.Ifx_Ssw_Tc5.*"; - select ".text.Cpu5_Main.*"; - select ".text.text_cpu5*"; - select "(.text.text_cpu5|.text.text_cpu5.*)"; - } - } - } - - /*Code Sections, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU5 - group (ordered, run_addr=mem:pfls5) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU4 - group ordered, run_addr=mem:pfls4) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU3 - group (ordered, run_addr=mem:pfls3) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, run_addr=mem:pfls2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, run_addr=mem:pfls0) -# endif - { - select ".text.fast.pfls.cpu0"; - select ".text.slow.pfls.cpu0"; - select ".text.5ms.pfls.cpu0"; - select ".text.10ms.pfls.cpu0"; - select ".text.callout.pfls.cpu0"; - select "(.text|.text.*)"; - } - } -} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel new file mode 100644 index 00000000000..1579c1b3354 --- /dev/null +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel @@ -0,0 +1,633 @@ +/**************************************************************************** + * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +#define __JOIN2(x,y) x##y +#define JOIN2(x,y) __JOIN2(x,y) +#define __JOIN3(x,y,z) x##y##z +#define JOIN3(x,y,z) __JOIN3(x,y,z) +#define __JOIN4(x,y,z,w) x##y##z##w +#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) + +#define LCF_PFLASH_KERNEL_START GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_PFLASH_KERNEL_SIZE GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_DSPR_KERNEL_START GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_DSPR_KERNEL_SIZE GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_PSPR_KERNEL_START GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_PSPR_KERNEL_SIZE GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_DLMU_KERNEL_START GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_DLMU_KERNEL_SIZE GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_KSTACK_START GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_KSTACK_SIZE GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID) + +#if CONFIG_CPU_COREID != 0 +#define LCF_SYSLOG_START JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_START) +#define LCF_SYSLOG_SIZE JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_SIZE) +#endif + +#define LCF_CSA_SIZE 40k +#define LCF_USTACK_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_HEAP_SIZE 4k + +#define LCF_CPU0 0 +#define LCF_CPU1 1 +#define LCF_CPU2 2 +#define LCF_CPU3 3 +#define LCF_CPU4 4 +#define LCF_CPU5 5 + +/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ +#define LCF_DEFAULT_HOST LCF_CPU0 + +#define LCF_CSA_OFFSET (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE) +#define LCF_ISTACK_OFFSET (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE) +#define LCF_USTACK_OFFSET (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE) +#define LCF_HEAP_OFFSET (LCF_USTACK_OFFSET - LCF_HEAP_SIZE) + +#define LCF_STARTPTR_CPU LCF_PFLASH_KERNEL_START +#define LCF_TRAPVEC_START (LCF_STARTPTR_CPU + 0x20) +#define LCF_INTVEC_START (LCF_PFLASH_KERNEL_START + LCF_PFLASH_KERNEL_SIZE - 0x2000) + +#define LCF_STARTPTR_NC_CPU0 NC_START(CORE0_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU1 NC_START(CORE1_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU2 NC_START(CORE2_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU3 NC_START(CORE3_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU4 NC_START(CORE4_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU5 NC_START(CORE5_PFLASH_KERNEL_START) + +#define INTTAB (LCF_INTVEC_START) + +#define RESET CORE0_PFLASH_KERNEL_START + +#include "tc1v1_6_2.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc39; +} + +derivative tc39 +{ + core tc + { + architecture = TC1V1.6.2; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.6.2; + import tc; // add all address spaces of core tc to core vtc for linking and locating + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory dsram // Data Scratch Pad Ram + { + mau = 8; + size = LCF_DSPR_KERNEL_SIZE; + type = ram; + map (dest=bus:tc:fpi_bus, dest_offset=DSPR_LOCAL_START, size=LCF_DSPR_KERNEL_SIZE, priority=8); + map (dest=bus:sri, dest_offset=LCF_DSPR_KERNEL_START, size=LCF_DSPR_KERNEL_SIZE); + } + + memory psram // Program Scratch Pad Ram + { + mau = 8; + size = LCF_PSPR_KERNEL_SIZE; + type = ram; + map (dest=bus:tc:fpi_bus, dest_offset=PSPR_LOCAL_START, size=LCF_PSPR_KERNEL_SIZE, priority=8); + map (dest=bus:sri, dest_offset=LCF_PSPR_KERNEL_START, size=LCF_PSPR_KERNEL_SIZE); + } + + memory pfls + { + mau = 8; + size = LCF_PFLASH_KERNEL_SIZE; + type = rom; + map cached (dest=bus:sri, dest_offset=LCF_PFLASH_KERNEL_START, size=LCF_PFLASH_KERNEL_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_KERNEL_START), reserved, size=LCF_PFLASH_KERNEL_SIZE); + } + + memory ucb + { + mau = 8; + size = 80K; + type = rom; + map (dest=bus:sri, dest_offset=0xae400000, reserved, size=80K); + } + + memory cpu_dlmu + { + mau = 8; + size = LCF_DLMU_KERNEL_SIZE; + type = ram; + map cached (dest=bus:sri, dest_offset=LCF_DLMU_KERNEL_START, size=LCF_DLMU_KERNEL_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_KERNEL_START), reserved, size=LCF_DLMU_KERNEL_SIZE); + } + + memory kstack + { + mau = 8; + size = LCF_KSTACK_SIZE; + type = ram; + map not_cached (dest=bus:sri, dest_offset=LCF_KSTACK_START, size=LCF_KSTACK_SIZE); + } + +#if CONFIG_CPU_COREID != 0 + memory syslog + { + mau = 8; + size = LCF_SYSLOG_SIZE; + type = ram; + map not_cached (dest=bus:sri, dest_offset=LCF_SYSLOG_START, size=LCF_SYSLOG_SIZE); + } +#endif + + section_setup :vtc:linear + { + heap "heap1" (min_size = LCF_HEAP_SIZE, align = 4); + heap "heap2" (min_size = LCF_HEAP_SIZE, align = 4); + } + + section_setup :vtc:linear + { + start_address + ( +#if CONFIG_CPU_COREID == 0 + symbol = "_START" +#elif CONFIG_CPU_COREID == 1 + symbol = "_START1" +#elif CONFIG_CPU_COREID == 2 + symbol = "_START2" +#elif CONFIG_CPU_COREID == 3 + symbol = "_START3" +#elif CONFIG_CPU_COREID == 4 + symbol = "_START4" +#elif CONFIG_CPU_COREID == 5 + symbol = "_START5" +#endif + ); + } + + section_setup :vtc:linear + { + stack "ustack_tc" (min_size = 1k, fixed, align = 8); + stack "istack_tc" (min_size = 1k, fixed, align = 8); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc"; + space = :tc:linear, :tc:abs24, :tc:abs18, :tc:csa; + } + ); + } + + /*Sections located at absolute fixed address*/ + + section_layout :vtc:linear + { + /*Fixed memory Allocations for stack memory and CSA*/ + group (ordered) + { + group ustack(align = 8, run_addr = mem:dsram[LCF_USTACK_OFFSET]) + { + stack "ustack_tc" (size = LCF_USTACK_SIZE); + } + "__USTACK"= sizeof(group:ustack) > 0 ? "_lc_ue_ustack_tc" : 0; + "__USTACK_END"="_lc_gb_ustack"; + "__USTACK0":= "__USTACK"; + "__USTACK1":= "__USTACK"; + "__USTACK2":= "__USTACK"; + "__USTACK3":= "__USTACK"; + "__USTACK4":= "__USTACK"; + "__USTACK5":= "__USTACK"; + + group istack(align = 8, run_addr = mem:dsram[LCF_ISTACK_OFFSET]) + { + stack "istack_tc" (size = LCF_ISTACK_SIZE); + } + "__ISTACK"= sizeof(group:istack) > 0 ? "_lc_ue_istack_tc" : 0; + "__ISTACK_END"="_lc_gb_istack"; + "__ISTACK0":="__ISTACK"; + "__ISTACK1":="__ISTACK"; + "__ISTACK2":="__ISTACK"; + "__ISTACK3":="__ISTACK"; + "__ISTACK4":="__ISTACK"; + "__ISTACK5":="__ISTACK"; + + group csa_tc(align = 64, attributes=rw, run_addr=mem:dsram[LCF_CSA_OFFSET]) + { + reserved "csa_tc" (size = LCF_CSA_SIZE); + } + "__CSA"= "_lc_ub_csa_tc"; + "__CSA_END"= "_lc_ue_csa_tc"; + "__CSA0":= "__CSA"; + "__CSA0_END":= "__CSA_END"; + "__CSA1":= "__CSA"; + "__CSA1_END":= "__CSA_END"; + "__CSA2":= "__CSA"; + "__CSA2_END":= "__CSA_END"; + "__CSA3":= "__CSA"; + "__CSA3_END":= "__CSA_END"; + "__CSA4":= "__CSA"; + "__CSA4_END":= "__CSA_END"; + "__CSA5":= "__CSA"; + "__CSA5_END":= "__CSA_END"; + } + + /*Fixed memory Allocations for _START*/ + group (ordered) + { + group interface_const (run_addr=mem:pfls[0x0020]) + { + select "*.interface_const"; + } + "__IF_CONST" := addressof(group:interface_const); + "__START0" := CORE0_PFLASH_KERNEL_START; + "__START1" := CORE1_PFLASH_KERNEL_START; + "__START2" := CORE2_PFLASH_KERNEL_START; + "__START3" := CORE3_PFLASH_KERNEL_START; + "__START4" := CORE4_PFLASH_KERNEL_START; + "__START5" := CORE5_PFLASH_KERNEL_START; + } + + /*Fixed memory Allocations for Trap Vector Table*/ + group (ordered) + { + group trapvec_tc (align = 8, run_addr=LCF_TRAPVEC_START) + { + section "trapvec_tc" (size=0x100, attributes=rx, fill=0) + { +#if CONFIG_CPU_COREID == 0 + select "(.text.traptab_cpu0*)"; +#elif CONFIG_CPU_COREID == 1 + select "(.text.traptab_cpu1*)"; +#elif CONFIG_CPU_COREID == 2 + select "(.text.traptab_cpu2*)"; +#elif CONFIG_CPU_COREID == 3 + select "(.text.traptab_cpu3*)"; +#elif CONFIG_CPU_COREID == 4 + select "(.text.traptab_cpu4*)"; +#elif CONFIG_CPU_COREID == 5 + select "(.text.traptab_cpu5*)"; +#endif + } + } + "__TRAPTAB_CPU0" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU1" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU2" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU3" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU4" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU5" := LCF_TRAPVEC_START; + } + + /*Fixed memory Allocations for Start up code*/ + group (ordered, attributes=rx) + { + group start_tc (run_addr=(LCF_STARTPTR_CPU)) + { +#if CONFIG_CPU_COREID == 0 + select "(.text.start*)"; +#elif CONFIG_CPU_COREID == 1 + select "(.text.start_cpu1*)"; +#elif CONFIG_CPU_COREID == 2 + select "(.text.start_cpu2*)"; +#elif CONFIG_CPU_COREID == 3 + select "(.text.start_cpu3*)"; +#elif CONFIG_CPU_COREID == 4 + select "(.text.start_cpu4*)"; +#elif CONFIG_CPU_COREID == 5 + select "(.text.start_cpu5*)"; +#endif + } + "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU3" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU4" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU5" := 1; /* Not used */ + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + group (ordered, attributes=rx) + { + group int_tab_tc (ordered) + { + group (run_addr=(INTTAB)+0x1FE0) select ".text.inttab0.intvec.0ff"; + } + "_lc_u_int_tab" = (LCF_INTVEC_START); + "__INTTAB_CPU0" = (LCF_INTVEC_START); + "__INTTAB_CPU1" = (LCF_INTVEC_START); + "__INTTAB_CPU2" = (LCF_INTVEC_START); + "__INTTAB_CPU3" = (LCF_INTVEC_START); + "__INTTAB_CPU4" = (LCF_INTVEC_START); + "__INTTAB_CPU5" = (LCF_INTVEC_START); + } + + /*Fixed memory Allocations for BMHD*/ + group (ordered) + { + group bmh_0_orig (run_addr=mem:ucb[0x4800]) + { + select ".rodata.bmhd_0_orig"; + } + group bmh_1_orig (run_addr=mem:ucb[0x5000]) + { + select ".rodata.bmhd_1_orig"; + } + group bmh_2_orig (run_addr=mem:ucb[0x5800]) + { + select ".rodata.bmhd_2_orig"; + } + group bmh_3_orig (run_addr=mem:ucb[0x6000]) + { + select ".rodata.bmhd_3_orig"; + } + group usercfg_0_org (run_addr=mem:ucb[0x8800]) + { + select ".rodata.usercfg_0_orig"; + } + group usercfg_0_cpy (run_addr=mem:ucb[0x9000]) + { + select ".rodata.usercfg_0_copy"; + } + } + } + + /*Near Abbsolute Addressable Data Sections*/ + section_layout :vtc:abs18 + { + /*Near Absolute Data, selectable with patterns and user defined sections*/ + group + { + group (ordered, attributes=rw, run_addr = mem:cpu_dlmu) + { + select "(.zdata.zlmudata|.zdata.zlmudata.*)"; + select "(.zbss.zlmubss|.zbss.zlmubss.*)"; + } + } + + /*Near Absolute Data, selectable by toolchain*/ + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) + { + group zdata(attributes=rw) + { + select "(.zdata|.zdata.*)"; + select "(.zbss|.zbss.*)"; + } + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + group + { + group (ordered, contiguous, align = 4, attributes=r, run_addr=mem:pfls) + { +#if CONFIG_CPU_COREID == 0 + select ".zrodata.Ifx_Ssw_Tc?.*"; + select ".zrodata.Cpu?_Main.*"; +#elif CONFIG_CPU_COREID == 1 + select ".zrodata.Ifx_Ssw_Tc1.*"; + select ".zrodata.Cpu1_Main.*"; +#elif CONFIG_CPU_COREID == 2 + select ".zrodata.Ifx_Ssw_Tc2.*"; + select ".zrodata.Cpu2_Main.*"; +#elif CONFIG_CPU_COREID == 3 + select ".zrodata.Ifx_Ssw_Tc3.*"; + select ".zrodata.Cpu3_Main.*"; +#elif CONFIG_CPU_COREID == 4 + select ".zrodata.Ifx_Ssw_Tc4.*"; + select ".zrodata.Cpu4_Main.*"; +#elif CONFIG_CPU_COREID == 5 + select ".zrodata.Ifx_Ssw_Tc5.*"; + select ".zrodata.Cpu5_Main.*"; +#endif + /*Near Absolute Const, selectable by toolchain*/ + select "(.zrodata|.zrodata.*)"; + } + } + } + + /*Relative A0/A1/A8/A9 Addressable Sections*/ + section_layout :vtc:linear + { + /*Relative A0 Addressable Data, selectable by toolchain*/ + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) + { + select "(.sdata|.sdata.*)"; + select "(.data_a0|.data_a0.*)"; + select "(.sbss|.sbss.*)"; + select "(.bss_a0|.bss_a0.*)"; + } + "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; + "__A0_MEM" = "_SMALL_DATA_"; + + /*Relative A1 Addressable Const, selectable by toolchain*/ + /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ + group a1 (ordered, align = 4, attributes=r, run_addr=mem:pfls) + { + select "(.srodata|.srodata.*)"; + select "(.ldata|.ldata.*)"; + select "(.rodata_a1|.rodata_a1.*)"; + } + "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; + "__A1_MEM" = "_LITERAL_DATA_"; + + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + group a9 (ordered, align = 4, run_addr=mem:dsram) + { + select "(.a9sdata|.a9sdata.*)"; + select "(.data_a9|.data_a9.*)"; + select "(.a9sbss|.a9sbss.*)"; + select "(.bss_a9|.bss_a9.*)"; + } + "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; + "__A9_MEM" = "_A9_DATA_"; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + group a8 (ordered, align = 4, run_addr=mem:pfls) + { + select "(.a8srodata|.a8srodata.*)"; + select "(.rodata_a8|.rodata_a8.*)"; + } + "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; + "__A8_MEM" = "_A8_DATA_"; + } + + /*kstack ram*/ + section_layout :vtc:linear + { + group kstack(ordered, contiguous, nocopy, run_addr=mem:kstack) + { + select "(.dtcm_stack|.dtcm_stack.*)"; + } + } + +#if CONFIG_CPU_COREID != 0 + /*syslog ram*/ + section_layout :vtc:linear + { + group syslog(ordered, contiguous, nocopy, run_addr=mem:syslog) + { + select "(.syslog|.syslog.*)"; + } + } +#endif + + /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ + section_layout :vtc:linear + { + /*Far Data Sections, selectable with patterns and user defined sections*/ + + /*DSRAM sections*/ + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) + { + group (attributes=rw) + { + select ".data.Ifx_Ssw_Tc?.*"; + select ".data.Cpu?_Main.*"; + select ".bss.Ifx_Ssw_Tc?.*"; + select ".bss.Cpu?_Main.*"; + select ".bss.os_scheduletable_misc.*"; + select ".bss.iob_initialize.*"; + } + + /*Heap1*/ + group heap1(attributes=rw) + { + heap "heap1" (size = LCF_HEAP_SIZE); + } + "_sheap":="_lc_ub_heap1"; + "_eheap":="__USTACK_END"; + } + + /*LMU Data sections*/ + group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_dlmu/not_cached) + { + select "(.data.uncached.*)"; + select "(.bss.uncached.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr=mem:cpu_dlmu) + { + group lmubss(attributes=rw, nocopy) + { + select "(.lmubss_cpu?|.lmubss_cpu?.*)"; + } + + group data(attributes=rw) + { + select "(.data|.data.*)"; + select "(.bss|.bss.*)"; + } + + /*Heap2 allocation*/ + group heap2(attributes=rw) + { + heap "heap2" (size = LCF_HEAP_SIZE); + } + "__DLMUHEAP":="_lc_ge_data"; + "__DLMUHEAP_END":=LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE; + } + + /*Far Const Sections, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, attributes=r, run_addr=mem:pfls) + { + select ".rodata.Ifx_Ssw_Tc?.*"; + select ".rodata.Cpu?_Main.*"; + } + } + + /*Far Const Sections, selectable by toolchain*/ + group (ordered, align = 4, run_addr=mem:pfls) + { + select "(.rodata|.rodata.*)"; + } + } + + /* PSRAM Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Program Scratchpad Sections*/ + group + { + group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram) + { + select "(.text.aurix_mtd_flash|.text.aurix_mtd_flash.*)"; + select "(.text.aurix_mtd_partition|.text.aurix_mtd_partition.*)"; + } + } + } + } + + /* FLS Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Cpu specific PFLASH Sections*/ + group + { + group (ordered, align = 4, attributes=rx, run_addr=mem:pfls) + { + select ".text.Ifx_Ssw_Tc?.*"; + select ".text.Cpu?_Main.*"; + select ".text.CompilerTasking.Ifx_C_Init"; + } + } + } + + /*Code Sections, selectable by toolchain*/ + group (ordered, run_addr=mem:pfls) + { + select "(.text|.text.*)"; + } + } +} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user new file mode 100644 index 00000000000..89c54f3f116 --- /dev/null +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user @@ -0,0 +1,189 @@ +/**************************************************************************** + * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +#define LCF_PFLASH_USER_START GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID) +#define LCF_PFLASH_USER_SIZE GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID) +#define LCF_DLMU_USER_START GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID) +#define LCF_DLMU_USER_SIZE GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID) +#define LCF_USTACK_START GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID) +#define LCF_USTACK_SIZE GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID) + +#define LCF_HEAP_SIZE 4k + +#include "tc1v1_6_2.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc39; +} + +derivative tc39 +{ + core tc + { + architecture = TC1V1.6.2; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.6.2; + import tc; // add all address spaces of core tc to core vtc for linking and locating + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory upfls + { + mau = 8; + size = LCF_PFLASH_USER_SIZE; + type = rom; + map cached (dest=bus:sri, dest_offset=LCF_PFLASH_USER_START, size=LCF_PFLASH_USER_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_USER_START), reserved, size=LCF_PFLASH_USER_SIZE); + } + + memory cpu_udlmu + { + mau = 8; + size = LCF_DLMU_USER_SIZE; + type = ram; + map cached (dest=bus:sri, dest_offset=LCF_DLMU_USER_START, size=LCF_DLMU_USER_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_USER_START), reserved, size=LCF_DLMU_USER_SIZE); + } + + memory ustack + { + mau = 8; + size = LCF_USTACK_SIZE; + type = ram; + map not_cached (dest=bus:sri, dest_offset=LCF_USTACK_START, size=LCF_USTACK_SIZE); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc"; + space = :tc:linear, :tc:abs24, :tc:abs18; + } + ); + } + + section_setup :vtc:linear + { + heap "uheap" (min_size = LCF_HEAP_SIZE, align = 4); + } + + /* user stack section */ + section_layout :vtc:linear + { + group ustack(ordered, contiguous, nocopy, run_addr=mem:ustack) + { + select "(.dtcm_stack|.dtcm_stack.*)"; + } + } + + /*Sections located at absolute fixed address*/ + section_layout :vtc:linear + { + group userspace(ordered, run_addr=LCF_PFLASH_USER_START) + { + select "(.userspace|.userspace.*)"; + } + "_suserspace" = "_lc_gb_userspace"; + "_euserspace" = "_lc_ge_userspace"; + + group text(ordered, run_addr=mem:upfls) + { + select "(.text|.text.*)"; + select "(.zrodata|.zrodata.*)"; + select "(.rodata|.rodata.*)"; + } + "_stext" = "_lc_gb_text"; + "_etext" = "_lc_ge_text"; + } + + /* Data & Bss section */ + section_layout :vtc:linear + { + group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu/not_cached) + { + select "(.data.uncached.*)"; + select "(.bss.uncached.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu) + { + group udata + { + select "(.data|.data.*)"; + select "(.zdata|.zdata.*)"; + } + "_sdata" = "_lc_gb_udata"; + "_edata" = "_lc_ge_udata"; + + /* bss section */ + group ubss + { + select "(.bss|.bss.*)"; + select "(.zbss|.zbss.*)"; + select "(.bbss|.bbss.*)"; + } + "_sbss" = "_lc_gb_ubss"; + "_ebss" = "_lc_ge_ubss"; + + /* heap section */ + group uheap + { + heap "uheap" (size = LCF_HEAP_SIZE); + } + "_sheap" = "_ebss"; + "_eheap" = LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE; + } + + group udata_rom(ordered, contiguous, load_addr=mem:upfls) + { + select "(.data|.data.*)"; + select "(.zdata|.zdata.*)"; + } + "_sdata_pflash" = "_lc_gb_udata_rom"; + #include "symbol_share.ld" + } +} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs index 75f1c3930a6..9692d30d55a 100644 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs @@ -25,9 +25,15 @@ include $(TOPDIR)/tools/Config.mk include $(TOPDIR)/arch/tricore/src/tc3xx/Toolchain.defs ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_Tasking_Tricore_Tc.lsl + TRICORE_TOOLCHAIN := Tasking else - ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_Gnuc_Tricore_Tc.lsl + TRICORE_TOOLCHAIN := Gnuc +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.kernel + +ifeq ($(CONFIG_BUILD_PROTECTED),y) + ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.user endif CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt b/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt index 299b5ed1458..503675f17e9 100644 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt +++ b/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt @@ -24,13 +24,19 @@ set(SRCS tc397_appinit.c tc397_boardinit.c tc397_bringup.c) target_sources(board PRIVATE ${SRCS}) -# TODO: make this the default and then allow boards to redefine if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - set_property( - GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/Lcf_Tasking_Tricore_Tc.lsl") + set(toolchain "Tasking") else() - set_property( - GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/Lcf_Gnuc_Tricore_Tc.lsl") + set(toolchain "Gnuc") +endif() + +set_property( + GLOBAL + PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.kernel") +if(CONFIG_BUILD_PROTECTED) + set_property( + GLOBAL + PROPERTY LD_SCRIPT_USER + "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.user") endif() diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt b/boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt new file mode 100644 index 00000000000..c8bc3a4497b --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/Kconfig b/boards/tricore/tc4da/triboard_tc4x9_com/Kconfig new file mode 100644 index 00000000000..9ae9d044c3d --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_TRIBOARD_TC4X9_COM +endif diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig b/boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig new file mode 100644 index 00000000000..1d60bc33ae8 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="tricore" +CONFIG_ARCH_BOARD="triboard_tc4x9_com" +CONFIG_ARCH_BOARD_TRIBOARD_TC4X9_COM=y +CONFIG_ARCH_CHIP="tc4da" +CONFIG_ARCH_CHIP_TC4DA=y +CONFIG_ARCH_CHIP_TC4XX=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_NUSER_INTERRUPTS=48 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TRICORE=y +CONFIG_BOARD_LOOPSPERMSEC=99369 +CONFIG_BOOT_RUNFROMSDRAM=y +CONFIG_BUILTIN=y +CONFIG_CPU_COREID=0 +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_NDEBUG=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x70000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2016 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSLOG_INTBUFFER=y +CONFIG_SYSLOG_MAX_CHANNELS=2 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_SCHED_EVENTS=y +CONFIG_SYSTEM_TIME64=y \ No newline at end of file diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/include/board.h b/boards/tricore/tc4da/triboard_tc4x9_com/include/board.h new file mode 100644 index 00000000000..e7447146ae3 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/include/board.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_H +#define __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +#endif /* __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_H */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h b/boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h new file mode 100644 index 00000000000..11a60dc745e --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h @@ -0,0 +1,457 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_MEMORYMAP_H +#define __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BANKA_CORE0_PFLASH_KERNEL_START 0x80000000 +#define BANKA_CORE0_PFLASH_KERNEL_SIZE 0x100000 /* 1024KB */ +#define BANKA_CORE0_PFLASH_USER_START 0x80100000 +#define BANKA_CORE0_PFLASH_USER_SIZE 0x100000 /* 1024KB */ +#define BANKA_CORE1_PFLASH_KERNEL_START 0x80200000 +#define BANKA_CORE1_PFLASH_KERNEL_SIZE 0x100000 /* 1024KB */ +#define BANKA_CORE1_PFLASH_USER_START 0x80300000 +#define BANKA_CORE1_PFLASH_USER_SIZE 0x280000 /* 2560KB */ +#define BANKA_CORE2_PFLASH_KERNEL_START 0x80580000 +#define BANKA_CORE2_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ +#define BANKA_CORE2_PFLASH_USER_START 0x80600000 +#define BANKA_CORE2_PFLASH_USER_SIZE 0x80000 /* 512KB */ +#define BANKA_CORE3_PFLASH_KERNEL_START 0x80680000 +#define BANKA_CORE3_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ +#define BANKA_CORE3_PFLASH_USER_START 0x80700000 +#define BANKA_CORE3_PFLASH_USER_SIZE 0xE0000 /* */ +#define BANKA_CORE4_PFLASH_KERNEL_START 0x807E0000 +#define BANKA_CORE4_PFLASH_KERNEL_SIZE 0x88000 /* 544KB */ +#define BANKA_CORE4_PFLASH_USER_START 0x80868000 +#define BANKA_CORE4_PFLASH_USER_SIZE 0xC4000 /* 784KB */ +#define BANKA_CORE5_PFLASH_KERNEL_START 0x8092C000 +#define BANKA_CORE5_PFLASH_KERNEL_SIZE 0x70000 /* 448KB */ +#define BANKA_CORE5_PFLASH_USER_START 0x8099C000 +#define BANKA_CORE5_PFLASH_USER_SIZE 0x64000 /* 400KB */ +#define BANKB_BL_PFLASH_START 0x82000000 +#define BANKB_BL_PFLASH_SIZE 0x40000 /* 256KB */ +#define BANKB_MBF_HASH_START 0x82040000 +#define BANKB_MBF_HASH_SIZE 0x4000 /* 16KB */ +#define BANKB_CORE0_PFLASH_KERNEL_START 0x82044000 +#define BANKB_CORE0_PFLASH_KERNEL_SIZE 0x160000 /* 1408KB */ +#define BANKB_CORE0_PFLASH_USER_START 0x821A4000 +#define BANKB_CORE0_PFLASH_USER_SIZE 0x5C000 /* 368KB */ +#define BANKB_VBMETA_START 0x821FC000 +#define BANKB_VBMETA_SIZE 0x4000 /* 16KB */ +#define BANKB_CORE1_PFLASH_KERNEL_START 0x82200000 +#define BANKB_CORE1_PFLASH_KERNEL_SIZE 0x100000 /* 1024KB */ +#define BANKB_CORE1_PFLASH_USER_START 0x82300000 +#define BANKB_CORE1_PFLASH_USER_SIZE 0x280000 /* 2560KB */ +#define BANKB_CORE2_PFLASH_KERNEL_START 0x82580000 +#define BANKB_CORE2_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ +#define BANKB_CORE2_PFLASH_USER_START 0x82600000 +#define BANKB_CORE2_PFLASH_USER_SIZE 0x80000 /* 512KB */ +#define BANKB_CORE3_PFLASH_KERNEL_START 0x82680000 +#define BANKB_CORE3_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ +#define BANKB_CORE3_PFLASH_USER_START 0x82700000 +#define BANKB_CORE3_PFLASH_USER_SIZE 0xE0000 /* 896KB */ +#define BANKB_CORE4_PFLASH_KERNEL_START 0x827E0000 +#define BANKB_CORE4_PFLASH_KERNEL_SIZE 0x88000 /* 544KB */ +#define BANKB_CORE4_PFLASH_USER_START 0x82868000 +#define BANKB_CORE4_PFLASH_USER_SIZE 0xC4000 /* 784KB */ +#define BANKB_CORE5_PFLASH_KERNEL_START 0x8292C000 +#define BANKB_CORE5_PFLASH_KERNEL_SIZE 0x70000 /* 448KB */ +#define BANKB_CORE5_PFLASH_USER_START 0x8299C000 +#define BANKB_CORE5_PFLASH_USER_SIZE 0x64000 /* 400KB */ +#define BANKA_CORE6_PFLASH_KERNEL_START 0x84000000 +#define BANKA_CORE6_PFLASH_KERNEL_SIZE 0x40000 /* 256KB */ +#define BANKA_CORE6_VBMETA_START 0x8403C000 +#define BANKA_CORE6_VBMETA_SIZE 0x4000 /* 16KB */ +#define BANKB_CORE6_PFLASH_KERNEL_START 0x84040000 +#define BANKB_CORE6_PFLASH_KERNEL_SIZE 0x40000 /* 256KB */ +#define BANKB_CORE6_VBMETA_START 0x8407C000 +#define BANKB_CORE6_VBMETA_SIZE 0x4000 /* 16KB */ +#define CORE6_RES_PFLASH_KERNEL_START 0x84080000 +#define CORE6_RES_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ +#define CORE0_STACK_KERNEL_START 0x70000000 +#define CORE0_STACK_KERNEL_SIZE 0x9800 /* 38KB */ +#define CORE0_STACK_USER_START 0x70009800 +#define CORE0_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE0_DSPR_KERNEL_START 0x70011800 +#define CORE0_DSPR_KERNEL_SIZE 0x2A800 /* 170KB */ +#define CORE0_DSPR_USER_START 0x7003C000 +#define CORE0_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE0_PSPR_KERNEL_START 0x70100000 +#define CORE0_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE0_PSPR_USER_START 0x70108000 +#define CORE0_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE0_DLMU_KERNEL_START 0x90020400 +#define CORE0_DLMU_KERNEL_SIZE 0x2AC00 /* 171KB */ +#define CORE0_DLMU_USER_START 0x9004B000 +#define CORE0_DLMU_USER_SIZE 0x35000 /* 212KB */ +#define CORE1_STACK_KERNEL_START 0x60000000 +#define CORE1_STACK_KERNEL_SIZE 0x8800 /* 34KB */ +#define CORE1_STACK_USER_START 0x60008800 +#define CORE1_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE1_DSPR_KERNEL_START 0x60010800 +#define CORE1_DSPR_KERNEL_SIZE 0x2B800 /* 174KB */ +#define CORE1_DSPR_USER_START 0x6003C000 +#define CORE1_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE1_PSPR_KERNEL_START 0x60100000 +#define CORE1_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE1_PSPR_USER_START 0x60108000 +#define CORE1_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE1_DLMU_KERNEL_START 0x90080000 +#define CORE1_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ +#define CORE1_DLMU_USER_START 0x900C0000 +#define CORE1_DLMU_USER_SIZE 0x40000 /* 256KB */ +#define CORE2_STACK_KERNEL_START 0x50000000 +#define CORE2_STACK_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE2_STACK_USER_START 0x50008000 +#define CORE2_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE2_DSPR_KERNEL_START 0x50010000 +#define CORE2_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ +#define CORE2_DSPR_USER_START 0x5003C000 +#define CORE2_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE2_PSPR_KERNEL_START 0x50100000 +#define CORE2_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE2_PSPR_USER_START 0x50108000 +#define CORE2_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE2_DLMU_KERNEL_START 0x90100000 +#define CORE2_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ +#define CORE2_DLMU_USER_START 0x90140000 +#define CORE2_DLMU_USER_SIZE 0x40000 /* 256KB */ +#define CORE3_STACK_KERNEL_START 0x40000000 +#define CORE3_STACK_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE3_STACK_USER_START 0x40008000 +#define CORE3_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE3_DSPR_KERNEL_START 0x40010000 +#define CORE3_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ +#define CORE3_DSPR_USER_START 0x4003C000 +#define CORE3_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE3_PSPR_KERNEL_START 0x40100000 +#define CORE3_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE3_PSPR_USER_START 0x40108000 +#define CORE3_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE3_DLMU_KERNEL_START 0x90180000 +#define CORE3_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ +#define CORE3_DLMU_USER_START 0x901C0000 +#define CORE3_DLMU_USER_SIZE 0x40000 /* 256KB */ +#define CORE4_STACK_KERNEL_START 0x30000000 +#define CORE4_STACK_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE4_STACK_USER_START 0x30008000 +#define CORE4_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE4_DSPR_KERNEL_START 0x30010000 +#define CORE4_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ +#define CORE4_DSPR_USER_START 0x3003C000 +#define CORE4_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE4_PSPR_KERNEL_START 0x30100000 +#define CORE4_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE4_PSPR_USER_START 0x30108000 +#define CORE4_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE4_DLMU_KERNEL_START 0x90200000 +#define CORE4_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ +#define CORE4_DLMU_USER_START 0x90240000 +#define CORE4_DLMU_USER_SIZE 0x40000 /* 256KB */ +#define CORE5_STACK_KERNEL_START 0x20000000 +#define CORE5_STACK_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE5_STACK_USER_START 0x20008000 +#define CORE5_STACK_USER_SIZE 0x8000 /* 32KB */ +#define CORE5_DSPR_KERNEL_START 0x20010000 +#define CORE5_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ +#define CORE5_DSPR_USER_START 0x2003C000 +#define CORE5_DSPR_USER_SIZE 0x0 /* 0KB */ +#define CORE5_PSPR_KERNEL_START 0x20100000 +#define CORE5_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ +#define CORE5_PSPR_USER_START 0x20108000 +#define CORE5_PSPR_USER_SIZE 0x8000 /* 32KB */ +#define CORE5_DLMU_KERNEL_START 0x90280000 +#define CORE5_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ +#define CORE5_DLMU_USER_START 0x902C0000 +#define CORE5_DLMU_USER_SIZE 0x40000 /* 256KB */ +#define CORE6_DSPR_KERNEL_START 0x10000000 +#define CORE6_DSPR_KERNEL_SIZE 0x3C000 /* 240KB */ +#define CORE6_PSPR_KERNEL_START 0x10100000 +#define CORE6_PSPR_KERNEL_SIZE 0x10000 /* 64KB */ +#define AURIX_RPMSG_SHMEM_START 0xB04D0000 +#define AURIX_RPMSG_SHMEM_SIZE 0x20000 /* 128KB */ +#define AURIX_RPMSG_CORE0CORE1_SYSLOG_START 0xB04F0000 +#define AURIX_RPMSG_CORE0CORE1_SYSLOG_SIZE 0x2000 /* 8KB */ +#define AURIX_RPMSG_CORE0CORE2_SYSLOG_START 0xB04F2000 +#define AURIX_RPMSG_CORE0CORE2_SYSLOG_SIZE 0x2000 /* 8KB */ +#define AURIX_RPMSG_CORE0CORE3_SYSLOG_START 0xB04F4000 +#define AURIX_RPMSG_CORE0CORE3_SYSLOG_SIZE 0x2000 /* 8KB */ +#define AURIX_RPMSG_CORE0CORE4_SYSLOG_START 0xB04F6000 +#define AURIX_RPMSG_CORE0CORE4_SYSLOG_SIZE 0x2000 /* 8KB */ +#define AURIX_RPMSG_CORE0CORE5_SYSLOG_START 0xB04F8000 +#define AURIX_RPMSG_CORE0CORE5_SYSLOG_SIZE 0x2000 /* 8KB */ +#define AURIX_RPMSG_CORE0CORECS_SYSLOG_START 0xB04FA000 +#define AURIX_RPMSG_CORE0CORECS_SYSLOG_SIZE 0x6000 /* 8KB */ +#define AURIX_SYSLOG_RPMSG_START 0xB04F0000 +#define AURIX_SYSLOG_RPMSG_SIZE 0x10000 /* 64KB */ +#define LMU2_UNUSED_START 0xB0565400 +#define LMU2_UNUSED_SIZE 0x1AC00 /* 107KB */ +#define LMU3_UNUSED_START 0xB0580000 +#define LMU3_UNUSED_SIZE 0x80000 /* 512KB */ +#define LMU4_UNUSED_START 0xB0600000 +#define LMU4_UNUSED_SIZE 0x80000 /* 512KB */ +#define LMU5_UNUSED_START 0xB0680000 +#define LMU5_UNUSED_SIZE 0x80000 /* 512KB */ +#define LMU6_UNUSED_START 0xB0700000 +#define LMU6_UNUSED_SIZE 0x80000 /* 512KB */ +#define LMU7_UNUSED_START 0xB0780000 +#define LMU7_UNUSED_SIZE 0x80000 /* 512KB */ +#define LMU8_UNUSED_START 0xB0800000 +#define LMU8_UNUSED_SIZE 0x80000 /* 512KB */ +#define LMU9_UNUSED_START 0xB0880000 +#define LMU9_UNUSED_SIZE 0x80000 /* 512KB */ +#define DFLASH0_NVM_START 0xAE000000 +#define DFLASH0_NVM_SIZE 0x40000 /* 256KB */ +#define DFLASH0_MANUFACTURY_START 0xAE040000 +#define DFLASH0_MANUFACTURY_SIZE 0x2800 /* 10K */ +#define DFLASH0_BSWLOG_START 0xAE042800 +#define DFLASH0_BSWLOG_SIZE 0x10000 /* 64K */ +#define DFLASH0_TRAPINFO_START 0xAE052800 +#define DFLASH0_TRAPINFO_SIZE 0x4000 /* 16K */ +#define DFLASH0_DFXLOG_START 0xAE056800 +#define DFLASH0_DFXLOG_SIZE 0x4000 /* 16K */ +#define DFLASH0_UNUSED_START 0xAE05A800 +#define DFLASH0_UNUSED_SIZE 0xA5800 /* 662K */ +#define DFLASH1_START 0xAE800000 +#define DFLASH1_SIZE 0x1E000 /* 120K */ +#define DFLASH1_SYSLOG_START 0xAE81E000 +#define DFLASH1_SYSLOG_SIZE 0x2000 /* 8K */ +#define UCB0_START 0xAE400000 +#define UCB0_SIZE 0x14000 /* 80K */ +#define UCB1_START 0xAEC00000 +#define UCB1_SIZE 0xD000 /* 52K */ +#define PERIPHERALS_START 0xE9800000 +#define PERIPHERALS_SIZE 0x118A0000 /* 287360K */ +#define CORE0_DCACHE_START 0x7003C000 +#define CORE0_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE1_DCACHE_START 0x6003C000 +#define CORE1_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE2_DCACHE_START 0x5003C000 +#define CORE2_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE3_DCACHE_START 0x4003C000 +#define CORE3_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE4_DCACHE_START 0x3003C000 +#define CORE4_DCACHE_SIZE 0x4000 /* 16K */ +#define CORE5_DCACHE_START 0x2003C000 +#define CORE5_DCACHE_SIZE 0x4000 /* 16K */ + +/**************************************************************************** + * Common macros + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_FLAT + +# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START +# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE +# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START +# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE +# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START +# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE +# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START +# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE +# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START +# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE +# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START +# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE +# define CORE6_PFLASH_KERNEL_START BANKA_CORE6_PFLASH_KERNEL_START +# define CORE6_PFLASH_KERNEL_SIZE BANKA_CORE6_PFLASH_KERNEL_SIZE + +#else + +# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START +# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE +# define CORE0_PFLASH_USER_START BANKA_CORE0_PFLASH_USER_START +# define CORE0_PFLASH_USER_SIZE BANKA_CORE0_PFLASH_USER_SIZE + +# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START +# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE +# define CORE1_PFLASH_USER_START BANKA_CORE1_PFLASH_USER_START +# define CORE1_PFLASH_USER_SIZE BANKA_CORE1_PFLASH_USER_SIZE + +# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START +# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE +# define CORE2_PFLASH_USER_START BANKA_CORE2_PFLASH_USER_START +# define CORE2_PFLASH_USER_SIZE BANKA_CORE2_PFLASH_USER_SIZE + +# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START +# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE +# define CORE3_PFLASH_USER_START BANKA_CORE3_PFLASH_USER_START +# define CORE3_PFLASH_USER_SIZE BANKA_CORE3_PFLASH_USER_SIZE + +# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START +# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE +# define CORE4_PFLASH_USER_START BANKA_CORE4_PFLASH_USER_START +# define CORE4_PFLASH_USER_SIZE BANKA_CORE4_PFLASH_USER_SIZE + +# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START +# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE +# define CORE5_PFLASH_USER_START BANKA_CORE5_PFLASH_USER_START +# define CORE5_PFLASH_USER_SIZE BANKA_CORE5_PFLASH_USER_SIZE + +# define CORE6_PFLASH_KERNEL_START BANKA_CORE6_PFLASH_KERNEL_START +# define CORE6_PFLASH_KERNEL_SIZE BANKA_CORE6_PFLASH_KERNEL_SIZE + +#endif + +#define BL_PFLASH_START BANKA_BL_PFLASH_START +#define BL_PFLASH_SIZE BANKA_BL_PFLASH_SIZE +#define BL_DLMU_START CORE0_DLMU_KERNEL_START +#define BL_DLMU_SIZE CORE0_DLMU_KERNEL_SIZE +#define BL_DSPR_START CORE0_DSPR_KERNEL_START +#define BL_DSPR_SIZE CORE0_DSPR_KERNEL_SIZE +#define BL_PSPR_START CORE0_PSPR_KERNEL_START +#define BL_PSPR_SIZE CORE0_PSPR_KERNEL_SIZE +#define MBF_HASH_START BANKA_MBF_HASH_START +#define MBF_HASH_SIZE BANKA_MBF_HASH_SIZE + +#define NC_START(addr) \ + ((addr) >= 0x80000000 && (addr) <= 0x9FFFFFFF ? (addr) + 0x20000000 : (addr)) + +#define AURIX_PERIPHERAL_BASE_ADDR 0xE9800000 +#define AURIX_PERIPHERAL_SIZE 0x118A0000 + +#define DSPR_LOCAL_START 0xD0000000 +#define PSPR_LOCAL_START 0xC0000000 + +#define BACKGROUND_START 0x10000000 +#define BACKGROUND_SIZE 0xEB0A0000 + +#define CORE0_DCACHE_KERNEL_START 0x7003C000 +#define CORE0_DCACHE_KERNEL_SIZE 0x4000 +#define CORE1_DCACHE_KERNEL_START 0x6003C000 +#define CORE1_DCACHE_KERNEL_SIZE 0x4000 +#define CORE2_DCACHE_KERNEL_START 0x5003C000 +#define CORE2_DCACHE_KERNEL_SIZE 0x4000 +#define CORE3_DCACHE_KERNEL_START 0x4003C000 +#define CORE3_DCACHE_KERNEL_SIZE 0x4000 +#define CORE4_DCACHE_KERNEL_START 0x3003C000 +#define CORE4_DCACHE_KERNEL_SIZE 0x4000 +#define CORE5_DCACHE_KERNEL_START 0x2003C000 +#define CORE5_DCACHE_KERNEL_SIZE 0x4000 + +#define CORE_PFLASH_KERNEL_START(COREID) CORE##COREID##_PFLASH_KERNEL_START +#define CORE_PFLASH_KERNEL_SIZE(COREID) CORE##COREID##_PFLASH_KERNEL_SIZE +#define GENERATE_CORE_PFLASH_KERNEL_START(COREID) CORE_PFLASH_KERNEL_START(COREID) +#define GENERATE_CORE_PFLASH_KERNEL_SIZE(COREID) CORE_PFLASH_KERNEL_SIZE(COREID) + +#define CORE_STACK_KERNEL_START(COREID) CORE##COREID##_STACK_KERNEL_START +#define CORE_STACK_KERNEL_SIZE(COREID) CORE##COREID##_STACK_KERNEL_SIZE +#define GENERATE_CORE_STACK_KERNEL_START(COREID) CORE_STACK_KERNEL_START(COREID) +#define GENERATE_CORE_STACK_KERNEL_SIZE(COREID) CORE_STACK_KERNEL_SIZE(COREID) + +#define CORE_DSPR_KERNEL_START(COREID) CORE##COREID##_DSPR_KERNEL_START +#define CORE_DSPR_KERNEL_SIZE(COREID) CORE##COREID##_DSPR_KERNEL_SIZE +#define GENERATE_CORE_DSPR_KERNEL_START(COREID) CORE_DSPR_KERNEL_START(COREID) +#define GENERATE_CORE_DSPR_KERNEL_SIZE(COREID) CORE_DSPR_KERNEL_SIZE(COREID) + +#define CORE_PSPR_KERNEL_START(COREID) CORE##COREID##_PSPR_KERNEL_START +#define CORE_PSPR_KERNEL_SIZE(COREID) CORE##COREID##_PSPR_KERNEL_SIZE +#define GENERATE_CORE_PSPR_KERNEL_START(COREID) CORE_PSPR_KERNEL_START(COREID) +#define GENERATE_CORE_PSPR_KERNEL_SIZE(COREID) CORE_PSPR_KERNEL_SIZE(COREID) + +#define CORE_DLMU_KERNEL_START(COREID) CORE##COREID##_DLMU_KERNEL_START +#define CORE_DLMU_KERNEL_SIZE(COREID) CORE##COREID##_DLMU_KERNEL_SIZE +#define GENERATE_CORE_DLMU_KERNEL_START(COREID) CORE_DLMU_KERNEL_START(COREID) +#define GENERATE_CORE_DLMU_KERNEL_SIZE(COREID) CORE_DLMU_KERNEL_SIZE(COREID) + +#define CORE_CALIB_KERNEL_START(COREID) CORE##COREID##_CALIB_KERNEL_START +#define CORE_CALIB_KERNEL_SIZE(COREID) CORE##COREID##_CALIB_KERNEL_SIZE +#define GENERATE_CORE_CALIB_KERNEL_START(COREID) CORE_CALIB_KERNEL_START(COREID) +#define GENERATE_CORE_CALIB_KERNEL_SIZE(COREID) CORE_CALIB_KERNEL_SIZE(COREID) + +#define CORE_DCACHE_KERNEL_START(COREID) CORE##COREID##_DCACHE_KERNEL_START +#define CORE_DCACHE_KERNEL_SIZE(COREID) CORE##COREID##_DCACHE_KERNEL_SIZE +#define GENERATE_CORE_DCACHE_KERNEL_START(COREID) CORE_DCACHE_KERNEL_START(COREID) +#define GENERATE_CORE_DCACHE_KERNEL_SIZE(COREID) CORE_DCACHE_KERNEL_SIZE(COREID) + +#ifndef CONFIG_BUILD_FLAT + +#define CORE_PFLASH_USER_START(COREID) CORE##COREID##_PFLASH_USER_START +#define CORE_PFLASH_USER_SIZE(COREID) CORE##COREID##_PFLASH_USER_SIZE +#define GENERATE_CORE_PFLASH_USER_START(COREID) CORE_PFLASH_USER_START(COREID) +#define GENERATE_CORE_PFLASH_USER_SIZE(COREID) CORE_PFLASH_USER_SIZE(COREID) + +#define CORE_STACK_USER_START(COREID) CORE##COREID##_STACK_USER_START +#define CORE_STACK_USER_SIZE(COREID) CORE##COREID##_STACK_USER_SIZE +#define GENERATE_CORE_STACK_USER_START(COREID) CORE_STACK_USER_START(COREID) +#define GENERATE_CORE_STACK_USER_SIZE(COREID) CORE_STACK_USER_SIZE(COREID) + +#define CORE_DSPR_USER_START(COREID) CORE##COREID##_DSPR_USER_START +#define CORE_DSPR_USER_SIZE(COREID) CORE##COREID##_DSPR_USER_SIZE +#define GENERATE_CORE_DSPR_USER_START(COREID) CORE_DSPR_USER_START(COREID) +#define GENERATE_CORE_DSPR_USER_SIZE(COREID) CORE_DSPR_USER_SIZE(COREID) + +#define CORE_PSPR_USER_START(COREID) CORE##COREID##_PSPR_USER_START +#define CORE_PSPR_USER_SIZE(COREID) CORE##COREID##_PSPR_USER_SIZE +#define GENERATE_CORE_PSPR_USER_START(COREID) CORE_PSPR_USER_START(COREID) +#define GENERATE_CORE_PSPR_USER_SIZE(COREID) CORE_PSPR_USER_SIZE(COREID) + +#define CORE_DLMU_USER_START(COREID) CORE##COREID##_DLMU_USER_START +#define CORE_DLMU_USER_SIZE(COREID) CORE##COREID##_DLMU_USER_SIZE +#define GENERATE_CORE_DLMU_USER_START(COREID) CORE_DLMU_USER_START(COREID) +#define GENERATE_CORE_DLMU_USER_SIZE(COREID) CORE_DLMU_USER_SIZE(COREID) + +#define CORE_CALIB_USER_START(COREID) CORE##COREID##_CALIB_USER_START +#define CORE_CALIB_USER_SIZE(COREID) CORE##COREID##_CALIB_USER_SIZE +#define GENERATE_CORE_CALIB_USER_START(COREID) CORE_CALIB_USER_START(COREID) +#define GENERATE_CORE_CALIB_USER_SIZE(COREID) CORE_CALIB_USER_SIZE(COREID) + +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel new file mode 100644 index 00000000000..69780d11f5b --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel @@ -0,0 +1,590 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +#define __JOIN2(x,y) x##y +#define JOIN2(x,y) __JOIN2(x,y) +#define __JOIN3(x,y,z) x##y##z +#define JOIN3(x,y,z) __JOIN3(x,y,z) +#define __JOIN4(x,y,z,w) x##y##z##w +#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) + +#define COREID_LST(x) JOIN2(x, CONFIG_CPU_COREID) +#define COREID_MID(x,y) JOIN3(x, CONFIG_CPU_COREID, y) + +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") +#if CONFIG_CPU_COREID == 0 +ENTRY(_START) +#endif + +__TRICORE_DERIVATE_MEMORY_MAP__ = 0x490; + +LCF_PFLASH_KERNEL_START = GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID); +LCF_PFLASH_KERNEL_SIZE = GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_DSPR_KERNEL_START = GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID); +LCF_DSPR_KERNEL_SIZE = GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_PSPR_KERNEL_START = GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID); +LCF_PSPR_KERNEL_SIZE = GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_DLMU_KERNEL_START = GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID); +LCF_DLMU_KERNEL_SIZE = GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID); +LCF_KSTACK_START = GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID); +LCF_KSTACK_SIZE = GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID); + +#if CONFIG_CPU_COREID != 0 +LCF_SYSLOG_START = JOIN3(AURIX_RPMSG_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_START); +LCF_SYSLOG_SIZE = JOIN3(AURIX_RPMSG_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_SIZE); +#endif + +LCF_CSA_SIZE = 40k; +LCF_USTACK_SIZE = CONFIG_IDLETHREAD_STACKSIZE; +LCF_ISTACK_SIZE = CONFIG_ARCH_INTERRUPTSTACK; + +LCF_CSA_OFFSET = (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE); +LCF_ISTACK_OFFSET = (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE); +LCF_USTACK_OFFSET = (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE); + +LCF_STARTPTR = LCF_PFLASH_KERNEL_START; +LCF_STARTPTR_NC = NC_START(LCF_STARTPTR); +LCF_TRAPVEC_START = LCF_STARTPTR + 0x100; + +COREID_LST(__INTTAB_CPU) = LCF_PFLASH_KERNEL_START; + +LCF_STARTPTR_NC_CPU0 = NC_START(CORE0_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU1 = NC_START(CORE1_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU2 = NC_START(CORE2_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU3 = NC_START(CORE3_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU4 = NC_START(CORE4_PFLASH_KERNEL_START); +LCF_STARTPTR_NC_CPU5 = NC_START(CORE5_PFLASH_KERNEL_START); +RESET = CORE0_PFLASH_KERNEL_START; + +MEMORY +{ + kstack (w!xp): org = LCF_KSTACK_START, len = LCF_KSTACK_SIZE + + dspr (w!xp): org = LCF_DSPR_KERNEL_START, len = LCF_DSPR_KERNEL_SIZE + pspr (w!xp): org = LCF_PSPR_KERNEL_START, len = LCF_PSPR_KERNEL_SIZE + + psram_local (w!xp): org = PSPR_LOCAL_START, len = LCF_PSPR_KERNEL_SIZE + + pfls (rx!p): org = LCF_PFLASH_KERNEL_START, len = LCF_PFLASH_KERNEL_SIZE + pfls_nc (rx!p): org = NC_START(LCF_PFLASH_KERNEL_START), len = LCF_PFLASH_KERNEL_SIZE + + ucb (rx!p): org = 0xae404800, len = 80K - 2K + + cpu_dlmu (w!xp): org = LCF_DLMU_KERNEL_START, len = LCF_DLMU_KERNEL_SIZE + cpu_dlmu_nc (w!xp): org = NC_START(LCF_DLMU_KERNEL_START), len = LCF_DLMU_KERNEL_SIZE + + rpmsg_shmem (w!xp): org = AURIX_RPMSG_SHMEM_START, len = AURIX_RPMSG_SHMEM_SIZE +#if CONFIG_CPU_COREID != 0 + syslogram (w!xp): org = LCF_SYSLOG_START, len = LCF_SYSLOG_SIZE +#endif +} + +/* map cached and non cached addresses */ +REGION_MIRROR("pfls", "pfls_nc") +REGION_MIRROR("cpu_dlmu", "cpu_dlmu_nc") + +/*Sections located at absolute fixed address*/ +/*Fixed memory Allocations for stack memory*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.ustack) (LCF_DSPR_KERNEL_START + LCF_USTACK_OFFSET): + { + PROVIDE(__USTACK_END = .); + PROVIDE(COREID_MID(__USTACK, _END) = .); + . = . + LCF_USTACK_SIZE; + PROVIDE(__USTACK = .); + PROVIDE(COREID_LST(__USTACK) = .); + } + + CORE_SEC(.istack) (LCF_DSPR_KERNEL_START + LCF_ISTACK_OFFSET): + { + PROVIDE(__ISTACK_END = .); + PROVIDE(COREID_MID(__ISTACK, _END) = .); + . = . + LCF_ISTACK_SIZE; + PROVIDE(__ISTACK = .); + PROVIDE(COREID_LST(__ISTACK) = .); + } + CORE_SEC(.csa) (LCF_DSPR_KERNEL_START + LCF_CSA_OFFSET): + { + PROVIDE(COREID_LST(__CSA) = .); + . = . + LCF_CSA_SIZE; + PROVIDE(COREID_MID(__CSA, _END) = .); + } +} + +/*Fixed memory Allocations for _START*/ +CORE_ID = GLOBAL ; +SECTIONS +{ + .start_tc (LCF_STARTPTR) : FLAGS(rxl) + { + KEEP (*(.start)); + KEEP (*(.start_cpu?)); + } > pfls + + .interface_const (LCF_STARTPTR + 0x20) : + { + __IF_CONST = .; + KEEP (*(.interface_const)); + } > pfls + + PROVIDE(__START = LCF_STARTPTR); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU3 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 1); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 1); +} + +/*Fixed memory Allocations for Trap Vector Table*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .traptab_tc (LCF_TRAPVEC_START) : + { + PROVIDE(COREID_LST(__TRAPTAB_CPU) = .); + KEEP (*(.COREID_LST(traptab_cpu))); + } > pfls +} + +/*Fixed memory Allocations for _START1 to 5 */ +CORE_ID = GLOBAL ; +SECTIONS +{ + PROVIDE(__START1 = CORE1_PFLASH_KERNEL_START); + PROVIDE(__START2 = CORE2_PFLASH_KERNEL_START); + PROVIDE(__START3 = CORE3_PFLASH_KERNEL_START); + PROVIDE(__START4 = CORE4_PFLASH_KERNEL_START); + PROVIDE(__START5 = CORE5_PFLASH_KERNEL_START); +} + +/*Fixed memory Allocations for Interrupt Vector Table*/ +SECTIONS +{ + /*Interrupt Vector Table*/ + .COREID_MID(inttab_tc, _0FF) (COREID_LST(__INTTAB_CPU) + 0x1FE0) : + { + . = ALIGN(8); + KEEP (*(.COREID_MID(intvec_tc, _255))); + . = ALIGN(0x2000); + } > pfls +} + +/* Fixed memory Allocations for BMHD*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .bmhd_0_org (0xae404800) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb + .bmhd_1_org (0xae405000) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb + .bmhd_2_org (0xae405800) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb + .bmhd_3_org (0xae406000) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb + .usercfg_0_org (0xae408800) : FLAGS(arl) { KEEP (*(.usercfg_0_orig)); } > ucb + .usercfg_0_cpy (0xae409000) : FLAGS(arl) { KEEP (*(.usercfg_0_copy)); } > ucb +} + +/*Relative A0/A1/A8/A9 Addressable Sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ + /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A0 Addressable Data, selectable by toolchain*/ + CORE_SEC(.sdata) : FLAGS(awsl) + { + *(.sdata) + *(.sdata.*) + . = ALIGN(4); + } > cpu_dlmu AT> pfls + + CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) + { + *(.sbss) + *(.sbss.*) + } > cpu_dlmu + _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; + __A0_MEM = _SMALL_DATA_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ + /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A1 Addressable Const, selectable by toolchain*/ + CORE_SEC(.sdata2) : FLAGS(arsl) + { + *(.srodata) + *(.srodata.*) + } > pfls + _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; + __A1_MEM = _SMALL_DATA2_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata4) : + { + *(.a9sdata) + *(.a9sdata.*) + . = ALIGN(4); + } > cpu_dlmu AT> pfls + + CORE_SEC(.sbss4) (NOLOAD) : + { + *(.a9sbss) + *(.a9sbss.*) + } > cpu_dlmu + + _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; + __A9_MEM = _SMALL_DATA4_; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata3) : FLAGS(arsl) + { + *(.rodata_a8) + *(.rodata_a8.*) + } > pfls + + _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; + __A8_MEM = _SMALL_DATA3_; +} + +/*kstack*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) + { + *(.dtcm_stack) + *(.dtcm_stack.*) + } > kstack +} + +/*data&bss*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.dspr_data) : FLAGS(awzl) + { + *Ifx_Ssw_Tc?.* (.data) + *Cpu?_Main.* (.data.*) + . = ALIGN(4); + } > dspr AT> pfls + + CORE_SEC(.dspr_bss) (NOLOAD) : FLAGS(awz) + { + *Ifx_Ssw_Tc?.* (.bss) + *Cpu?_Main.* (.bss.*) + *os_scheduletable_misc.* (.bss.*) + *iob_initialize.* (.bss.*) + . = ALIGN(4); + } > dspr + + CORE_SEC(.zdata) : FLAGS(awzl) + { + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.z.*) + . = ALIGN(4); + } > cpu_dlmu AT> pfls + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + } > cpu_dlmu + + CORE_SEC(.data) : FLAGS(awl) + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(4); + } > cpu_dlmu AT> pfls + + CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) + { + *(.bss) + *(.bss.*) + *(.lmubss_cpu?) + *(.lmubss_cpu?.*) + *(.gnu.linkonce.b.*) + } > cpu_dlmu +} + +/*Heap*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .dlmuheap (NOLOAD) : FLAGS(aw) + { + . = ALIGN(4); + __DLMUHEAP = ABSOLUTE(.); + __DLMUHEAP_END = ABSOLUTE(LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE); + } > cpu_dlmu + + .heap (NOLOAD) : FLAGS(aw) + { + . = ALIGN(4); + _sheap = ABSOLUTE(.); + _eheap = ABSOLUTE(__USTACK_END); + } > dspr +} + +/*syslog*/ +#if CONFIG_CPU_COREID != 0 +CORE_ID = GLOBAL; +SECTIONS +{ + .syslog (NOLOAD) : FLAGS(aw) + { + . = ALIGN(4); + *(.syslog) + *(.syslog.*) + } > syslogram +} +#endif + +/*rodata*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + /* + * Create the clear and copy tables that tell the startup code + * which memory areas to clear and to copy, respectively. + */ + . = ALIGN(4) ; + PROVIDE(__clear_table = .); + LONG(0 + ADDR(.dspr_bss)); LONG(SIZEOF(.dspr_bss)); + LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); + LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); + + LONG(-1); LONG(-1); + PROVIDE(__clear_table_powerOn = .); + LONG(-1); LONG(-1); + PROVIDE(__copy_table = .); + LONG(LOADADDR(.dspr_data)); LONG(0 + ADDR(.dspr_data)); LONG(SIZEOF(.dspr_data)); + LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); + LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); + LONG(LOADADDR(.psram_text)); LONG(0 + ADDR(.psram_text)); LONG(SIZEOF(.psram_text)); + LONG(-1); LONG(-1); LONG(-1); + PROVIDE(__copy_table_powerOn = .) ; + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(8); + } > pfls +} + +/*Code selections*/ +/*Code Sections, selectable with patterns and user defined sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *Ifx_Ssw_Tc?.* (.zrodata) + *Cpu?_Main.* (.zrodata) + *(.zrodata_cpu?) + *(.zrodata) + *(.zrodata.*) + } > pfls + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + .init : + { + PROVIDE(__init_start = .); + KEEP(*(.init)) + KEEP(*(.init*)) + PROVIDE(__init_end = .); + . = ALIGN(8); + + } > pfls + + .fini : + { + PROVIDE(__fini_start = .); + KEEP(*(.fini)) + KEEP(*(.fini*)) + PROVIDE(__fini_end = .); + . = ALIGN(8); + } > pfls + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + CORE_SEC(.psram_text) : FLAGS(awxl) + { + . = ALIGN(4); + *aurix_mtd_flash.*(.text) + *aurix_mtd_flash.*(.text.*) + *aurix_mtd_partition.*(.text) + *aurix_mtd_partition.*(.text.*) + . = ALIGN(4); + } > pspr AT> pfls + + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(4); + *Ifx_Ssw_Tc?.*(.text) + *Cpu?_Main.*(.text) + *Ifx_Ssw_Tc?.*(.text.*) + *Cpu?_Main.*(.text.*) + *(.text) + *(.text.*) + *(.gcc_except_table) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(8); + } > pfls + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : ALIGN(8) + { + KEEP (*(.eh_frame_hdr)) + . = ALIGN(8); + } > pfls + + .eh_frame : ALIGN(8) + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > pfls + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + _sinit = ABSOLUTE(.); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + _einit = ABSOLUTE(.); + . = ALIGN(8); + } > pfls + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > pfls + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user new file mode 100644 index 00000000000..98393894ed5 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user @@ -0,0 +1,264 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") + +LCF_PFLASH_USER_START = GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID); +LCF_PFLASH_USER_SIZE = GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID); +LCF_DLMU_USER_START = GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID); +LCF_DLMU_USER_SIZE = GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID); +LCF_USTACK_START = GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID); +LCF_USTACK_SIZE = GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID); + +MEMORY +{ + upfls (rx!p): org = LCF_PFLASH_USER_START, len = LCF_PFLASH_USER_SIZE + upfls_nc (rx!p): org = NC_START(LCF_PFLASH_USER_START), len = LCF_PFLASH_USER_SIZE + + cpu_udlmu (w!xp): org = LCF_DLMU_USER_START, len = LCF_DLMU_USER_SIZE + cpu_udlmu_nc (w!xp): org = NC_START(LCF_DLMU_USER_START), len = LCF_DLMU_USER_SIZE + + ustack (w!xp): org = LCF_USTACK_START, len = LCF_USTACK_SIZE +} + +/* map cached and non cached addresses */ +REGION_MIRROR("upfls", "upfls_nc") +REGION_MIRROR("cpu_udlmu", "cpu_udlmu_nc") + +/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ + +/*Code Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + .userspace : ALIGN(64) + { + _suserspace = ABSOLUTE(.); + KEEP(*(.userspace)) + . = ALIGN(64); /* userspace align to 64 to keep the address continuous for MBF */ + _euserspace = ABSOLUTE(.); + } > upfls + + CORE_SEC(.text) : FLAGS(axl) + { + _stext = ABSOLUTE(.); + *(.text) + *(.text.*) + *(.zrodata) + *(.zrodata.*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.gcc_except_table) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(4); + _etext = ABSOLUTE(.); + } > upfls + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : ALIGN(8) + { + KEEP (*(.eh_frame_hdr)) + . = ALIGN(8); + } > upfls + + .eh_frame : ALIGN(8) + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > upfls + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + _sinit = ABSOLUTE(.); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + _einit = ABSOLUTE(.); + . = ALIGN(8); + } > upfls + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ destructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > upfls + + _eronly = ABSOLUTE(.); + + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} + +/*Far Data Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) + { + *(.dtcm_stack) + *(.dtcm_stack.*) + } > ustack + + CORE_SEC(.data) : FLAGS(awzl) + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.z.*) + . = ALIGN(2); + _edata = ABSOLUTE(.); + } > cpu_udlmu AT> upfls + + CORE_SEC(.bss) (NOLOAD): FLAGS(awz) + { + _sbss = ABSOLUTE(.); + *(.bss) + *(.bss.*) + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > cpu_udlmu + + .heap (NOLOAD) : FLAGS(aw) + { + _sheap = ABSOLUTE(.); + _eheap = ABSOLUTE(LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE); + } > cpu_udlmu + + _sdata_pflash = LOADADDR(.data); +} + +#if CONFIG_CPU_COREID == 5 +/* This sections is added to reserve last 4 bytes of flash in core5's user + * space. This is because the car's diagnostic service will query this area, + * and if the area has been erased but not written to, the query will cause + * an exception. Since the page size of pflash is 32 bytes, we reserve 32 + * bytes instead of 4 bytes. + */ + +CORE_ID = GLOBAL; +SECTIONS +{ + .flash_reserve (LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) : { + . = ALIGN(32); + FILL(0x55); + . = . + 28; + LONG(0x55555555); + } > upfls +} +#endif diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel new file mode 100644 index 00000000000..79dc34e3891 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel @@ -0,0 +1,639 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +#define __JOIN2(x,y) x##y +#define JOIN2(x,y) __JOIN2(x,y) +#define __JOIN3(x,y,z) x##y##z +#define JOIN3(x,y,z) __JOIN3(x,y,z) +#define __JOIN4(x,y,z,w) x##y##z##w +#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) + +#ifdef USE_PREFIX +# define K_PREFIX(x) kernel_##x +# define K_PREFIX_COREID_LST(x) JOIN3(kernel_, x, CONFIG_CPU_COREID) +# define K_PREFIX_COREID_MID(x,y) JOIN4(kernel_, x, CONFIG_CPU_COREID, y) +#else +# define K_PREFIX(x) x +# define K_PREFIX_COREID_LST(x) JOIN2(x, CONFIG_CPU_COREID) +# define K_PREFIX_COREID_MID(x,y) JOIN3(x, CONFIG_CPU_COREID, y) +#endif + +#define LCF_PFLASH_KERNEL_START GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_PFLASH_KERNEL_SIZE GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_DSPR_KERNEL_START GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_DSPR_KERNEL_SIZE GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_PSPR_KERNEL_START GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_PSPR_KERNEL_SIZE GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_DLMU_KERNEL_START GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_DLMU_KERNEL_SIZE GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID) +#define LCF_KSTACK_START GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID) +#define LCF_KSTACK_SIZE GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID) + +#if CONFIG_CPU_COREID != 0 +#define LCF_SYSLOG_START JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_START) +#define LCF_SYSLOG_SIZE JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_SIZE) +#endif + +#define LCF_CSA_SIZE 40k +#define LCF_USTACK_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_HEAP_SIZE 4k + +#define LCF_CPU0 0 +#define LCF_CPU1 1 +#define LCF_CPU2 2 +#define LCF_CPU3 3 +#define LCF_CPU4 4 +#define LCF_CPU5 5 + +/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ +#define LCF_DEFAULT_HOST LCF_CPU0 + +#define LCF_CSA_OFFSET (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE) +#define LCF_ISTACK_OFFSET (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE) +#define LCF_USTACK_OFFSET (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE) +#define LCF_HEAP_OFFSET (LCF_USTACK_OFFSET - LCF_HEAP_SIZE) + +#define LCF_STARTPTR_CPU LCF_PFLASH_KERNEL_START +#define LCF_TRAPVEC_START (LCF_STARTPTR_CPU + 0x20) +#define LCF_INTVEC_START LCF_PFLASH_KERNEL_START + +#define LCF_STARTPTR_NC_CPU0 NC_START(CORE0_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU1 NC_START(CORE1_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU2 NC_START(CORE2_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU3 NC_START(CORE3_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU4 NC_START(CORE4_PFLASH_KERNEL_START) +#define LCF_STARTPTR_NC_CPU5 NC_START(CORE5_PFLASH_KERNEL_START) + +#define INTTAB (LCF_INTVEC_START) + +#define RESET CORE0_PFLASH_KERNEL_START + +#include "tc1v1_8.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc4D; +} + +derivative tc4D +{ + core tc + { + architecture = TC1V1.8; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.8; + import tc; // add all address spaces of core tc to core vtc for linking and locating + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory dsram // Data Scratch Pad Ram + { + mau = 8; + size = LCF_DSPR_KERNEL_SIZE; + type = ram; + map (dest=bus:tc:fpi_bus, dest_offset=DSPR_LOCAL_START, size=LCF_DSPR_KERNEL_SIZE, priority=8); + map (dest=bus:sri, dest_offset=LCF_DSPR_KERNEL_START, size=LCF_DSPR_KERNEL_SIZE); + } + + memory psram // Program Scratch Pad Ram + { + mau = 8; + size = LCF_PSPR_KERNEL_SIZE; + type = ram; + map (dest=bus:tc:fpi_bus, dest_offset=PSPR_LOCAL_START, size=LCF_PSPR_KERNEL_SIZE, priority=8); + map (dest=bus:sri, dest_offset=LCF_PSPR_KERNEL_START, size=LCF_PSPR_KERNEL_SIZE); + } + + memory pfls + { + mau = 8; + size = LCF_PFLASH_KERNEL_SIZE; + type = rom; + map cached (dest=bus:sri, dest_offset=LCF_PFLASH_KERNEL_START, size=LCF_PFLASH_KERNEL_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_KERNEL_START), reserved, size=LCF_PFLASH_KERNEL_SIZE); + } + + memory ucb + { + mau = 8; + size = 80K; + type = rom; + map (dest=bus:sri, dest_offset=0xae400000, reserved, size=80K); + } + + memory cpu_dlmu + { + mau = 8; + size = LCF_DLMU_KERNEL_SIZE; + type = ram; + map cached (dest=bus:sri, dest_offset=LCF_DLMU_KERNEL_START, size=LCF_DLMU_KERNEL_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_KERNEL_START), reserved, size=LCF_DLMU_KERNEL_SIZE); + } + + memory kstack + { + mau = 8; + size = LCF_KSTACK_SIZE; + type = ram; + map not_cached (dest=bus:sri, dest_offset=LCF_KSTACK_START, size=LCF_KSTACK_SIZE); + } + +#if CONFIG_CPU_COREID != 0 + memory syslog + { + mau = 8; + size = LCF_SYSLOG_SIZE; + type = ram; + map not_cached (dest=bus:sri, dest_offset=LCF_SYSLOG_START, size=LCF_SYSLOG_SIZE); + } +#endif + + section_setup :vtc:linear + { + heap "heap1" (min_size = LCF_HEAP_SIZE, align = 4); + heap "heap2" (min_size = LCF_HEAP_SIZE, align = 4); + } + + section_setup :vtc:linear + { + start_address + ( +#if CONFIG_CPU_COREID == 0 + symbol = "_START" +#elif CONFIG_CPU_COREID == 1 + symbol = "_START1" +#elif CONFIG_CPU_COREID == 2 + symbol = "_START2" +#elif CONFIG_CPU_COREID == 3 + symbol = "_START3" +#elif CONFIG_CPU_COREID == 4 + symbol = "_START4" +#elif CONFIG_CPU_COREID == 5 + symbol = "_START5" +#endif + ); + } + + section_setup :vtc:linear + { + stack "ustack_tc" (min_size = 1k, fixed, align = 8); + stack "istack_tc" (min_size = 1k, fixed, align = 8); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc"; + space = :tc:linear, :tc:abs24, :tc:abs18; + } + ); + } + + /*Sections located at absolute fixed address*/ + + section_layout :vtc:linear + { + /*Fixed memory Allocations for stack memory*/ + group (ordered) + { + group ustack(align = 8, run_addr = mem:dsram[LCF_USTACK_OFFSET]) + { + stack "ustack_tc" (size = LCF_USTACK_SIZE); + } + "__USTACK"= sizeof(group:ustack) > 0 ? "_lc_ue_ustack_tc" : 0; + "__USTACK_END"="_lc_gb_ustack"; + "__USTACK0_END"="_lc_gb_ustack"; + "__USTACK1_END"="_lc_gb_ustack"; + "__USTACK2_END"="_lc_gb_ustack"; + "__USTACK3_END"="_lc_gb_ustack"; + "__USTACK4_END"="_lc_gb_ustack"; + "__USTACK5_END"="_lc_gb_ustack"; + "__USTACK0":= "__USTACK"; + "__USTACK1":= "__USTACK"; + "__USTACK2":= "__USTACK"; + "__USTACK3":= "__USTACK"; + "__USTACK4":= "__USTACK"; + "__USTACK5":= "__USTACK"; + + group istack(align = 8, run_addr = mem:dsram[LCF_ISTACK_OFFSET]) + { + stack "istack_tc" (size = LCF_ISTACK_SIZE); + } + "__ISTACK"= sizeof(group:istack) > 0 ? "_lc_ue_istack_tc" : 0; + "__ISTACK_END"="_lc_gb_istack"; + "__ISTACK0":="__ISTACK"; + "__ISTACK1":="__ISTACK"; + "__ISTACK2":="__ISTACK"; + "__ISTACK3":="__ISTACK"; + "__ISTACK4":="__ISTACK"; + "__ISTACK5":="__ISTACK"; + } + + /*Fixed memory Allocations for _START*/ + group (ordered) + { + group interface_const (run_addr=mem:pfls[0x0020]) + { + select "*.interface_const"; + } + "__IF_CONST" := addressof(group:interface_const); + "__START0" := CORE0_PFLASH_KERNEL_START; + "__START1" := CORE1_PFLASH_KERNEL_START; + "__START2" := CORE2_PFLASH_KERNEL_START; + "__START3" := CORE3_PFLASH_KERNEL_START; + "__START4" := CORE4_PFLASH_KERNEL_START; + "__START5" := CORE5_PFLASH_KERNEL_START; + } + + /*Fixed memory Allocations for Trap Vector Table*/ + group (ordered) + { + group trapvec_tc (align = 8, run_addr=LCF_TRAPVEC_START) + { + section "trapvec_tc" (size=0x100, attributes=rx, fill=0) + { +#if CONFIG_CPU_COREID == 0 + select "(.text.traptab_cpu0*)"; +#elif CONFIG_CPU_COREID == 1 + select "(.text.traptab_cpu1*)"; +#elif CONFIG_CPU_COREID == 2 + select "(.text.traptab_cpu2*)"; +#elif CONFIG_CPU_COREID == 3 + select "(.text.traptab_cpu3*)"; +#elif CONFIG_CPU_COREID == 4 + select "(.text.traptab_cpu4*)"; +#elif CONFIG_CPU_COREID == 5 + select "(.text.traptab_cpu5*)"; +#endif + } + } + "__TRAPTAB_CPU0" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU1" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU2" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU3" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU4" := LCF_TRAPVEC_START; + "__TRAPTAB_CPU5" := LCF_TRAPVEC_START; + } + + /*Fixed memory Allocations for Start up code*/ + group (ordered, attributes=rx) + { + group start_tc (run_addr=(LCF_STARTPTR_CPU)) + { +#if CONFIG_CPU_COREID == 0 + select "(.text.start*)"; +#elif CONFIG_CPU_COREID == 1 + select "(.text.start_cpu1*)"; +#elif CONFIG_CPU_COREID == 2 + select "(.text.start_cpu2*)"; +#elif CONFIG_CPU_COREID == 3 + select "(.text.start_cpu3*)"; +#elif CONFIG_CPU_COREID == 4 + select "(.text.start_cpu4*)"; +#elif CONFIG_CPU_COREID == 5 + select "(.text.start_cpu5*)"; +#endif + } + "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU3" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU4" := 1; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU5" := 1; /* Not used */ + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + group (ordered, attributes=rx) + { + group int_tab_tc (ordered) + { + group (run_addr=(INTTAB)+0x1FE0) select ".text.inttab0.intvec.0ff"; + } + "_lc_u_int_tab" = (LCF_INTVEC_START); + "__INTTAB_CPU0" = (LCF_INTVEC_START); + "__INTTAB_CPU1" = (LCF_INTVEC_START); + "__INTTAB_CPU2" = (LCF_INTVEC_START); + "__INTTAB_CPU3" = (LCF_INTVEC_START); + "__INTTAB_CPU4" = (LCF_INTVEC_START); + "__INTTAB_CPU5" = (LCF_INTVEC_START); + } + + /*Fixed memory Allocations for BMHD*/ + group (ordered) + { + group bmh_0_orig (run_addr=mem:ucb[0x4800]) + { + select ".rodata.bmhd_0_orig"; + } + group bmh_1_orig (run_addr=mem:ucb[0x5000]) + { + select ".rodata.bmhd_1_orig"; + } + group bmh_2_orig (run_addr=mem:ucb[0x5800]) + { + select ".rodata.bmhd_2_orig"; + } + group bmh_3_orig (run_addr=mem:ucb[0x6000]) + { + select ".rodata.bmhd_3_orig"; + } + group usercfg_0_org (run_addr=mem:ucb[0x8800]) + { + select ".rodata.usercfg_0_orig"; + } + group usercfg_0_cpy (run_addr=mem:ucb[0x9000]) + { + select ".rodata.usercfg_0_copy"; + } + } + } + + /*Near Abbsolute Addressable Data Sections*/ + section_layout :vtc:abs18 + { + /*Near Absolute Data, selectable with patterns and user defined sections*/ + group + { + group (ordered, attributes=rw, run_addr = mem:cpu_dlmu) + { + select "(.zdata.zlmudata|.zdata.zlmudata.*)"; + select "(.zbss.zlmubss|.zbss.zlmubss.*)"; + } + } + + /*Near Absolute Data, selectable by toolchain*/ + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) + { + group zdata(attributes=rw) + { + select "(.zdata|.zdata.*)"; + select "(.zbss|.zbss.*)"; + } + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + group + { + group (ordered, contiguous, align = 4, attributes=r, run_addr=mem:pfls) + { +#if CONFIG_CPU_COREID == 0 + select ".zrodata.Ifx_Ssw_Tc?.*"; + select ".zrodata.Cpu?_Main.*"; +#elif CONFIG_CPU_COREID == 1 + select ".zrodata.Ifx_Ssw_Tc1.*"; + select ".zrodata.Cpu1_Main.*"; +#elif CONFIG_CPU_COREID == 2 + select ".zrodata.Ifx_Ssw_Tc2.*"; + select ".zrodata.Cpu2_Main.*"; +#elif CONFIG_CPU_COREID == 3 + select ".zrodata.Ifx_Ssw_Tc3.*"; + select ".zrodata.Cpu3_Main.*"; +#elif CONFIG_CPU_COREID == 4 + select ".zrodata.Ifx_Ssw_Tc4.*"; + select ".zrodata.Cpu4_Main.*"; +#elif CONFIG_CPU_COREID == 5 + select ".zrodata.Ifx_Ssw_Tc5.*"; + select ".zrodata.Cpu5_Main.*"; +#endif + /*Near Absolute Const, selectable by toolchain*/ + select "(.zrodata|.zrodata.*)"; + } + } + } + + /*Relative A0/A1/A8/A9 Addressable Sections*/ + section_layout :vtc:linear + { + /*Relative A0 Addressable Data, selectable by toolchain*/ + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) + { + select "(.sdata|.sdata.*)"; + select "(.data_a0|.data_a0.*)"; + select "(.sbss|.sbss.*)"; + select "(.bss_a0|.bss_a0.*)"; + } + "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; + "__A0_MEM" = "_SMALL_DATA_"; + + /*Relative A1 Addressable Const, selectable by toolchain*/ + /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ + group a1 (ordered, align = 4, attributes=r, run_addr=mem:pfls) + { + select "(.srodata|.srodata.*)"; + select "(.ldata|.ldata.*)"; + select "(.rodata_a1|.rodata_a1.*)"; + } + "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; + "__A1_MEM" = "_LITERAL_DATA_"; + + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + group a9 (ordered, align = 4, run_addr=mem:dsram) + { + select "(.a9sdata|.a9sdata.*)"; + select "(.data_a9|.data_a9.*)"; + select "(.a9sbss|.a9sbss.*)"; + select "(.bss_a9|.bss_a9.*)"; + } + "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; + "__A9_MEM" = "_A9_DATA_"; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + group a8 (ordered, align = 4, run_addr=mem:pfls) + { + select "(.a8srodata|.a8srodata.*)"; + select "(.rodata_a8|.rodata_a8.*)"; + } + "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; + "__A8_MEM" = "_A8_DATA_"; + } + + /*kstack ram*/ + section_layout :vtc:linear + { + group kstack(ordered, contiguous, nocopy, run_addr=mem:kstack) + { + select "(.dtcm_stack|.dtcm_stack.*)"; + } + } + +#if CONFIG_CPU_COREID != 0 + /*syslog ram*/ + section_layout :vtc:linear + { + group syslog(ordered, contiguous, nocopy, run_addr=mem:syslog) + { + select "(.syslog|.syslog.*)"; + } + } +#endif + + /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ + section_layout :vtc:linear + { + /*Far Data Sections, selectable with patterns and user defined sections*/ + + /*DSRAM sections*/ + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) + { + group (attributes=rw) + { + select ".data.Ifx_Ssw_Tc?.*"; + select ".data.Cpu?_Main.*"; + select ".bss.Ifx_Ssw_Tc?.*"; + select ".bss.Cpu?_Main.*"; + select ".bss.os_scheduletable_misc.*"; + select ".bss.iob_initialize.*"; + select "(.dspr_data|.dspr_data.*)"; + } + + group (attributes=rw, nocopy) + { + select "(.dspr_bss|.dspr_bss.*)"; + } + + /*Heap1*/ + group heap1(attributes=rw) + { + heap "heap1" (size = LCF_HEAP_SIZE); + } + "_sheap":="_lc_ub_heap1"; + "_eheap":="__USTACK_END"; + } + + /*LMU Data sections*/ + group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_dlmu/not_cached) + { + select "(.data.uncached.*)"; + select "(.bss.uncached.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr=mem:cpu_dlmu) + { + group lmubss(attributes=rw, nocopy) + { + select "(.lmubss_cpu?|.lmubss_cpu?.*)"; + } + + group data(attributes=rw) + { + select "(.data|.data.*)"; + select "(.bss|.bss.*)"; + } + + /*Heap2 allocation*/ + group heap2(attributes=rw) + { + heap "heap2" (size = LCF_HEAP_SIZE); + } + "__DLMUHEAP":="_lc_ge_data"; + "__DLMUHEAP_END":=LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE; + } + + /*Far Const Sections, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, attributes=r, run_addr=mem:pfls) + { + select ".rodata.Ifx_Ssw_Tc?.*"; + select ".rodata.Cpu?_Main.*"; + } + } + + /*Far Const Sections, selectable by toolchain*/ + group (ordered, align = 4, run_addr=mem:pfls) + { + select "(.rodata|.rodata.*)"; + select "(.constant|.constant.*)"; + } + } + + /* PSRAM Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Program Scratchpad Sections*/ + group + { + group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram) + { + select "(.text.aurix_mtd_flash|.text.aurix_mtd_flash.*)"; + select "(.text.aurix_mtd_partition|.text.aurix_mtd_partition.*)"; + } + } + } + } + + /* FLS Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Cpu specific PFLASH Sections*/ + group + { + group (ordered, align = 4, attributes=rx, run_addr=mem:pfls) + { + select ".text.Ifx_Ssw_Tc?.*"; + select ".text.Cpu?_Main.*"; + select ".text.CompilerTasking.Ifx_C_Init"; + } + } + } + + /*Code Sections, selectable by toolchain*/ + group text(ordered, contiguous, fill = 0, run_addr=mem:pfls) + { + select "(.text|.text.*)"; + } + "_stext" = "_lc_gb_text"; + "_etext" = "_lc_ge_text"; + } +} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user new file mode 100644 index 00000000000..0bb924ba689 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user @@ -0,0 +1,204 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "arch/board/board_memorymap.h" + +#define LCF_PFLASH_USER_START GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID) +#define LCF_PFLASH_USER_SIZE GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID) +#define LCF_DLMU_USER_START GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID) +#define LCF_DLMU_USER_SIZE GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID) +#define LCF_USTACK_START GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID) +#define LCF_USTACK_SIZE GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID) + +#define LCF_HEAP_SIZE 4k + +#include "tc1v1_8.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc4D; +} + +derivative tc4D +{ + core tc + { + architecture = TC1V1.8; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.8; + import tc; // add all address spaces of core tc to core vtc for linking and locating + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory upfls + { + mau = 8; + size = LCF_PFLASH_USER_SIZE; + type = rom; + map cached (dest=bus:sri, dest_offset=LCF_PFLASH_USER_START, size=LCF_PFLASH_USER_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_USER_START), reserved, size=LCF_PFLASH_USER_SIZE); + } + + memory cpu_udlmu + { + mau = 8; + size = LCF_DLMU_USER_SIZE; + type = ram; + map cached (dest=bus:sri, dest_offset=LCF_DLMU_USER_START, size=LCF_DLMU_USER_SIZE); + map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_USER_START), reserved, size=LCF_DLMU_USER_SIZE); + } + + memory ustack + { + mau = 8; + size = LCF_USTACK_SIZE; + type = ram; + map not_cached (dest=bus:sri, dest_offset=LCF_USTACK_START, size=LCF_USTACK_SIZE); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc"; + space = :tc:linear, :tc:abs24, :tc:abs18; + } + ); + } + + section_setup :vtc:linear + { + heap "uheap" (min_size = LCF_HEAP_SIZE, align = 4); + } + + /* user stack section */ + section_layout :vtc:linear + { + group ustack(ordered, contiguous, nocopy, run_addr=mem:ustack) + { + select "(.dtcm_stack|.dtcm_stack.*)"; + } + } + + /*Sections located at absolute fixed address*/ + section_layout :vtc:linear + { + group userspace(ordered, run_addr=LCF_PFLASH_USER_START) + { + select "(.userspace|.userspace.*)"; + } + "_suserspace" = "_lc_gb_userspace"; + "_euserspace" = "_lc_ge_userspace"; + + group text(ordered, contiguous, fill = 0, run_addr=mem:upfls) + { + select "(.text|.text.*)"; + select "(.zrodata|.zrodata.*)"; + select "(.rodata|.rodata.*)"; + select "(.constant|.constant.*)"; + } + "_stext" = "_lc_gb_text"; + "_etext" = "_lc_ge_text"; + } + + /* Data & Bss section */ + section_layout :vtc:linear + { + group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu/not_cached) + { + select "(.data.uncached.*)"; + select "(.bss.uncached.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu) + { + group udata + { + select "(.data|.data.*)"; + select "(.zdata|.zdata.*)"; + } + "_sdata" = "_lc_gb_udata"; + "_edata" = "_lc_ge_udata"; + + /* bss section */ + group ubss + { + select "(.bss|.bss.*)"; + select "(.zbss|.zbss.*)"; + select "(.bbss|.bbss.*)"; + } + "_sbss" = "_lc_gb_ubss"; + "_ebss" = "_lc_ge_ubss"; + + /* heap section */ + group uheap + { + heap "uheap" (size = LCF_HEAP_SIZE); + } + "_sheap" = "_ebss"; + "_eheap" = LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE; + } + + group udata_rom(ordered, contiguous, load_addr=mem:upfls) + { + select "(.data|.data.*)"; + select "(.zdata|.zdata.*)"; + } + "_sdata_pflash" = "_lc_gb_udata_rom"; + } +#if CONFIG_CPU_COREID == 5 + /* This sections is added to reserve last 4 bytes of flash in core5's user + * space. This is because the car's diagnostic service will query this area, + * and if the area has been erased but not written to, the query will cause + * an exception. Since the page size of pflash is 32 bytes, we reserve 32 + * bytes instead of 4 bytes. + */ + section_layout :vtc:linear + { + group flash_reserve(ordered, run_addr=LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) + { + reserved "flash_reserve" ( size = 32, attributes = r, fill = 0x55 ); + } + } +#endif +} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs new file mode 100644 index 00000000000..d015a3ceca6 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs @@ -0,0 +1,44 @@ +############################################################################ +# boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/tricore/src/tc4xx/Toolchain.defs + +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) + TRICORE_TOOLCHAIN := Tasking +else + TRICORE_TOOLCHAIN := Gnuc +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.kernel + +ifeq ($(CONFIG_BUILD_PROTECTED),y) + ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.user +endif + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt b/boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt new file mode 100644 index 00000000000..bcadeea22ba --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt @@ -0,0 +1,42 @@ +# ############################################################################## +# boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS tc4da_appinit.c tc4da_boardinit.c tc4da_bringup.c) + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_TRICORE_TOOLCHAIN_TASKING) + set(toolchain "Tasking") +else() + set(toolchain "Gnuc") +endif() + +set_property( + GLOBAL + PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.kernel") +if(CONFIG_BUILD_PROTECTED) + set_property( + GLOBAL + PROPERTY LD_SCRIPT_USER + "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.user") +endif() diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile b/boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile new file mode 100644 index 00000000000..3203a4e0d99 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile @@ -0,0 +1,31 @@ +############################################################################ +# boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = tc4da_boardinit.c tc4da_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += tc4da_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h new file mode 100644 index 00000000000..9cb69f9b2b8 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_SRC_TC4DA_H +#define __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_SRC_TC4DA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4da_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int tc4da_bringup(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_SRC_TC4DA_H */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_appinit.c b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_appinit.c new file mode 100644 index 00000000000..b239a347fc5 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_appinit.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_appinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "tc4da.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return tc4da_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c new file mode 100644 index 00000000000..adfdb89a8be --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "chip.h" +#include "tc4da.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4da_memory_initialize + * + * Description: + * All i.MX6 architectures must provide the following entry point. This + * entry point is called early in the initialization before memory has + * been configured. This board-specific function is responsible for + * configuring any on-board memories. + * + * Logic in tc4da_memory_initialize must be careful to avoid using any + * global variables because those will be uninitialized at the time this + * function is called. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void tc4da_memory_initialize(void) +{ + /* SDRAM was initialized by a bootloader in the supported configurations. */ +} + +/**************************************************************************** + * Name: tc4da_board_initialize + * + * Description: + * All i.MX6 architectures must provide the following entry point. This + * entry point is called in the initialization phase -- after + * tc4da_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void tc4da_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + tc4da_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c new file mode 100644 index 00000000000..b802b389f03 --- /dev/null +++ b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "tc4da.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4da_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int tc4da_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/tools/nxstyle.c b/tools/nxstyle.c index 78db86bd765..eec380b3975 100644 --- a/tools/nxstyle.c +++ b/tools/nxstyle.c @@ -724,6 +724,15 @@ static const char *g_white_files[] = */ "phy62xx/phyplus_wdt.c", + + /* Skip infineon illd files + * Ref: + * arch/tricore/src/illd + */ + + "Ifx_Cfg_Ssw.c", + "Ifx_Cfg_Ssw.h", + "Ifx_Cfg.h", NULL };