mirror of
https://github.com/apache/nuttx.git
synced 2026-05-23 14:58:13 +08:00
risc-v/litex: Add 64-bit S-mode vexiiriscv support for litex.
Most of the peripheral support matches litex vexriscv-smp. * arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64. * arch/risc-v/src/litex/Make.defs arch/risc-v/src/litex/hardware/litex_clint.h arch/risc-v/src/litex/hardware/litex_memorymap.h arch/risc-v/src/litex/hardware/litex_plic.h arch/risc-v/src/litex/litex_irq.c arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV conditional where vexriscv_smp conditionals are. * boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config. * boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion. * boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map. * boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for toolchain happiness matching other RISC-V linker scripts. (This commit was written with assistance from Claude Code.) Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
This commit is contained in:
Justin Erenkrantz
committed by
Alan C. Assis
Alan C. Assis
parent
1f5cd930a4
commit
7298977894
+19
-2
@@ -44,7 +44,6 @@ config ARCH_CHIP_K210
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config ARCH_CHIP_LITEX
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bool "Enjoy Digital LITEX VEXRISCV"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_DCACHE
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@@ -53,7 +52,7 @@ config ARCH_CHIP_LITEX
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select LIBC_FDT
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select DEVICE_TREE
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---help---
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA or RV64GC).
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config ARCH_CHIP_BL602
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bool "BouffaloLab BL602"
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@@ -783,9 +782,11 @@ choice
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config LITEX_CORE_VEXRISCV
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bool "vexriscv core"
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select ARCH_RV32
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config LITEX_CORE_VEXRISCV_SMP
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bool "vexriscv_smp core"
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select ARCH_RV32
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select ARCH_HAVE_MPU
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select ARCH_RV_ISA_C
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select ARCH_MMU_TYPE_SV32
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@@ -795,6 +796,22 @@ config LITEX_CORE_VEXRISCV_SMP
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select ARCH_HAVE_ELF_EXECUTABLE
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select ARCH_HAVE_PERF_EVENTS
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config LITEX_CORE_VEXIIRISCV
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bool "vexiiriscv core"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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select ARCH_MMU_TYPE_SV39
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ARCH_HAVE_ELF_EXECUTABLE
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select ARCH_HAVE_PERF_EVENTS
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endchoice # LITEX Core Selection
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endif # ARCH_CHIP_LITEX
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@@ -26,6 +26,8 @@ include common/Make.defs
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# the first object file, so it will appear at address 0
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ifeq ($(CONFIG_LITEX_CORE_VEXRISCV_SMP),y)
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HEAD_ASRC = litex_shead.S
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else ifeq ($(CONFIG_LITEX_CORE_VEXIIRISCV),y)
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HEAD_ASRC = litex_shead.S
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else
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HEAD_ASRC = litex_head.S
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endif
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@@ -26,7 +26,7 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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#define LITEX_CLINT_MSIP (LITEX_CLINT_BASE + 0x0000)
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#define LITEX_CLINT_MTIMECMP (LITEX_CLINT_BASE + 0x4000)
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@@ -38,6 +38,6 @@
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#define LITEX_CLINT_MTIME (LITEX_CPUTIMER_BASE + 0x04)
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#define LITEX_CLINT_MTIMECMP (LITEX_CPUTIMER_BASE + 0x0C)
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#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP */
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#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP || CONFIG_LITEX_CORE_VEXIIRISCV */
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#endif /* __ARCH_RISCV_SRC_LITEX_HARDWARE_LITEX_CLINT_H */
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@@ -37,7 +37,7 @@
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/* Register Base Address ****************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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#define LITEX_CLINT_BASE 0xf0010000
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#define LITEX_PLIC_BASE 0xf0c00000
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#define LITEX_ETHMAC_BASE 0xf0002000
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@@ -33,7 +33,7 @@
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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# define LITEX_PLIC_PRIORITY (LITEX_PLIC_BASE + 0x000000)
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# define LITEX_PLIC_PENDING1 (LITEX_PLIC_BASE + 0x001000)
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@@ -68,8 +68,8 @@ void up_irqinitialize(void)
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/* litex vexriscv dont have priority and threshold control */
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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/* litex vexriscv_smp does. */
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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/* litex vexriscv_smp and vexiiriscv do. */
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/* Set priority for all global interrupts to 1 (lowest) */
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@@ -106,7 +106,7 @@ void up_irqinitialize(void)
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*
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****************************************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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void up_disable_irq(int irq)
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{
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int extirq;
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@@ -187,7 +187,7 @@ void up_disable_irq(int irq)
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*
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****************************************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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void up_enable_irq(int irq)
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{
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int extirq;
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@@ -49,7 +49,7 @@
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* riscv_dispatch_irq
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****************************************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
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void *riscv_dispatch_irq(uintptr_t vector, uintreg_t *regs)
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{
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int irq = (vector & 0x3f);
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@@ -0,0 +1,74 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_DISABLE_PTHREAD is not set
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# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set
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# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set
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# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set
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# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set
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# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set
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# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
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# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
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# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
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# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set
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# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set
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# CONFIG_NSH_DISABLEBG is not set
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# CONFIG_NSH_DISABLE_LOSMART is not set
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# CONFIG_NSH_DISABLE_UNAME is not set
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# CONFIG_STANDARD_SERIAL is not set
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CONFIG_ARCH="risc-v"
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CONFIG_ARCH_BOARD="arty_a7"
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CONFIG_ARCH_BOARD_ARTY_A7=y
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CONFIG_ARCH_CHIP="litex"
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CONFIG_ARCH_CHIP_LITEX=y
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CONFIG_ARCH_INTERRUPTSTACK=8192
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CONFIG_ARCH_RISCV=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARCH_USE_S_MODE=y
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CONFIG_BOARDCTL_RESET=y
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CONFIG_BOARD_LOOPSPERMSEC=10000
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEFAULT_SMALL=y
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CONFIG_DEV_ZERO=y
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CONFIG_EXAMPLES_HELLO=y
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CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
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CONFIG_FS_PROCFS=y
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CONFIG_IDLETHREAD_STACKSIZE=8192
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INIT_STACKSIZE=8192
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBC_PERROR_STDOUT=y
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CONFIG_LIBC_STRERROR=y
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CONFIG_LITEX_CORE_VEXIIRISCV=y
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CONFIG_LITEX_CUSTOM_IRQ_DEFINITIONS_PATH="../../../../boards/risc-v/litex/arty_a7/include/vexii_irq.h"
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CONFIG_LITEX_CUSTOM_MEMORY_MAP_PATH="../../../../boards/risc-v/litex/arty_a7/include/vexii_memorymap.h"
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CONFIG_LITEX_USE_CUSTOM_IRQ_DEFINITIONS=y
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CONFIG_LITEX_USE_CUSTOM_MEMORY_MAP=y
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CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=64
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CONFIG_NSH_STRERROR=y
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CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192
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CONFIG_PTHREAD_STACK_DEFAULT=8192
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CONFIG_RAM_SIZE=268435456
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CONFIG_RAM_START=0x40000000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_WAITPID=y
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CONFIG_STACK_COLORATION=y
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CONFIG_START_DAY=20
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CONFIG_START_MONTH=3
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CONFIG_START_YEAR=2020
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CONFIG_SYSTEM_NSH=y
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CONFIG_TASK_NAME_SIZE=12
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CONFIG_TESTING_GETPRIME=y
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CONFIG_UART0_RXBUFSIZE=128
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CONFIG_UART0_SERIAL_CONSOLE=y
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CONFIG_UART0_TXBUFSIZE=128
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@@ -0,0 +1,67 @@
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/****************************************************************************
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* boards/risc-v/litex/arty_a7/include/vexii_irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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* Auto-generated: 2025-12-28 11:16:55
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* Source: LiteX soc.h
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*
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****************************************************************************/
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#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H
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#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/mode.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Custom IRQ definitions for LiteX VexiiRISCV core */
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/* Map RISC-V external IRQs to NuttX IRQ numbers */
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#define LITEX_IRQ_UART0 (RISCV_IRQ_EXT + 1)
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#define LITEX_IRQ_TIMER0 (RISCV_IRQ_EXT + 2)
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#define LITEX_IRQ_ETHMAC (RISCV_IRQ_EXT + 3)
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#define LITEX_IRQ_GPIO_BASE (RISCV_IRQ_EXT + 4)
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#define LITEX_IRQ_GPIO_LENGTH 8
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/* The last hardware IRQ number */
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#define LITEX_IRQ_LAST (LITEX_IRQ_GPIO_BASE + LITEX_IRQ_GPIO_LENGTH)
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/* Second level GPIO interrupts if enabled */
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#ifdef CONFIG_LITEX_GPIO_IRQ
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# define LITEX_NIRQ_GPIO (LITEX_IRQ_GPIO_LENGTH * 32)
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# define LITEX_FIRST_GPIOIRQ (LITEX_IRQ_LAST + 1)
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# define LITEX_LAST_GPIOIRQ (LITEX_FIRST_GPIOIRQ + LITEX_NIRQ_GPIO)
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#else
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# define LITEX_NIRQ_GPIO 0
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#endif
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/* Total number of IRQs */
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#define NR_IRQS (LITEX_IRQ_LAST + LITEX_NIRQ_GPIO + 1)
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#endif /* __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H */
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@@ -0,0 +1,58 @@
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/****************************************************************************
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* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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* Auto-generated: 2025-12-28 11:16:55
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* Source: LiteX csr.h
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*
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****************************************************************************/
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#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H
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#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Custom memory map for LiteX VexiiRISCV core */
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/* Core Peripherals */
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#define LITEX_CLINT_BASE 0xf0010000UL
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#define LITEX_PLIC_BASE 0xf0c00000UL
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/* SOC Peripherals */
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#define LITEX_UART0_BASE 0xf0001000UL
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#define LITEX_TIMER0_BASE 0xf0001800UL
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/* Ethernet (if enabled) */
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#define LITEX_ETHMAC_BASE 0xf0002000UL
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#define LITEX_ETHPHY_BASE 0xf0002800UL
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/* Other Peripherals */
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#define LITEX_CTRL_BASE 0xf0000000UL
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#define LITEX_DDRPHY_BASE 0xf0000800UL
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#define LITEX_IDENTIFIER_MEM_BASE 0xf0003000UL
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#define LITEX_LEDS_BASE 0xf0003800UL
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#define LITEX_SDRAM_BASE 0xf0004000UL
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#endif /* __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H */
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@@ -68,6 +68,8 @@ SECTIONS
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_edata = ABSOLUTE(.);
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} > sram AT > progmem
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PROVIDE(__global_pointer$ = _sdata + ((_edata - _sdata) / 2));
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.bss : ALIGN(4) {
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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