diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 13fb1557151..b9d7bd31fad 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -44,7 +44,6 @@ config ARCH_CHIP_K210 config ARCH_CHIP_LITEX bool "Enjoy Digital LITEX VEXRISCV" - select ARCH_RV32 select ARCH_RV_ISA_M select ARCH_RV_ISA_A select ARCH_DCACHE @@ -53,7 +52,7 @@ config ARCH_CHIP_LITEX select LIBC_FDT select DEVICE_TREE ---help--- - Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA). + Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA or RV64GC). config ARCH_CHIP_BL602 bool "BouffaloLab BL602" @@ -783,9 +782,11 @@ choice config LITEX_CORE_VEXRISCV bool "vexriscv core" + select ARCH_RV32 config LITEX_CORE_VEXRISCV_SMP bool "vexriscv_smp core" + select ARCH_RV32 select ARCH_HAVE_MPU select ARCH_RV_ISA_C select ARCH_MMU_TYPE_SV32 @@ -795,6 +796,22 @@ config LITEX_CORE_VEXRISCV_SMP select ARCH_HAVE_ELF_EXECUTABLE select ARCH_HAVE_PERF_EVENTS +config LITEX_CORE_VEXIIRISCV + bool "vexiiriscv core" + select ARCH_RV64 + select ARCH_RV_ISA_M + select ARCH_RV_ISA_A + select ARCH_RV_ISA_C + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARCH_HAVE_MPU + select ARCH_MMU_TYPE_SV39 + select ARCH_HAVE_ADDRENV + select ARCH_NEED_ADDRENV_MAPPING + select ARCH_HAVE_S_MODE + select ARCH_HAVE_ELF_EXECUTABLE + select ARCH_HAVE_PERF_EVENTS + endchoice # LITEX Core Selection endif # ARCH_CHIP_LITEX diff --git a/arch/risc-v/src/litex/Make.defs b/arch/risc-v/src/litex/Make.defs index b2e1ba55fb6..736fb2ed8cd 100644 --- a/arch/risc-v/src/litex/Make.defs +++ b/arch/risc-v/src/litex/Make.defs @@ -26,6 +26,8 @@ include common/Make.defs # the first object file, so it will appear at address 0 ifeq ($(CONFIG_LITEX_CORE_VEXRISCV_SMP),y) HEAD_ASRC = litex_shead.S +else ifeq ($(CONFIG_LITEX_CORE_VEXIIRISCV),y) +HEAD_ASRC = litex_shead.S else HEAD_ASRC = litex_head.S endif diff --git a/arch/risc-v/src/litex/hardware/litex_clint.h b/arch/risc-v/src/litex/hardware/litex_clint.h index 13ff369a7e8..d475d6e77ad 100644 --- a/arch/risc-v/src/litex/hardware/litex_clint.h +++ b/arch/risc-v/src/litex/hardware/litex_clint.h @@ -26,7 +26,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) #define LITEX_CLINT_MSIP (LITEX_CLINT_BASE + 0x0000) #define LITEX_CLINT_MTIMECMP (LITEX_CLINT_BASE + 0x4000) @@ -38,6 +38,6 @@ #define LITEX_CLINT_MTIME (LITEX_CPUTIMER_BASE + 0x04) #define LITEX_CLINT_MTIMECMP (LITEX_CPUTIMER_BASE + 0x0C) -#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP */ +#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP || CONFIG_LITEX_CORE_VEXIIRISCV */ #endif /* __ARCH_RISCV_SRC_LITEX_HARDWARE_LITEX_CLINT_H */ diff --git a/arch/risc-v/src/litex/hardware/litex_memorymap.h b/arch/risc-v/src/litex/hardware/litex_memorymap.h index 69f774f4840..54cc063254d 100644 --- a/arch/risc-v/src/litex/hardware/litex_memorymap.h +++ b/arch/risc-v/src/litex/hardware/litex_memorymap.h @@ -37,7 +37,7 @@ /* Register Base Address ****************************************************/ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) #define LITEX_CLINT_BASE 0xf0010000 #define LITEX_PLIC_BASE 0xf0c00000 #define LITEX_ETHMAC_BASE 0xf0002000 diff --git a/arch/risc-v/src/litex/hardware/litex_plic.h b/arch/risc-v/src/litex/hardware/litex_plic.h index 08ea1f24774..126da3e064a 100644 --- a/arch/risc-v/src/litex/hardware/litex_plic.h +++ b/arch/risc-v/src/litex/hardware/litex_plic.h @@ -33,7 +33,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) # define LITEX_PLIC_PRIORITY (LITEX_PLIC_BASE + 0x000000) # define LITEX_PLIC_PENDING1 (LITEX_PLIC_BASE + 0x001000) diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c index 61d0d8b0a1e..a07ee939555 100644 --- a/arch/risc-v/src/litex/litex_irq.c +++ b/arch/risc-v/src/litex/litex_irq.c @@ -68,8 +68,8 @@ void up_irqinitialize(void) /* litex vexriscv dont have priority and threshold control */ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP - /* litex vexriscv_smp does. */ +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) + /* litex vexriscv_smp and vexiiriscv do. */ /* Set priority for all global interrupts to 1 (lowest) */ @@ -106,7 +106,7 @@ void up_irqinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) void up_disable_irq(int irq) { int extirq; @@ -187,7 +187,7 @@ void up_disable_irq(int irq) * ****************************************************************************/ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) void up_enable_irq(int irq) { int extirq; diff --git a/arch/risc-v/src/litex/litex_irq_dispatch.c b/arch/risc-v/src/litex/litex_irq_dispatch.c index e2903be3519..9a435ddf58b 100644 --- a/arch/risc-v/src/litex/litex_irq_dispatch.c +++ b/arch/risc-v/src/litex/litex_irq_dispatch.c @@ -49,7 +49,7 @@ * riscv_dispatch_irq ****************************************************************************/ -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP +#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV) void *riscv_dispatch_irq(uintptr_t vector, uintreg_t *regs) { int irq = (vector & 0x3f); diff --git a/boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig b/boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig new file mode 100644 index 00000000000..830eefba0b6 --- /dev/null +++ b/boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="arty_a7" +CONFIG_ARCH_BOARD_ARTY_A7=y +CONFIG_ARCH_CHIP="litex" +CONFIG_ARCH_CHIP_LITEX=y +CONFIG_ARCH_INTERRUPTSTACK=8192 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LITEX_CORE_VEXIIRISCV=y +CONFIG_LITEX_CUSTOM_IRQ_DEFINITIONS_PATH="../../../../boards/risc-v/litex/arty_a7/include/vexii_irq.h" +CONFIG_LITEX_CUSTOM_MEMORY_MAP_PATH="../../../../boards/risc-v/litex/arty_a7/include/vexii_memorymap.h" +CONFIG_LITEX_USE_CUSTOM_IRQ_DEFINITIONS=y +CONFIG_LITEX_USE_CUSTOM_MEMORY_MAP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192 +CONFIG_PTHREAD_STACK_DEFAULT=8192 +CONFIG_RAM_SIZE=268435456 +CONFIG_RAM_START=0x40000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=20 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2020 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TESTING_GETPRIME=y +CONFIG_UART0_RXBUFSIZE=128 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_UART0_TXBUFSIZE=128 diff --git a/boards/risc-v/litex/arty_a7/include/vexii_irq.h b/boards/risc-v/litex/arty_a7/include/vexii_irq.h new file mode 100644 index 00000000000..77bbb5a6ed2 --- /dev/null +++ b/boards/risc-v/litex/arty_a7/include/vexii_irq.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/risc-v/litex/arty_a7/include/vexii_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * Auto-generated: 2025-12-28 11:16:55 + * Source: LiteX soc.h + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H +#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Custom IRQ definitions for LiteX VexiiRISCV core */ + +/* Map RISC-V external IRQs to NuttX IRQ numbers */ + +#define LITEX_IRQ_UART0 (RISCV_IRQ_EXT + 1) +#define LITEX_IRQ_TIMER0 (RISCV_IRQ_EXT + 2) +#define LITEX_IRQ_ETHMAC (RISCV_IRQ_EXT + 3) +#define LITEX_IRQ_GPIO_BASE (RISCV_IRQ_EXT + 4) +#define LITEX_IRQ_GPIO_LENGTH 8 + +/* The last hardware IRQ number */ + +#define LITEX_IRQ_LAST (LITEX_IRQ_GPIO_BASE + LITEX_IRQ_GPIO_LENGTH) + +/* Second level GPIO interrupts if enabled */ + +#ifdef CONFIG_LITEX_GPIO_IRQ +# define LITEX_NIRQ_GPIO (LITEX_IRQ_GPIO_LENGTH * 32) +# define LITEX_FIRST_GPIOIRQ (LITEX_IRQ_LAST + 1) +# define LITEX_LAST_GPIOIRQ (LITEX_FIRST_GPIOIRQ + LITEX_NIRQ_GPIO) +#else +# define LITEX_NIRQ_GPIO 0 +#endif + +/* Total number of IRQs */ + +#define NR_IRQS (LITEX_IRQ_LAST + LITEX_NIRQ_GPIO + 1) + +#endif /* __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H */ diff --git a/boards/risc-v/litex/arty_a7/include/vexii_memorymap.h b/boards/risc-v/litex/arty_a7/include/vexii_memorymap.h new file mode 100644 index 00000000000..b92004115ea --- /dev/null +++ b/boards/risc-v/litex/arty_a7/include/vexii_memorymap.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * boards/risc-v/litex/arty_a7/include/vexii_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * Auto-generated: 2025-12-28 11:16:55 + * Source: LiteX csr.h + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H +#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Custom memory map for LiteX VexiiRISCV core */ + +/* Core Peripherals */ + +#define LITEX_CLINT_BASE 0xf0010000UL +#define LITEX_PLIC_BASE 0xf0c00000UL + +/* SOC Peripherals */ + +#define LITEX_UART0_BASE 0xf0001000UL +#define LITEX_TIMER0_BASE 0xf0001800UL + +/* Ethernet (if enabled) */ + +#define LITEX_ETHMAC_BASE 0xf0002000UL +#define LITEX_ETHPHY_BASE 0xf0002800UL + +/* Other Peripherals */ + +#define LITEX_CTRL_BASE 0xf0000000UL +#define LITEX_DDRPHY_BASE 0xf0000800UL +#define LITEX_IDENTIFIER_MEM_BASE 0xf0003000UL +#define LITEX_LEDS_BASE 0xf0003800UL +#define LITEX_SDRAM_BASE 0xf0004000UL + +#endif /* __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H */ diff --git a/boards/risc-v/litex/arty_a7/scripts/ld.script b/boards/risc-v/litex/arty_a7/scripts/ld.script index 24a1bc3854f..c23fad5ac31 100644 --- a/boards/risc-v/litex/arty_a7/scripts/ld.script +++ b/boards/risc-v/litex/arty_a7/scripts/ld.script @@ -68,6 +68,8 @@ SECTIONS _edata = ABSOLUTE(.); } > sram AT > progmem + PROVIDE(__global_pointer$ = _sdata + ((_edata - _sdata) / 2)); + .bss : ALIGN(4) { _sbss = ABSOLUTE(.); *(.bss .bss.*)