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jjlange
2019-06-05 09:58:24 -05:00
parent 3c11d9e7f0 215a146f2e
commit 6d135294ba
3080 changed files with 125348 additions and 26116 deletions
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<html>
<head>
<title>NuttShell</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
<p>Last Updated: February 11, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<div class="container">
<div class="toc">
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
@@ -21,7 +14,7 @@
</tr>
</table>
<center><table width ="80%">
<table width ="80%" class="toc_table">
<tr>
<td>
<table>
@@ -626,7 +619,21 @@
<a href="#index">Index</a>
</td>
</tr>
</table></center>
</table></table>
</div>
<div class="main">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
<p>Last Updated: February 11, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<table width ="100%">
<tr bgcolor="#e4e4e4">
@@ -1494,7 +1501,7 @@ date [-s &quot;MMM DD HH:MM:SS YYYY&quot;]
Only one format is used both on display and when setting the date/time:
<code>MMM DD HH:MM:SS YYYY</code>. For example,
<ul><pre>
data -s &quot;Sep 1 11:30:00 2011&quot;
date -s &quot;Sep 1 11:30:00 2011&quot;
</pre></ul>
</p>
<p>
@@ -3731,7 +3738,7 @@ nsh&gt;
</tr>
<tr>
<td><b><code>kill</code></b></td>
<td>!<code>CONFIG_DISABLE_SIGNALS</code></td>
<td>&nbsp;</td>
<td><code>CONFIG_NSH_DISABLE_KILL</code></td>
</tr>
<tr>
@@ -3881,7 +3888,7 @@ nsh&gt;
</tr>
<tr>
<td><b><code>sleep</code></b></td>
<td>!<code>CONFIG_DISABLE_SIGNALS</code></td>
<td>&nbsp;</td>
<td><code>CONFIG_NSH_DISABLE_SLEEP</code></td>
</tr>
<tr>
@@ -3941,7 +3948,7 @@ nsh&gt;
</tr>
<tr>
<td><b><code>usleep</code></b></td>
<td>!<code>CONFIG_DISABLE_SIGNALS</code></td>
<td>&nbsp;</td>
<td><code>CONFIG_NSH_DISABLE_USLEEP</code></td>
</tr>
<tr>
@@ -3996,12 +4003,12 @@ nsh&gt;
<tr>
<td><b><code>ping</code></b></td>
<td><code>CONFIG_NET</code> &amp;&amp; <code>CONFIG_NET_ICMP</code> &amp;&amp;
<code>CONFIG_NET_ICMP_SOCKET</code> &amp;&amp; <code>CONFIG_SYSTEM_PING</code> &amp;&amp; !<code>CONFIG_DISABLE_SIGNALS</code> &amp;&amp; !<code>CONFIG_DISABLE_POLL</code></td>
<code>CONFIG_NET_ICMP_SOCKET</code> &amp;&amp; <code>CONFIG_SYSTEM_PING</code></td>
</tr>
<tr>
<td><b><code>ping6</code></b></td>
<td><code>CONFIG_NET</code> &amp;&amp; <code>CONFIG_NET_ICMPv6</code> &amp;&amp;
<code>CONFIG_NET_ICMPv6_SOCKET</code> &amp;&amp; <code>CONFIG_SYSTEM_PING6</code> &amp;&amp; !<code>CONFIG_DISABLE_SIGNALS</code> &amp;&amp; !<code>CONFIG_DISABLE_POLL</code></td>
<code>CONFIG_NET_ICMPv6_SOCKET</code> &amp;&amp; <code>CONFIG_SYSTEM_PING6</code></td>
</tr>
</table></center>
@@ -5912,5 +5919,7 @@ xxd -i romfs_img >nsh_romfsimg.h
</ul></td>
</tr></table>
</div>
</div>
</body>
</html>
Documentation/NuttX.html
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<html>
<head>
<title>NuttX</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: March 25, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<div class="container">
<div class="toc">
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
@@ -21,7 +14,7 @@
</tr>
</table>
<center><table width ="80%">
<table width ="80%" class="toc_table">
<tr>
<td>
<table>
@@ -102,7 +95,20 @@
</table>
</td>
</tr>
</table></center>
</table>
</div>
<div class="main">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: May 19, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<table width ="100%">
<tr bgcolor="#e4e4e4">
@@ -1461,11 +1467,11 @@
<h2>Released Versions</h2>
<p>
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
The current release is NuttX 7.29.
NuttX 7.29 is the 129<sup>th</sup> release of NuttX.
It was released on March 25, 2019, and is available for download from the
The current release is NuttX 7.30.
NuttX 7.30 is the 130<sup>th</sup> release of NuttX.
It was released on May 19, 2019, and is available for download from the
<a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
Note that the release consists of two tarballs: <code>nuttx-7.29.tar.gz</code> and <code>apps-7.29.tar.gz</code>.
Note that the release consists of two tarballs: <code>nuttx-7.30.tar.gz</code> and <code>apps-7.30.tar.gz</code>.
Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
</p>
@@ -1474,7 +1480,7 @@
<ul>
<li><b>nuttx</b>.
<ul><p>
Release notes for NuttX 7.29 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
Release notes for NuttX 7.30 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
The ChangeLog for the current release is at the bottom of that file.
@@ -1482,7 +1488,7 @@
</li></ul>
<li><b>apps</b>.
<ul><p>
Release notes for NuttX 7.29 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
Release notes for NuttX 7.30 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
The ChangeLog for the current release is at the bottom of that file.
@@ -1540,8 +1546,8 @@
<li><a href="#armcortexr4">ARM Cortex-R4</a> (2)</li>
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (10)</li>
<li><a href="#armcortexm3">ARM Cortex-M3</a> (39)</li>
<li><a href="#armcortexm4">ARM Cortex-M4</a> (55)</li>
<li><a href="#armcortexm7">ARM Cortex-M7</a> (13)</li>
<li><a href="#armcortexm4">ARM Cortex-M4</a> (56)</li>
<li><a href="#armcortexm7">ARM Cortex-M7</a> (14)</li>
</ul>
<li>Atmel AVR
<ul>
@@ -1755,6 +1761,11 @@
<li><a href="#efm32gg">EFM32 Giant Gecko</a> <small>(ARM Cortex-M3)</small></li>
</ul>
</li>
<li>Sony.
<ul>
<li><a href="#cxd56xx">CXD56<i>xx</i></a> <small>(6 x ARM Cortex-M4)</small></li>
</ul>
</li>
<li>STMicroelectronics
<ul>
<li><a href="#str71x">STMicro STR71x</a> <small>(ARM7TDMI)</small></li>
@@ -3197,33 +3208,8 @@ nsh>
Contributed by Juha Niskanen in NuttX-7.21.
</li>
</ul>
<p>
<b>STATUS:</b>
</p>
<ul>
<li>
<b>NuttX-7.21</b>.
In this initial release, the level of support for the STM32 F0 family is minimal.
Certainly enough is in place to support a robust NSH configuration.
There are also unverified I2C and USB device drivers available in
NuttX-7.21.
</li>
<li>
<b>NuttX-7.28</b>
Added support for GPIO EXTI. From Mateusz Sfafoni.
</li>
<li>
<b>NuttX-7.29</b>
Added an SPI driver. From Mateusz Sfafoni.
</li>
</p>
</td>
</tr>
<tr>
<td><br></td>
<td><hr></td>
</tr>
<tr>
<td><br></td>
<td>
@@ -3242,9 +3228,39 @@ nsh>
Contributed byMateusz Sfafoni in NuttX-7.28.
</li>
</ul>
</tr>
<tr>
<td><br></td>
<td>
<p>
<b>STATUS:</b>
Status for both the STM32F0xx and STM32L0xx is show together since the two parts share many drivers in common.
</p>
<ul>
<li>
<b>NuttX-7.21</b>.
In this initial release, the level of support for the STM32 F0 family is minimal.
Certainly enough is in place to support a robust NSH configuration.
There are also unverified I2C and USB device drivers available in
NuttX-7.21.
</li>
<li>
<b>NuttX-7.28</b>
Added support for GPIO EXTI. From Mateusz Sfafoni.
</li>
<li>
<b>NuttX-7.29</b>
Added an SPI driver. From Mateusz Sfafoni.
</li>
<li>
<b>NuttX-7.30</b>
Added ADC and I2C drivers. From Mateusz Szafoni.
Add AES and RND drivers for the L0. From Mateusz Szafoni.
Add support for HS148 for L0. From Mateusz Szafoni.
</li>
</p>
</td>
</tr>
<tr>
<td><br></td>
<td><hr></td>
@@ -3906,7 +3922,7 @@ nsh>
<td>
<p>
<a name="lc823450"><b>ON Semiconductor LC823450 (Dual core ARM Cortex-M3)</b>.</a>
In NuttX-7.22, Masayuki Ishakawa contributed support for both the LC823450 architecture and for ON Semiconductor's <b>LC823450XGEVK board</b>:
In NuttX-7.22, Masayuki Ishikawa contributed support for both the LC823450 architecture and for ON Semiconductor's <b>LC823450XGEVK board</b>:
</p>
<blockquote>
The LC823450XGEVK is an audio processing system Evaluation Board Kit used to demonstrate the LC823450. This part can record and playback, and offers High-Resolution 32-bit & 192 kHz audio processing capability. It is possible to cover most of the functions necessary for a portable audio with only this LSI as follows. It has Dual CPU and DSP with High processing capability, and internal 1656K-Byte SRAM, which make it possible to implement large scale program. And it has integrated analog functions (low-power Class D HP amplifier, PLL, ADC etc.) so that PCB space and cost is reduced, and it has various interface (USB, SD, SPI, UART, etc.) to make extensibility high. Also it is provided with various function including SBC/AAC codec by DSP and UART and ASRC (Asynchronous Sample Rate Converter) for Bluetooth® audio. It is very small chip size in spite of the multi-funciton as described above and it realizes the low power consumption. Therefore, it is applicable to portable audio markets such as Wireless headsets and will show high performance.
@@ -3917,8 +3933,8 @@ nsh>
</p>
<p>
This port is intended to test LC823450 features including SMP. Supported peripherals include UART, TIMER, RTC, GPIO, DMA, I2C, SPI, LCD, eMMC, and USB device.
ADC, Watchdog, IPC2, and I2S support was added by Masayuki Ishakawa in NuttX-7.23.
Bluetooth, SPI, and <i>PROTECTED</i> build support were added by Masayuki Ishakawa in NuttX-7.26.
ADC, Watchdog, IPC2, and I2S support was added by Masayuki Ishikawa in NuttX-7.23.
Bluetooth, SPI, and <i>PROTECTED</i> build support were added by Masayuki Ishikawa in NuttX-7.26.
Support for for SPI flash boot was added in NuttX-7.28.
</p>
</td>
@@ -4208,6 +4224,7 @@ nsh>
</td>
</tr>
</tr>
<tr>
<td><br></td>
<td><hr></td>
@@ -4216,8 +4233,32 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f302x"><b>STMicro STM32 F302 (STM32 F3 family)</b>.</a>
Architecture (only) support for the STM32 F302 was contributed in NuttX-7.10 by Ben Dyer (vi the PX4 team and David Sidrane).
<a name="cxd56xx"><b>Sony CXD56<i>xx</i></a></b> (6 x ARM Cortex-M4).</a>
Support for the CXD56<i>xx</i> was introduced by Nobuto Kobayashi in NuttX-7.30.
</p>
<p>
<b>Sony Spresence</b>.</a>
Basic support for the Sony Spresense board was include in the contribution of Nobuto Kobayashi in NuttX-7.30. <i>NOTE</i>: This is a bare bone basic Spresense port sufficient for running a NuttShell (NSH) and should not be confused with the full Spresence SDK offered from Sony.
</p>
Spresense is a compact development board based on Sony’s power-efficient multicore microcontroller CXD5602. Features:
</p>
<ul>
<li>Integrated GPS: Embedded GNSS with support for GPS, QZSS.</li>
<li>Hi-res audio output and multi mic inputs" Advanced 192kHz/24 bit audio codec and amplifier for audio output, and support for up to 8 mic input channels.</li>
<li>Multicore microcontroller: Spresense is powered by Sony's CXD5602 microcontroller (ARM® Cortex®-M4F × 6 cores), with a clock speed of 156 MHz.</li>
</ul>
</td>
</tr>
<tr>
<td><br></td>
<td><hr></td>
</tr>
<tr>
<td><br></td>
<td>
<p>
<a name="stm32f302x"><b>STMicro STM32 F302</b> (STM32 F3 family).</a>
Architecture (only) support for the STM32 F302 was contributed in NuttX-7.10 by Ben Dyer (via the PX4 team and David Sidrane).
</p>
<p>
Support for the Nucleo-F302R8 board was added by raiden00pl in NuttX-7.27.
@@ -4233,7 +4274,7 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f303x"><b>STMicro STM32 F303 (STM32 F3 family)</b>.</a>
<a name="stm32f303x"><b>STMicro STM32 F303</b> (STM32 F3 family).</a>
<p>
<ul>
<li><p>
@@ -4273,7 +4314,7 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f334x"><b>STMicro STM32 F334 (STM32 F3 family, ARM Cortex-M4)</b>.</a>
<a name="stm32f334x"><b>STMicro STM32 F334</b> (STM32 F3 family, ARM Cortex-M4).</a>
</p>
<p>
Support for the STMicro <b>STM32F334-Disco</b> board was contributed by Mateusz Szafoni in NuttX-7.22 and for the <b>Nucleo-STM32F334R8</b> was contributed in an earlier release.
@@ -4289,7 +4330,7 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f372x"><b>STMicro STM32 F372/F373 (Cortex-M4)</b>.</a>
<a name="stm32f372x"><b>STMicro STM32 F372/F373</b> (ARM Cortex-M4).</a>
<p>
<p>
Basic architecture support for the STM32F372/F373 was contributed by Marten Svanfeldt in NuttX 7.9.
@@ -4306,7 +4347,7 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f4x1"><b>STMicro STM324x1 (STM32 F4 family)</b>.</a>
<a name="stm32f4x1"><b>STMicro STM324x1</b> (STM32 F4 family).</a>
<p>
<ul>
<p>
@@ -4347,7 +4388,7 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f410"><b>STMicro STM32410 (STM32 F4 family)</b>.</a>
<a name="stm32f410"><b>STMicro STM32410</b> (STM32 F4 family).</a>
<p>
<ul>
<p>
@@ -4364,7 +4405,7 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32f407x"><b>STMicro STM32405x/407x (STM32 F4 family)</b>.</a>
<a name="stm32f407x"><b>STMicro STM32405x/407x</b> (STM32 F4 family).</a>
<p>
<ul>
<p>
@@ -4761,6 +4802,10 @@ nsh>
<ul>
<li>DAC and ADC drivers were contributed by Juha Niskanen.</li>
</ul>
<p>
<b>NuttX-7.30</b>.
<ul>
<li>Added USB FS device driver, CRS and HSI38 support from Juha Niskanen.</li>
</p>
</td>
</tr>
@@ -5537,6 +5582,9 @@ Mem: 29232 5920 23312 23312
See the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-144/README.txt">README.txt</a> file for further information.
</p>
</ul>
<p><b>STATUS</b>:
See <a href="#stm32f7drivers">below</a> for STM32 F7 driver availability.
</p>
</td>
</tr>
@@ -5556,6 +5604,7 @@ Mem: 29232 5920 23312 23312
<p>
<b>STM32F746G Discovery</b>.
One port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
The first release of the STM32F746G_DISCO port was available in NuttX-7.11.
Refer to the <a href="http://www.st.com/stm32f7-discovery">STMicro web site</a> for further information about this board.
</p>
</li>
@@ -5569,17 +5618,8 @@ Mem: 29232 5920 23312 23312
<ul>
<p>
<b>STATUS:</b>
</p>
<ul>
<p>
The basic STM32F746G-DISCO port is complete and there are two, verified configurations available.
Both configurations use the NuttShell (NSH) and a serial console; one includes Ethernet support.
The first release of the STM32F746G_DISCO port was available in NuttX-7.11.
</p>
</p>
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm32f746g-disco/README.txt" target="_blank">README</a> file for further information.
</p>
</ul>
</p>
</ul>
<p>
<a name="stm32f7drivers"><b>STM32 F7 Driver Status:</b></a>
@@ -5596,9 +5636,22 @@ Mem: 29232 5920 23312 23312
David Sidrane contributed PWR, RTC, BBSRAM, and DBGMCU support.
Lok Tep contribed SPI, I2c, ADC, SDMMC, and USB device driver support.
</li>
<li>
<p><b>NuttX-7.22</b>.
Titus von Boxberg also contributed LTDC support for the onboard LCD in NuttX-7.22.
</p>
</li>
<li>
<p><b>NuttX-7.29</b>.
In NuttX-7.29, Valmantas Paliksa added a timer lowerhalf driver for STM32F7, ITM syslog support, a CAN driver with support for three bxCAN interfaces, and STM32F7 Quad SPI support.
In NuttX-7.29, Valmantas Paliksa added a timer lowerhalf driver for STM32F7, ITM syslog support, a CAN driver with support for three bxCAN interfaces, and STM32F7 Quad SPI support.
Support for DMA and USB OTG was added by Mateusz Szafoni in NuttX-7.29.
</p>
</li>
<li>
<p><b>NuttX-7.30</b>.
From Eduard Niesner contributed a PWM driver.
Added UID access from Valmantas Paliksa.
USB High speed driver was added for STM32F7 series by Ramtin Amin.
</li>
</ul>
</td>
@@ -5663,15 +5716,12 @@ Mem: 29232 5920 23312 23312
<li>Ethernet connector compliant with IEEE-802.3-2002 and PoE</li>
</ul>
<p>
Refer to the http://www.st.com website for further information about this board (search keyword: stm32f769i-disco)
</p>
<p>
Titus von Boxberg also contributed LTDC support for the onboard LCD in NuttX-7.22.
See the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-144/README.txt">README.txt</a> file for further information.
Refer to the http://www.st.com website for further information about this board (search keyword: stm32f769i-disco).
See also the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-144/README.txt">README.txt</a> file for further information.
</p>
</li>
</ul>
<p>
<p><b>STATUS</b>:
See <a href="#stm32f7drivers">above</a> for STM32 F7 driver availability.
</p>
</td>
@@ -5696,15 +5746,29 @@ Mem: 29232 5920 23312 23312
This is a member of the Nucleo-144 board family.
Support for this board was also added NuttX-7.26.
See the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-h743zi/README.txt">README.txt</a> file for further information.
</p>
<p>
The basic NSH configuration is fully, thanks to the bring-up efforts of Mateusz Szafoni.
This port is port is still a work in progress and additional drivers are being ported from the F7 family.
</p>
</li>
</ul>
<p>
<b>NuttX-7.29</b>
Support for DMA and USB OTG was added by Mateusz Szafoni in NuttX-7.29.
</tr>
<tr>
<td><br></td>
<td>
<p><b>Driver Availability</b>:</p>
<ul>
<li>
<p><b>NuttX-7.27</b>.
Add I2C and SPI support for the STM32H7. From Mateusz Szafoni.
</p>
</li>
<li>
<p><b>NuttX-7.30</b>.
Added support for Ethernet, SDMMC, and Timer drivers. All from Jukka Laitinen.
</p>
</li>
</p>
</td>
</tr>
@@ -5733,9 +5797,13 @@ Mem: 29232 5920 23312 23312
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/imxrt1050-evk/README.txt" target="_blank">README</a> file for further information.
</p></li>
<li><p>
The basic IMXRT1060-EVK port is complete but un-verified as of NuttX-7.27.
The basic IMXRT1060-EVK port was complete but un-verified as of NuttX-7.27 but has been fully verified since NuttX-7.27
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/imxrt1060-evk/README.txt" target="_blank">README</a> file for more current status information.
</p></li>
<li><p>
Architecture-only support for the IMXRT1020 family was contributed in NuttX-7.30 by Dave Marples.
Board support is anticipated in the next release.
</p></li>
</ul>
<p>
<b>i.MX RT Driver Status:</b>
@@ -7046,5 +7114,7 @@ if [ -x "$WINELOADER" ]; then exec "$WINELOADER" "$appname" "$@"; fi
</p>
</small>
</div>
</div>
</body>
</html>
Documentation/NuttXBinfmt.html
+1
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@@ -1,6 +1,7 @@
<html>
<head>
<title>NuttX Binary Loader</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
Documentation/NuttXCCodingStandard.html
+22 -14
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@@ -2,22 +2,12 @@
<head>
<title>NuttX C Coding Standard</title>
<meta name="author" content="Gregory Nutt">
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: February 5, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<body>
<div class="container">
<div class="toc">
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
@@ -74,6 +64,21 @@
<a href="#hfilestructure">A.2 C Header File Structure</a>
</ul>
</ul>
</div>
<div class="main">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: February 5, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<table width ="100%">
<tr bgcolor="#e4e4e4">
@@ -2984,5 +2989,8 @@ Each is preceded by a function header similar to the above.</i></p>
</pre>
<p><i>Ending with the header file <a href="#idempotence">idempotence</a> <code>#endif</code>.</i></p>
</div>
</div>
</body>
</html>
Documentation/NuttXDemandPaging.html
+1
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@@ -1,6 +1,7 @@
<html>
<head>
<title>On-Demand Paging</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
Documentation/NuttXNxFlat.html
+1
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@@ -1,6 +1,7 @@
<html>
<head>
<title>NXFLAT</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
Documentation/NuttxPortingGuide.html
+35 -29
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@@ -2,22 +2,13 @@
<head>
<title>NuttX Porting Guide</title>
<meta name="author" content="Gregory Nutt">
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec">
<i>NuttX RTOS Porting Guide</i>
</font></big></h1>
<p>Last Updated: February 18, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<body>
<div class="container">
<div class="toc">
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
@@ -238,6 +229,22 @@
<a href="#apndxconfigs">Appendix A: NuttX Configuration Settings</a><br>
<a href="#apndxtrademarks">Appendix B: Trademarks</a>
</ul>
</div>
<div class="main">
<hr><hr>
<table width ="100%">
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec">
<i>NuttX RTOS Porting Guide</i>
</font></big></h1>
<p>Last Updated: May 25, 2019</p>
</td>
</tr>
</table>
<hr><hr>
<table width ="100%">
<tr bgcolor="#e4e4e4">
@@ -481,7 +488,7 @@
<p>
<b>Configuration Files</b>.
The NuttX configuration consists of logic in processor architecture directories, chip/SoC directories, and board configuration directories.
The NuttX configuration consists of logic in processor architecture directories, <i>chip/SoC</i> directories, and board configuration directories.
The complete configuration is specified by several settings in the NuttX configuration file.
</p>
<ul>
@@ -1773,7 +1780,7 @@ The specific environmental definitions are unique for each board but should incl
This strict layering is enforced in the NuttX build system by controlling the compiler include paths: Higher level code can never include header files from either; of the platform-specific source directories; microcontroller-specific code can never include header files from the board-specific source directories. The board-specific directories are, then, at the bottom of the layered hierarchy.
</p>
<p>
An exception to these inclusion restrictions is the platform-specific <i>include/</i>. These are made available to higher level OS logic. The microcontroller-specific include directory will be linked at <code>include/arch/chip</code> and, hence, can be included like <code>#include &lt;arch/chip/chip.h</code>.
An exception to these inclusion restrictions is the platform-specific <i>include/</i>. These are made available to higher level OS logic. The microcontroller-specific include directory will be linked at <code>include/arch/chip</code> and, hence, can be included like <code>#include &lt;arch/hardware/chip.h</code>.
Similarly, the board-specific include directory will be linked at <code>include/arch/board</code> and, hence, can be included like <code>#include &lt;arch/board/board.h</code>.
</p>
<p>
@@ -2176,10 +2183,6 @@ The specific environmental definitions are unique for each board but should incl
handler now.
</li>
</ol>
<p>
This API is <i>NOT</i> required if <code>CONFIG_DISABLE_SIGNALS</code>
is defined.
</p>
<h3><a name="upallocateheap">4.2.15 <code>up_allocate_heap()</code></a></h3>
<p><b>Function Prototype</b>: <code>void up_allocate_heap(FAR void **heap_start, size_t *heap_size);</code></p>
@@ -5168,7 +5171,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
<li>
<p>
<b>Examples</b>:
<code>arch/arm/src/chip/lm_serial.c</code>, <code>arch/arm/src/lpc214x/lpc214x_serial.c</code>, <code>arch/z16/src/z16f/z16f_serial.c</code>, etc.
<code>arch/arm/src/stm32/stm32_serial.c</code>, <code>arch/arm/src/lpc214x/lpc214x_serial.c</code>, <code>arch/z16/src/z16f/z16f_serial.c</code>, etc.
</p>
</li>
</ul>
@@ -5201,7 +5204,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
The controller-specific, &quot;upper half&quot; touchscreen drivers reside in the directory <code>drivers/input</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific touchscreen drivers reside in either: (1) The <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the processor architectures that have build in touchscreen controllers or (2) the <code>configs/</code><i>&lt;board&gt;</i><code>/src/</code> directory for boards that use an external touchscreen controller chip.
Platform-specific touchscreen drivers reside in either: (1) The <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the processor architectures that have build in touchscreen controllers or (2) the <code>configs/</code><i>&lt;board&gt;</i><code>/src/</code> directory for boards that use an external touchscreen controller chip.
</li>
</ul>
@@ -5226,7 +5229,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
Common analog logic and share-able analog drivers reside in the <code>drivers/analog/</code>.
</li>
<li>
Platform-specific drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> analog peripheral devices.
Platform-specific drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> analog peripheral devices.
</li>
</ul>
@@ -5312,7 +5315,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
The generic, &quot;upper half&quot; PWM driver resides at <code>drivers/pwm.c</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific PWM drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> PWM peripheral devices.
Platform-specific PWM drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> PWM peripheral devices.
</li>
</ul>
@@ -5343,7 +5346,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
The generic, &quot;upper half&quot; CAN driver resides at <code>drivers/can.c</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific CAN drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> CAN peripheral devices.
Platform-specific CAN drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> CAN peripheral devices.
</li>
</ul>
<p>
@@ -5411,7 +5414,7 @@ for (i = 0; i &lt;= nread - CAN_MSGLEN(0); i += msglen)
The generic, &quot;upper half&quot; Quadrature Encoder driver resides at <code>drivers/sensors/qencoder.c</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific Quadrature Encoder drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> Quadrature Encoder peripheral devices.
Platform-specific Quadrature Encoder drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> Quadrature Encoder peripheral devices.
</li>
</ul>
@@ -5440,7 +5443,7 @@ for (i = 0; i &lt;= nread - CAN_MSGLEN(0); i += msglen)
The generic, &quot;upper half&quot; timer driver resides at <code>drivers/timers/timer.c</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific timer drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> timer peripheral devices.
Platform-specific timer drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> timer peripheral devices.
</li>
</ul>
@@ -5469,7 +5472,7 @@ for (i = 0; i &lt;= nread - CAN_MSGLEN(0); i += msglen)
The generic, &quot;upper half&quot; RTC driver resides at <code>drivers/timers/rtc.c</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific RTC drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> RTC peripheral devices.
Platform-specific RTC drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> RTC peripheral devices.
</li>
</ul>
@@ -5498,7 +5501,7 @@ for (i = 0; i &lt;= nread - CAN_MSGLEN(0); i += msglen)
The generic, &quot;upper half&quot; watchdog timer driver resides at <code>drivers/timers/watchdog.c</code>.
</li>
<li><b>&quot;Lower Half&quot; Drivers</b>.
Platform-specific watchdog timer drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;chip&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> watchdog timer peripheral devices.
Platform-specific watchdog timer drivers reside in <code>arch/</code><i>&lt;architecture&gt;</i><code>/src/</code><i>&lt;hardware&gt;</i> directory for the specific processor <i>&lt;architecture&gt;</i> and for the specific <i>&lt;chip&gt;</i> watchdog timer peripheral devices.
</li>
</ul>
@@ -6470,7 +6473,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
<ul><pre>
#include &lt;syslog.h&gt;
int syslog(int priority, FAR const IPTR char *format, ...);
int vsyslog(int priority, FAR const IPTR char *src, va_list ap);
void vsyslog(int priority, FAR const IPTR char *src, va_list ap);
</pre></ul>
<p><b>Description:</b>
<code>syslog()</code> generates a log message. The priority argument is formed by ORing the facility and the level values (see <code>include/syslog.h</code>). The remaining arguments are a format, as in <code>printf()</code> and any arguments to the format.
@@ -7301,6 +7304,9 @@ void (*notify)(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate
standard as a development guideline only.
</p>
</div>
</div>
</body>
</html>
Documentation/NuttxUserGuide.html
+4 -12
View File
@@ -3,6 +3,7 @@
<head>
<title>NuttX Users Manual</title>
<meta name="AUTHOR" content="Gregory Nutt">
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
@@ -1476,9 +1477,8 @@ int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *p
</p>
<ul><pre>
#include &lt;spawn.h&gt;
#ifndef CONFIG_DISABLE_SIGNALS
int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, FAR sigset_t *sigmask);
#endif
</pre></ul>
<p>
<b>Description:</b>
@@ -1598,9 +1598,8 @@ int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy);
</p>
<ul><pre>
#include &lt;spawn.h&gt;
#ifndef CONFIG_DISABLE_SIGNALS
int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, FAR const sigset_t *sigmask);
#endif
</pre></ul>
<p>
<b>Description:</b>
@@ -8618,14 +8617,7 @@ interface of the same name.
</p>
<p>
<b>Configuration Settings</b>.
In order to use the <code>poll()</code> API, the following must be defined
in your NuttX configuration file:
</p>
<ul>
<li><code>CONFIG_DISABLE_POLL</code> NOT defined</li>
</ul>
<p>
In order to use the select with TCP/IP sockets test, you must also have the following additional things
In order to use the select with TCP/IP sockets test, you must have the following things
selected in your NuttX configuration file:
</p>
<ul>
Documentation/NxWidgets.html
+1
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@@ -1,6 +1,7 @@
<html>
<head>
<title>NxWidgets</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
<hr><hr>
Documentation/README.html
+14 -4
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@@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: March 13, 2019</p>
<p>Last Updated: June 4, 2019</p>
</td>
</tr>
</table>
@@ -29,9 +29,13 @@ nuttx/
|- arch/
| |
| |- arm/
| | |- src
| | |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/lpc214x/README.txt" target="_blank">lpc214x/README.txt</a>
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/stm32l4/README.txt" target="_blank">stm32l4/README.txt</a>
| | `- src
| | |- common
| | | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/common/README_lwl_console.txt" target="_blank"><b>README_lwl_console.txt</b></a>
| | |- lpc214x
| | | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/lpc214x/README.txt" target="_blank">README.txt</a>
| | `- stm32l4
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/stm32l4/README.txt" target="_blank">stm32l4/README.txt</a>
| |- renesas/
| | |- include/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/renesas/include/README.txt" target="_blank">README.txt</a>
@@ -63,6 +67,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/arduino-due/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- avr32dev1/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/avr32dev1/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- axoloti/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/axoloti/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- b-l475e-iot01a/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/b-l475e-iot01a/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- bambino-200e/
@@ -153,6 +159,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/lpcxpresso-lpc1768/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- lpcxpresso-lpc54628/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/lpcxpresso-lpc54628/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- makerlisp/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/makerlisp/README.txt" target="_blank"><b><i>README.txt</i></b></a>\
| |- maple/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/maple/README.txt" target="_blank"><b><i>README.txt</i></b></a>\
| |- max32660-evsys/
@@ -286,6 +294,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sim/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- skp16c26/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/skp16c26/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- spresense/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/spresense/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm3210e-eval/
| | |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3210e-eval/RIDE/README.txt" target="_blank">RIDE/README.txt</a>
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3210e-eval/README.txt" target="_blank"><b><i>README.txt</i></b></a>
Documentation/UsbTrace.html
+1
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@@ -1,6 +1,7 @@
<html>
<head>
<title>NuttX USB Trace Capability</title>
<link rel="stylesheet" href="style.css">
</head>
<body background="backgd.gif">
Documentation/style.css
+84
View File
@@ -0,0 +1,84 @@
body
{
background: none;
font-family: sans-serif;
height: 100%;
}
a
{
color: #dd2f2f;
text-decoration: none;
}
a:hover
{
text-decoration: underline;
}
code
{
font-family: "Bitstream Vera Sans Mono";
color: #2b4893;
background: #f4f4f4;
padding-left: 0.25em;
padding-right: 0.25em;
}
pre
{
font-family: "Bitstream Vera Sans Mono";
background: #f4f4f4;
padding: 1em;
}
.container
{
overflow-x: hidden;
}
.toc
{
top: 0;
left: 0;
float: left;
width: 22%;
font-size: 80%;
overflow-y: scroll;
height: 100%;
position: fixed;
}
.toc tbody
{
font-size: 80%;
}
.toc .toc_table
{
margin-left: 1em;
}
.toc ul
{
padding-left: 1.5em;
}
.toc > ul
{
padding-left: 1.0em;
}
.toc h1
{
padding-left: 0.5em;
padding-top: 0.5em;
}
.main
{
padding-left: 1em;
padding-right: 1em;
width: 75%;
float: right;
}
README.txt
+12 -2
View File
@@ -1707,8 +1707,12 @@ nuttx/
| |
| |- arm/
| | `- src
| | |- lpc214x/README.txt
| | `- stm32l4/README.txt
| | |- common
| | | `- README_lwl_console.txt
| | |- lpc214x
| | | `-README.txt
| | `- stm32l4
| | `- README.txt
| |- renesas/
| | |- include/
| | | `-README.txt
@@ -1738,6 +1742,8 @@ nuttx/
| | `- README.txt
| |- avr32dev1/
| | `- README.txt
| |- axoloti/
| | `- README.txt
| |- b-l475e-iot01a/
| | `- README.txt
| |- bambino-200e/
@@ -1827,6 +1833,8 @@ nuttx/
| | `- README.txt
| |- lpcxpresso-lpc54628/
| | `- README.txt
| |- makerlisp/
| | `- README.txt
| |- maple/
| | `- README.txt
| |- max32660-evsys/
@@ -1959,6 +1967,8 @@ nuttx/
| | `- README.txt
| |- skp16c26/
| | `- README.txt
| |- spresense/
| | `- README.txt
| |- stm3210e-eval/
| | |- RIDE/README.txt
| | `- README.txt
ReleaseNotes
+620 -10
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File diff suppressed because it is too large Load Diff
TODO
+3 -11
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@@ -1,4 +1,4 @@
NuttX TODO List (Last updated March 18, 2019)
NuttX TODO List (Last updated April 29, 2019)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -31,7 +31,7 @@ nuttx/:
apps/ and other Add-Ons:
(2) Network Utilities (apps/netutils/)
(1) Network Utilities (apps/netutils/)
(1) NuttShell (NSH) (apps/nshlib)
(1) System libraries apps/system (apps/system)
(1) Modbus (apps/modbus)
@@ -560,7 +560,7 @@ o SMP
This would also be an essential part of a high priority,
nested interrupt implementation (unrelated).
Status: Open
Priority: Low. There are no know issues with the current non-maskable
Priority: Low. There are no known issues with the current non-maskable
SGI implementation. This change would, however, lead to
simplification in the design and permit commonality with
other, non-GIC implementations.
@@ -2720,14 +2720,6 @@ o Network Utilities (apps/netutils/)
Status: Open
Priority: Medium
Title: NETWORK MONITOR NOT GENERALLY AVAILABLE
Description: The NSH network management logic has general applicability
but is currently useful only because it is embedded in the NSH
module. It should be moved to apps/system or, better,
apps/netutils.
Status: Open
Priority: Low
o NuttShell (NSH) (apps/nshlib)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
arch/arm/Kconfig
+40 -3
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@@ -317,6 +317,12 @@ config ARCH_CHIP_STM32L0
---help---
STMicro STM32L0 architectures (ARM Cortex-M0).
config ARCH_CHIP_STM32G0
bool "STMicro STM32 G0"
select ARCH_CORTEXM0
---help---
STMicro STM32G0 architectures (ARM Cortex-M0).
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_CORTEXM7
@@ -328,6 +334,8 @@ config ARCH_CHIP_STM32F7
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_TIMEKEEPING
---help---
STMicro STM32 architectures (ARM Cortex-M7).
@@ -400,6 +408,18 @@ config ARCH_CHIP_XMC4
---help---
Infineon XMC4xxx(ARM Cortex-M4) architectures
config ARCH_CHIP_CXD56XX
bool "Sony CXD56xx"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_SDIO if MMCSD
---help---
Sony CXD56XX (ARM Cortex-M4) architectures
endchoice
config ARCH_ARM7TDMI
@@ -663,13 +683,14 @@ config ARCH_CHIP
default "sam34" if ARCH_CHIP_SAM34
default "samv7" if ARCH_CHIP_SAMV7
default "stm32" if ARCH_CHIP_STM32
default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
default "stm32f7" if ARCH_CHIP_STM32F7
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
default "str71x" if ARCH_CHIP_STR71X
default "tms570" if ARCH_CHIP_TMS570
default "xmc4" if ARCH_CHIP_XMC4
default "cxd56xx" if ARCH_CHIP_CXD56XX
config ARCH_HAVE_TRUSTZONE
bool
@@ -792,6 +813,19 @@ config ARM_SEMIHOSTING_HOSTFS
---help---
Mount HostFS through semihosting.
config ARM_LWL_CONSOLE
bool "Lightweight Link Console Support"
default n
depends on DEV_CONSOLE && ARCH_CHIP_STM32
---help---
Use the lightweight link console which provides console over a
debug channel by means of shared memory. A terminal application
for openocd as the debugger is available in tools/ocdconsole.py.
Currently only available for STM32 architectures, but easily
added to other ARM architectures be addd up_low_console.c to the
architecture Make.defs file.
if ARCH_CORTEXM0
source arch/arm/src/armv6-m/Kconfig
endif
@@ -894,8 +928,8 @@ endif
if ARCH_CHIP_STM32
source arch/arm/src/stm32/Kconfig
endif
if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
source arch/arm/src/stm32f0l0/Kconfig
if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
source arch/arm/src/stm32f0l0g0/Kconfig
endif
if ARCH_CHIP_STM32F7
source arch/arm/src/stm32f7/Kconfig
@@ -915,5 +949,8 @@ endif
if ARCH_CHIP_XMC4
source arch/arm/src/xmc4/Kconfig
endif
if ARCH_CHIP_CXD56XX
source arch/arm/src/cxd56xx/Kconfig
endif
endif # ARCH_ARM
arch/arm/include/arm/irq.h
-2
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@@ -138,7 +138,6 @@
#ifndef __ASSEMBLY__
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
@@ -156,7 +155,6 @@ struct xcptcontext
uint32_t saved_pc;
uint32_t saved_cpsr;
#endif
/* Register save area */
arch/arm/include/armv6-m/irq.h
-3
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@@ -164,7 +164,6 @@ struct xcpt_syscall_s
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
@@ -191,8 +190,6 @@ struct xcptcontext
*/
uint32_t sigreturn;
# endif
#endif
#ifdef CONFIG_LIB_SYSCALL
arch/arm/include/armv7-a/irq.h
+1 -5
View File
@@ -229,7 +229,6 @@ struct xcpt_syscall_s
#ifndef __ASSEMBLY__
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/
@@ -247,14 +246,13 @@ struct xcptcontext
uint32_t saved_pc;
uint32_t saved_cpsr;
# ifdef CONFIG_BUILD_KERNEL
#ifdef CONFIG_BUILD_KERNEL
/* This is the saved address to use when returning from a user-space
* signal handler.
*/
uint32_t sigreturn;
# endif
#endif
/* Register save area */
@@ -302,11 +300,9 @@ struct xcptcontext
FAR uint32_t *ustkptr; /* Saved user stack pointer */
FAR uint32_t *kstack; /* Allocate base of the (aligned) kernel stack */
#ifndef CONFIG_DISABLE_SIGNALS
FAR uint32_t *kstkptr; /* Saved kernel stack pointer */
#endif
#endif
#endif
};
#endif
arch/arm/include/armv7-m/irq.h
-2
View File
@@ -119,7 +119,6 @@ struct xcpt_syscall_s
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
@@ -151,7 +150,6 @@ struct xcptcontext
uint32_t sigreturn;
# endif
#endif
#ifdef CONFIG_LIB_SYSCALL
arch/arm/include/armv7-r/irq.h
+1 -6
View File
@@ -229,7 +229,6 @@ struct xcpt_syscall_s
#ifndef __ASSEMBLY__
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/
@@ -247,14 +246,12 @@ struct xcptcontext
uint32_t saved_pc;
uint32_t saved_cpsr;
# ifdef CONFIG_BUILD_KERNEL
#ifdef CONFIG_BUILD_KERNEL
/* This is the saved address to use when returning from a user-space
* signal handler.
*/
uint32_t sigreturn;
# endif
#endif
/* Register save area */
@@ -302,11 +299,9 @@ struct xcptcontext
FAR uint32_t *ustkptr; /* Saved user stack pointer */
FAR uint32_t *kstack; /* Allocate base of the (aligned) kernel stack */
#ifndef CONFIG_DISABLE_SIGNALS
FAR uint32_t *kstkptr; /* Saved kernel stack pointer */
#endif
#endif
#endif
};
#endif
arch/arm/include/cxd56xx/chip.h
+104
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@@ -0,0 +1,104 @@
/*****************************************************************************
* arch/arm/include/cxd56xx/chip.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
#define __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CXD56M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
#define CXD56M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define CXD56M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define CXD56M4_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
#define NVIC_SYSH_PRIORITY_MIN CXD56M4_SYSH_PRIORITY_MIN
#define NVIC_SYSH_PRIORITY_DEFAULT CXD56M4_SYSH_PRIORITY_DEFAULT
#define NVIC_SYSH_PRIORITY_MAX CXD56M4_SYSH_PRIORITY_MAX
#define NVIC_SYSH_PRIORITY_STEP CXD56M4_SYSH_PRIORITY_STEP
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the up_irq_save() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H */
arch/arm/include/cxd56xx/irq.h
+272
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@@ -0,0 +1,272 @@
/****************************************************************************
* arch/arm/include/cxd56xx/irq.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_IRQ_H
#define __ARCH_ARM_INCLUDE_CXD56XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define CXD56_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define CXD56_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define CXD56_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define CXD56_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define CXD56_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define CXD56_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define CXD56_IRQ_SIGNVALUE (7) /* Vector 7: Sign value */
#define CXD56_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define CXD56_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define CXD56_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define CXD56_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define CXD56_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */
/* Cortex-M4 External interrupts (vectors >= 16) */
#define CXD56_IRQ_PMU (CXD56_IRQ_EXTINT+0) /**< PMU IRQ number */
#define CXD56_IRQ_CRG (CXD56_IRQ_EXTINT+1) /**< CRG IRQ number */
#define CXD56_IRQ_HVDD (CXD56_IRQ_EXTINT+2) /**< HVDD IRQ number */
#define CXD56_IRQ_LP (CXD56_IRQ_EXTINT+3) /**< LP IRQ number */
#define CXD56_IRQ_RTC0_A0 (CXD56_IRQ_EXTINT+4) /**< RTC0_A0 IRQ number */
#define CXD56_IRQ_RTC0_A1 (CXD56_IRQ_EXTINT+5) /**< RTC0_A1 IRQ number */
#define CXD56_IRQ_RTC0_A2 (CXD56_IRQ_EXTINT+6) /**< RTC0_A2 IRQ number */
#define CXD56_IRQ_RTC1_A0 (CXD56_IRQ_EXTINT+7) /**< RTC1_A0 IRQ number */
#define CXD56_IRQ_RTC1_A1 (CXD56_IRQ_EXTINT+8) /**< RTC1_A1 IRQ number */
#define CXD56_IRQ_RTC1_A2 (CXD56_IRQ_EXTINT+9) /**< RTC1_A2 IRQ number */
#define CXD56_IRQ_RTC_INT (CXD56_IRQ_EXTINT+10) /**< RTC_INT IRQ number */
#define CXD56_IRQ_UART1 (CXD56_IRQ_EXTINT+11) /**< UART1 IRQ number */
#define CXD56_IRQ_UART0 (CXD56_IRQ_EXTINT+12) /**< UART0 IRQ number */
#define CXD56_IRQ_HOSTIF_0 (CXD56_IRQ_EXTINT+13) /**< HOSTIF_0 IRQ number */
#define CXD56_IRQ_HOSTIF_1 (CXD56_IRQ_EXTINT+14) /**< HOSTIF_1 IRQ number */
#define CXD56_IRQ_HOSTIF_2 (CXD56_IRQ_EXTINT+15) /**< HOSTIF_2 IRQ number */
#define CXD56_IRQ_SCU_SPI (CXD56_IRQ_EXTINT+16) /**< SCU_0 SPI IRQ number */
#define CXD56_IRQ_SCU_I2C0 (CXD56_IRQ_EXTINT+17) /**< SCU_1 I2C1 IRQ number */
#define CXD56_IRQ_SCU_I2C1 (CXD56_IRQ_EXTINT+18) /**< SCU_2 I2C2 IRQ number */
#define CXD56_IRQ_SCU_3 (CXD56_IRQ_EXTINT+19) /**< SCU_3 SCU IRQ number */
#define CXD56_IRQ_EXDEVICE_0 (CXD56_IRQ_EXTINT+20) /**< EXDEVICE_0 IRQ number */
#define CXD56_IRQ_EXDEVICE_1 (CXD56_IRQ_EXTINT+21) /**< EXDEVICE_1 IRQ number */
#define CXD56_IRQ_EXDEVICE_2 (CXD56_IRQ_EXTINT+22) /**< EXDEVICE_2 IRQ number */
#define CXD56_IRQ_EXDEVICE_3 (CXD56_IRQ_EXTINT+23) /**< EXDEVICE_3 IRQ number */
#define CXD56_IRQ_EXDEVICE_4 (CXD56_IRQ_EXTINT+24) /**< EXDEVICE_4 IRQ number */
#define CXD56_IRQ_EXDEVICE_5 (CXD56_IRQ_EXTINT+25) /**< EXDEVICE_5 IRQ number */
#define CXD56_IRQ_EXDEVICE_6 (CXD56_IRQ_EXTINT+26) /**< EXDEVICE_6 IRQ number */
#define CXD56_IRQ_EXDEVICE_7 (CXD56_IRQ_EXTINT+27) /**< EXDEVICE_7 IRQ number */
#define CXD56_IRQ_EXDEVICE_8 (CXD56_IRQ_EXTINT+28) /**< EXDEVICE_8 IRQ number */
#define CXD56_IRQ_EXDEVICE_9 (CXD56_IRQ_EXTINT+29) /**< EXDEVICE_9 IRQ number */
#define CXD56_IRQ_EXDEVICE_10 (CXD56_IRQ_EXTINT+30) /**< EXDEVICE_10 IRQ number */
#define CXD56_IRQ_EXDEVICE_11 (CXD56_IRQ_EXTINT+31) /**< EXDEVICE_11 IRQ number */
#define CXD56_IRQ_DMA_A_0 (CXD56_IRQ_EXTINT+32) /**< DMA_A_0 IRQ number */
#define CXD56_IRQ_DMA_A_1 (CXD56_IRQ_EXTINT+33) /**< DMA_A_1 IRQ number */
#define CXD56_IRQ_DMA_A_2 (CXD56_IRQ_EXTINT+34) /**< DMA_A_2 IRQ number */
#define CXD56_IRQ_DMA_A_3 (CXD56_IRQ_EXTINT+35) /**< DMA_A_3 IRQ number */
#define CXD56_IRQ_DMA_A_4 (CXD56_IRQ_EXTINT+36) /**< DMA_A_4 IRQ number */
#define CXD56_IRQ_DMA_A_5 (CXD56_IRQ_EXTINT+37) /**< DMA_A_5 IRQ number */
#define CXD56_IRQ_DMA_A_6 (CXD56_IRQ_EXTINT+38) /**< DMA_A_6 IRQ number */
#define CXD56_IRQ_DMA_A_7 (CXD56_IRQ_EXTINT+39) /**< DMA_A_7 IRQ number */
#define CXD56_IRQ_DMA_A_8 (CXD56_IRQ_EXTINT+40) /**< DMA_A_8 IRQ number */
#define CXD56_IRQ_DMA_A_9 (CXD56_IRQ_EXTINT+41) /**< DMA_A_9 IRQ number */
#define CXD56_IRQ_DMA_A_10 (CXD56_IRQ_EXTINT+42) /**< DMA_A_10 IRQ number */
#define CXD56_IRQ_DMA_A_11 (CXD56_IRQ_EXTINT+43) /**< DMA_A_11 IRQ number */
#define CXD56_IRQ_DMA_A_12 (CXD56_IRQ_EXTINT+44) /**< DMA_A_12 IRQ number */
#define CXD56_IRQ_DMA_A_13 (CXD56_IRQ_EXTINT+45) /**< DMA_A_13 IRQ number */
#define CXD56_IRQ_DMA_A_14 (CXD56_IRQ_EXTINT+46) /**< DMA_A_14 IRQ number */
#define CXD56_IRQ_DMA_A_15 (CXD56_IRQ_EXTINT+47) /**< DMA_A_15 IRQ number */
#define CXD56_IRQ_DMA_A_16 (CXD56_IRQ_EXTINT+48) /**< DMA_A_16 IRQ number */
#define CXD56_IRQ_DMA_A_17 (CXD56_IRQ_EXTINT+49) /**< DMA_A_17 IRQ number */
#define CXD56_IRQ_DMA_A_18 (CXD56_IRQ_EXTINT+50) /**< DMA_A_18 IRQ number */
#define CXD56_IRQ_DMA_A_19 (CXD56_IRQ_EXTINT+51) /**< DMA_A_19 IRQ number */
#define CXD56_IRQ_DMA_A_20 (CXD56_IRQ_EXTINT+52) /**< DMA_A_20 IRQ number */
#define CXD56_IRQ_DMA_A_21 (CXD56_IRQ_EXTINT+53) /**< DMA_A_21 IRQ number */
#define CXD56_IRQ_DMA_A_22 (CXD56_IRQ_EXTINT+54) /**< DMA_A_22 IRQ number */
#define CXD56_IRQ_DMA_A_23 (CXD56_IRQ_EXTINT+55) /**< DMA_A_23 IRQ number */
#define CXD56_IRQ_DMA_A_24 (CXD56_IRQ_EXTINT+56) /**< DMA_A_24 IRQ number */
#define CXD56_IRQ_DMA_A_25 (CXD56_IRQ_EXTINT+57) /**< DMA_A_25 IRQ number */
#define CXD56_IRQ_DMA_A_26 (CXD56_IRQ_EXTINT+58) /**< DMA_A_26 IRQ number */
#define CXD56_IRQ_DMA_A_27 (CXD56_IRQ_EXTINT+59) /**< DMA_A_27 IRQ number */
#define CXD56_IRQ_DMA_A_28 (CXD56_IRQ_EXTINT+60) /**< DMA_A_28 IRQ number */
#define CXD56_IRQ_DMA_A_29 (CXD56_IRQ_EXTINT+61) /**< DMA_A_29 IRQ number */
#define CXD56_IRQ_DMA_A_30 (CXD56_IRQ_EXTINT+62) /**< DMA_A_30 IRQ number */
#define CXD56_IRQ_DMA_A_31 (CXD56_IRQ_EXTINT+63) /**< DMA_A_31 IRQ number */
#define CXD56_IRQ_DMA_B_0 (CXD56_IRQ_EXTINT+64) /**< DMA_B_0 IRQ number */
#define CXD56_IRQ_DMA_B_1 (CXD56_IRQ_EXTINT+65) /**< DMA_B_1 IRQ number */
#define CXD56_IRQ_DMA_C_0 (CXD56_IRQ_EXTINT+66) /**< DMA_C_0 IRQ number */
#define CXD56_IRQ_DMA_C_1 (CXD56_IRQ_EXTINT+67) /**< DMA_C_1 IRQ number */
#define CXD56_IRQ_DMA_D_0 (CXD56_IRQ_EXTINT+68) /**< DMA_D_0 IRQ number */
#define CXD56_IRQ_DMA_D_1 (CXD56_IRQ_EXTINT+69) /**< DMA_D_1 IRQ number */
#define CXD56_IRQ_SAKE_NSEC (CXD56_IRQ_EXTINT+70) /**< SAKE_NSEC IRQ number */
#define CXD56_IRQ_SAKE_SEC (CXD56_IRQ_EXTINT+71) /**< SAKE_SEC IRQ number */
#define CXD56_IRQ_USB_VBUS (CXD56_IRQ_EXTINT+72) /**< USB_VBUS IRQ number */
#define CXD56_IRQ_USB_VBUSN (CXD56_IRQ_EXTINT+73) /**< USB_VBUSN IRQ number */
#define CXD56_IRQ_SPIM (CXD56_IRQ_EXTINT+74) /**< SPI0 IRQ number */
#define CXD56_IRQ_I2CM (CXD56_IRQ_EXTINT+75) /**< I2C0 IRQ number */
#define CXD56_IRQ_DEBUG0 (CXD56_IRQ_EXTINT+76) /**< DEBUG0 IRQ number */
#define CXD56_IRQ_DEBUG1 (CXD56_IRQ_EXTINT+77) /**< DEBUG1 IRQ number */
#define CXD56_IRQ_FIFO_TO (CXD56_IRQ_EXTINT+78) /**< FIFO_TO IRQ number */
#define CXD56_IRQ_FIFO_FROM (CXD56_IRQ_EXTINT+79) /**< FIFO_FROM IRQ number */
#define CXD56_IRQ_SPH0 (CXD56_IRQ_EXTINT+80) /**< SPH0 IRQ number */
#define CXD56_IRQ_SPH1 (CXD56_IRQ_EXTINT+81) /**< SPH1 IRQ number */
#define CXD56_IRQ_SPH2 (CXD56_IRQ_EXTINT+82) /**< SPH2 IRQ number */
#define CXD56_IRQ_SPH3 (CXD56_IRQ_EXTINT+83) /**< SPH3 IRQ number */
#define CXD56_IRQ_SPH4 (CXD56_IRQ_EXTINT+84) /**< SPH4 IRQ number */
#define CXD56_IRQ_SPH5 (CXD56_IRQ_EXTINT+85) /**< SPH5 IRQ number */
#define CXD56_IRQ_SPH6 (CXD56_IRQ_EXTINT+86) /**< SPH6 IRQ number */
#define CXD56_IRQ_SPH7 (CXD56_IRQ_EXTINT+87) /**< SPH7 IRQ number */
#define CXD56_IRQ_SPH8 (CXD56_IRQ_EXTINT+88) /**< SPH8 IRQ number */
#define CXD56_IRQ_SPH9 (CXD56_IRQ_EXTINT+89) /**< SPH9 IRQ number */
#define CXD56_IRQ_SPH10 (CXD56_IRQ_EXTINT+90) /**< SPH10 IRQ number */
#define CXD56_IRQ_SPH11 (CXD56_IRQ_EXTINT+91) /**< SPH11 IRQ number */
#define CXD56_IRQ_SPH12 (CXD56_IRQ_EXTINT+92) /**< SPH12 IRQ number */
#define CXD56_IRQ_SPH13 (CXD56_IRQ_EXTINT+93) /**< SPH13 IRQ number */
#define CXD56_IRQ_SPH14 (CXD56_IRQ_EXTINT+94) /**< SPH14 IRQ number */
#define CXD56_IRQ_SPH15 (CXD56_IRQ_EXTINT+95) /**< SPH15 IRQ number */
#define CXD56_IRQ_SW_INT (CXD56_IRQ_EXTINT+96) /**< SW_INT IRQ number */
#define CXD56_IRQ_TIMER0 (CXD56_IRQ_EXTINT+97) /**< TIMER0 IRQ number */
#define CXD56_IRQ_TIMER1 (CXD56_IRQ_EXTINT+98) /**< TIMER1 IRQ number */
#define CXD56_IRQ_TIMER2 (CXD56_IRQ_EXTINT+99) /**< TIMER2 IRQ number */
#define CXD56_IRQ_WDT_INT (CXD56_IRQ_EXTINT+100) /**< WDT_INT IRQ number */
#define CXD56_IRQ_WDT_RES (CXD56_IRQ_EXTINT+101) /**< WDT_RES IRQ number */
#define CXD56_IRQ_AUDIO_0 (CXD56_IRQ_EXTINT+102) /**< AUDIO_0(MIC) IRQ number */
#define CXD56_IRQ_AUDIO_1 (CXD56_IRQ_EXTINT+103) /**< AUDIO_1(I2S1) IRQ number */
#define CXD56_IRQ_AUDIO_2 (CXD56_IRQ_EXTINT+104) /**< AUDIO_2(I2S2) IRQ number */
#define CXD56_IRQ_AUDIO_3 (CXD56_IRQ_EXTINT+105) /**< AUDIO_3(CODEC) IRQ number */
#define CXD56_IRQ_GE2D (CXD56_IRQ_EXTINT+106) /**< APP_IMG 2D Graphics Engine IRQ number */
#define CXD56_IRQ_ROT (CXD56_IRQ_EXTINT+107) /**< APP_IMG_ROTation IRQ number */
#define CXD56_IRQ_CISIF (CXD56_IRQ_EXTINT+108) /**< APP_IMG CISIF IRQ number */
#define CXD56_IRQ_IMG_WSPI (CXD56_IRQ_EXTINT+109) /**< APP_IMG WSSP IRQ number */
#define CXD56_IRQ_IDMAC (CXD56_IRQ_EXTINT+110) /**< APP_IMG DMAC IRQ number */
#define CXD56_IRQ_APP_UART (CXD56_IRQ_EXTINT+111) /**< APP_IMG UART IRQ number */
#define CXD56_IRQ_VSYNC (CXD56_IRQ_EXTINT+112) /**< APP_IMG VSYNC IRQ number */
#define CXD56_IRQ_IMG_SPI (CXD56_IRQ_EXTINT+113) /**< APP_IMG SSP IRQ number */
#define CXD56_IRQ_EMMC (CXD56_IRQ_EXTINT+114) /**< APP_PER EMMC IRQ number */
#define CXD56_IRQ_SDIO (CXD56_IRQ_EXTINT+115) /**< APP_PER SDIO IRQ number */
#define CXD56_IRQ_USB_INT (CXD56_IRQ_EXTINT+116) /**< APP_PER USB_INT IRQ number */
#define CXD56_IRQ_USB_SYS (CXD56_IRQ_EXTINT+117) /**< APP_PER USB_SYS IRQ number */
#define CXD56_IRQ_APP_DMAC0 (CXD56_IRQ_EXTINT+118) /**< APP_DMAC0 IRQ number */
#define CXD56_IRQ_APP_DMAC1 (CXD56_IRQ_EXTINT+119) /**< APP_DMAC1 IRQ number */
#define CXD56_IRQ_APP_SAKE_NSEC (CXD56_IRQ_EXTINT+120) /**< APP_SAKE_NSEC IRQ number */
#define CXD56_IRQ_APP_SAKE_SEC (CXD56_IRQ_EXTINT+121) /**< APP_SAKE_SEC IRQ number */
#define CXD56_IRQ_SKDMAC_0 (CXD56_IRQ_EXTINT+122) /**< APP_SAKE_DMAC_0 IRQ number */
#define CXD56_IRQ_SKDMAC_1 (CXD56_IRQ_EXTINT+123) /**< APP_SAKE_DMAC_1 IRQ number */
#define CXD56_IRQ_APP_PPB (CXD56_IRQ_EXTINT+124) /**< reserved */
#define CXD56_IRQ_GPS_OR (CXD56_IRQ_EXTINT+125) /**< GNSS_OR IRQ number */
#define CXD56_IRQ_SFC (CXD56_IRQ_EXTINT+126) /**< SFC IRQ number */
#define CXD56_IRQ_PMIC (CXD56_IRQ_EXTINT+127) /**< PMIC IRQ number */
#define CXD56_IRQ_NEXTINT (128)
#define CXD56_IRQ_NIRQS (CXD56_IRQ_EXTINT+CXD56_IRQ_NEXTINT)
/* Total number of IRQ numbers (This will need to be revisited if/when the
* Cortex-M0 is supported)
*/
#define NR_VECTORS CXD56_IRQ_NIRQS
#define NR_IRQS CXD56_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
#if 0
# define CXD56M0_IRQ_NIRQS (CXD56_IRQ_EXTINT + CXD56M0_IRQ_NEXTINT)
#endif
/* Total number of IRQ numbers (This will need to be revisited if/when the
* Cortex-M0 is supported)
*/
#if 0
# define NR_VECTORS CXD56M0_IRQ_NIRQS
# define NR_IRQS CXD56M0_IRQ_NIRQS
#endif
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_IRQ_H */
arch/arm/include/cxd56xx/pin.h
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/****************************************************************************
* arch/arm/include/cxd56xx/pin.h
*
* Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_PIN_H
#define __ARCH_ARM_INCLUDE_CXD56XX_PIN_H
/****************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Pin number Definitions */
#define PIN_RTC_CLK_IN (0)
/* SYS GPIO: system power domain GPIOs */
#define PIN_I2C4_BCK (1)
#define PIN_I2C4_BDT (2)
#define PIN_PMIC_INT (3)
#define PIN_RTC_IRQ_OUT (4)
#define PIN_AP_CLK (5)
#define PIN_GNSS_1PPS_OUT (6)
#define PIN_SPI0_CS_X (17)
#define PIN_SPI0_SCK (18)
#define PIN_SPI0_MOSI (19)
#define PIN_SPI0_MISO (20)
#define PIN_SPI1_CS_X (21)
#define PIN_SPI1_SCK (22)
#define PIN_SPI1_IO0 (23)
#define PIN_SPI1_IO1 (24)
#define PIN_SPI1_IO2 (25)
#define PIN_SPI1_IO3 (26)
#define PIN_SPI2_CS_X (27)
#define PIN_SPI2_SCK (28)
#define PIN_SPI2_MOSI (29)
#define PIN_SPI2_MISO (30)
#define PIN_HIF_IRQ_OUT (31)
#define PIN_HIF_GPIO0 (32)
#define PIN_SEN_IRQ_IN (37)
#define PIN_SPI3_CS0_X (38)
#define PIN_SPI3_CS1_X (39)
#define PIN_SPI3_CS2_X (40)
#define PIN_SPI3_SCK (41)
#define PIN_SPI3_MOSI (42)
#define PIN_SPI3_MISO (43)
#define PIN_I2C0_BCK (44)
#define PIN_I2C0_BDT (45)
#define PIN_PWM0 (46)
#define PIN_PWM1 (47)
#define PIN_PWM2 (48)
#define PIN_PWM3 (49)
/* APP GPIO: application power domain GPIOs */
#define PIN_IS_CLK (56)
#define PIN_IS_VSYNC (57)
#define PIN_IS_HSYNC (58)
#define PIN_IS_DATA0 (59)
#define PIN_IS_DATA1 (60)
#define PIN_IS_DATA2 (61)
#define PIN_IS_DATA3 (62)
#define PIN_IS_DATA4 (63)
#define PIN_IS_DATA5 (64)
#define PIN_IS_DATA6 (65)
#define PIN_IS_DATA7 (66)
#define PIN_UART2_TXD (67)
#define PIN_UART2_RXD (68)
#define PIN_UART2_CTS (69)
#define PIN_UART2_RTS (70)
#define PIN_SPI4_CS_X (71)
#define PIN_SPI4_SCK (72)
#define PIN_SPI4_MOSI (73)
#define PIN_SPI4_MISO (74)
#define PIN_EMMC_CLK (75)
#define PIN_SPI5_SCK (PIN_EMMC_CLK)
#define PIN_EMMC_CMD (76)
#define PIN_SPI5_CS_X (PIN_EMMC_CMD)
#define PIN_EMMC_DATA0 (77)
#define PIN_SPI5_MOSI (PIN_EMMC_DATA0)
#define PIN_EMMC_DATA1 (78)
#define PIN_SPI5_MISO (PIN_EMMC_DATA1)
#define PIN_EMMC_DATA2 (79)
#define PIN_EMMC_DATA3 (80)
#define PIN_SDIO_CLK (81)
#define PIN_SDIO_CMD (82)
#define PIN_SDIO_DATA0 (83)
#define PIN_SDIO_DATA1 (84)
#define PIN_SDIO_DATA2 (85)
#define PIN_SDIO_DATA3 (86)
#define PIN_SDIO_CD (87)
#define PIN_SDIO_WP (88)
#define PIN_SDIO_CMDDIR (89)
#define PIN_SDIO_DIR0 (90)
#define PIN_SDIO_DIR1_3 (91)
#define PIN_SDIO_CLKI (92)
#define PIN_I2S0_BCK (93)
#define PIN_I2S0_LRCK (94)
#define PIN_I2S0_DATA_IN (95)
#define PIN_I2S0_DATA_OUT (96)
#define PIN_I2S1_BCK (97)
#define PIN_I2S1_LRCK (98)
#define PIN_I2S1_DATA_IN (99)
#define PIN_I2S1_DATA_OUT (100)
#define PIN_MCLK (101)
#define PIN_PDM_CLK (102)
#define PIN_PDM_IN (103)
#define PIN_PDM_OUT (104)
#define PIN_USB_VBUSINT (105)
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_PIN_H */
arch/arm/include/cxd56xx/pm.h
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/****************************************************************************
* arch/arm/include/cxd56xx/pm.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/**
* @file pm.h
*/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_PM_H
#define __ARCH_ARM_INCLUDE_CXD56XX_PM_H
/*-----------------------------------------------------------------------------
* include files
*---------------------------------------------------------------------------*/
#include <queue.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Boot Cause definitions */
#define PM_BOOT_POR_NORMAL (0x00000000ul) /** Power On Reset like as battery attached */
#define PM_BOOT_POR_DEADBATT (0x00000001ul) /** Battery charged from DeadBattery state */
#define PM_BOOT_WDT_REBOOT (0x00000002ul) /** System WDT expired or Explicitly Self Reboot */
#define PM_BOOT_WDT_RESET (0x00000004ul) /** Chip WDT expired (might be used in HV-only system) */
#define PM_BOOT_DEEP_WKUPL (0x00000008ul) /** In DeepSleep state, Detected WKUPL signal */
#define PM_BOOT_DEEP_WKUPS (0x00000010ul) /** In DeepSleep state, Detected WKUPS signal */
#define PM_BOOT_DEEP_RTC (0x00000020ul) /** In DeepSleep state, RTC Alarm expired */
#define PM_BOOT_DEEP_USB_ATTACH (0x00000040ul) /** In DeepSleep state, USB Connected */
#define PM_BOOT_DEEP_OTHERS (0x00000080ul) /** In DeepSleep state, Reserved others cause occurred */
#define PM_BOOT_COLD_SCU_INT (0x00000100ul) /** In ColdSleep state, Detected SCU Interrupt */
#define PM_BOOT_COLD_RTC (0x00001e00ul) /** In ColdSleep state, RTC Alarm Interrupt */
#define PM_BOOT_COLD_RTC_ALM0 (0x00000200ul) /** In ColdSleep state, RTC Alarm0 expired */
#define PM_BOOT_COLD_RTC_ALM1 (0x00000400ul) /** In ColdSleep state, RTC Alarm1 expired */
#define PM_BOOT_COLD_RTC_ALM2 (0x00000800ul) /** In ColdSleep state, RTC Alarm2 expired */
#define PM_BOOT_COLD_RTC_ALMERR (0x00001000ul) /** In ColdSleep state, RTC Alarm Error occurred */
#define PM_BOOT_COLD_GPIO (0x0fff0000ul) /** In ColdSleep state, Detected GPIO interrupt */
#define PM_BOOT_COLD_SEN_INT (0x10000000ul) /** In ColdSleep state, Detected SEN_INT Interrupt */
#define PM_BOOT_COLD_PMIC_INT (0x20000000ul) /** In ColdSleep state, Detected PMIC Interrupt */
#define PM_BOOT_COLD_USB_DETACH (0x40000000ul) /** In ColdSleep state, USB Disconnected */
#define PM_BOOT_COLD_USB_ATTACH (0x80000000ul) /** In ColdSleep state, USB Connected */
/* SRAM power status definitions */
#define PMCMD_RAM_OFF 0 /* Power off */
#define PMCMD_RAM_RET 1 /* Retention */
#define PMCMD_RAM_ON 3 /* Power on */
/* FrequencyLock request flag definitions */
#define PM_CPUFREQLOCK_FLAG_HV (0x0001) /* request HV */
#define PM_CPUFREQLOCK_FLAG_LV (0x4000) /* request LV */
/* FrequencyLock identifier tag helper macro function */
#define PM_CPUFREQLOCK_TAG(prefix1, prefix2, num) \
(((prefix1) << 24) + ((prefix2) << 16) + (num))
/* FrequencyLock initializer macro function */
# define PM_CPUFREQLOCK_INIT(_tag, _flag) \
{ \
.count = 0, \
.info = _tag, \
.flag = _flag, \
}
/* WakeLock identifier tag helper macro function */
#define PM_CPUWAKELOCK_TAG(prefix1, prefix2, num) \
(((prefix1) << 24) + ((prefix2) << 16) + (num))
/* WakeLock initializer macro function */
#define PM_CPUWAKELOCK_INIT(_tag) \
{ \
.count = 0, \
.info = _tag, \
}
/****************************************************************************
* Public Types
****************************************************************************/
/* slee mode definitions */
enum pm_sleepmode_e
{
PM_SLEEP_DEEP,
PM_SLEEP_COLD,
};
/* FreqLock structure */
struct pm_cpu_freqlock_s
{
struct sq_entry_s sq_entry;
int count;
uint32_t info;
int flag;
};
/* WakeLock structure */
struct pm_cpu_wakelock_s
{
struct sq_entry_s sq_entry;
int count;
uint32_t info;
};
/* Definitions for pmic notify */
enum pmic_notify_e
{
PMIC_NOTIFY_ALARM = 0,
PMIC_NOTIFY_WKUPS,
PMIC_NOTIFY_WKUPL,
PMIC_NOTIFY_LOWBATT,
PMIC_NOTIFY_MAX
};
/* callback function for pmic notify */
typedef void (*pmic_notify_t)(void *arg);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: up_pmstatdump
*
* Description:
* Print architecture specific power status
*
****************************************************************************/
int up_pmramctrl(int cmd, uintptr_t addr, size_t size);
#ifdef CONFIG_DEBUG_PM
/****************************************************************************
* Name: up_pmstatdump
*
* Description:
* Print architecture specific power status
*
****************************************************************************/
void up_pmstatdump(void);
#else
# define up_pmstatdump()
#endif
/****************************************************************************
* Name: up_pm_acquire_freqlock
*
* Description:
* Acquire the specified freqlock. If the higher freqlock is acquired, the
* system can clockup until it is released.
*
* Parameter:
* lock - the pointer of a wakelock variable
*
****************************************************************************/
void up_pm_acquire_freqlock(struct pm_cpu_freqlock_s *lock);
/****************************************************************************
* Name: up_pm_release_freqlock
*
* Description:
* Release the specified freqlock. If the freqlock are released, the system
* can drop to the lower clock mode for power saving.
*
* Parameter:
* lock - the pointer of a freqlock variable
*
****************************************************************************/
void up_pm_release_freqlock(struct pm_cpu_freqlock_s *lock);
/****************************************************************************
* Name: up_pm_get_freqlock_count
*
* Description:
* Get the locked count of the specified freqlock
*
* Parameter:
* lock - the pointer of a freqlock variable
*
* Return:
* the locked count of the specified freqlock
*
****************************************************************************/
int up_pm_get_freqlock_count(struct pm_cpu_freqlock_s *lock);
/****************************************************************************
* Name: up_pm_acquire_wakelock
*
* Description:
* Acquire the specified wakelock. If any wakelock is acquired, CPU can't
* enter to the hot sleep state.
*
* Parameter:
* lock - the pointer of a wakelock variable
*
****************************************************************************/
void up_pm_acquire_wakelock(struct pm_cpu_wakelock_s *lock);
/****************************************************************************
* Name: up_pm_release_wakelock
*
* Description:
* Release the specified wakelock. If all of the wakelock are released,
* CPU can enter to the hot sleep state.
*
* Parameter:
* lock - the pointer of a wakelock variable
*
****************************************************************************/
void up_pm_release_wakelock(struct pm_cpu_wakelock_s *lock);
/****************************************************************************
* Name: up_pm_count_acquire_wakelock
*
* Description:
* Count the total number of wakelock
*
* Return:
* the total number of wakelock
*
****************************************************************************/
int up_pm_count_acquire_wakelock(void);
/****************************************************************************
* Name: up_pm_get_bootcause
*
* Description:
* Get the system boot cause. This boot cause indicates the cause why the
* system is launched from the state of power-off, deep sleep or cold sleep.
* Each boot cause is defined as PM_BOOT_XXX.
*
* Return:
* Boot cause
*
****************************************************************************/
uint32_t up_pm_get_bootcause(void);
/****************************************************************************
* Name: up_pm_get_bootmask
*
* Description:
* Get the system boot mask. This boot mask indicates whether the specified
* bit is enabled or not as the boot cause. If a bit of boot mask is set,
* the boot cause is enabled. Each boot mask is defined as PM_BOOT_XXX.
*
* Return:
* Boot mask
*
****************************************************************************/
uint32_t up_pm_get_bootmask(void);
/****************************************************************************
* Name: up_pm_set_bootmask
*
* Description:
* Enable the boot cause of the specified bit.
*
* Parameter:
* mask - OR of Boot mask definied as PM_BOOT_XXX
*
* Return:
* Updated boot mask
*
****************************************************************************/
uint32_t up_pm_set_bootmask(uint32_t mask);
/****************************************************************************
* Name: up_pm_clr_bootmask
*
* Description:
* Disable the boot cause of the specified bit.
*
* Parameter:
* mask - OR of Boot mask definied as PM_BOOT_XXX
*
* Return:
* Updated boot mask
*
****************************************************************************/
uint32_t up_pm_clr_bootmask(uint32_t mask);
/****************************************************************************
* Name: up_pm_sleep
*
* Description:
* Enter sleep mode. This function never returns.
*
* Parameter:
* mode - PM_SLEEP_DEEP or PM_SLEEP_COLD
*
****************************************************************************/
int up_pm_sleep(enum pm_sleepmode_e mode);
/****************************************************************************
* Name: up_pm_reboot
*
* Description:
* System reboot. This function never returns.
*
****************************************************************************/
int up_pm_reboot(void);
/****************************************************************************
* Name: up_pmic_set_notify
*
* Description:
* Register a callback for pmic interrupt
*
* Input Parameter:
* kind - A kind of pmic interrupt defined as pmic_notify_e
* cb - A callback function for a kind of pmic interrupt
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
#ifdef CONFIG_CXD56_PMIC_INT
int up_pmic_set_notify(int kind, pmic_notify_t cb);
#else
# define up_pmic_set_notify(kind, cb)
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_PM_H */
arch/arm/include/cxd56xx/usbdev.h
+65
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/****************************************************************************
* arch/arm/include/cxd56xx/usbdev.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H
#define __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H
/********************************************************************************************
* Included Files
********************************************************************************************/
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* BOARDIOC_USBDEV_SETNOTIFYSIG signal value ************************************************/
#define USBDEV_STATE_DETACH 0
#define USBDEV_STATE_ATTACH 1
/*
* The BOARDIOC_USBDEV_SETNOTIFYSIG signal output the VBUS connection state
* and supply current value to the signal handler argument (sival_int).
*
* Please use the following macros.
*
* - USBDEV_CONNECTED : Get VBUS connection state.
* - USBDEV_POWER_CURRENT : Get VBUS supply current.
*/
#define USBDEV_CONNECTED(x) (0xffff & ((x)>>16))
#define USBDEV_POWER_CURRENT(x) (0xffff & (x))
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H */
arch/arm/include/imxrt/chip.h
+41 -25
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/*****************************************************************************
* arch/arm/include/imxrt/chip.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,27 +32,42 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
*****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
/************************************************************************************
/*****************************************************************************
* Included Files
************************************************************************************/
*****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/*****************************************************************************
* Pre-processor Definitions
************************************************************************************/
*****************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A)
/* MIMXRT1021CAG4A - 144 pin, 400MHz Industrial
* MIMXRT1021CAF4A - 100 pin, 400MHz Industrial
* MIMXRT1021DAF5A - 100 pin, 500MHz Consumer
* MIMXRT1021DAG5A - 144 pin, 500MHz Consumer
*/
# define IMXRT_OCRAM_SIZE (256 * 1024) /* 256Kb OCRAM */
# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
/* but 4 doesn't exist */
#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
* MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
@@ -63,9 +78,9 @@
# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
* MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
* MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
@@ -78,27 +93,28 @@
# error "Unknown i.MX RT chip type"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the
* greater the priority of the corresponding interrupt. The i.MX RT processor
* implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
/* NVIC priority levels ******************************************************
/* Each priority field holds an 8-bit priority value, 0-15. The lower the
* value, the greater the priority of the corresponding interrupt. The i.MX
* RT processor implements only bits[7:4] of each field, bits[3:0] read as
* zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
/************************************************************************************
/*****************************************************************************
* Public Types
************************************************************************************/
*****************************************************************************/
/************************************************************************************
/*****************************************************************************
* Public Data
************************************************************************************/
*****************************************************************************/
/************************************************************************************
/*****************************************************************************
* Public Functions
************************************************************************************/
*****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
arch/arm/include/imxrt/imxrt102x_irq.h
+469
View File
@@ -0,0 +1,469 @@
/****************************************************************************************
* arch/arm/include/imxrt/imxrt105x_irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Dave Marples <dave@marples.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H
#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* External interrupts (priority levels >= 256) *****************************************/
#define IMXRT_IRQ_EDMA0_16 (IMXRT_IRQ_EXTINT + 0) /* eDMA Channel 0/16 Transfer Complete */
#define IMXRT_IRQ_EDMA1_17 (IMXRT_IRQ_EXTINT + 1) /* eDMA Channel 1/17 Transfer Complete */
#define IMXRT_IRQ_EDMA2_18 (IMXRT_IRQ_EXTINT + 2) /* eDMA Channel 2/18 Transfer Complete */
#define IMXRT_IRQ_EDMA3_19 (IMXRT_IRQ_EXTINT + 3) /* eDMA Channel 3/19 Transfer Complete */
#define IMXRT_IRQ_EDMA4_20 (IMXRT_IRQ_EXTINT + 4) /* eDMA Channel 4/20 Transfer Complete */
#define IMXRT_IRQ_EDMA5_21 (IMXRT_IRQ_EXTINT + 5) /* eDMA Channel 5/21 Transfer Complete */
#define IMXRT_IRQ_EDMA6_22 (IMXRT_IRQ_EXTINT + 6) /* eDMA Channel 6/22 Transfer Complete */
#define IMXRT_IRQ_EDMA7_23 (IMXRT_IRQ_EXTINT + 7) /* eDMA Channel 7/23 Transfer Complete */
#define IMXRT_IRQ_EDMA8_24 (IMXRT_IRQ_EXTINT + 8) /* eDMA Channel 8/24 Transfer Complete */
#define IMXRT_IRQ_EDMA9_25 (IMXRT_IRQ_EXTINT + 9) /* eDMA Channel 9/25 Transfer Complete */
#define IMXRT_IRQ_EDMA10_26 (IMXRT_IRQ_EXTINT + 10) /* eDMA Channel 10/26 Transfer Complete */
#define IMXRT_IRQ_EDMA11_27 (IMXRT_IRQ_EXTINT + 11) /* eDMA Channel 11/27 Transfer Complete */
#define IMXRT_IRQ_EDMA12_28 (IMXRT_IRQ_EXTINT + 12) /* eDMA Channel 12/28 Transfer Complete */
#define IMXRT_IRQ_EDMA13_29 (IMXRT_IRQ_EXTINT + 13) /* eDMA Channel 13/29 Transfer Complete */
#define IMXRT_IRQ_EDMA14_30 (IMXRT_IRQ_EXTINT + 14) /* eDMA Channel 14/30 Transfer Complete */
#define IMXRT_IRQ_EDMA15_31 (IMXRT_IRQ_EXTINT + 15) /* eDMA Channel 15/31 Transfer Complete */
#define IMXRT_IRQ_EDMA_ERROR (IMXRT_IRQ_EXTINT + 16) /* Error Interrupt, Channels 0-15 / 16-31 */
#define IMXRT_IRQ_CM70 (IMXRT_IRQ_EXTINT + 17) /* CTI trigger outputs (internal: CTIIRQ[0]) */
#define IMXRT_IRQ_CM71 (IMXRT_IRQ_EXTINT + 18) /* CTI trigger outputs (internal: CTIIRQ[1]) */
#define IMXRT_IRQ_CM7CP (IMXRT_IRQ_EXTINT + 19) /* CorePlatform exception IRQ */
#define IMXRT_IRQ_LPUART1 (IMXRT_IRQ_EXTINT + 20) /* UART1 TX/RX interrupt */
#define IMXRT_IRQ_LPUART2 (IMXRT_IRQ_EXTINT + 21) /* UART2 TX/RX interrupt */
#define IMXRT_IRQ_LPUART3 (IMXRT_IRQ_EXTINT + 22) /* UART3 TX/RX interrupt */
#define IMXRT_IRQ_LPUART4 (IMXRT_IRQ_EXTINT + 23) /* UART4 TX/RX interrupt */
#define IMXRT_IRQ_LPUART5 (IMXRT_IRQ_EXTINT + 24) /* UART5 TX/RX interrupt */
#define IMXRT_IRQ_LPUART6 (IMXRT_IRQ_EXTINT + 25) /* UART6 TX/RX interrupt */
#define IMXRT_IRQ_LPUART7 (IMXRT_IRQ_EXTINT + 26) /* UART7 TX/RX interrupt */
#define IMXRT_IRQ_LPUART8 (IMXRT_IRQ_EXTINT + 27) /* UART8 TX/RX interrupt */
#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */
#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */
#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */
#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C4 Interrupt */
#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */
#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */
#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */
#define IMXRT_IRQ_LPSPI4 (IMXRT_IRQ_EXTINT + 35) /* LPSPI4 interrupt */
#define IMXRT_IRQ_CAN1 (IMXRT_IRQ_EXTINT + 36) /* CAN1 interrupt */
#define IMXRT_IRQ_CAN2 (IMXRT_IRQ_EXTINT + 37) /* CAN2 interrupt */
#define IMXRT_IRQ_CM7FR (IMXRT_IRQ_EXTINT + 38) /* FlexRAM address fault */
#define IMXRT_IRQ_KPP (IMXRT_IRQ_EXTINT + 39) /* Keypad Interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 40) RESERVED */
#define IMXRT_IRQ_GPRIRQ (IMXRT_IRQ_EXTINT + 41) /* Notify cores on exception while boot */
/* RESERVED (IMXRT_IRQ_EXTINT + 42) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 43) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 44) RESERVED */
#define IMXRT_IRQ_WDOG2 (IMXRT_IRQ_EXTINT + 45) /* Watchdog Timer reset */
#define IMXRT_IRQ_SNVS (IMXRT_IRQ_EXTINT + 46) /* SNVS Functional Interrupt */
#define IMXRT_IRQ_SNVSSEC (IMXRT_IRQ_EXTINT + 47) /* SNVS Security Interrupt */
#define IMXRT_IRQ_SNVSSB (IMXRT_IRQ_EXTINT + 48) /* ON-OFF short button press */
#define IMXRT_IRQ_CSU (IMXRT_IRQ_EXTINT + 49) /* CSU Interrupt Request 1 */
#define IMXRT_IRQ_DCP (IMXRT_IRQ_EXTINT + 50) /* DCP channel/CRC interrupts (channel != 0) */
#define IMXRT_IRQ_DCP0 (IMXRT_IRQ_EXTINT + 51) /* DCP channel 0 interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 52) RESERVED */
#define IMXRT_IRQ_TRNG (IMXRT_IRQ_EXTINT + 53) /* TRNG Interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 54) RESERVED */
#define IMXRT_IRQ_BEE (IMXRT_IRQ_EXTINT + 55) /* BEE IRQ */
#define IMXRT_IRQ_SAI1 (IMXRT_IRQ_EXTINT + 56) /* SAI1 interrupt (RX/TX) */
#define IMXRT_IRQ_SAI2 (IMXRT_IRQ_EXTINT + 57) /* SAI2 interrupt (RX/TX) */
#define IMXRT_IRQ_SAI3RX (IMXRT_IRQ_EXTINT + 58) /* SAI3 RX interrupt (RX/TX) */
#define IMXRT_IRQ_SAI3TX (IMXRT_IRQ_EXTINT + 59) /* SAI3 TX interrupt (RX/TX) */
#define IMXRT_IRQ_SPDIF (IMXRT_IRQ_EXTINT + 60) /* SPDIF interrupt */
#define IMXRT_IRQ_PMU (IMXRT_IRQ_EXTINT + 61) /* Brown-out event 1.1, 2.5 or 3.0 regulators */
/* RESERVED (IMXRT_IRQ_EXTINT + 62) RESERVED */
#define IMXRT_IRQ_TEMP (IMXRT_IRQ_EXTINT + 63) /* Temperature Monitor */
#define IMXRT_IRQ_TEMPPANIC (IMXRT_IRQ_EXTINT + 64) /* TempSensor panic */
#define IMXRT_IRQ_USBPHY0 (IMXRT_IRQ_EXTINT + 65) /* USBPHY (UTMI0) interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 66) RESERVED */
#define IMXRT_IRQ_ADC1 (IMXRT_IRQ_EXTINT + 67) /* ADC1 interrupt */
#define IMXRT_IRQ_ADC2 (IMXRT_IRQ_EXTINT + 68) /* ADC2 interrupt */
#define IMXRT_IRQ_DCDC (IMXRT_IRQ_EXTINT + 69) /* DCDC interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 70) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 71) RESERVED */
#define IMXRT_IRQ_GPIO1_0 (IMXRT_IRQ_EXTINT + 72) /* GPIO1 INT0 interrupt */
#define IMXRT_IRQ_GPIO1_1 (IMXRT_IRQ_EXTINT + 73) /* GPIO1 INT1 interrupt */
#define IMXRT_IRQ_GPIO1_2 (IMXRT_IRQ_EXTINT + 74) /* GPIO1 INT2 interrupt */
#define IMXRT_IRQ_GPIO1_3 (IMXRT_IRQ_EXTINT + 75) /* GPIO1 INT3 interrupt */
#define IMXRT_IRQ_GPIO1_4 (IMXRT_IRQ_EXTINT + 76) /* GPIO1 INT4 interrupt */
#define IMXRT_IRQ_GPIO1_5 (IMXRT_IRQ_EXTINT + 77) /* GPIO1 INT5 interrupt */
#define IMXRT_IRQ_GPIO1_6 (IMXRT_IRQ_EXTINT + 78) /* GPIO1 INT6 interrupt */
#define IMXRT_IRQ_GPIO1_7 (IMXRT_IRQ_EXTINT + 79) /* GPIO1 INT7 interrupt */
#define IMXRT_IRQ_GPIO1_0_15 (IMXRT_IRQ_EXTINT + 80) /* GPIO1 INT0-15 interrupt */
#define IMXRT_IRQ_GPIO1_16_31 (IMXRT_IRQ_EXTINT + 81) /* GPIO1 INT16-31 interrupt */
#define IMXRT_IRQ_GPIO2_0_15 (IMXRT_IRQ_EXTINT + 82) /* GPIO2 INT0-15 interrupt */
#define IMXRT_IRQ_GPIO2_16_31 (IMXRT_IRQ_EXTINT + 83) /* GPIO2 INT16-31 interrupt */
#define IMXRT_IRQ_GPIO3_0_15 (IMXRT_IRQ_EXTINT + 84) /* GPIO3 INT0-15 interrupt */
#define IMXRT_IRQ_GPIO3_16_31 (IMXRT_IRQ_EXTINT + 85) /* GPIO3 INT16-31 interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 86) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 87) RESERVED */
#define IMXRT_IRQ_GPIO5_0_15 (IMXRT_IRQ_EXTINT + 88) /* GPIO5 INT0-15 interrupt */
#define IMXRT_IRQ_GPIO5_16_31 (IMXRT_IRQ_EXTINT + 89) /* GPIO5 INT16-31 interrupt */
#define IMXRT_IRQ_FLEXIO1 (IMXRT_IRQ_EXTINT + 90) /* FlexIO Interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 91) RESERVED */
#define IMXRT_IRQ_WDOG1 (IMXRT_IRQ_EXTINT + 92) /* Watchdog Timer reset */
#define IMXRT_IRQ_RTWDOG (IMXRT_IRQ_EXTINT + 93) /* Watchdog Timer reset */
#define IMXRT_IRQ_EWM (IMXRT_IRQ_EXTINT + 94) /* EWM interrupt */
#define IMXRT_IRQ_CCM_1 (IMXRT_IRQ_EXTINT + 95) /* CCM interrupt 1 */
#define IMXRT_IRQ_CCM_2 (IMXRT_IRQ_EXTINT + 96) /* CCM interrupt 2 */
#define IMXRT_IRQ_GPC (IMXRT_IRQ_EXTINT + 97) /* GPC interrupt 1 */
#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 99) RESERVED */
#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
#define IMXRT_IRQ_FLEXPWM1_3 (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */
#define IMXRT_IRQ_FLEXPWM1_F (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt OR reload error */
/* RESERVED (IMXRT_IRQ_EXTINT + 107) RESERVED */
#define IMXRT_IRQ_FLEXSPI (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */
#define IMXRT_IRQ_SEMC (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */
#define IMXRT_IRQ_USDHC1 (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */
#define IMXRT_IRQ_USDHC2 (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 112) RESERVED */
#define IMXRT_IRQ_USBOTG1 (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */
#define IMXRT_IRQ_ENET (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */
#define IMXRT_IRQ_ENET1588 (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */
#define IMXRT_IRQ_XBAR1_0_1 (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */
#define IMXRT_IRQ_XBAR1_2_3 (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */
#define IMXRT_IRQ_ADCETC_0 (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */
#define IMXRT_IRQ_ADCETC_1 (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */
#define IMXRT_IRQ_ADCETC_2 (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */
#define IMXRT_IRQ_ADCETC_ERR (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */
#define IMXRT_IRQ_PIT (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */
#define IMXRT_IRQ_ACMP1 (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */
#define IMXRT_IRQ_ACMP2 (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */
#define IMXRT_IRQ_ACMP3 (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */
#define IMXRT_IRQ_ACMP4 (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 127) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 128) RESERVED */
#define IMXRT_IRQ_ENC1 (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */
#define IMXRT_IRQ_ENC2 (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 131) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 132) RESERVED */
#define IMXRT_IRQ_QTIMER1 (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */
#define IMXRT_IRQ_QTIMER2 (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 135) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 136) RESERVED */
#define IMXRT_IRQ_FLEXPWM2_0 (IMXRT_IRQ_EXTINT + 137) /* FLEXPWM2 capture/compare/reload 0 interrupt */
#define IMXRT_IRQ_FLEXPWM2_1 (IMXRT_IRQ_EXTINT + 138) /* FLEXPWM2 capture/compare/reload 1 interrupt */
#define IMXRT_IRQ_FLEXPWM2_2 (IMXRT_IRQ_EXTINT + 139) /* FLEXPWM2 capture/compare/reload 1 interrupt */
#define IMXRT_IRQ_FLEXPWM2_3 (IMXRT_IRQ_EXTINT + 140) /* FLEXPWM2 capture/compare/reload 3 interrupt */
#define IMXRT_IRQ_FLEXPWM2_F (IMXRT_IRQ_EXTINT + 141) /* FLEXPWM2 fault interrupt */
/* RESERVED (IMXRT_IRQ_EXTINT + 142) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 143) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 144) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 146) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 147) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 148) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 149) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 150) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 151) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 152) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 153) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 154) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 155) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 156) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 157) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 158) RESERVED */
/* RESERVED (IMXRT_IRQ_EXTINT + 159) RESERVED */
#define IMXRT_IRQ_NEXTINT 160
/* GPIO second level interrupt **********************************************************/
#define IMXRT_GPIO_IRQ_FIRST (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT)
#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
/* GPIO1 has dedicated interrupts for pins 0-7
* REVISIT: I am assuming that you really cannot use the dedicated and the multiplex
* interrupts concurrently.
*/
# define IMXRT_IRQ_GPIO1_0 (_IMXRT_GPIO1_0_15_BASE + 0) /* GPIO1 pin 0 interrupt */
# define IMXRT_IRQ_GPIO1_1 (_IMXRT_GPIO1_0_15_BASE + 1) /* GPIO1 pin 1 interrupt */
# define IMXRT_IRQ_GPIO1_2 (_IMXRT_GPIO1_0_15_BASE + 2) /* GPIO1 pin 2 interrupt */
# define IMXRT_IRQ_GPIO1_3 (_IMXRT_GPIO1_0_15_BASE + 3) /* GPIO1 pin 3 interrupt */
# define IMXRT_IRQ_GPIO1_4 (_IMXRT_GPIO1_0_15_BASE + 4) /* GPIO1 pin 4 interrupt */
# define IMXRT_IRQ_GPIO1_5 (_IMXRT_GPIO1_0_15_BASE + 5) /* GPIO1 pin 5 interrupt */
# define IMXRT_IRQ_GPIO1_6 (_IMXRT_GPIO1_0_15_BASE + 6) /* GPIO1 pin 6 interrupt */
# define IMXRT_IRQ_GPIO1_7 (_IMXRT_GPIO1_0_15_BASE + 7) /* GPIO1 pin 7 interrupt */
# define IMXRT_IRQ_GPIO1_8 (_IMXRT_GPIO1_0_15_BASE + 8) /* GPIO1 pin 8 interrupt */
# define IMXRT_IRQ_GPIO1_9 (_IMXRT_GPIO1_0_15_BASE + 9) /* GPIO1 pin 9 interrupt */
# define IMXRT_IRQ_GPIO1_10 (_IMXRT_GPIO1_0_15_BASE + 10) /* GPIO1 pin 10 interrupt */
# define IMXRT_IRQ_GPIO1_11 (_IMXRT_GPIO1_0_15_BASE + 11) /* GPIO1 pin 11 interrupt */
# define IMXRT_IRQ_GPIO1_12 (_IMXRT_GPIO1_0_15_BASE + 12) /* GPIO1 pin 12 interrupt */
# define IMXRT_IRQ_GPIO1_13 (_IMXRT_GPIO1_0_15_BASE + 13) /* GPIO1 pin 13 interrupt */
# define IMXRT_IRQ_GPIO1_14 (_IMXRT_GPIO1_0_15_BASE + 14) /* GPIO1 pin 14 interrupt */
# define IMXRT_IRQ_GPIO1_15 (_IMXRT_GPIO1_0_15_BASE + 15) /* GPIO1 pin 15 interrupt */
# define _IMXRT_GPIO1_8_15_NIRQS 16
# define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS)
#else
# define _IMXRT_GPIO1_8_15_NIRQS 0
# define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE
#endif
#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ
# define IMXRT_IRQ_GPIO1_16 (_IMXRT_GPIO1_16_31_BASE + 0) /* GPIO1 pin 16 interrupt */
# define IMXRT_IRQ_GPIO1_17 (_IMXRT_GPIO1_16_31_BASE + 1) /* GPIO1 pin 17 interrupt */
# define IMXRT_IRQ_GPIO1_18 (_IMXRT_GPIO1_16_31_BASE + 2) /* GPIO1 pin 18 interrupt */
# define IMXRT_IRQ_GPIO1_19 (_IMXRT_GPIO1_16_31_BASE + 3) /* GPIO1 pin 19 interrupt */
# define IMXRT_IRQ_GPIO1_20 (_IMXRT_GPIO1_16_31_BASE + 4) /* GPIO1 pin 10 interrupt */
# define IMXRT_IRQ_GPIO1_21 (_IMXRT_GPIO1_16_31_BASE + 5) /* GPIO1 pin 21 interrupt */
# define IMXRT_IRQ_GPIO1_22 (_IMXRT_GPIO1_16_31_BASE + 6) /* GPIO1 pin 22 interrupt */
# define IMXRT_IRQ_GPIO1_23 (_IMXRT_GPIO1_16_31_BASE + 7) /* GPIO1 pin 23 interrupt */
# define IMXRT_IRQ_GPIO1_24 (_IMXRT_GPIO1_16_31_BASE + 8) /* GPIO1 pin 24 interrupt */
# define IMXRT_IRQ_GPIO1_25 (_IMXRT_GPIO1_16_31_BASE + 9) /* GPIO1 pin 25 interrupt */
# define IMXRT_IRQ_GPIO1_26 (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */
# define IMXRT_IRQ_GPIO1_27 (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */
# define IMXRT_IRQ_GPIO1_28 (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */
# define IMXRT_IRQ_GPIO1_29 (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */
# define IMXRT_IRQ_GPIO1_30 (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */
# define IMXRT_IRQ_GPIO1_31 (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */
# define _IMXRT_GPIO1_16_31_NIRQS 16
# define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS)
# define IMXRT_GPIO1_NIRQS (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS)
#else
# define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE
# define IMXRT_GPIO1_NIRQS _IMXRT_GPIO1_8_15_NIRQS
#endif
#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ
# define IMXRT_IRQ_GPIO2_0 (_IMXRT_GPIO2_0_15_BASE + 0) /* GPIO2 pin 0 interrupt */
# define IMXRT_IRQ_GPIO2_1 (_IMXRT_GPIO2_0_15_BASE + 1) /* GPIO2 pin 1 interrupt */
# define IMXRT_IRQ_GPIO2_2 (_IMXRT_GPIO2_0_15_BASE + 2) /* GPIO2 pin 2 interrupt */
# define IMXRT_IRQ_GPIO2_3 (_IMXRT_GPIO2_0_15_BASE + 3) /* GPIO2 pin 3 interrupt */
# define IMXRT_IRQ_GPIO2_4 (_IMXRT_GPIO2_0_15_BASE + 4) /* GPIO2 pin 4 interrupt */
# define IMXRT_IRQ_GPIO2_5 (_IMXRT_GPIO2_0_15_BASE + 5) /* GPIO2 pin 5 interrupt */
# define IMXRT_IRQ_GPIO2_6 (_IMXRT_GPIO2_0_15_BASE + 6) /* GPIO2 pin 6 interrupt */
# define IMXRT_IRQ_GPIO2_7 (_IMXRT_GPIO2_0_15_BASE + 7) /* GPIO2 pin 7 interrupt */
# define IMXRT_IRQ_GPIO2_8 (_IMXRT_GPIO2_0_15_BASE + 8) /* GPIO2 pin 8 interrupt */
# define IMXRT_IRQ_GPIO2_9 (_IMXRT_GPIO2_0_15_BASE + 9) /* GPIO2 pin 9 interrupt */
# define IMXRT_IRQ_GPIO2_10 (_IMXRT_GPIO2_0_15_BASE + 10) /* GPIO2 pin 10 interrupt */
# define IMXRT_IRQ_GPIO2_11 (_IMXRT_GPIO2_0_15_BASE + 11) /* GPIO2 pin 11 interrupt */
# define IMXRT_IRQ_GPIO2_12 (_IMXRT_GPIO2_0_15_BASE + 12) /* GPIO2 pin 12 interrupt */
# define IMXRT_IRQ_GPIO2_13 (_IMXRT_GPIO2_0_15_BASE + 13) /* GPIO2 pin 13 interrupt */
# define IMXRT_IRQ_GPIO2_14 (_IMXRT_GPIO2_0_15_BASE + 14) /* GPIO2 pin 14 interrupt */
# define IMXRT_IRQ_GPIO2_15 (_IMXRT_GPIO2_0_15_BASE + 15) /* GPIO2 pin 15 interrupt */
# define _IMXRT_GPIO2_0_15_NIRQS 16
# define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS)
#else
# define _IMXRT_GPIO2_0_15_NIRQS 0
# define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE
#endif
#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ
# define IMXRT_IRQ_GPIO2_16 (_IMXRT_GPIO2_16_31_BASE + 0) /* GPIO2 pin 16 interrupt */
# define IMXRT_IRQ_GPIO2_17 (_IMXRT_GPIO2_16_31_BASE + 1) /* GPIO2 pin 17 interrupt */
# define IMXRT_IRQ_GPIO2_18 (_IMXRT_GPIO2_16_31_BASE + 2) /* GPIO2 pin 18 interrupt */
# define IMXRT_IRQ_GPIO2_19 (_IMXRT_GPIO2_16_31_BASE + 3) /* GPIO2 pin 19 interrupt */
# define IMXRT_IRQ_GPIO2_20 (_IMXRT_GPIO2_16_31_BASE + 4) /* GPIO2 pin 20 interrupt */
# define IMXRT_IRQ_GPIO2_21 (_IMXRT_GPIO2_16_31_BASE + 5) /* GPIO2 pin 21 interrupt */
# define IMXRT_IRQ_GPIO2_22 (_IMXRT_GPIO2_16_31_BASE + 6) /* GPIO2 pin 22 interrupt */
# define IMXRT_IRQ_GPIO2_23 (_IMXRT_GPIO2_16_31_BASE + 7) /* GPIO2 pin 23 interrupt */
# define IMXRT_IRQ_GPIO2_24 (_IMXRT_GPIO2_16_31_BASE + 8) /* GPIO2 pin 24 interrupt */
# define IMXRT_IRQ_GPIO2_25 (_IMXRT_GPIO2_16_31_BASE + 9) /* GPIO2 pin 25 interrupt */
# define IMXRT_IRQ_GPIO2_26 (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */
# define IMXRT_IRQ_GPIO2_27 (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */
# define IMXRT_IRQ_GPIO2_28 (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */
# define IMXRT_IRQ_GPIO2_29 (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */
# define IMXRT_IRQ_GPIO2_30 (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */
# define IMXRT_IRQ_GPIO2_31 (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */
# define _IMXRT_GPIO2_16_31_NIRQS 16
# define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS)
# define IMXRT_GPIO2_NIRQS (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS)
#else
# define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE
# define IMXRT_GPIO2_NIRQS _IMXRT_GPIO2_0_15_NIRQS
#endif
#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ
# define IMXRT_IRQ_GPIO3_0 (_IMXRT_GPIO3_0_15_BASE + 0) /* GPIO3 pin 0 interrupt */
# define IMXRT_IRQ_GPIO3_1 (_IMXRT_GPIO3_0_15_BASE + 1) /* GPIO3 pin 1 interrupt */
# define IMXRT_IRQ_GPIO3_2 (_IMXRT_GPIO3_0_15_BASE + 2) /* GPIO3 pin 2 interrupt */
# define IMXRT_IRQ_GPIO3_3 (_IMXRT_GPIO3_0_15_BASE + 3) /* GPIO3 pin 3 interrupt */
# define IMXRT_IRQ_GPIO3_4 (_IMXRT_GPIO3_0_15_BASE + 4) /* GPIO3 pin 4 interrupt */
# define IMXRT_IRQ_GPIO3_5 (_IMXRT_GPIO3_0_15_BASE + 5) /* GPIO3 pin 5 interrupt */
# define IMXRT_IRQ_GPIO3_6 (_IMXRT_GPIO3_0_15_BASE + 6) /* GPIO3 pin 6 interrupt */
# define IMXRT_IRQ_GPIO3_7 (_IMXRT_GPIO3_0_15_BASE + 7) /* GPIO3 pin 7 interrupt */
# define IMXRT_IRQ_GPIO3_8 (_IMXRT_GPIO3_0_15_BASE + 8) /* GPIO3 pin 8 interrupt */
# define IMXRT_IRQ_GPIO3_9 (_IMXRT_GPIO3_0_15_BASE + 9) /* GPIO3 pin 9 interrupt */
# define IMXRT_IRQ_GPIO3_10 (_IMXRT_GPIO3_0_15_BASE + 10) /* GPIO3 pin 10 interrupt */
# define IMXRT_IRQ_GPIO3_11 (_IMXRT_GPIO3_0_15_BASE + 11) /* GPIO3 pin 11 interrupt */
# define IMXRT_IRQ_GPIO3_12 (_IMXRT_GPIO3_0_15_BASE + 12) /* GPIO3 pin 12 interrupt */
# define IMXRT_IRQ_GPIO3_13 (_IMXRT_GPIO3_0_15_BASE + 13) /* GPIO3 pin 13 interrupt */
# define IMXRT_IRQ_GPIO3_14 (_IMXRT_GPIO3_0_15_BASE + 14) /* GPIO3 pin 14 interrupt */
# define IMXRT_IRQ_GPIO3_15 (_IMXRT_GPIO3_0_15_BASE + 15) /* GPIO3 pin 15 interrupt */
# define _IMXRT_GPIO3_0_15_NIRQS 16
# define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS)
#else
# define _IMXRT_GPIO3_0_15_NIRQS 0
# define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE
#endif
#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
# define IMXRT_IRQ_GPIO3_16 (_IMXRT_GPIO3_16_31_BASE + 0) /* GPIO3 pin 16 interrupt */
# define IMXRT_IRQ_GPIO3_17 (_IMXRT_GPIO3_16_31_BASE + 1) /* GPIO3 pin 17 interrupt */
# define IMXRT_IRQ_GPIO3_18 (_IMXRT_GPIO3_16_31_BASE + 2) /* GPIO3 pin 18 interrupt */
# define IMXRT_IRQ_GPIO3_19 (_IMXRT_GPIO3_16_31_BASE + 3) /* GPIO3 pin 19 interrupt */
# define IMXRT_IRQ_GPIO3_20 (_IMXRT_GPIO3_16_31_BASE + 4) /* GPIO3 pin 20 interrupt */
# define IMXRT_IRQ_GPIO3_21 (_IMXRT_GPIO3_16_31_BASE + 5) /* GPIO3 pin 21 interrupt */
# define IMXRT_IRQ_GPIO3_22 (_IMXRT_GPIO3_16_31_BASE + 6) /* GPIO3 pin 22 interrupt */
# define IMXRT_IRQ_GPIO3_23 (_IMXRT_GPIO3_16_31_BASE + 7) /* GPIO3 pin 23 interrupt */
# define IMXRT_IRQ_GPIO3_24 (_IMXRT_GPIO3_16_31_BASE + 8) /* GPIO3 pin 24 interrupt */
# define IMXRT_IRQ_GPIO3_25 (_IMXRT_GPIO3_16_31_BASE + 9) /* GPIO3 pin 25 interrupt */
# define IMXRT_IRQ_GPIO3_26 (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */
# define IMXRT_IRQ_GPIO3_27 (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */
# define IMXRT_IRQ_GPIO3_28 (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */
# define IMXRT_IRQ_GPIO3_29 (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */
# define IMXRT_IRQ_GPIO3_30 (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */
# define IMXRT_IRQ_GPIO3_31 (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */
# define _IMXRT_GPIO3_16_31_NIRQS 16
# define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS)
# define IMXRT_GPIO3_NIRQS (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS)
#else
# define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO3_16_31_BASE
# define IMXRT_GPIO3_NIRQS _IMXRT_GPIO3_0_15_NIRQS
#endif
/* There is no GPIO4 on this chip */
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
# define IMXRT_IRQ_GPIO5_0 (_IMXRT_GPIO5_0_15_BASE + 0) /* GPIO5 pin 0 interrupt */
# define IMXRT_IRQ_GPIO5_1 (_IMXRT_GPIO5_0_15_BASE + 1) /* GPIO5 pin 1 interrupt */
# define IMXRT_IRQ_GPIO5_2 (_IMXRT_GPIO5_0_15_BASE + 2) /* GPIO5 pin 2 interrupt */
# define IMXRT_IRQ_GPIO5_3 (_IMXRT_GPIO5_0_15_BASE + 3) /* GPIO5 pin 3 interrupt */
# define IMXRT_IRQ_GPIO5_4 (_IMXRT_GPIO5_0_15_BASE + 4) /* GPIO5 pin 4 interrupt */
# define IMXRT_IRQ_GPIO5_5 (_IMXRT_GPIO5_0_15_BASE + 5) /* GPIO5 pin 5 interrupt */
# define IMXRT_IRQ_GPIO5_6 (_IMXRT_GPIO5_0_15_BASE + 6) /* GPIO5 pin 6 interrupt */
# define IMXRT_IRQ_GPIO5_7 (_IMXRT_GPIO5_0_15_BASE + 7) /* GPIO5 pin 7 interrupt */
# define IMXRT_IRQ_GPIO5_8 (_IMXRT_GPIO5_0_15_BASE + 8) /* GPIO5 pin 8 interrupt */
# define IMXRT_IRQ_GPIO5_9 (_IMXRT_GPIO5_0_15_BASE + 9) /* GPIO5 pin 9 interrupt */
# define IMXRT_IRQ_GPIO5_10 (_IMXRT_GPIO5_0_15_BASE + 10) /* GPIO5 pin 10 interrupt */
# define IMXRT_IRQ_GPIO5_11 (_IMXRT_GPIO5_0_15_BASE + 11) /* GPIO5 pin 11 interrupt */
# define IMXRT_IRQ_GPIO5_12 (_IMXRT_GPIO5_0_15_BASE + 12) /* GPIO5 pin 12 interrupt */
# define IMXRT_IRQ_GPIO5_13 (_IMXRT_GPIO5_0_15_BASE + 13) /* GPIO5 pin 13 interrupt */
# define IMXRT_IRQ_GPIO5_14 (_IMXRT_GPIO5_0_15_BASE + 14) /* GPIO5 pin 14 interrupt */
# define IMXRT_IRQ_GPIO5_15 (_IMXRT_GPIO5_0_15_BASE + 15) /* GPIO5 pin 15 interrupt */
# define _IMXRT_GPIO5_0_15_NIRQS 16
# define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS)
#else
# define _IMXRT_GPIO5_0_15_NIRQS 0
# define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE
#endif
#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
# define IMXRT_IRQ_GPIO5_16 (_IMXRT_GPIO5_16_31_BASE + 0) /* GPIO5 pin 16 interrupt */
# define IMXRT_IRQ_GPIO5_17 (_IMXRT_GPIO5_16_31_BASE + 1) /* GPIO5 pin 17 interrupt */
# define IMXRT_IRQ_GPIO5_18 (_IMXRT_GPIO5_16_31_BASE + 2) /* GPIO5 pin 18 interrupt */
# define IMXRT_IRQ_GPIO5_19 (_IMXRT_GPIO5_16_31_BASE + 3) /* GPIO5 pin 19 interrupt */
# define IMXRT_IRQ_GPIO5_20 (_IMXRT_GPIO5_16_31_BASE + 4) /* GPIO5 pin 20 interrupt */
# define IMXRT_IRQ_GPIO5_21 (_IMXRT_GPIO5_16_31_BASE + 5) /* GPIO5 pin 21 interrupt */
# define IMXRT_IRQ_GPIO5_22 (_IMXRT_GPIO5_16_31_BASE + 6) /* GPIO5 pin 22 interrupt */
# define IMXRT_IRQ_GPIO5_23 (_IMXRT_GPIO5_16_31_BASE + 7) /* GPIO5 pin 23 interrupt */
# define IMXRT_IRQ_GPIO5_24 (_IMXRT_GPIO5_16_31_BASE + 8) /* GPIO5 pin 24 interrupt */
# define IMXRT_IRQ_GPIO5_25 (_IMXRT_GPIO5_16_31_BASE + 9) /* GPIO5 pin 25 interrupt */
# define IMXRT_IRQ_GPIO5_26 (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */
# define IMXRT_IRQ_GPIO5_27 (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */
# define IMXRT_IRQ_GPIO5_28 (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */
# define IMXRT_IRQ_GPIO5_29 (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */
# define IMXRT_IRQ_GPIO5_30 (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */
# define IMXRT_IRQ_GPIO5_31 (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */
# define _IMXRT_GPIO5_16_31_NIRQS 16
# define IMXRT_GPIO5_NIRQS (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS)
#else
# define IMXRT_GPIO5_NIRQS _IMXRT_GPIO5_0_15_NIRQS
#endif
#define IMXRT_GPIO_NIRQS (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \
IMXRT_GPIO3_NIRQS + IMXRT_GPIO5_NIRQS)
#define IMXRT_GPIO_IRQ_LAST (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS)
/* Total number of IRQ numbers **********************************************************/
#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H */
arch/arm/include/imxrt/irq.h
+31 -23
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/include/imxrt/irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,53 +32,61 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
#define __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
/****************************************************************************************
/*****************************************************************************
* Included Files
****************************************************************************************/
*****************************************************************************/
#include <nuttx/config.h>
#include <arch/imxrt/chip.h>
/****************************************************************************************
/*****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
*****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words
* of memory in the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define IMXRT_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
#define IMXRT_IRQ_RESERVED (0) /* Reserved vector .. only used with
CONFIG_DEBUG_FEATURES */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define IMXRT_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
/* Vector 1: Reset (not handled by IRQ) */
#define IMXRT_IRQ_NMI (2) /* Vector 2: Non-Maskable Int (NMI) */
#define IMXRT_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define IMXRT_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define IMXRT_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define IMXRT_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define IMXRT_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define IMXRT_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define IMXRT_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define IMXRT_IRQ_PENDSV (14) /* Vector 14: Pendable SSR */
#define IMXRT_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define IMXRT_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define IMXRT_IRQ_EXTINT (16) /* Vector number of the first ext int */
#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include <arch/imxrt/imxrt102x_irq.h>
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include <arch/imxrt/imxrt105x_irq.h>
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include <arch/imxrt/imxrt106x_irq.h>
@@ -86,15 +94,15 @@
# error Unrecognized i.MX RT architecture
#endif
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
@@ -104,9 +112,9 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************************
/****************************************************************************
* Public Function Prototypes
****************************************************************************************/
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
arch/arm/include/stm32f0l0/chip.h → arch/arm/include/stm32f0l0g0/chip.h
+154 -67
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/include/stm32f0l0/chip.h
* arch/arm/include/stm32f0l0g0/chip.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
/************************************************************************************
* Included Files
@@ -57,12 +57,13 @@
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 2 /* Two USARTs modules */
# define STM32_NCAN 0 /* No CAN controllers */
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 1 /* One DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 1 /* One DAC channel */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
@@ -83,16 +84,14 @@
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 4 /* Four USARTs module */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 10 /* Ten external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channel */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 17 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
@@ -113,16 +112,14 @@
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 4 /* Four USARTs module */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 16 /* 16 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channel */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 18 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
@@ -143,16 +140,14 @@
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 4 /* Four USARTs module */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 16 /* 16 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channel */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 24 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
@@ -173,16 +168,14 @@
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NDMA 2 /* DMA1, DMA2 */
# define STM32_NUSART 6 /* Six USARTs modules */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 10 /* 10 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channel */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 17 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
@@ -204,16 +197,14 @@
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NDMA 2 /* DMA1, DMA2 */
# define STM32_NUSART 8 /* Eight USARTs modules */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 16 /* 16 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channel */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# define STM32_NCAP 24 /* Capacitive sensing channels */
@@ -222,10 +213,44 @@
# endif
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \
defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \
defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \
defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \
defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \
defined(CONFIG_ARCH_CHIP_STM32G071RB)
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
* (with DMA) and TIM21-22 without DMA */
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
/* Two LPTIMER */
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */
# define STM32_NDMA 1 /* One DMA1, 7-channels */
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
/* One LPUART */
# define STM32_NCAN 0 /* No CAN controllers */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 0 /* No USB OTG */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC 1 /* (1) ADC1, 12-channels */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 0 /* No CRC module */
# define STM32_NRNG 0 /* No Random number generator (RNG) */
# define STM32_NCAP 0 /* No Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
/* STM32L EnergyLite Line ***********************************************************/
/* STM32L03XX - With LCD
* STM32L02XX - No LCD
/* STM32L073XX - With LCD
* STM32L072XX - No LCD
* STM32L071XX - Access line, no LCD
*
* STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM
* STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM
@@ -236,6 +261,87 @@
* STM32L0XXVX - 100-pins
*/
#elif defined(CONFIG_ARCH_CHIP_STM32L071K8)
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
* (with DMA) and TIM21-22 without DMA */
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
/* 1 LPTIMER */
# define STM32_NSPI 1 /* 1 SPI modules SPI1 */
# define STM32_NI2S 0 /* 0 I2S module */
# define STM32_NI2C 2 /* 2 I2C */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */
/* 1 LPUART */
# define STM32_NCAN 0 /* 0 CAN controllers */
# define STM32_NLCD 0 /* 0 LCD */
# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 0 /* 0 DAC channel */
# define STM32_NCOMP 2 /* 2 Analog Comparators */
# define STM32_NCRC 0 /* 0 CRC module */
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \
defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \
defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \
defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ)
# define STM32_NATIM 0 /* 0 advanced timers */
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
* (with DMA) and TIM21-22 without DMA */
# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
/* 1 LPTIMER */
# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */
# define STM32_NI2S 1 /* 1 I2S module */
# define STM32_NI2C 3 /* 3 I2C */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */
/* 1 LPUART */
# define STM32_NCAN 0 /* 0 CAN controllers */
# define STM32_NLCD 0 /* 0 LCD */
# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 0 /* 0 DAC channel */
# define STM32_NCOMP 2 /* 2 Analog Comparators */
# define STM32_NCRC 0 /* 0 CRC module */
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ)
# define STM32_NATIM 0 /* 0 advanced timers */
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
* (with DMA) and TIM21-22 without DMA */
# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
/* 1 LPTIMER */
# define STM32_NSPI 1 /* 1 SPI modules SPI1 */
# define STM32_NI2S 0 /* 0 I2S module */
# define STM32_NI2C 3 /* 3 I2C */
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */
/* 1 LPUART */
# define STM32_NCAN 0 /* 0 CAN controllers */
# define STM32_NLCD 0 /* 0 LCD */
# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 0 /* 0 DAC channel */
# define STM32_NCOMP 2 /* 2 Analog Comparators */
# define STM32_NCRC 0 /* 0 CRC module */
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \
defined(CONFIG_ARCH_CHIP_STM32L072VZ)
# define STM32_NATIM 0 /* No advanced timers */
@@ -255,11 +361,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit ADC module */
# define STM32_NADCCHAN 14 /* 14 channels */
# define STM32_NADCINT 0 /* ? internal channels vs external? */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -283,9 +386,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC 1 /* (1) ADC1, 14-channels */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -310,11 +412,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit ADC module */
# define STM32_NADCCHAN 14 /* 14 channels */
# define STM32_NADCINT 0 /* ? internal channels vs external? */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -339,11 +438,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit ADC module */
# define STM32_NADCCHAN 14 /* 14 channels */
# define STM32_NADCINT 0 /* ? internal channels vs external? */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -369,11 +465,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit ADC module */
# define STM32_NADCCHAN 14 /* 14 channels */
# define STM32_NADCINT 0 /* ? internal channels vs external? */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -398,11 +491,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit ADC module */
# define STM32_NADCCHAN 14 /* 14 channels */
# define STM32_NADCINT 0 /* ? internal channels vs external? */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -427,11 +517,8 @@
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NCEC 0 /* No HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit ADC module */
# define STM32_NADCCHAN 14 /* 14 channels */
# define STM32_NADCINT 0 /* ? internal channels vs external? */
# define STM32_NDAC 2 /* Two DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NADC 1 /* One 12-bit module */
# define STM32_NDAC 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCRC 1 /* One CRC module */
# define STM32_NRNG 1 /* One Random number generator (RNG) */
@@ -465,4 +552,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */
arch/arm/include/stm32f0l0/irq.h → arch/arm/include/stm32f0l0g0/irq.h
+8 -6
View File
@@ -38,8 +38,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
/****************************************************************************
* Included Files
@@ -48,7 +48,7 @@
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************
* Pre-processor Definitions
@@ -79,9 +79,11 @@
/* Include MCU-specific external interrupt definitions */
#if defined(CONFIG_ARCH_CHIP_STM32F0)
# include <arch/stm32f0l0/stm32f0_irq.h>
# include <arch/stm32f0l0g0/stm32f0_irq.h>
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include <arch/stm32f0l0/stm32l0_irq.h>
# include <arch/stm32f0l0g0/stm32l0_irq.h>
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
# include <arch/stm32f0l0g0/stm32g0_irq.h>
#else
# error Unrecognized STM32 Cortex M0 family
#endif
@@ -117,4 +119,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */
arch/arm/include/stm32f0l0/stm32f0_irq.h → arch/arm/include/stm32f0l0g0/stm32f0_irq.h
+46 -29
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/stm32f0l0/stm32f0_irq.h
* arch/arm/include/stm32f0l0g0/stm32f0_irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -38,8 +38,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
/****************************************************************************
* Included Files
@@ -47,7 +47,7 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************
* Pre-processor Definitions
@@ -58,7 +58,7 @@
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32f0l0/irq.h
* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
*/
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */
@@ -70,29 +70,46 @@
#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */
#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */
#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */
#define STM32_IRQ_DMA_CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA_CH1 */
#define STM32_IRQ_DMA_CH23 (STM32_IRQ_EXTINT + 10) /* 0: DMA_CH2_3 and DMA2_CH1_2 */
#define STM32_IRQ_DMA_CH4567 (STM32_IRQ_EXTINT + 11) /* 1: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
#define STM32_IRQ_ADC_COMP (STM32_IRQ_EXTINT + 12) /* 2: ADC_COMP */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 3: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 4: TIM1_CC */
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 5: TIM2 */
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 6: TIM3 */
#define STM32_IRQ_TIM6_DAC (STM32_IRQ_EXTINT + 17) /* 7: TIM6 and DAC */
#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 8: TIM7 */
#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 9: TIM14 */
#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 0: TIM15 */
#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 1: TIM16 */
#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 2: TIM17 */
#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 3: I2C1 */
#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 4: I2C2 */
#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 5: SPI1 */
#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 6: SPI2 */
#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 7: USART1 */
#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 8: USART2 */
#define STM32_IRQ_USART345678 (STM32_IRQ_EXTINT + 29) /* 9: USART3_4_5_6_7_8 */
#define STM32_IRQ_CEC_CAN (STM32_IRQ_EXTINT + 30) /* 0: HDMI CEC and CAN */
#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 1: USB */
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH1 */
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH2 */
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */
#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */
#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */
#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */
#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */
#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */
#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */
#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */
#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */
#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */
#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */
#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */
#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */
#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 29) /* 29: USART5 */
#define STM32_IRQ_USART6 (STM32_IRQ_EXTINT + 29) /* 29: USART6 */
#define STM32_IRQ_USART7 (STM32_IRQ_EXTINT + 29) /* 29: USART7 */
#define STM32_IRQ_USART8 (STM32_IRQ_EXTINT + 29) /* 29: USART8 */
#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */
#define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */
#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */
#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */
@@ -125,4 +142,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */
arch/arm/include/stm32f0l0g0/stm32g0_irq.h
+142
View File
@@ -0,0 +1,142 @@
/****************************************************************************************************
* arch/arm/include/stm32f0l0g0/stm32g0_irq.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
*/
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */
#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash */
#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */
#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */
#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */
#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */
#define STM32_IRQ_UCPD12 (STM32_IRQ_EXTINT + 8) /* 8: UCPD1_2 */
#define STM32_IRQ_EXTI32_33 (STM32_IRQ_EXTINT + 8) /* 8: EXTI_32_33 */
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */
#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
#define STM32_IRQ_EXTI17_18 (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */
#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */
#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */
#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */
#define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */
#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */
#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */
#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */
#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */
#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */
#define STM32_IRQ_EXTI23 (STM32_IRQ_EXTINT + 23) /* 23: EXTI_23 */
#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */
#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */
#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */
#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */
#define STM32_IRQ_EXTI25 (STM32_IRQ_EXTINT + 27) /* 27: EXTI_25 */
#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */
#define STM32_IRQ_EXTI26 (STM32_IRQ_EXTINT + 28) /* 28: EXTI_26 */
#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 */
#define STM32_IRQ_EXTI28 (STM32_IRQ_EXTINT + 29) /* 29: EXTI_28 */
#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */
#define STM32_IRQ_EXTI27 (STM32_IRQ_EXTINT + 30) /* 30: EXTI_27 */
#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 31) /* 31: AES */
#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */
#define STM32_IRQ_NEXTINT (32)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */
arch/arm/include/stm32f0l0/stm32l0_irq.h → arch/arm/include/stm32f0l0g0/stm32l0_irq.h
+6 -6
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32f0l0/stm32_irq.h
* arch/arm/include/stm32f0l0g0/stm32l0_irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@@ -35,8 +35,8 @@
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
/****************************************************************************************************
* Included Files
@@ -44,7 +44,7 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************************************
* Pre-processor Definitions
@@ -55,7 +55,7 @@
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32f0l0/irq.h
* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
*/
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
@@ -129,4 +129,4 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */
arch/arm/include/stm32h7/chip.h
+12 -8
View File
@@ -122,17 +122,21 @@
/* Diversification based on Family and package */
// TODO:
// #if defined(CONFIG_STM32F7_HAVE_FMC)
// # define STM32F7_NFMC 1 /* Have FMC memory controller */
// #else
// # define STM32F7_NFMC 0 /* No FMC memory controller */
// #endif
#if defined(CONFIG_STM32H7_HAVE_ETHERNET)
# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */
#else
# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
/* NVIC priority levels *************************************************************/
#if defined(CONFIG_STM32F7_HAVE_FMC)
# define STM32F7_NFMC 1 /* Have FMC memory controller */
#else
# define STM32F7_NFMC 0 /* No FMC memory controller */
#endif
/* NVIC priority levels **********************************************************o***/
/* 16 Programmable interrupt levels */
// TODO: check this
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
arch/arm/src/a1x/a1x_irq.h
+1 -1
View File
@@ -41,7 +41,7 @@
****************************************************************************/
#include <nuttx/config.h>
#include "chip/a1x_intc.h"
#include "hardware/a1x_intc.h"
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/a1x/a1x_lowputc.c
+1 -1
View File
@@ -48,7 +48,7 @@
#include "up_arch.h"
#include "a1x_config.h"
#include "chip/a1x_uart.h"
#include "hardware/a1x_uart.h"
#include "a1x_pio.h"
/****************************************************************************
arch/arm/src/a1x/a1x_pio.c
+1 -1
View File
@@ -53,7 +53,7 @@
#include "chip.h"
#include "a1x_pio.h"
#include "chip/a1x_pio.h"
#include "hardware/a1x_pio.h"
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/a1x/a1x_pio.h
+1 -1
View File
@@ -45,7 +45,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "chip/a1x_pio.h"
#include "hardware/a1x_pio.h"
/************************************************************************************
* Pre-processor Definitions
arch/arm/src/a1x/a1x_serial.c
+1 -1
View File
@@ -62,7 +62,7 @@
#include "up_internal.h"
#include "chip.h"
#include "chip/a1x_uart.h"
#include "hardware/a1x_uart.h"
#include "a1x_pio.h"
#include "a1x_serial.h"
arch/arm/src/a1x/a1x_serial.h
+1 -1
View File
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip/a1x_uart.h"
#include "hardware/a1x_uart.h"
#include "a1x_config.h"
#include "a1x_pio.h"
arch/arm/src/a1x/a1x_timerisr.c
+1 -1
View File
@@ -49,7 +49,7 @@
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip/a1x_timer.h"
#include "hardware/a1x_timer.h"
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/a1x/chip.h
+1 -1
View File
@@ -42,7 +42,7 @@
#include <nuttx/config.h>
#include "chip/a1x_memorymap.h"
#include "hardware/a1x_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/a1x/chip/a10_memorymap.h → arch/arm/src/a1x/hardware/a10_memorymap.h
+4 -4
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/a1x/a10_memorymap.h
* arch/arm/src/a1x/hardware/a10_memorymap.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_A1X_CHIP_A10_MEMORYMAP_H
#define __ARCH_ARM_SRC_A1X_CHIP_A10_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H
#define __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H
/************************************************************************************
* Included Files
@@ -615,4 +615,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_A1X_CHIP_A10_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H */
arch/arm/src/a1x/chip/a10_piocfg.h → arch/arm/src/a1x/hardware/a10_piocfg.h
+5 -5
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/a1x/chip/a10_piocfg.h
* arch/arm/src/a1x/hardware/a10_piocfg.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,15 +33,15 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H
#define __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H
#define __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/a1x_memorymap.h"
#include "hardware/a1x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
@@ -609,4 +609,4 @@
#define PIO_UART7_TX_1 (PIO_PERIPH3 | PIO_PORT_PIOI | PIO_PIN20)
#define PIO_UART7_TX_2 (PIO_PERIPH3 | PIO_PORT_PIOA | PIO_PIN14)
#endif /* __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H */
#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H */
arch/arm/src/a1x/chip/a1x_intc.h → arch/arm/src/a1x/hardware/a1x_intc.h
+5 -5
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/a1x/chip/a1x_intc.h
* arch/arm/src/a1x/hardware/a1x_intc.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,15 +33,15 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H
#define __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/a1x_memorymap.h"
#include "hardware/a1x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
@@ -203,4 +203,4 @@
#define INTC_PRIO_MASK(n) (3 << INTC_PRIO_SHIFT(n))
# define INTC_PRIO(n,p) ((uint32_t)(p) << INTC_PRIO_SHIFT(n))
#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H */
#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H */
arch/arm/src/a1x/chip/a1x_memorymap.h → arch/arm/src/a1x/hardware/a1x_memorymap.h
+5 -5
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/a1x/chip/a1x_memorymap.h
* arch/arm/src/a1x/hardware/a1x_memorymap.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_MEMORYMAP_H
#define __ARCH_ARM_SRC_A1X_CHIP_A1X_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H
/************************************************************************************
* Included Files
@@ -44,9 +44,9 @@
#include <arch/a1x/chip.h>
#if defined(CONFIG_ARCH_CHIP_A10)
# include "chip/a10_memorymap.h"
# include "hardware/a10_memorymap.h"
#else
# error Unrecognized A1X architecture
#endif
#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H */
arch/arm/src/a1x/chip/a1x_pio.h → arch/arm/src/a1x/hardware/a1x_pio.h
+5 -5
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/a1x/chip/a1x_pio.h
* arch/arm/src/a1x/hardware/a1x_pio.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,15 +33,15 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H
#define __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/a1x_memorymap.h"
#include "hardware/a1x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
@@ -217,4 +217,4 @@
/* SDRAM Pad Pull Register */
/* REVISIT: Missing register bit definitions */
#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H */
#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H */

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